thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
17 lines
625 B
Markdown
17 lines
625 B
Markdown
# sim/tb — Testbenches
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Per-subsystem SystemVerilog / Verilog testbenches.
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Planned layout (created as each subsystem lands its first stub):
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- `tb/memory/` — memory map and arbitration tests.
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- `tb/dmac/` — EE DMAC channel tests.
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- `tb/gif_gs/` — GIF packet intake and GS register decode tests.
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- `tb/sif/` — EE<->IOP mailbox/DMA tests.
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- `tb/ee/` — EE core directed tests.
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- `tb/iop/` — IOP core and IOP-DMA directed tests.
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- `tb/vif_vu/` — VIF unpack and VU microprogram tests.
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Rule: no testbench directory is created until the matching subsystem has a
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contract in `docs/contracts/` and a stub in `rtl/`.
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