ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
sim/tb — Testbenches
Per-subsystem SystemVerilog / Verilog testbenches.
Planned layout (created as each subsystem lands its first stub):
tb/memory/— memory map and arbitration tests.tb/dmac/— EE DMAC channel tests.tb/gif_gs/— GIF packet intake and GS register decode tests.tb/sif/— EE<->IOP mailbox/DMA tests.tb/ee/— EE core directed tests.tb/iop/— IOP core and IOP-DMA directed tests.tb/vif_vu/— VIF unpack and VU microprogram tests.
Rule: no testbench directory is created until the matching subsystem has a
contract in docs/contracts/ and a stub in rtl/.