# sim/tb — Testbenches

Per-subsystem SystemVerilog / Verilog testbenches.

Planned layout (created as each subsystem lands its first stub):

- `tb/memory/` — memory map and arbitration tests.
- `tb/dmac/` — EE DMAC channel tests.
- `tb/gif_gs/` — GIF packet intake and GS register decode tests.
- `tb/sif/` — EE<->IOP mailbox/DMA tests.
- `tb/ee/` — EE core directed tests.
- `tb/iop/` — IOP core and IOP-DMA directed tests.
- `tb/vif_vu/` — VIF unpack and VU microprogram tests.

Rule: no testbench directory is created until the matching subsystem has a
contract in `docs/contracts/` and a stub in `rtl/`.