thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
66 lines
2.7 KiB
Markdown
66 lines
2.7 KiB
Markdown
# FPGA Prior Art (Adjacent Consoles)
|
|
|
|
Codex correctly noted that no credible open-source HDL PS2 core surfaced. What
|
|
*did* surface, and what Codex did not log, is a small cluster of PSX-on-FPGA
|
|
projects. None are PS2, but they are the closest real-world templates for how
|
|
a console-generation FPGA effort is scoped, built, and validated.
|
|
|
|
## PSX_MiSTer — Robert Peip (FPGAzumSpass)
|
|
|
|
- Repo: https://github.com/MiSTer-devel/PSX_MiSTer
|
|
- Most feature-complete and widely-used PSX FPGA core.
|
|
- Author's prior work: GBA, Atari Lynx, WonderSwan cores on MiSTer.
|
|
|
|
The methodology is the useful part, not the RTL:
|
|
|
|
1. Peip wrote his own cycle-accurate PSX *software* emulator first.
|
|
2. Only then did he start the FPGA implementation, using the emulator as a
|
|
continuous cycle-level golden model.
|
|
3. Test vectors and traces were generated by the emulator and replayed into
|
|
the RTL under simulation.
|
|
|
|
Why this matters for retroDE_ps2:
|
|
|
|
- This is the only known methodology that has produced a credible, accurate
|
|
console-gen FPGA core from open-source work. Worth taking seriously as a
|
|
starting playbook, even if the final plan diverges.
|
|
- It implies the reference-emulator choice (PCSX2 vs DobieStation vs Play! vs
|
|
a purpose-built tiny one) is an architectural decision, not just a
|
|
debugging nicety.
|
|
|
|
## PS-FPGA
|
|
|
|
- Repo: https://github.com/PS-FPGA/ps-fpga
|
|
- Separate PSX-on-FPGA effort. Useful as a comparison point for project
|
|
organization, module decomposition, and test harness layout.
|
|
|
|
## pgate1/PlayStation_on_FPGA
|
|
|
|
- Repo: https://github.com/pgate1/PlayStation_on_FPGA
|
|
- Smaller / more hobbyist-scale PSX FPGA. Useful as a "minimum viable scaffold"
|
|
reference if the project needs a leaner starting shape than PSX_MiSTer.
|
|
|
|
## What these do not give us
|
|
|
|
- Zero usable RTL for EE, GS, VU0/VU1, VIF, GIF, SPU2, or the DMAC. The PSX's
|
|
GPU is not a GS, its CPU is not an R5900, and it has no VU complex. Nothing
|
|
transfers as a datapath.
|
|
- No GIF/GS packet path equivalent. This is a PS2-specific problem the PSX
|
|
cores did not need to solve.
|
|
|
|
## What they do give us
|
|
|
|
- A methodology template: golden-reference emulator → RTL with cycle-level
|
|
trace comparison.
|
|
- A feel for scope discipline: PSX took Peip years *with* strong prior FPGA
|
|
experience. PS2 is materially larger.
|
|
- Practical file layout, build, testbench, and host-integration patterns on
|
|
MiSTer-class platforms.
|
|
|
|
## Planning implication
|
|
|
|
Before Phase 0 lock, it is worth deciding explicitly whether retroDE_ps2 will
|
|
follow the "cycle-accurate reference emulator first" pattern, adopt an
|
|
existing emulator (PCSX2 or DobieStation) as the golden model, or take a
|
|
different validation approach entirely. The answer changes Phase 1 scope.
|