thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
57 lines
2.7 KiB
Markdown
57 lines
2.7 KiB
Markdown
# Official Sony Documentation
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Codex's pass leaned on `ps2tek` as the low-level reference. `ps2tek` is
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excellent but community-compiled. For register semantics where authority
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matters, the two original Sony manuals below sit one layer closer to silicon.
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## GS User's Manual v6.0
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- Primary register reference for the Graphics Synthesizer.
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- Covers the privileged register block at `0x12000000`: `PMODE`, `SMODE1/2`,
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`SYNCH1/2`, `SYNCHV`, `SRFSH`, `DISPFB1/2`, `DISPLAY1/2`, `EXTBUF`,
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`EXTDATA`, `EXTWRITE`, `BGCOLOR`, `CSR`, `IMR`, `BUSDIR`, `SIGLBLID`.
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- Covers GS-internal host-visible registers (PRIM, PRMODE, RGBAQ, ST, UV, XYZ,
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TEX0/1, CLAMP, FOG, TRXPOS, TRXREG, TRXDIR, etc.) and their packet forms.
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- Authoritative for PCRTC output-side behavior that `ps2tek` summarizes.
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Location: `GS Users Manual` — https://usermanual.wiki/Pdf/GSUsersManual.1012076781/html
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Suggested use: primary reference for any GIF/GS implementation work. When
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`ps2tek` and this manual disagree on a register detail, defer to the manual.
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## VU User's Manual
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- Official reference for VU0 and VU1.
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- Defines the dual-pipeline 64-bit doubleword instruction format (upper +
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lower pipe).
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- Defines register files: 32 × 128-bit VF, 16 × 16-bit VI.
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- Defines VU memories: VU0 has 4 KiB MicroMem0 + 4 KiB VU Mem0; VU1 has
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16 KiB MicroMem1 + 16 KiB VU Mem1.
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- Defines the two execution modes: micro mode (VU as standalone microprogram
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engine) and macro mode (VU0 as EE COP2; VU1 usually in micro).
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- Covers VIF-to-VU interaction enough to interpret microprogram upload paths.
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Location: `VU User's Manual (Emotion Engine Vector Operation Unit Guide)` —
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https://studylib.net/doc/25815876/vuusersmanual.158394566
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Suggested use: primary reference for VIF/VU workstream (Codex workstream 4).
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Re-read before locking any instruction-decode or pipeline-timing decision.
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## Why these matter for FPGA planning
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- Emulator source trees encode *one interpretation* of Sony's hardware. When
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the RTL has to behave like silicon at a cycle or packet level, the original
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manuals are the tiebreaker.
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- Several non-GS "hacks" in PCSX2 exist because the emulator's floating-point
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behavior diverges from the VU/EE spec. Reading the manual clarifies which of
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those are true hardware quirks vs. emulator workarounds — a distinction that
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matters more for FPGA than for software emulation.
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## Caveats
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- Both manuals are Sony confidential documents that leaked years ago. They are
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the authoritative source on register semantics but were never officially
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published. Treat them as technical reference, not as a licensing document.
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- Version drift: the GS manual is v6.0 in the linked copy. Late-silicon
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revisions may not be covered exhaustively.
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