thejayman77 b29fb17a11 QSF: OPTIMIZATION_MODE AGGRESSIVE AREA -> BALANCED (close -0.103ns EMIF path)
After the fog prune the design clock closed (+0.631ns) but a 310MHz EMIF path
missed by 103ps: the Z-req FIFO read-address register u_zc_emit|u_req|raddr_hi1_q[4]
fans out to 6 spread M20K blocks. Quartus flagged TMC-20551 (needs more register
duplication), which AGGRESSIVE AREA mode was suppressing. That mode is a leftover
from the resolved LAB-overflow era; utilization has headroom (ALM 85%, DSP 45%,
RAM unaffected by opt mode). BALANCED lets the fitter duplicate the address
register to close the path. QSF-only, no RTL change.

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-07-20 22:04:00 -04:00

retroDE_ps2 Planning Docs

This directory is the working design scaffold for the PS2 core.

Purpose:

  • define the intended repository shape before RTL lands,
  • define subsystem boundaries before implementation choices harden,
  • document what each block owns, what crosses the boundary, and how we will validate it.

Recommended reading order:

  1. repo_layout.md
  2. phase0_checklist.md
  3. contracts/README.md
  4. stub_module_plan.md
  5. wave2_dma_gif_plan.md
  6. wave25_memory_backed_dma_plan.md
  7. wave26_multi_beat_dma_plan.md

Relationship to references/:

  • references/ is the research library.
  • docs/ is the project-definition layer.

Rule of thumb:

  • If a file explains PS2 hardware as it exists, it belongs under references/.
  • If a file explains how retroDE_ps2 intends to model, partition, or validate that hardware, it belongs under docs/.
S
Description
No description provided
Readme 8.2 MiB
Languages
SystemVerilog 75.5%
Verilog 15.4%
Tcl 4.7%
HTML 1.1%
Python 1%
Other 2.3%