<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2026.03.02.18:44:04"
 outputDirectory="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Agilex 5"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="A5EB013BB23BE4SCS"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="4"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_BOARD"
     type="String"
     defaultValue="default"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_S0_AXI4_CLOCK_IN_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_S0_AXI4_CLOCK_IN_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_S0_AXI4_CLOCK_IN_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_S0_AXI4_CPU_INFO_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_S0_AXI4LITE_CLOCK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_S0_AXI4LITE_CLOCK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_S0_AXI4LITE_CLOCK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_S0_AXI4LITE_CPU_INFO_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_REF_CLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_REF_CLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_REF_CLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <interface name="s0_axi4_clock_in" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="s0_axi4_clock_in" direction="input" role="clk" width="1" />
  </interface>
  <interface name="core_init_n" kind="reset" start="0">
   <property name="associatedClock" value="" />
   <property name="synchronousEdges" value="NONE" />
   <port name="core_init_n" direction="input" role="reset_n" width="1" />
  </interface>
  <interface name="s0_axi4_ctrl_ready" kind="reset" start="1">
   <property name="associatedClock" value="" />
   <property name="associatedDirectReset" value="" />
   <property name="associatedResetSinks" value="none" />
   <property name="synchronousEdges" value="NONE" />
   <port name="s0_axi4_reset_n" direction="output" role="reset_n" width="1" />
  </interface>
  <interface name="s0_axi4" kind="axi4" start="0">
   <property name="associatedClock" value="s0_axi4_clock_in" />
   <property name="associatedReset" value="s0_axi4_ctrl_ready" />
   <property name="optionalAssociatedReset" value="false" />
   <property name="trustzoneAware" value="true" />
   <property name="wakeupSignals" value="false" />
   <property name="uniqueIdSupport" value="false" />
   <property name="poison" value="false" />
   <property name="traceSignals" value="false" />
   <property name="isTranslator" value="false" />
   <property name="maximumOutstandingReads" value="1" />
   <property name="maximumOutstandingWrites" value="1" />
   <property name="maximumOutstandingTransactions" value="1" />
   <property name="dataCheck" value="false" />
   <property name="addressCheck" value="false" />
   <property name="securityAttribute" value="false" />
   <property name="userData" value="false" />
   <property name="readAcceptanceCapability" value="64" />
   <property name="writeAcceptanceCapability" value="64" />
   <property name="combinedAcceptanceCapability" value="64" />
   <property name="readDataReorderingDepth" value="1" />
   <property name="bridgesToMaster" value="" />
   <property name="dfhFeatureGuid" value="0" />
   <property name="dfhGroupId" value="0" />
   <property name="dfhParameterId" value="" />
   <property name="dfhParameterName" value="" />
   <property name="dfhParameterVersion" value="" />
   <property name="dfhParameterData" value="" />
   <property name="dfhParameterDataLength" value="" />
   <property name="dfhFeatureMajorVersion" value="0" />
   <property name="dfhFeatureMinorVersion" value="0" />
   <property name="dfhFeatureId" value="35" />
   <property name="dfhFeatureType" value="3" />
   <property name="noNarrowTransfer" value="false" />
   <port name="s0_axi4_awaddr" direction="input" role="awaddr" width="30" />
   <port name="s0_axi4_awburst" direction="input" role="awburst" width="2" />
   <port name="s0_axi4_awid" direction="input" role="awid" width="7" />
   <port name="s0_axi4_awlen" direction="input" role="awlen" width="8" />
   <port name="s0_axi4_awlock" direction="input" role="awlock" width="1" />
   <port name="s0_axi4_awqos" direction="input" role="awqos" width="4" />
   <port name="s0_axi4_awsize" direction="input" role="awsize" width="3" />
   <port name="s0_axi4_awvalid" direction="input" role="awvalid" width="1" />
   <port name="s0_axi4_awuser" direction="input" role="awuser" width="14" />
   <port name="s0_axi4_awprot" direction="input" role="awprot" width="3" />
   <port name="s0_axi4_awready" direction="output" role="awready" width="1" />
   <port name="s0_axi4_araddr" direction="input" role="araddr" width="30" />
   <port name="s0_axi4_arburst" direction="input" role="arburst" width="2" />
   <port name="s0_axi4_arid" direction="input" role="arid" width="7" />
   <port name="s0_axi4_arlen" direction="input" role="arlen" width="8" />
   <port name="s0_axi4_arlock" direction="input" role="arlock" width="1" />
   <port name="s0_axi4_arqos" direction="input" role="arqos" width="4" />
   <port name="s0_axi4_arsize" direction="input" role="arsize" width="3" />
   <port name="s0_axi4_arvalid" direction="input" role="arvalid" width="1" />
   <port name="s0_axi4_aruser" direction="input" role="aruser" width="14" />
   <port name="s0_axi4_arprot" direction="input" role="arprot" width="3" />
   <port name="s0_axi4_arready" direction="output" role="arready" width="1" />
   <port name="s0_axi4_wdata" direction="input" role="wdata" width="256" />
   <port name="s0_axi4_wstrb" direction="input" role="wstrb" width="32" />
   <port name="s0_axi4_wlast" direction="input" role="wlast" width="1" />
   <port name="s0_axi4_wvalid" direction="input" role="wvalid" width="1" />
   <port name="s0_axi4_wready" direction="output" role="wready" width="1" />
   <port name="s0_axi4_bready" direction="input" role="bready" width="1" />
   <port name="s0_axi4_bid" direction="output" role="bid" width="7" />
   <port name="s0_axi4_bresp" direction="output" role="bresp" width="2" />
   <port name="s0_axi4_bvalid" direction="output" role="bvalid" width="1" />
   <port name="s0_axi4_rready" direction="input" role="rready" width="1" />
   <port name="s0_axi4_rdata" direction="output" role="rdata" width="256" />
   <port name="s0_axi4_rid" direction="output" role="rid" width="7" />
   <port name="s0_axi4_rlast" direction="output" role="rlast" width="1" />
   <port name="s0_axi4_rresp" direction="output" role="rresp" width="2" />
   <port name="s0_axi4_rvalid" direction="output" role="rvalid" width="1" />
  </interface>
  <interface name="s0_axi4lite_clock" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="s0_axi4lite_clock" direction="input" role="clk" width="1" />
  </interface>
  <interface name="s0_axi4lite_reset_n" kind="reset" start="0">
   <property name="associatedClock" value="s0_axi4lite_clock" />
   <property name="synchronousEdges" value="DEASSERT" />
   <port name="s0_axi4lite_reset_n" direction="input" role="reset_n" width="1" />
  </interface>
  <interface name="s0_axi4lite" kind="axi4lite" start="0">
   <property name="associatedClock" value="s0_axi4lite_clock" />
   <property name="associatedReset" value="s0_axi4lite_reset_n" />
   <property name="optionalAssociatedReset" value="false" />
   <property name="trustzoneAware" value="true" />
   <property name="wakeupSignals" value="false" />
   <property name="uniqueIdSupport" value="false" />
   <property name="poison" value="false" />
   <property name="traceSignals" value="false" />
   <property name="isTranslator" value="false" />
   <property name="maximumOutstandingReads" value="1" />
   <property name="maximumOutstandingWrites" value="1" />
   <property name="maximumOutstandingTransactions" value="1" />
   <property name="dataCheck" value="false" />
   <property name="addressCheck" value="false" />
   <property name="securityAttribute" value="false" />
   <property name="userData" value="false" />
   <property name="readAcceptanceCapability" value="1" />
   <property name="writeAcceptanceCapability" value="1" />
   <property name="combinedAcceptanceCapability" value="1" />
   <property name="readDataReorderingDepth" value="1" />
   <property name="bridgesToMaster" value="" />
   <property name="dfhFeatureGuid" value="0" />
   <property name="dfhGroupId" value="0" />
   <property name="dfhParameterId" value="" />
   <property name="dfhParameterName" value="" />
   <property name="dfhParameterVersion" value="" />
   <property name="dfhParameterData" value="" />
   <property name="dfhParameterDataLength" value="" />
   <property name="dfhFeatureMajorVersion" value="0" />
   <property name="dfhFeatureMinorVersion" value="0" />
   <property name="dfhFeatureId" value="35" />
   <property name="dfhFeatureType" value="3" />
   <port name="s0_axi4lite_awaddr" direction="input" role="awaddr" width="27" />
   <port name="s0_axi4lite_awprot" direction="input" role="awprot" width="3" />
   <port name="s0_axi4lite_awvalid" direction="input" role="awvalid" width="1" />
   <port
       name="s0_axi4lite_awready"
       direction="output"
       role="awready"
       width="1" />
   <port name="s0_axi4lite_araddr" direction="input" role="araddr" width="27" />
   <port name="s0_axi4lite_arprot" direction="input" role="arprot" width="3" />
   <port name="s0_axi4lite_arvalid" direction="input" role="arvalid" width="1" />
   <port
       name="s0_axi4lite_arready"
       direction="output"
       role="arready"
       width="1" />
   <port name="s0_axi4lite_wdata" direction="input" role="wdata" width="32" />
   <port name="s0_axi4lite_wstrb" direction="input" role="wstrb" width="4" />
   <port name="s0_axi4lite_wvalid" direction="input" role="wvalid" width="1" />
   <port name="s0_axi4lite_wready" direction="output" role="wready" width="1" />
   <port name="s0_axi4lite_bready" direction="input" role="bready" width="1" />
   <port name="s0_axi4lite_bresp" direction="output" role="bresp" width="2" />
   <port name="s0_axi4lite_bvalid" direction="output" role="bvalid" width="1" />
   <port name="s0_axi4lite_rready" direction="input" role="rready" width="1" />
   <port name="s0_axi4lite_rdata" direction="output" role="rdata" width="32" />
   <port name="s0_axi4lite_rresp" direction="output" role="rresp" width="2" />
   <port name="s0_axi4lite_rvalid" direction="output" role="rvalid" width="1" />
  </interface>
  <interface name="mem_0" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="mem_0_cs" direction="output" role="mem_cs" width="1" />
   <port name="mem_0_ca" direction="output" role="mem_ca" width="6" />
   <port name="mem_0_cke" direction="output" role="mem_cke" width="1" />
   <port name="mem_0_dq" direction="bidir" role="mem_dq" width="32" />
   <port name="mem_0_dqs_t" direction="bidir" role="mem_dqs_t" width="4" />
   <port name="mem_0_dqs_c" direction="bidir" role="mem_dqs_c" width="4" />
   <port name="mem_0_dmi" direction="bidir" role="mem_dmi" width="4" />
  </interface>
  <interface name="mem_ck_0" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="mem_0_ck_t" direction="output" role="mem_ck_t" width="1" />
   <port name="mem_0_ck_c" direction="output" role="mem_ck_c" width="1" />
  </interface>
  <interface name="mem_reset_n" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="mem_0_reset_n" direction="output" role="mem_reset_n" width="1" />
  </interface>
  <interface name="oct_0" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="oct_rzqin_0" direction="input" role="oct_rzqin" width="1" />
  </interface>
  <interface name="ref_clk" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="ref_clk" direction="input" role="clk" width="1" />
  </interface>
 </perimeter>
 <entity
   kind="EMIF_Qsys_emif_io96b_lpddr4_0"
   version="1.0"
   name="EMIF_Qsys_emif_io96b_lpddr4_0">
  <parameter name="AUTO_S0_AXI4_CLOCK_IN_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_S0_AXI4_CLOCK_IN_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_S0_AXI4_CLOCK_IN_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="AUTO_BOARD" value="default" />
  <parameter name="AUTO_REF_CLK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_S0_AXI4LITE_CPU_INFO_ID" value="" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="AUTO_REF_CLK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_REF_CLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_S0_AXI4LITE_CLOCK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_S0_AXI4LITE_CLOCK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_S0_AXI4_CPU_INFO_ID" value="" />
  <parameter name="AUTO_S0_AXI4LITE_CLOCK_CLOCK_DOMAIN" value="-1" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/synth/EMIF_Qsys_emif_io96b_lpddr4_0.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/synth/EMIF_Qsys_emif_io96b_lpddr4_0.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0.ip" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/emif_io96b/ip_lpddr4/emif_io96b_lpddr4_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcmodel.components.tclelement.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopc.generator.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.ddmwriter.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcdocument.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.hdlwriter.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcmodel.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.common.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.intel.quartus.ngpd.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.intel.shared.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jacl1.3.2a.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/commons-text-1.10.0.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/commons-lang3-3.12.0.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/guava-32.0.1-jre.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jfreechart-1.5.0.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/miglayout-swing-5.2.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/docking-frames-common-1.1.2_20c.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/bare-bones-browser-launch-3.2.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jaxb-api.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jaxb-jxc.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jaxb-runtime.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jaxb-xjc.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/codemodel.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/dtd-parser.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/FastInfoset.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/istack-commons-runtime.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/istack-commons-tools.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/javax.activation-api.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/relaxng-datatype.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/rngom.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/stax-ex.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/txw2.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/xsom.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/failureaccess-1.0.1.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/listenablefuture-9999.0-empty-to-avoid-conflict-with-guava.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jsr305-3.0.2.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/checker-qual-3.33.0.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/j2objc-annotations-2.8.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/miglayout-core-5.2.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/docking-frames-core-1.1.2_20c.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/commons-io-2.13.0.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.model.common.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/antlr4-runtime-4.7.2.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopclibrary.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.ipxact.module.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.intel.quartus.dni.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcreport.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopc.qsymbol.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcmodel.transforms.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.hypericonnect.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.tcl.interpreter.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/emif_io96b/ip_cal/ip/emif_io96b_cal_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/alt_mem_if/alt_mem_if_jtag_master/alt_mem_if_jtag_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_avalon_st_jtag_interface_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_bytes_to_packets/altera_avalon_st_bytes_to_packets_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_packets_to_master/altera_avalon_packets_to_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry"</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: HMC=0 (0: Wide/1: Slim) is_used=1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tck_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcl_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcl_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tch_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tch_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tras to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trrd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trcd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tccdmw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsq to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trpre to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trpst to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqss_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqss_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twpre to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twpst to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twtr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trppb to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trpab to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtp to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdipw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdss to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdsh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsl to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tck_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tch_abs_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tch_abs_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcl_abs_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcl_abs_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting clkCyclesToAverageOver to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tjit_per_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tjit_per_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tjit_cc_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tjit_cc_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckdl to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckdlRollingWindowL to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckdm to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckdlRollingWindowM to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckds to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckdlRollingWindowS to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsl_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsh_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tras_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_start to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtp_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trcd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trppb_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trpab_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tras_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twr_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twtr_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trrd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trpste to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting txp to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting txp_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trfcab to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trfcpb to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trefw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting txsv to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting txsv_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckckel to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckckel_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting writeTL to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting readTL to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tsr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tsr_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tinit1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tinit2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tinit3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tinit4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tinit5 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqcal to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqlat to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tck_min_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tck_max_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tiscke_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tihcke_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_min_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_max_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsq_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tiscke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tihcke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting powerUpTime to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqreset to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqreset_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tadr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvreflong to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcaent to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrz to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tsdramDerating to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelcmd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckehcmd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelpd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tescke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcmdcke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckckeh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcsckeh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twlmrd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twldqsen to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twls to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twlh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twlo to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twlo_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelcmd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckehcmd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelpd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcke_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tODTon_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tODTon_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tODToff_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tODToff_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tfaw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tppd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcipw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twrwtr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twrwtr_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtrrd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtrrd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtm to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtm_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcsvref to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tfc to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdstrain to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdhtrain to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tpw_reset to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckprecs to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckpstcs to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspe to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspx to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckprecs_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckpstcs_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspe_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspx_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelck_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckprewl_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckpstwl_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrcg_enable to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrcg_disable to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqlat_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqscke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqscke_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckehdqs to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrw_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrefmed to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrefshort to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tfcmed to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tfcshort to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twtm to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twtm_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcscke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqcke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqcke_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckckeh_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcmdcke_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tpgm to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tpgm_exit to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tpgmpst to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tescke_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrwckel to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrwckel_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tsdo to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tsdo_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting txsr_abort to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckprewl to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckpstwl to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tlat to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tosco to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tfaw_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspe_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tosco_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtwcorrection to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tpbr2pbr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcmdtp to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tderate to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspe_se to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspx_se to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_random_ch_a to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_random_ch_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcacdm2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspe_se_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspx_se_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcacdm2_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trefrate to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trefrate_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq_variation to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq_variation_ch_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq_variation_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsta to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrefweak to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrefca_long to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrefca_short to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twdqstol to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trfmab to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trfmpb to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckj to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_drift to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_drift_win to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcs_a to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcs_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcke_a to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcke_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a5 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b5 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_a0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_a1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_b0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_b1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_a0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_a1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_b0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_b1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_a0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_a1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_b0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_b1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_a0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_a1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_b0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_b1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_a0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_a1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_b0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_b1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_a0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_a1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_b0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_b1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a5 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a6 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a7 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a8 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a9 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a10 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a11 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a12 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a13 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a14 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a15 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a2O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a3O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a4O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a5O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a6O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a7O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a8O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a9O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a10O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a11O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a12O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a13O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a14O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a15O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b5 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b6 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b7 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b8 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b9 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b10 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b11 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b12 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b13 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b14 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b15 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b2O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b3O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b4O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b5O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b6O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b7O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b8O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b9O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b10O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b11O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b12O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b13O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b14O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b15O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegDeviceInfo to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegDevFt1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegDevFt2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegIoCfg1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegRefOrTemp to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegBasicCfg1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegBasicCfg2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegBasicCfg3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegBasicCfg4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegTestMode to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegIOCalib to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg11 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg12 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg13 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg14 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg15 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg16 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg17 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg18 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg19 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg20 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg21 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg22 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg23 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg32 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg40 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting minNumOfRefsReqd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numRefsPostponedMax to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numRefsPulledInMax to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg24 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting validDataBeatDuringMRR to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numRefsWithin2trefi to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting autoRefreshAtSREntry to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting VrefCASetting to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting VrefCADelta to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting VrefDQSetting to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting VrefDQDelta to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting delayDeratingAfterMR4ReadCycles to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numCumulativeRefsPostponedMax to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numCumulativeRefsPulledInMax to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting macLimit to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg25 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg26 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numDqsPulsesInWriteLeveling to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg31 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numDqsPulsesInCATraining to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dqsJitterVariance to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg27 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg36 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg37 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting autoRefreshAtSRExit to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting useTmrwInsteadOfTfc to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting isSRCountedForPullin to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting zqIgnoreCrossChannelErrors to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting zqLatchCheckPDClockStop to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dqsOscCheckPDClockStop to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting isTrefiFixedForMaxPullin to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting refPostponeInTrefw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegDef to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting refreshReq to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting refreshDebugInfo to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting noXOnDataLineDuringMRR to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting skipInitialization to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting corruptOnMissingRefresh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting startRefreshCountPostFirstWrite to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting vrefSettings to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting generalSettings to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting ckeAsync to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting trainingSettings to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting ignoreTrainingSetupHoldErrors to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting enhancedRefresh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting fifoDuringTrfcTxsr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting checkCKPulsePostCATrain to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dbiDuringMRR to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting isRefreshAllowedPostMaxPullin to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting firstCycleViolations to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting delayAutoPrecharge to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting latchVrefcaOn2DqsPulse to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting ignoreRefabIntfaw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting extraCyclesPriorClockStop to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting useIgnoredRefPostMaxPullin to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting violationsAtClockStopEntry to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting zqCalCheckPDClockStop to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting writePreAmble4tck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dqsValidRegionDuringWrite to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting lpddr4e to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting extraWritePambleViolation to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting discountRefreshPostSRExit to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting corruptWriteLevelingDataOnSetupHoldErr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting exploration to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting enableTdqsicycCheck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting prevDataOnSetupHoldErr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting updateDQSOscReg to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting lowerByteDevice to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting randomDqsJitter to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting randomDqsGlitch to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting bypassModel to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting enableClkErrors to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting randomDqsGlitch_ch_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dqsSharedBetweenChannels to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting isDiffValidInSEMode to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting randomInsteadOfXInWriteDataOnBurstErr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting skipMissedBeatDuringWriteBurst to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting allowInvalidClkDuringtCKFSPESEMode to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting startInSelfRefreshState to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting trCallbackOnNop to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting clkStopChecks to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting isNopValid to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting lpddr4x to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting doNotAllowResetInInit to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting support64GbDensityPerDie to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CK_t_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CK_c_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CK_t_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CK_c_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CKE_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CKE_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CS_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CS_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CA_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CA_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting ODT_CA_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting ODT_CA_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQ_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQ_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQS_t_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQS_c_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQS_t_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQS_c_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DMI_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DMI_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting RESET_n to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dataCallbackForInvalidDataBeatDuringMRR to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting applyRefRateAfterMR4BackdoorWrite to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting disRAAUpdateWhenShorttREFI to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting lowInsteadOfXForInvalidCalibData to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting skipCkDiffCheckDuringSeToDiffSwitch to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting controlledRandDqsck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting monitorMode to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting resetMemContentsAfterReset to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting memSizeMbits to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numBanks to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting columnAddrWidth to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global dq_per_dqs</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0A</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0B</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0C</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0D</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0E</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0F</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC1X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC2X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC3X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC4X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC5X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC6X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC7X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC8X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC9X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RCAX</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RCBX</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global Per_Bank_Refresh</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of numBanks: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter numBanks.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; numBanks = 8.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of rowWidth: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; rowWidth = 15.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of colWidth: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; colWidth = 10.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DQ_A: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter DQ_A.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; DQ_A = 16.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DQS_t_A: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter DQS_t_A.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; DQS_t_A = 2.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of memSizeMbits: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter memSizeMbits.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; memSizeMbits = 4096.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of minNumOfRefsReqd: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter minNumOfRefsReqd.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; minNumOfRefsReqd = 8192.0.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of data_mask_en: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; data_mask_en = true.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of modeRegBasicCfg4: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter modeRegBasicCfg4.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; modeRegBasicCfg4 = 0.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of dq_per_dqs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter dq_per_dqs.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; dq_per_dqs = 8.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; Burst_Length = 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; CasLatencyList = 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; WR_CAS_Lat = 18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; SimMhzList = 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; AP_Sim = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; Additive_Lat = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; RDPREAMBLE_EN = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; BOF_EN = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; WLS_EN = 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; RDDBI_EN = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; WRDBI_EN = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; RDPSTMBLE_EN = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; WRPSTMBLE_EN = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; CRC_EN = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; CRC_Enable = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; BANKModeList = 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; RD_Link_ECC = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; WR_Link_ECC = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; X8_Device = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; CA_Parity_Lat = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; Fine_Granularity_Refresh = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; Per_Bank_Refresh = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; VDD_RANGE = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; DFI_Cmd_Ratio_4to1 = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; is_x4 = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TSR_NS = 15.0: tsr = SOMA_UNASSIGNED --&gt; {15.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Global Parameter txsr does not exist</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TXP_NS = 7.5: txp = SOMA_UNASSIGNED --&gt; {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Global Parameter tccd does not exist</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRTP_NS = 7.5: trtp = SOMA_UNASSIGNED --&gt; {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRCD_NS = 18.0: trcd = SOMA_UNASSIGNED --&gt; {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRPPB_NS = 18.0: trppb = SOMA_UNASSIGNED --&gt; {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRPAB_NS = 21.0: trpab = SOMA_UNASSIGNED --&gt; {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRAS_NS = 42.0: tras = SOMA_UNASSIGNED --&gt; {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TWR_NS = 18.0: twr = SOMA_UNASSIGNED --&gt; {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TWTR_NS = 10.0: twtr = SOMA_UNASSIGNED --&gt; {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRRD_NS = 10.0: trrd = SOMA_UNASSIGNED --&gt; {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TPPD_CYC = 4.0: tppd = SOMA_UNASSIGNED --&gt; {4.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TFAW_NS = 40.0: tfaw = SOMA_UNASSIGNED --&gt; {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Global Parameter trc does not exist</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">converting from NS to ms (MEM_TREFW_NS=3.2E7)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TREFW_MS = 32.0: trefw = SOMA_UNASSIGNED --&gt; {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Global Parameter trefi does not exist</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRFCAB_NS = 180.0: trfcab = SOMA_UNASSIGNED --&gt; {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRFCPB_NS = 90.0: trfcpb = SOMA_UNASSIGNED --&gt; {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKE_NS = 7.5: tcke = SOMA_UNASSIGNED --&gt; {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCMDCKE_NS = 2.81: tcmdcke = SOMA_UNASSIGNED --&gt; {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKELCK_NS = 5.0: tckelck = SOMA_UNASSIGNED --&gt; {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCSCKE_NS = 1.75: tcscke = SOMA_UNASSIGNED --&gt; {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKCKEH_NS = 2.81: tckckeh = SOMA_UNASSIGNED --&gt; {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCSCKEH_NS = 1.75: tcsckeh = SOMA_UNASSIGNED --&gt; {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TMRWCKEL_NS = 14.0: tmrwckel = SOMA_UNASSIGNED --&gt; {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TZQCKE_NS = 2.81: tzqcke = SOMA_UNASSIGNED --&gt; {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">converting from NS to cyc (MEM_TMRR_NS=7.5)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TMRR_CYC = 8.0: tmrr = SOMA_UNASSIGNED --&gt; {8.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TMRW_NS = 10.0: tmrw = SOMA_UNASSIGNED --&gt; {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TMRD_NS = 14.0: tmrd = SOMA_UNASSIGNED --&gt; {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TESCKE_NS = 2.81: tescke = SOMA_UNASSIGNED --&gt; {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">converting from NS to us (MEM_TZQCAL_NS=1000.0)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TZQCAL_US = 1.0: tzqcal = SOMA_UNASSIGNED --&gt; {1.0 us}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TZQLAT_NS = 30.0: tzqlat = SOMA_UNASSIGNED --&gt; {30.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">converting from NS to ps (MEM_TDQSCK_MAX_NS=3.5)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TDQSCK_MAX_PS = 3500.0: tdqsck_max = SOMA_UNASSIGNED --&gt; {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">converting from NS to ps (MEM_TDQSCK_MIN_NS=1.5)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TDQSCK_MIN_PS = 1500.0: tdqsck_min = SOMA_UNASSIGNED --&gt; {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKCKEL_NS = 5.0: tckckel = SOMA_UNASSIGNED --&gt; {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKELCMD_NS = 5.0: tckelcmd = SOMA_UNASSIGNED --&gt; {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKEHCMD_NS = 7.5: tckehcmd = SOMA_UNASSIGNED --&gt; {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_drive_strength: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_drive_strength = 6.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_rtt_dq: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_rtt_dq = 5.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_rx_vref_dq: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_rx_vref_dq = 20.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_rx_vref_dq_range: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_rx_vref_dq_range = 0.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_ca_vref_range: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_ca_vref_range = 1.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_ca_vref_value: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_ca_vref_value = 13.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_ca_comm_odt: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_ca_comm_odt = 3.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_ck_odt_en: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_ck_odt_en = 1.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_cs_odt_en: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_cs_odt_en = 1.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_ca_odt_dis: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_ca_odt_dis = 0.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of componentDdrSOMA: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Rows_Supported: Parameter value 18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_Columns_Supported: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Columns_Supported: Parameter value 11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep_x40: Parameter value false</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of numChannels: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of HMC_Interface: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_enabled: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Memory_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: cadence_reg__MEM_DP_REDUCTION: is_lockstep_x40=false num_channels=1 dq_per_channel=32 hmc_interface=0 ecc_enabled=0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__START" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__START --&gt; Returned 0: CADENCE_DEBUG_REG: START:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DRAM_CLASS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DRAM_CLASS --&gt; Returned 11: CADENCE_DEBUG_REG: DRAM_CLASS:RW:8:4:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CONTROLLER_ID" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CONTROLLER_ID --&gt; Returned 4166: CADENCE_DEBUG_REG: CONTROLLER_ID:RD:16:16:=0x1046</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CONTROLLER_VERSION (CONTROLLER_VERSION RD CONTROLLER_VERSION ZERO ZERO FULL CTL {{Holds the controller version id. READ-ONLY }} 32 OPEN WIRE WIRE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MAX_ROW_REG (MAX_ROW_REG RD ROW_WIDTH ZERO ROW_WIDTH ROW_WIDTH CTL {{Holds the maximum width of memory address bus. READ-ONLY }} 96 OPEN WIRE WIRE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MAX_COL_REG" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_Columns_Supported: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Columns_Supported: Parameter value 11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MAX_COL_REG --&gt; Returned 11: CADENCE_DEBUG_REG: MAX_COL_REG:RD:8:4:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MAX_CS_REG (MAX_CS_REG RD MAX_CS ZERO MAX_CS FULL CTL {{Holds the maximum number of chip selects available. READ-ONLY }} 112 OPEN WIRE WIRE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WRITE_DATA_FIFO_DEPTH (WRITE_DATA_FIFO_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the controller core write data latency queue. READ-ONLY }} 120 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WRITE_DATA_FIFO_PTR_WIDTH (WRITE_DATA_FIFO_PTR_WIDTH RD {} ZERO ZERO FULL CTL {{Reports the width of the controller core write data latency queue pointer. READ-ONLY }} 128 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MEMCD_RMODW_FIFO_DEPTH (MEMCD_RMODW_FIFO_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the controller core read/modify/write FIFO. READ-ONLY }} 136 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MEMCD_RMODW_FIFO_PTR_WIDTH (MEMCD_RMODW_FIFO_PTR_WIDTH RD {} ZERO ZERO FULL CTL {{Reports the width of the controller core read/modify/write FIFO pointer. READ-ONLY }} 152 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ASYNC_CDC_STAGES (ASYNC_CDC_STAGES RD {} ZERO ZERO FULL CTL {{Reports the number of synchronizer delays specified for the asynchronous boundary crossings. READ-ONLY }} 160 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AXI0_CMDFIFO_LOG2_DEPTH (AXI0_CMDFIFO_LOG2_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the AXI port 0 command FIFO. Value is the log2 value of the depth. READ-ONLY }} 168 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AXI0_RDFIFO_LOG2_DEPTH (AXI0_RDFIFO_LOG2_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the AXI port 0 read data FIFO. Value is the log2 value of the depth. READ-ONLY }} 176 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AXI0_WR_ARRAY_LOG2_DEPTH (AXI0_WR_ARRAY_LOG2_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the AXI port 0 write data array. Value is the log2 value of the depth. READ-ONLY }} 184 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AXI0_TRANS_WRFIFO_LOG2_DEPTH (AXI0_TRANS_WRFIFO_LOG2_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the AXI port 0 transition write data FIFO. Value is the log2 value of the depth. READ-ONLY }} 192 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH (AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the AXI port 0 write command processing FIFO. Value is the log2 value of the depth. READ-ONLY }} 200 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NO_AUTO_MRR_INIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NO_AUTO_MRR_INIT --&gt; Returned 0: CADENCE_DEBUG_REG: NO_AUTO_MRR_INIT:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MRR_ERROR_STATUS (MRR_ERROR_STATUS RD {} ZERO ZERO FULL CTL {{Indicates that an MRR was issued while in self-refresh. Value of 1 indicates a violation. READ-ONLY }} 256 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_FREQ_RATIO 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_FREQ_RATIO 0 --&gt; Returned 2: CADENCE_DEBUG_REG: DFI_FREQ_RATIO_F0:RW:8:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_FREQ_RATIO 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_FREQ_RATIO 1 --&gt; Returned 2: CADENCE_DEBUG_REG: DFI_FREQ_RATIO_F1:RW:16:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_FREQ_RATIO 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_FREQ_RATIO 2 --&gt; Returned 2: CADENCE_DEBUG_REG: DFI_FREQ_RATIO_F2:RW:24:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_CMD_RATIO" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_CMD_RATIO --&gt; Returned 2: CADENCE_DEBUG_REG: DFI_CMD_RATIO:RD:0:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_VALUE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_VALUE --&gt; Returned 1: CADENCE_DEBUG_REG: ODT_VALUE:RW:8:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHY_INDEP_TRAIN_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHY_INDEP_TRAIN_MODE --&gt; Returned 1: CADENCE_DEBUG_REG: PHY_INDEP_TRAIN_MODE:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TSREF2PHYMSTR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TSREF2PHYMSTR --&gt; Returned 16: CADENCE_DEBUG_REG: TSREF2PHYMSTR:RW:24:6:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHY_INDEP_INIT_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHY_INDEP_INIT_MODE --&gt; Returned 1: CADENCE_DEBUG_REG: PHY_INDEP_INIT_MODE:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFIBUS_FREQ 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFIBUS_FREQ 0 --&gt; Returned 0: CADENCE_DEBUG_REG: DFIBUS_FREQ_F0:RW:8:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFIBUS_FREQ 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFIBUS_FREQ 1 --&gt; Returned 1: CADENCE_DEBUG_REG: DFIBUS_FREQ_F1:RW:16:5:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFIBUS_FREQ 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFIBUS_FREQ 2 --&gt; Returned 2: CADENCE_DEBUG_REG: DFIBUS_FREQ_F2:RW:24:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__FREQ_CHANGE_TYPE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FREQ_CHANGE_TYPE 0 --&gt; Returned 0: CADENCE_DEBUG_REG: FREQ_CHANGE_TYPE_F0:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__FREQ_CHANGE_TYPE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FREQ_CHANGE_TYPE 1 --&gt; Returned 1: CADENCE_DEBUG_REG: FREQ_CHANGE_TYPE_F1:RW:8:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__FREQ_CHANGE_TYPE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FREQ_CHANGE_TYPE 2 --&gt; Returned 2: CADENCE_DEBUG_REG: FREQ_CHANGE_TYPE_F2:RW:16:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS (LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS RD {} ZERO ZERO FULL CTL {{Error response for Software issued Low power command while DQS Oscillator is in progress. READ-ONLY }} 376 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_PER_CS_OOV_TRAINING_STATUS (DQS_OSC_PER_CS_OOV_TRAINING_STATUS RD {} ZERO ZERO FULL CTL {{Set the CS information for which DQS oscillator is having out of variance value. READ-ONLY }} 384 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_TST" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_TST --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_TST:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_MPC_CMD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_MPC_CMD --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_MPC_CMD:RW:0:28:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_LSB_REG" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_LSB_REG --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_LSB_REG:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_MSB_REG" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_MSB_REG --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_MSB_REG:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_ENABLE:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_PERIOD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_PERIOD --&gt; Returned 512: CADENCE_DEBUG_REG: DQS_OSC_PERIOD:RW:0:15:=0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__FUNC_VALID_CYCLES" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FUNC_VALID_CYCLES --&gt; Returned 2: CADENCE_DEBUG_REG: FUNC_VALID_CYCLES:RW:16:4:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_NORM_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_NORM_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_NORM_THRESHOLD:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_HIGH_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_HIGH_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_HIGH_THRESHOLD:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_TIMEOUT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_TIMEOUT --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_TIMEOUT:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_PROMOTE_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_PROMOTE_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_PROMOTE_THRESHOLD:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__OSC_VARIANCE_LIMIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__OSC_VARIANCE_LIMIT --&gt; Returned 16: CADENCE_DEBUG_REG: OSC_VARIANCE_LIMIT:RW:0:16:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_REQUEST" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_REQUEST --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_REQUEST:WR:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WCKO_OSC_PERIOD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WCKO_OSC_PERIOD --&gt; Returned 512: CADENCE_DEBUG_REG: WCKO_OSC_PERIOD:RW:0:15:=0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSCO 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tosco: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSCO 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSCO_F0:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSCO 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tosco: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSCO 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSCO_F1:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSCO 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tosco: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSCO 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSCO_F2:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSC_TRK_CALC 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {ttrkcalcinit ttrkcalccur}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalcinit: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalccur: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSC_TRK_CALC 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSC_TRK_CALC_F0:RW:8:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSC_TRK_CALC 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {ttrkcalcinit ttrkcalccur}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalcinit: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalccur: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSC_TRK_CALC 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSC_TRK_CALC_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSC_TRK_CALC 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {ttrkcalcinit ttrkcalccur}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalcinit: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalccur: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSC_TRK_CALC 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSC_TRK_CALC_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_0_CS0 (DQS_OSC_BASE_VALUE_0_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 0 on chip 0. READ-ONLY DEV=0 }} 768 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_1_CS0 (DQS_OSC_BASE_VALUE_1_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 1 on chip 0. READ-ONLY DEV=1 }} 784 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_2_CS0 (DQS_OSC_BASE_VALUE_2_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 2 on chip 0. READ-ONLY DEV=2 }} 800 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_3_CS0 (DQS_OSC_BASE_VALUE_3_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 3 on chip 0. READ-ONLY DEV=3 }} 816 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_4_CS0 (DQS_OSC_BASE_VALUE_4_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 4 on chip 0. READ-ONLY DEV=4 }} 832 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_5_CS0 (DQS_OSC_BASE_VALUE_5_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 5 on chip 0. READ-ONLY DEV=5 }} 848 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_6_CS0 (DQS_OSC_BASE_VALUE_6_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 6 on chip 0. READ-ONLY DEV=6 }} 864 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_7_CS0 (DQS_OSC_BASE_VALUE_7_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 7 on chip 0. READ-ONLY DEV=7 }} 880 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_8_CS0 (DQS_OSC_BASE_VALUE_8_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 8 on chip 0. READ-ONLY DEV=8 }} 896 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_0_CS1 (DQS_OSC_BASE_VALUE_0_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 0 on chip 1. READ-ONLY DEV=0 }} 912 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_1_CS1 (DQS_OSC_BASE_VALUE_1_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 1 on chip 1. READ-ONLY DEV=1 }} 928 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_2_CS1 (DQS_OSC_BASE_VALUE_2_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 2 on chip 1. READ-ONLY DEV=2 }} 944 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_3_CS1 (DQS_OSC_BASE_VALUE_3_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 3 on chip 1. READ-ONLY DEV=3 }} 960 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_4_CS1 (DQS_OSC_BASE_VALUE_4_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 4 on chip 1. READ-ONLY DEV=4 }} 976 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_5_CS1 (DQS_OSC_BASE_VALUE_5_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 5 on chip 1. READ-ONLY DEV=5 }} 992 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_6_CS1 (DQS_OSC_BASE_VALUE_6_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 6 on chip 1. READ-ONLY DEV=6 }} 1008 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_7_CS1 (DQS_OSC_BASE_VALUE_7_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 7 on chip 1. READ-ONLY DEV=7 }} 1024 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_8_CS1 (DQS_OSC_BASE_VALUE_8_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 8 on chip 1. READ-ONLY DEV=8 }} 1040 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_STATUS (DQS_OSC_STATUS RD {} ZERO ZERO FULL CTL {{Holds the overflow and out of variance status associated with the resp. interrupts. Bit (0) set indicates overflow of DQS oscillator,bit (1) set indicates overflow of WCKO oscillator,bit (2) set indicates oov of DQS oscillator,bit (3) set indicates oov of WCKO oscillator. READ-ONLY }} 1056 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_0_CS0 (WCKO_OSC_BASE_VALUE_0_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 0 on chip 0. READ-ONLY DEV=0 }} 1064 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_1_CS0 (WCKO_OSC_BASE_VALUE_1_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 1 on chip 0. READ-ONLY DEV=1 }} 1088 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_2_CS0 (WCKO_OSC_BASE_VALUE_2_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 2 on chip 0. READ-ONLY DEV=2 }} 1104 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_3_CS0 (WCKO_OSC_BASE_VALUE_3_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 3 on chip 0. READ-ONLY DEV=3 }} 1120 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_4_CS0 (WCKO_OSC_BASE_VALUE_4_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 4 on chip 0. READ-ONLY DEV=4 }} 1136 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_5_CS0 (WCKO_OSC_BASE_VALUE_5_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 5 on chip 0. READ-ONLY DEV=5 }} 1152 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_6_CS0 (WCKO_OSC_BASE_VALUE_6_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 6 on chip 0. READ-ONLY DEV=6 }} 1168 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_7_CS0 (WCKO_OSC_BASE_VALUE_7_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 7 on chip 0. READ-ONLY DEV=7 }} 1184 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_8_CS0 (WCKO_OSC_BASE_VALUE_8_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 8 on chip 0. READ-ONLY DEV=8 }} 1200 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_0_CS1 (WCKO_OSC_BASE_VALUE_0_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 0 on chip 1. READ-ONLY DEV=0 }} 1216 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_1_CS1 (WCKO_OSC_BASE_VALUE_1_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 1 on chip 1. READ-ONLY DEV=1 }} 1232 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_2_CS1 (WCKO_OSC_BASE_VALUE_2_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 2 on chip 1. READ-ONLY DEV=2 }} 1248 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_3_CS1 (WCKO_OSC_BASE_VALUE_3_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 3 on chip 1. READ-ONLY DEV=3 }} 1264 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_4_CS1 (WCKO_OSC_BASE_VALUE_4_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 4 on chip 1. READ-ONLY DEV=4 }} 1280 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_5_CS1 (WCKO_OSC_BASE_VALUE_5_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 5 on chip 1. READ-ONLY DEV=5 }} 1296 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_6_CS1 (WCKO_OSC_BASE_VALUE_6_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 6 on chip 1. READ-ONLY DEV=6 }} 1312 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_7_CS1 (WCKO_OSC_BASE_VALUE_7_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 7 on chip 1. READ-ONLY DEV=7 }} 1328 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_8_CS1 (WCKO_OSC_BASE_VALUE_8_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 8 on chip 1. READ-ONLY DEV=8 }} 1344 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_IN_PROGRESS_STATUS (DQS_OSC_IN_PROGRESS_STATUS RD {} ZERO ZERO FULL CTL {{DQS Oscillator is in progress.Set '1' DQS OSC is in progress  READ-ONLY }} 1360 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CA_PARITY_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CA_PARITY_EN --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CA_PARITY_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CASLAT_LIN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CASLAT_LIN 0 --&gt; Returned 44: CADENCE_DEBUG_REG: CASLAT_LIN_F0:RW:0:8:=0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WRLAT_WITH_PL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Overriding HMC WRLAT with parity latency to 18.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WRLAT_WITH_PL 0 --&gt; Returned 18: CADENCE_DEBUG_REG: WRLAT_F0:RW:8:7:=0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDITIVE_LAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDITIVE_LAT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ADDITIVE_LAT_F0:RW:16:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_PARITY_LAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_PARITY_LAT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_PARITY_LAT_F0:RW:24:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSSR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSSR 0 --&gt; Returned 30: CADENCE_DEBUG_REG: TCSSR_F0:RW:0:8:=0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKSTAB 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKSTAB 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TCKSTAB_F0:RW:8:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD_PAR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD_PAR 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TMOD_PAR_F0:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CASLAT_LIN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CASLAT_LIN 1 --&gt; Returned 44: CADENCE_DEBUG_REG: CASLAT_LIN_F1:RW:8:8:=0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WRLAT_WITH_PL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Overriding HMC WRLAT with parity latency to 18.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WRLAT_WITH_PL 1 --&gt; Returned 18: CADENCE_DEBUG_REG: WRLAT_F1:RW:16:7:=0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDITIVE_LAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDITIVE_LAT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ADDITIVE_LAT_F1:RW:24:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_PARITY_LAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_PARITY_LAT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_PARITY_LAT_F1:RW:0:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSSR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSSR 1 --&gt; Returned 30: CADENCE_DEBUG_REG: TCSSR_F1:RW:8:8:=0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKSTAB 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKSTAB 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TCKSTAB_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD_PAR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD_PAR 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TMOD_PAR_F1:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CASLAT_LIN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CASLAT_LIN 2 --&gt; Returned 44: CADENCE_DEBUG_REG: CASLAT_LIN_F2:RW:16:8:=0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WRLAT_WITH_PL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Overriding HMC WRLAT with parity latency to 18.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WRLAT_WITH_PL 2 --&gt; Returned 18: CADENCE_DEBUG_REG: WRLAT_F2:RW:24:7:=0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDITIVE_LAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDITIVE_LAT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ADDITIVE_LAT_F2:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_PARITY_LAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_PARITY_LAT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_PARITY_LAT_F2:RW:8:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSSR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSSR 2 --&gt; Returned 30: CADENCE_DEBUG_REG: TCSSR_F2:RW:16:8:=0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKSTAB 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKSTAB 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TCKSTAB_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD_PAR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD_PAR 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TMOD_PAR_F2:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TBST_INT_INTERVAL" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_RMW: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_RMW: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TBST_INT_INTERVAL --&gt; Returned 4: CADENCE_DEBUG_REG: TBST_INT_INTERVAL:RW:0:3:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd tccd_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_s}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD --&gt; Returned 8: CADENCE_DEBUG_REG: TCCD:RW:8:5:=0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_F0:RW:16:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR 0 0 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCD_L_WR_F0:RW:24:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR2 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr2_time tccd_l_wr2_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_x4: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_x4: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR2 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_WR2_F0:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD 0 0 --&gt; Returned 11: CADENCE_DEBUG_REG: TRRD_F0:RW:8:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_L 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_l trrd_l_clk trrd_l_time tRRD_L tRRD_L_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_L 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_L_F0:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_dlr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_DLR_F0:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRC 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_135V_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trc trc_minTck tRC_time tRC_cycle}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRC 0 0 --&gt; Returned 65: CADENCE_DEBUG_REG: TRC_F0:RW:0:9:=0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MIN 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MIN 0 0 --&gt; Returned 45: CADENCE_DEBUG_REG: TRAS_MIN_F0:RW:16:9:=0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR 0 0 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_F0:RW:0:7:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_F0:RW:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_AP 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_AP 0 0 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_AP_F0:RW:16:9:=0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L_AP 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L_AP 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_AP_F0:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP 0 0 --&gt; Returned 20: CADENCE_DEBUG_REG: TRP_F0:RW:16:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW 0 0 --&gt; Returned 43: CADENCE_DEBUG_REG: TFAW_F0:RW:0:9:=0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw_dlr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TFAW_DLR_F0:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_F1:RW:0:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR 0 1 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCD_L_WR_F1:RW:8:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR2 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr2_time tccd_l_wr2_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_x4: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_x4: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR2 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_WR2_F1:RW:16:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 1 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD 0 1 --&gt; Returned 11: CADENCE_DEBUG_REG: TRRD_F1:RW:24:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_L 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_l trrd_l_clk trrd_l_time tRRD_L tRRD_L_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_L 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_L_F1:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_dlr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_DLR_F1:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRC 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_135V_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trc trc_minTck tRC_time tRC_cycle}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRC 0 1 --&gt; Returned 65: CADENCE_DEBUG_REG: TRC_F1:RW:16:9:=0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MIN 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MIN 0 1 --&gt; Returned 45: CADENCE_DEBUG_REG: TRAS_MIN_F1:RW:0:9:=0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR 0 1 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_F1:RW:16:7:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_F1:RW:24:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_AP 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_AP 0 1 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_AP_F1:RW:0:9:=0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L_AP 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L_AP 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_AP_F1:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP 0 1 --&gt; Returned 20: CADENCE_DEBUG_REG: TRP_F1:RW:0:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW 0 1 --&gt; Returned 43: CADENCE_DEBUG_REG: TFAW_F1:RW:8:9:=0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw_dlr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TFAW_DLR_F1:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_F2:RW:16:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR 0 2 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCD_L_WR_F2:RW:24:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR2 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr2_time tccd_l_wr2_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_x4: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_x4: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR2 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_WR2_F2:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 2 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD 0 2 --&gt; Returned 11: CADENCE_DEBUG_REG: TRRD_F2:RW:8:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_L 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_l trrd_l_clk trrd_l_time tRRD_L tRRD_L_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_L 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_L_F2:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_dlr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_DLR_F2:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRC 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_135V_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trc trc_minTck tRC_time tRC_cycle}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRC 0 2 --&gt; Returned 65: CADENCE_DEBUG_REG: TRC_F2:RW:0:9:=0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MIN 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MIN 0 2 --&gt; Returned 45: CADENCE_DEBUG_REG: TRAS_MIN_F2:RW:16:9:=0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR 0 2 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_F2:RW:0:7:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_F2:RW:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_AP 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_AP 0 2 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_AP_F2:RW:16:9:=0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L_AP 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L_AP 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_AP_F2:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP 0 2 --&gt; Returned 20: CADENCE_DEBUG_REG: TRP_F2:RW:16:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW 0 2 --&gt; Returned 43: CADENCE_DEBUG_REG: TFAW_F2:RW:0:9:=0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw_dlr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TFAW_DLR_F2:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_DLR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_DLR --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_DLR:RW:0:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trtp trtp_minTck trtp_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trtp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TRTP_F0:RW:8:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP_AP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP_AP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRTP_AP_F0:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_DELAY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd_time tmrd_clk tmpc_delay_time tmpc_delay_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_DELAY 0 --&gt; Returned 11: CADENCE_DEBUG_REG: TMPC_DELAY_F0:RW:24:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod tmod_clk tmod_time tMOD_time tMOD_cycle}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod_max}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_max: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd tmrd_minTck tmrw_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrd: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD 0 --&gt; Returned 15: CADENCE_DEBUG_REG: TMOD_F0:RW:8:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MAX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MAX 0 --&gt; Returned 55555: CADENCE_DEBUG_REG: TRAS_MAX_F0:RW:0:20:=0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKE 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKE_F0:RW:24:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKESR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckesr tckesr_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsrfc}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsrfc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKESR 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKESR_F0:RW:0:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCDMW 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccdmw: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCCDMW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCDMW 0 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCDMW_F0:RW:8:6:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSH 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tCSH}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCSH: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSH 0 --&gt; Returned 3: CADENCE_DEBUG_REG: TCSH_F0:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCACSH 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCACSH 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TCACSH_F0:RW:24:8:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trtp trtp_minTck trtp_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trtp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TRTP_F1:RW:0:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP_AP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP_AP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRTP_AP_F1:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_DELAY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd_time tmrd_clk tmpc_delay_time tmpc_delay_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_DELAY 1 --&gt; Returned 11: CADENCE_DEBUG_REG: TMPC_DELAY_F1:RW:16:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod tmod_clk tmod_time tMOD_time tMOD_cycle}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod_max}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_max: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd tmrd_minTck tmrw_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrd: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD 1 --&gt; Returned 15: CADENCE_DEBUG_REG: TMOD_F1:RW:0:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MAX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MAX 1 --&gt; Returned 55555: CADENCE_DEBUG_REG: TRAS_MAX_F1:RW:8:20:=0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKE 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKE_F1:RW:0:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKESR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckesr tckesr_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsrfc}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsrfc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKESR 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKESR_F1:RW:8:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCDMW 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccdmw: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCCDMW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCDMW 1 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCDMW_F1:RW:16:6:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSH 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tCSH}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCSH: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSH 1 --&gt; Returned 3: CADENCE_DEBUG_REG: TCSH_F1:RW:24:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCACSH 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCACSH 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TCACSH_F1:RW:0:8:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trtp trtp_minTck trtp_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trtp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TRTP_F2:RW:8:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP_AP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP_AP 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRTP_AP_F2:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_DELAY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd_time tmrd_clk tmpc_delay_time tmpc_delay_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_DELAY 2 --&gt; Returned 11: CADENCE_DEBUG_REG: TMPC_DELAY_F2:RW:24:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod tmod_clk tmod_time tMOD_time tMOD_cycle}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod_max}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_max: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd tmrd_minTck tmrw_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrd: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD 2 --&gt; Returned 15: CADENCE_DEBUG_REG: TMOD_F2:RW:8:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MAX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MAX 2 --&gt; Returned 55555: CADENCE_DEBUG_REG: TRAS_MAX_F2:RW:0:20:=0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKE 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKE_F2:RW:24:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKESR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckesr tckesr_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsrfc}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsrfc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKESR 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKESR_F2:RW:0:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCDMW 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccdmw: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCCDMW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCDMW 2 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCDMW_F2:RW:8:6:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSH 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tCSH}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCSH: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSH 2 --&gt; Returned 3: CADENCE_DEBUG_REG: TCSH_F2:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCACSH 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCACSH 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TCACSH_F2:RW:24:8:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPPD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tppd}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tppd: Parameter value {4.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {4.0 clk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPPD 0 --&gt; Returned 4: CADENCE_DEBUG_REG: TPPD_F0:RW_D:0:3:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPPD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tppd}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tppd: Parameter value {4.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {4.0 clk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPPD 1 --&gt; Returned 4: CADENCE_DEBUG_REG: TPPD_F1:RW_D:8:3:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPPD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tppd}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tppd: Parameter value {4.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {4.0 clk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPPD 2 --&gt; Returned 4: CADENCE_DEBUG_REG: TPPD_F2:RW_D:16:3:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMOD_OPT_THRESHOLD will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMRD_OPT_THRESHOLD will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WRITEINTERP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WRITEINTERP --&gt; Returned 0: CADENCE_DEBUG_REG: WRITEINTERP:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_MULTI_CYCLE_ENABLE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_MULTI_CYCLE_ENABLE 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_MULTI_CYCLE_ENABLE_F0:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_MULTI_CYCLE_ENABLE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_MULTI_CYCLE_ENABLE 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_MULTI_CYCLE_ENABLE_F1:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_MULTI_CYCLE_ENABLE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_MULTI_CYCLE_ENABLE 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_MULTI_CYCLE_ENABLE_F2:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_CS_LOW" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_CS_LOW --&gt; Returned 4: CADENCE_DEBUG_REG: TMPC_CS_LOW:RW:8:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_SETUP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_SETUP --&gt; Returned 3: CADENCE_DEBUG_REG: TMPC_SETUP:RW:16:4:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_HOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_HOLD --&gt; Returned 3: CADENCE_DEBUG_REG: TMPC_HOLD:RW:24:4:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_REQ --&gt; FAKED 3: CADENCE_DEBUG_REG: MPC_REQ:WR:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_CS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_CS --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_CS:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_OPCODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_OPCODE --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_OPCODE:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_PROMOTE_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_PROMOTE_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_PROMOTE_THRESHOLD:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MPC_ERROR_STATUS (MPC_ERROR_STATUS RD {} ZERO ZERO FULL CTL {{Indicates if a MPC request was attempted when the Controller was in Self-Refresh Long or Self-Refresh Short with Memory Clock Gating state. READ-ONLY }} 2656 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRCD 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRCD 0 0 --&gt; Returned 20: CADENCE_DEBUG_REG: TRCD_F0:RW:8:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWR 0 0 --&gt; Returned 21: CADENCE_DEBUG_REG: TWR_F0:RW:16:8:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRCD 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRCD 0 1 --&gt; Returned 20: CADENCE_DEBUG_REG: TRCD_F1:RW:24:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWR 0 1 --&gt; Returned 21: CADENCE_DEBUG_REG: TWR_F1:RW:0:8:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRCD 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRCD 0 2 --&gt; Returned 20: CADENCE_DEBUG_REG: TRCD_F2:RW:8:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWR 0 2 --&gt; Returned 21: CADENCE_DEBUG_REG: TWR_F2:RW:16:8:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrr tmrr_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrr: Parameter value {8.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {8.0 clk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrr_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRR --&gt; Returned 8: CADENCE_DEBUG_REG: TMRR:RW:24:8:=0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPRR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmprr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPRR --&gt; Returned 0: CADENCE_DEBUG_REG: TMPRR:RW:0:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of AP_Sim: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AP --&gt; Returned 0: CADENCE_DEBUG_REG: AP:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CONCURRENTAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CONCURRENTAP --&gt; Returned 1: CADENCE_DEBUG_REG: CONCURRENTAP:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_LOCKOUT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_LOCKOUT --&gt; Returned 1: CADENCE_DEBUG_REG: TRAS_LOCKOUT:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDAL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdal: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDAL 0 --&gt; Returned 41: CADENCE_DEBUG_REG: TDAL_F0:RW:0:8:=0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDAL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdal: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDAL 1 --&gt; Returned 41: CADENCE_DEBUG_REG: TDAL_F1:RW:8:8:=0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDAL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdal: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDAL 2 --&gt; Returned 41: CADENCE_DEBUG_REG: TDAL_F2:RW:16:8:=0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BSTLEN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BSTLEN --&gt; Returned 4: CADENCE_DEBUG_REG: BSTLEN:RW_D:24:6:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 0 0 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F0_0:RW:0:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 0 1 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F1_0:RW:8:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 0 2 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F2_0:RW:16:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 1 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 1 0 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F0_1:RW:24:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 1 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 1 1 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F1_1:RW:0:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 1 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 1 2 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F2_1:RW:8:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MEM_3DS_SUPPORT_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MEM_3DS_SUPPORT_EN --&gt; Returned 0: CADENCE_DEBUG_REG: MEM_3DS_SUPPORT_EN:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LOGICAL_CS_MAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of componentDdrSOMA: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LOGICAL_CS_MAP --&gt; Returned 0: CADENCE_DEBUG_REG: LOGICAL_CS_MAP:RW:24:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PRECHARGE_DLR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PRECHARGE_DLR --&gt; Returned 8: CADENCE_DEBUG_REG: PRECHARGE_DLR:RW:0:8:=0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__REG_DIMM_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__REG_DIMM_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: REG_DIMM_ENABLE:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDRESS_MIRRORING" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter is_addr_mirror_en does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDRESS_MIRRORING --&gt; Returned 0: CADENCE_DEBUG_REG: ADDRESS_MIRRORING:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDRESS_INVERSION" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDRESS_INVERSION --&gt; Returned 0: CADENCE_DEBUG_REG: ADDRESS_INVERSION:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PDA_INVERT_DEV_CS0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PDA_INVERT_DEV_CS0 --&gt; Returned 0: CADENCE_DEBUG_REG: PDA_INVERT_DEV_CS0:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PDA_INVERT_DEV_CS1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PDA_INVERT_DEV_CS1 --&gt; Returned 0: CADENCE_DEBUG_REG: PDA_INVERT_DEV_CS1:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PDA_INVERT_ECC_DEV_CS0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PDA_INVERT_ECC_DEV_CS0 --&gt; Returned 0: CADENCE_DEBUG_REG: PDA_INVERT_ECC_DEV_CS0:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PDA_INVERT_ECC_DEV_CS1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PDA_INVERT_ECC_DEV_CS1 --&gt; Returned 0: CADENCE_DEBUG_REG: PDA_INVERT_ECC_DEV_CS1:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__OPTIMAL_RMODW_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Burst_RMW_Optimize: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_RMW: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_RMW: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__OPTIMAL_RMODW_EN --&gt; Returned 1: CADENCE_DEBUG_REG: OPTIMAL_RMODW_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__OPTIMAL_RMODW_WRITE_REDUC_EN will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NO_MEMORY_DM" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of data_mask_en: Parameter value true</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NO_MEMORY_DM --&gt; Returned 0: CADENCE_DEBUG_REG: NO_MEMORY_DM:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CW_REQ --&gt; FAKED 0: CADENCE_DEBUG_REG: CW_REQ:WR:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CWW_SW_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CWW_SW_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: CWW_SW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CWW_SW_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CWW_SW_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: CWW_SW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CWW_SW_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CWW_SW_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: CWW_SW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RDIMM_CWW_ERROR_STATUS (RDIMM_CWW_ERROR_STATUS RD {} ZERO ZERO FULL CTL {{Indicates if a RDIMM CWW request was attempted when the Controller was in Self-Refresh Long or Self-Refresh Short with Memory Clock Gating state. READ-ONLY }} 2992 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TMRD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrw tmrw_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrw: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrw tmrw_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrw: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TMRD --&gt; Returned 11: CADENCE_DEBUG_REG: RDIMM_TMRD:RW:0:16:=0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F0_0:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F1_0:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F2_0:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F0_1:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F1_1:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F2_1:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_DFS_CW_MAP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_DFS_CW_MAP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_DFS_CW_MAP_F0:RW:0:27:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_DFS_CW_MAP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_DFS_CW_MAP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_DFS_CW_MAP_F1:RW:0:27:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_DFS_CW_MAP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_DFS_CW_MAP 2 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_DFS_CW_MAP_F2:RW:0:27:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CW_MAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CW_MAP --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CW_MAP:RW:0:27:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CW_HOLD_CKE_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CW_HOLD_CKE_EN --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CW_HOLD_CKE_EN:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TSTAB 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {6 us}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TSTAB 0 --&gt; Returned 6404: CADENCE_DEBUG_REG: RDIMM_TSTAB_F0:RW:8:24:=0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TSTAB 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {6 us}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TSTAB 1 --&gt; Returned 6404: CADENCE_DEBUG_REG: RDIMM_TSTAB_F1:RW:0:24:=0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TSTAB 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {6 us}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TSTAB 2 --&gt; Returned 6404: CADENCE_DEBUG_REG: RDIMM_TSTAB_F2:RW:0:24:=0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_MAP_DIMM 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_MAP_DIMM 0 --&gt; Returned 3: CADENCE_DEBUG_REG: CS_MAP_DIMM_0:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_MAP_DIMM 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_MAP_DIMM 1 --&gt; Returned 0: CADENCE_DEBUG_REG: CS_MAP_DIMM_1:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DDR4_DIMM_3DS_PIN_MUXING_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DDR4_DIMM_3DS_PIN_MUXING_EN --&gt; Returned 0: CADENCE_DEBUG_REG: DDR4_DIMM_3DS_PIN_MUXING_EN:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DDR4_DIMM_CID0_MAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DDR4_DIMM_CID0_MAP --&gt; Returned 0: CADENCE_DEBUG_REG: DDR4_DIMM_CID0_MAP:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANK0_MAP_DIMM 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANK0_MAP_DIMM 0 --&gt; Returned 1: CADENCE_DEBUG_REG: RANK0_MAP_DIMM_0:RW:24:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANK0_MAP_DIMM 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANK0_MAP_DIMM 1 --&gt; Returned 0: CADENCE_DEBUG_REG: RANK0_MAP_DIMM_1:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TMRD_L" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TMRD_L --&gt; Returned 16: CADENCE_DEBUG_REG: RDIMM_TMRD_L:RW:8:5:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TMRD_L2" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TMRD_L2 --&gt; Returned 32: CADENCE_DEBUG_REG: RDIMM_TMRD_L2:RW:16:6:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TMRC" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TMRC --&gt; Returned 16: CADENCE_DEBUG_REG: RDIMM_TMRC:RW:24:5:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LRDIMM_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Load_Reduced_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LRDIMM_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: LRDIMM_ENABLE:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRROD1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRROD1 --&gt; Returned 0: CADENCE_DEBUG_REG: TMRROD1:RW:8:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRROD2" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRROD2 --&gt; Returned 0: CADENCE_DEBUG_REG: TMRROD2:RW:16:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CW_VAL" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CW_VAL --&gt; Returned 0: CADENCE_DEBUG_REG: CW_VAL:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CW_NUM" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CW_NUM --&gt; Returned 0: CADENCE_DEBUG_REG: CW_NUM:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CW_CS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CW_CS --&gt; Returned 1: CADENCE_DEBUG_REG: CW_CS:RW:16:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CA_PARITY_ERROR (CA_PARITY_ERROR RD {} ZERO ZERO FULL CTL {{Contains one hot indication of registered DIMM parity errors. Value of 1 indicates an error on that DIMM. READ-ONLY }} 4384 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREFRESH --&gt; FAKED 1: CADENCE_DEBUG_REG: AREFRESH:WR:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AREF_STATUS (AREF_STATUS RD {} ZERO ZERO FULL CTL {{Indicates a SR error associated with the AREF interrupt. Value of 1 indicates a violation. READ-ONLY }} 4400 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AREF_SW_ACK (AREF_SW_ACK RD {} ZERO ZERO FULL CTL {{Indicates a aref request is done corresponding to SW aref request. Value of 1 indicates sw aref req done . READ-ONLY }} 4408 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TREF_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TREF_ENABLE --&gt; Returned 1: CADENCE_DEBUG_REG: TREF_ENABLE:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_OPT_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_OPT_THRESHOLD --&gt; Returned 3: CADENCE_DEBUG_REG: TRFC_OPT_THRESHOLD:RW:8:3:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_COMPARISON_FOR_REFRESH_DEPTH" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_COMPARISON_FOR_REFRESH_DEPTH --&gt; Returned 16: CADENCE_DEBUG_REG: CS_COMPARISON_FOR_REFRESH_DEPTH:RW:16:6:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC 0 --&gt; Returned 193: CADENCE_DEBUG_REG: TRFC_F0:RW:0:10:=0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TREF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TREF 0 --&gt; Returned 4162: CADENCE_DEBUG_REG: TREF_F0:RW:0:20:=0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_DLR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfc_dlr1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_DLR 0 --&gt; Returned 96: CADENCE_DEBUG_REG: TRFC_DLR_F0:RW:0:10:=0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC 1 --&gt; Returned 193: CADENCE_DEBUG_REG: TRFC_F1:RW:16:10:=0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TREF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TREF 1 --&gt; Returned 4162: CADENCE_DEBUG_REG: TREF_F1:RW:0:20:=0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_DLR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfc_dlr1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_DLR 1 --&gt; Returned 96: CADENCE_DEBUG_REG: TRFC_DLR_F1:RW:0:10:=0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC 2 --&gt; Returned 193: CADENCE_DEBUG_REG: TRFC_F2:RW:16:10:=0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TREF 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TREF 2 --&gt; Returned 4162: CADENCE_DEBUG_REG: TREF_F2:RW:0:20:=0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_DLR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfc_dlr1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_DLR 2 --&gt; Returned 96: CADENCE_DEBUG_REG: TRFC_DLR_F2:RW:0:10:=0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TREF_INTERVAL" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TREF_INTERVAL --&gt; Returned 5: CADENCE_DEBUG_REG: TREF_INTERVAL:RW:0:20:=0x000005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_F0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_DLR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_DLR 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_DLR_F0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_F1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_DLR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_DLR 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_DLR_F1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_F2:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_DLR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_DLR 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_DLR_F2:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F0_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F0_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F0_0:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F0_0:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F1_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F1_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F1_0:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F1_0:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F2_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F2_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F2_0:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F2_0:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F0_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F0_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F0_1:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F0_1:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F1_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F1_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F1_1:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F1_1:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F2_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F2_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F2_1:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F2_1:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RFM_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RFM_EN --&gt; Returned 0: CADENCE_DEBUG_REG: RFM_EN:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__REF_RFM_PRIO" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__REF_RFM_PRIO --&gt; Returned 1: CADENCE_DEBUG_REG: REF_RFM_PRIO:RW:8:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RAA_CNT_DECR_PER_REF" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RAA_CNT_DECR_PER_REF --&gt; Returned 0: CADENCE_DEBUG_REG: RAA_CNT_DECR_PER_REF:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RAAIMT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RAAIMT --&gt; Returned 0: CADENCE_DEBUG_REG: RAAIMT:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RAAMMT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RAAMMT --&gt; Returned 0: CADENCE_DEBUG_REG: RAAMMT:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RFM_SB_CONT_EN_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RFM_SB_CONT_EN_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: RFM_SB_CONT_EN_THRESHOLD:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RFM_NORM_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RFM_NORM_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: RFM_NORM_THRESHOLD:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RFM_HIGH_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RFM_HIGH_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: RFM_HIGH_THRESHOLD:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 0 0 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F0_0:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F0_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 0 0 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F0_0:RW:0:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 0 0 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F0_0:RW:8:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 0 0 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F0_0:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F0_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 0 1 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F1_0:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F1_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 1 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 0 1 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F1_0:RW:16:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 0 1 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F1_0:RW:24:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 0 1 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F1_0:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F1_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 0 2 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F2_0:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F2_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 2 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 0 2 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F2_0:RW:0:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 0 2 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F2_0:RW:8:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 0 2 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F2_0:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F2_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 1 0 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F0_1:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F0_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 1 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 1 0 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F0_1:RW:16:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 1 0 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F0_1:RW:24:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 1 0 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F0_1:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F0_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 1 1 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F1_1:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F1_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 1 1 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 1 1 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F1_1:RW:0:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 1 1 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F1_1:RW:8:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 1 1 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F1_1:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F1_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 1 2 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F2_1:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F2_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 1 2 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 1 2 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F2_1:RW:16:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 1 2 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F2_1:RW:24:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 1 2 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F2_1:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F2_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PBR_MODE_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Per_Bank_Refresh: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PBR_MODE_EN --&gt; Returned 1: CADENCE_DEBUG_REG: PBR_MODE_EN:RW:0:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__SELECT_BANK_IN_Q" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__SELECT_BANK_IN_Q --&gt; Returned 0: CADENCE_DEBUG_REG: SELECT_BANK_IN_Q:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PBR_NUMERIC_ORDER" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PBR_NUMERIC_ORDER --&gt; Returned 0: CADENCE_DEBUG_REG: PBR_NUMERIC_ORDER:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PBR_CONT_REQ_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PBR_CONT_REQ_EN --&gt; Returned 1: CADENCE_DEBUG_REG: PBR_CONT_REQ_EN:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_PBR_CONT_EN_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_PBR_CONT_EN_THRESHOLD --&gt; Returned 18: CADENCE_DEBUG_REG: AREF_PBR_CONT_EN_THRESHOLD:RW:0:5:=0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPDEX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txp txp_minTck txp_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of txp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPDEX 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TPDEX_F0:RW:8:16:=0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPDEX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txp txp_minTck txp_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of txp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPDEX 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TPDEX_F1:RW:0:16:=0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPDEX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txp txp_minTck txp_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of txp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPDEX 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TPDEX_F2:RW:16:16:=0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRRI 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrri: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRRI 0 --&gt; Returned 23: CADENCE_DEBUG_REG: TMRRI_F0:RW:0:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRRI 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrri: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRRI 1 --&gt; Returned 23: CADENCE_DEBUG_REG: TMRRI_F1:RW:8:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRRI 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrri: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRRI 2 --&gt; Returned 23: CADENCE_DEBUG_REG: TMRRI_F2:RW:16:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCS 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCS 0 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCS_F0:RW:24:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCS 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCS 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCS_F0:RW:0:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRWCKEL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrwckel tmrwckel_minTck tmrwckel_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrwckel: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRWCKEL 0 --&gt; Returned 15: CADENCE_DEBUG_REG: TMRWCKEL_F0:RW:8:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCKE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcke tzqcke_minTck tzqcke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCKE 0 --&gt; Returned 3: CADENCE_DEBUG_REG: TZQCKE_F0:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCS 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCS 1 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCS_F1:RW:24:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCS 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCS 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCS_F1:RW:0:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRWCKEL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrwckel tmrwckel_minTck tmrwckel_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrwckel: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRWCKEL 1 --&gt; Returned 15: CADENCE_DEBUG_REG: TMRWCKEL_F1:RW:8:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCKE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcke tzqcke_minTck tzqcke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCKE 1 --&gt; Returned 3: CADENCE_DEBUG_REG: TZQCKE_F1:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCS 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCS 2 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCS_F2:RW:24:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCS 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCS 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCS_F2:RW:0:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRWCKEL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrwckel tmrwckel_minTck tmrwckel_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrwckel: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRWCKEL 2 --&gt; Returned 15: CADENCE_DEBUG_REG: TMRWCKEL_F2:RW:8:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCKE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcke tzqcke_minTck tzqcke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCKE 2 --&gt; Returned 3: CADENCE_DEBUG_REG: TZQCKE_F2:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcscke tcscke_minTck tcscke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcscke: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKE 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKE_F0:RW:24:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_DEFAULT_VAL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_DEFAULT_VAL 0 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_DEFAULT_VAL_F0:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcscke tcscke_minTck tcscke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcscke: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKE 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKE_F1:RW:8:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_DEFAULT_VAL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_DEFAULT_VAL 1 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_DEFAULT_VAL_F1:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcscke tcscke_minTck tcscke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcscke: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKE 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKE_F2:RW:24:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_DEFAULT_VAL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_DEFAULT_VAL 2 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_DEFAULT_VAL_F2:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsrd}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsrd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsdll}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsdll: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lowPower: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSR 0 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSR_F0:RW:8:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSNR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsnr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsnr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txs}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSNR 0 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSNR_F0:RW:0:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCPDED 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCPDED 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TCPDED_F0:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsrd}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsrd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsdll}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsdll: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lowPower: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSR 1 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSR_F1:RW:0:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSNR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsnr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsnr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txs}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSNR 1 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSNR_F1:RW:16:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCPDED 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCPDED 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TCPDED_F1:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsrd}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsrd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsdll}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsdll: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lowPower: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSR 2 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSR_F2:RW:8:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSNR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsnr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsnr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txs}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSNR 2 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSNR_F2:RW:0:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCPDED 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCPDED 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TCPDED_F2:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__SRX_NOP_CMDS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__SRX_NOP_CMDS --&gt; Returned 5: CADENCE_DEBUG_REG: SRX_NOP_CMDS:RW:24:4:=0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TSR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsr tsr_minTck tSR tSR_minTck tsr_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tsr: Parameter value {15.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TSR 0 --&gt; Returned 17: CADENCE_DEBUG_REG: TSR_F0:RW:0:8:=0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TESCKE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tescke tescke_minTck tescke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tescke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TESCKE 0 --&gt; Returned 3: CADENCE_DEBUG_REG: TESCKE_F0:RW:8:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKEH 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcsckeh tcsckeh_minTck tcsckeh_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcsckeh: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKEH 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKEH_F0:RW:16:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCMD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCMD 0 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCMD_F0:RW:24:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCMD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCMD 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCMD_F0:RW:0:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKCKEL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckel tckckel_minTck tckckel_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckel: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKCKEL 0 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKCKEL_F0:RW:8:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELPD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELPD 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKELPD_F0:RW:16:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TSR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsr tsr_minTck tSR tSR_minTck tsr_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tsr: Parameter value {15.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TSR 1 --&gt; Returned 17: CADENCE_DEBUG_REG: TSR_F1:RW:24:8:=0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TESCKE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tescke tescke_minTck tescke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tescke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TESCKE 1 --&gt; Returned 3: CADENCE_DEBUG_REG: TESCKE_F1:RW:0:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKEH 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcsckeh tcsckeh_minTck tcsckeh_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcsckeh: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKEH 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKEH_F1:RW:8:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCMD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCMD 1 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCMD_F1:RW:16:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCMD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCMD 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCMD_F1:RW:24:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKCKEL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckel tckckel_minTck tckckel_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckel: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKCKEL 1 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKCKEL_F1:RW:0:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELPD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELPD 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKELPD_F1:RW:8:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TSR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsr tsr_minTck tSR tSR_minTck tsr_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tsr: Parameter value {15.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TSR 2 --&gt; Returned 17: CADENCE_DEBUG_REG: TSR_F2:RW:16:8:=0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TESCKE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tescke tescke_minTck tescke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tescke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TESCKE 2 --&gt; Returned 3: CADENCE_DEBUG_REG: TESCKE_F2:RW:24:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKEH 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcsckeh tcsckeh_minTck tcsckeh_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcsckeh: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKEH 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKEH_F2:RW:0:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCMD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCMD 2 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCMD_F2:RW:8:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCMD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCMD 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCMD_F2:RW:16:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKCKEL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckel tckckel_minTck tckckel_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckel: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKCKEL 2 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKCKEL_F2:RW:24:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELPD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELPD 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKELPD_F2:RW:0:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCMDCKE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcmdcke tcmdcke_minTck tcmdcke_clk tactpden tprpden trefpden tCMDPD tCMDPD_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcmdcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tactpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tprpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCMDCKE 0 --&gt; Returned 3: CADENCE_DEBUG_REG: TCMDCKE_F0:RW:8:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCMDCKE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcmdcke tcmdcke_minTck tcmdcke_clk tactpden tprpden trefpden tCMDPD tCMDPD_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcmdcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tactpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tprpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCMDCKE 1 --&gt; Returned 3: CADENCE_DEBUG_REG: TCMDCKE_F1:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCMDCKE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcmdcke tcmdcke_minTck tcmdcke_clk tactpden tprpden trefpden tCMDPD tCMDPD_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcmdcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tactpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tprpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCMDCKE 2 --&gt; Returned 3: CADENCE_DEBUG_REG: TCMDCKE_F2:RW:24:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PWRUP_SREFRESH_EXIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PWRUP_SREFRESH_EXIT --&gt; Returned 0: CADENCE_DEBUG_REG: PWRUP_SREFRESH_EXIT:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__SREFRESH_EXIT_NO_REFRESH" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__SREFRESH_EXIT_NO_REFRESH --&gt; Returned 0: CADENCE_DEBUG_REG: SREFRESH_EXIT_NO_REFRESH:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ENABLE_QUICK_SREFRESH" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ENABLE_QUICK_SREFRESH --&gt; Returned 1: CADENCE_DEBUG_REG: ENABLE_QUICK_SREFRESH:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKE_DELAY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKE_DELAY --&gt; Returned 0: CADENCE_DEBUG_REG: CKE_DELAY:RW:24:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DFS_CMD will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DFS_STATUS will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_FREQ_CHANGE_STATE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_FREQ_CHANGE_STATE --&gt; Returned 1: CADENCE_DEBUG_REG: DFI_FREQ_CHANGE_STATE:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WAIT_FOR_SW_AFTER_DFS will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFS_ZQ_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFS_ZQ_EN --&gt; Returned 1: CADENCE_DEBUG_REG: DFS_ZQ_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFS_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFS_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: DFS_PROMOTE_THRESHOLD_F0:RW:8:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 0 --&gt; Returned 0: CADENCE_DEBUG_REG: POST_DFS_WAIT_TIME_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFS_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFS_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: DFS_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 1 --&gt; Returned 0: CADENCE_DEBUG_REG: POST_DFS_WAIT_TIME_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFS_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFS_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: DFS_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 2 --&gt; Returned 0: CADENCE_DEBUG_REG: POST_DFS_WAIT_TIME_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ZQ_STATUS_LOG (ZQ_STATUS_LOG RD {} ZERO ZERO FULL CTL {{Indicates what kind of ZQ command was terminated without execution that caused the ZQ status interrupt to assert. Bit (0) correlates to a ZQ cal init, reset, short or long command. Bit (1) correlates to a ZQ cal start command. Bit (2) correlates to a ZQ cal latch command. Value of 1 indicates that that type of command was received, but terminated without execution. READ-ONLY }} 6480 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRP_OPT_THRESHOLD will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRAS_OPT_THRESHOLD will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__FM_NORM_CQ_DISCONNECT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__FM_HIGH_CQ_DISCONNECT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__FM_DISCONNECT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 0 --&gt; Returned 3: CADENCE_DEBUG_REG: UPD_CTRLUPD_NORM_THRESHOLD_F0:RW:0:16:=0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 0 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_HIGH_THRESHOLD_F0:RW:16:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_TIMEOUT 0 --&gt; Returned 5: CADENCE_DEBUG_REG: UPD_CTRLUPD_TIMEOUT_F0:RW:0:16:=0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 0 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 1 --&gt; Returned 3: CADENCE_DEBUG_REG: UPD_CTRLUPD_NORM_THRESHOLD_F1:RW:16:16:=0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 1 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_HIGH_THRESHOLD_F1:RW:0:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_TIMEOUT 1 --&gt; Returned 5: CADENCE_DEBUG_REG: UPD_CTRLUPD_TIMEOUT_F1:RW:16:16:=0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 1 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 2 --&gt; Returned 3: CADENCE_DEBUG_REG: UPD_CTRLUPD_NORM_THRESHOLD_F2:RW:0:16:=0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 2 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_HIGH_THRESHOLD_F2:RW:16:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_TIMEOUT 2 --&gt; Returned 5: CADENCE_DEBUG_REG: UPD_CTRLUPD_TIMEOUT_F2:RW:0:16:=0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 2 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_RD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_RD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_RD_F0:RW:16:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_WR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_WR 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_WR_F0:RW:24:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_FS 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_FS 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_FS_F0:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_TOGGLE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_TOGGLE 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_TOGGLE_F0:RW:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_FAST_TOGGLE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_FAST_TOGGLE 0 --&gt; Returned 4: CADENCE_DEBUG_REG: TDFI_WCK_FAST_TOGGLE_F0:RW:16:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_DIS 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_DIS 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_DIS_F0:RW:24:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_RD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_RD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_RD_F1:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_WR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_WR 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_WR_F1:RW:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_FS 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_FS 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_FS_F1:RW:16:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_TOGGLE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_TOGGLE 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_TOGGLE_F1:RW:24:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_FAST_TOGGLE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_FAST_TOGGLE 1 --&gt; Returned 4: CADENCE_DEBUG_REG: TDFI_WCK_FAST_TOGGLE_F1:RW:0:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_DIS 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_DIS 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_DIS_F1:RW:8:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_RD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_RD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_RD_F2:RW:16:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_WR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_WR 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_WR_F2:RW:24:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_FS 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_FS 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_FS_F2:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_TOGGLE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_TOGGLE 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_TOGGLE_F2:RW:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_FAST_TOGGLE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_FAST_TOGGLE 2 --&gt; Returned 4: CADENCE_DEBUG_REG: TDFI_WCK_FAST_TOGGLE_F2:RW:16:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_DIS 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_DIS 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_DIS_F2:RW:24:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WCK_ON will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WCK_OFF will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WCK_GROUP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WCK_GROUP --&gt; Returned 2: CADENCE_DEBUG_REG: WCK_GROUP:RW:16:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WCK_WR_FREERUN will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WCK_MODE will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCK_SYNCED (WCK_SYNCED RD {} ZERO ZERO FULL CTL {{Indicates the WCK is synced for each chip select. Bit (0) correlates to cs0, bit (1) correlates to cs1, etc. A value of 1 indicates that a CAS WCK2CK Sync command has been issued to that chip select and the WCK2CK is still synced. READ-ONLY }} 6960 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__CAS_TO_CAS_WS_OFF_VAL will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX 0 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_F0:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 0 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE0_F0:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 0 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE1_F0:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 0 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE2_F0:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 0 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE3_F0:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_RESP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_RESP 0 --&gt; Returned 29134: CADENCE_DEBUG_REG: TDFI_PHYMSTR_RESP_F0:RW:0:20:=0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX 1 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_F1:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 1 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE0_F1:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 1 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE1_F1:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 1 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE2_F1:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 1 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE3_F1:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_RESP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_RESP 1 --&gt; Returned 29134: CADENCE_DEBUG_REG: TDFI_PHYMSTR_RESP_F1:RW:0:20:=0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX 2 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_F2:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 2 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE0_F2:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 2 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE1_F2:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 2 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE2_F2:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 2 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE3_F2:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_RESP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_RESP 2 --&gt; Returned 29134: CADENCE_DEBUG_REG: TDFI_PHYMSTR_RESP_F2:RW:0:20:=0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_NO_AREF" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_NO_AREF --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_NO_AREF:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PHYMSTR_ERROR_STATUS (PHYMSTR_ERROR_STATUS RD {} ZERO ZERO FULL CTL {{Identifies the source of any DFI PHY Master Interface errors. Value of 1 indicates a timing violation of the associated timing parameter. Bit (0) set indicates a TDFI_PHYMSTR_MAX or TDFI_PHYMSTR_TYPEn_MAX parmaeter violation and bit (1) set indicates a TDFI_PHYMSTR_RESP parameter violation. READ-ONLY }} 7744 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_DFI_VERSION_4P0V1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_DFI_VERSION_4P0V1 --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_DFI_VERSION_4P0V1:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_TRAIN_AFTER_INIT_COMPLETE:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_NORM_THRESHOLD_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_HIGH_THRESHOLD_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_TIMEOUT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_TIMEOUT_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_NORM_THRESHOLD_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_HIGH_THRESHOLD_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_TIMEOUT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_TIMEOUT_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_NORM_THRESHOLD_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_HIGH_THRESHOLD_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_TIMEOUT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_TIMEOUT_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_COMMAND_MRR_REGNUM" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_COMMAND_MRR_REGNUM --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_COMMAND_MRR_REGNUM:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_CONTROL" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_CONTROL --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_CONTROL:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_COMMAND --&gt; FAKED 0: CADENCE_DEBUG_REG: PPR_COMMAND:WR:8:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_COMMAND_MRW_REGNUM" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_COMMAND_MRW_REGNUM --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_COMMAND_MRW_REGNUM:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_COMMAND_MRW_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_COMMAND_MRW_DATA --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_COMMAND_MRW_DATA:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_ROW_ADDRESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_ROW_ADDRESS --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_ROW_ADDRESS:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_BANK_ADDRESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_BANK_ADDRESS --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_BANK_ADDRESS:RW:24:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_CS_ADDRESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_CS_ADDRESS --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_CS_ADDRESS:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_CID_ADDRESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_CID_ADDRESS --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_CID_ADDRESS:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_DATA --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_DATA:RW:0:256:=0x0000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_ECC" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_ECC --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_ECC:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PPR_STATUS (PPR_STATUS RD {} PPR_STATUS_INIT ZERO FULL CTL {{Reports the status of the PPR operation. Bit (0) set indicates that PPR operations are now allowed and bit (1) set indicates if the last PPR command is complete. READ-ONLY }} 8480 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__POST_INIT_SW_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__POST_INIT_SW_MODE --&gt; Returned 0: CADENCE_DEBUG_REG: POST_INIT_SW_MODE:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_BOOT_STATE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_BOOT_STATE --&gt; Returned 0: CADENCE_DEBUG_REG: DFI_BOOT_STATE:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__X8_DEVICE_EN will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DATA2CMD_RATIO 0 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_ARCH_MODE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_ARCH_MODE 0 --&gt; Returned 0: CADENCE_DEBUG_REG: BANK_ARCH_MODE_F0:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DVFSC_MODE 0 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_LINK_ECC_EN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RD_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_LINK_ECC_EN 0 --&gt; Returned 0: CADENCE_DEBUG_REG: RD_LINK_ECC_EN_F0:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_LINK_ECC_EN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WR_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_LINK_ECC_EN 0 --&gt; Returned 0: CADENCE_DEBUG_REG: WR_LINK_ECC_EN_F0:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DATA2CMD_RATIO 1 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_ARCH_MODE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_ARCH_MODE 1 --&gt; Returned 0: CADENCE_DEBUG_REG: BANK_ARCH_MODE_F1:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DVFSC_MODE 1 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_LINK_ECC_EN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RD_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_LINK_ECC_EN 1 --&gt; Returned 0: CADENCE_DEBUG_REG: RD_LINK_ECC_EN_F1:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_LINK_ECC_EN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WR_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_LINK_ECC_EN 1 --&gt; Returned 0: CADENCE_DEBUG_REG: WR_LINK_ECC_EN_F1:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DATA2CMD_RATIO 2 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_ARCH_MODE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_ARCH_MODE 2 --&gt; Returned 0: CADENCE_DEBUG_REG: BANK_ARCH_MODE_F2:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DVFSC_MODE 2 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_LINK_ECC_EN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RD_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_LINK_ECC_EN 2 --&gt; Returned 0: CADENCE_DEBUG_REG: RD_LINK_ECC_EN_F2:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_LINK_ECC_EN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WR_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_LINK_ECC_EN 2 --&gt; Returned 0: CADENCE_DEBUG_REG: WR_LINK_ECC_EN_F2:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 0 --&gt; Returned 0: CADENCE_DEBUG_REG: DVFSQ_MODE_F0:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 1 --&gt; Returned 0: CADENCE_DEBUG_REG: DVFSQ_MODE_F1:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 2 --&gt; Returned 0: CADENCE_DEBUG_REG: DVFSQ_MODE_F2:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_NORM_THRESHOLD_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_HIGH_THRESHOLD_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_TIMEOUT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_TIMEOUT_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_NORM_THRESHOLD_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_HIGH_THRESHOLD_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_TIMEOUT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_TIMEOUT_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_NORM_THRESHOLD_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_HIGH_THRESHOLD_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_TIMEOUT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_TIMEOUT_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WR_LINK_ECC_SBE_MR_VAL_0 (WR_LINK_ECC_SBE_MR_VAL_0 RD {} {ZERO 0} ZERO FULL CTL {{MR43 single-bit error data (bits 6:0) for all devices accessed by periodic Write Link ECC MRR commands. READ-ONLY. }} 8960 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WR_LINK_ECC_DBE_MR_VAL_0 (WR_LINK_ECC_DBE_MR_VAL_0 RD {} {ZERO 0} ZERO FULL CTL {{MR43 double-bit error data (bit 7) for all devices accessed by periodic Write Link ECC MRR commands. READ-ONLY. }} 8992 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WR_LINK_ECC_SBE_MR_VAL_1 (WR_LINK_ECC_SBE_MR_VAL_1 RD {} {ZERO 1} ZERO FULL CTL {{MR43 single-bit error data (bits 6:0) for all devices accessed by periodic Write Link ECC MRR commands. READ-ONLY. }} 9024 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WR_LINK_ECC_DBE_MR_VAL_1 (WR_LINK_ECC_DBE_MR_VAL_1 RD {} {ZERO 1} ZERO FULL CTL {{MR43 double-bit error data (bit 7) for all devices accessed by periodic Write Link ECC MRR commands. READ-ONLY. }} 9056 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_DOUBLE_BIT_ERROR (RD_LINK_ECC_DOUBLE_BIT_ERROR RD {} ZERO ZERO FULL CTL {{A double bit error was detected on READ LINK ECC for a Port Read, Bit 0 is LSB of memory data bus (DQ) }} 9064 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMW_RD_LINK_ECC_DOUBLE_BIT_ERROR (RMW_RD_LINK_ECC_DOUBLE_BIT_ERROR RD {} ZERO ZERO FULL CTL {{A double bit error was detected on READ LINK ECC for a RMW-Read, Bit 0 is LSB of memory data bus (DQ) }} 9072 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_COUNT_0 (RD_LINK_ECC_SBE_COUNT_0 RD {} ZERO ZERO FULL CTL {{Number of times single bit errors have occurred. 0 is byte position  from least significant byte of  memory data bus (DQ). Counter will be cleared  on RD LINK ECC SBE Interrupt read   }} 9080 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_SYNDROME_0 (RD_LINK_ECC_SBE_SYNDROME_0 RD {} ZERO ZERO FULL CTL {{Syndrome for most recent error, 0 is byte position  from least significant byte of  memory data bus (DQ). Syndrome will be cleared  on RD LINK ECC SBE Interrupt read   }} 9088 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_COUNT_1 (RD_LINK_ECC_SBE_COUNT_1 RD {} ZERO ZERO FULL CTL {{Number of times single bit errors have occurred. 1 is byte position  from least significant byte of  memory data bus (DQ). Counter will be cleared  on RD LINK ECC SBE Interrupt read   }} 9104 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_SYNDROME_1 (RD_LINK_ECC_SBE_SYNDROME_1 RD {} ZERO ZERO FULL CTL {{Syndrome for most recent error, 1 is byte position  from least significant byte of  memory data bus (DQ). Syndrome will be cleared  on RD LINK ECC SBE Interrupt read   }} 9120 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_COUNT_2 (RD_LINK_ECC_SBE_COUNT_2 RD {} ZERO ZERO FULL CTL {{Number of times single bit errors have occurred. 2 is byte position  from least significant byte of  memory data bus (DQ). Counter will be cleared  on RD LINK ECC SBE Interrupt read   }} 9136 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_SYNDROME_2 (RD_LINK_ECC_SBE_SYNDROME_2 RD {} ZERO ZERO FULL CTL {{Syndrome for most recent error, 2 is byte position  from least significant byte of  memory data bus (DQ). Syndrome will be cleared  on RD LINK ECC SBE Interrupt read   }} 9152 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_COUNT_3 (RD_LINK_ECC_SBE_COUNT_3 RD {} ZERO ZERO FULL CTL {{Number of times single bit errors have occurred. 3 is byte position  from least significant byte of  memory data bus (DQ). Counter will be cleared  on RD LINK ECC SBE Interrupt read   }} 9168 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_SYNDROME_3 (RD_LINK_ECC_SBE_SYNDROME_3 RD {} ZERO ZERO FULL CTL {{Syndrome for most recent error, 3 is byte position  from least significant byte of  memory data bus (DQ). Syndrome will be cleared  on RD LINK ECC SBE Interrupt read   }} 9184 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelck tckelck_minTck tckelck_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelck: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRE 0 --&gt; Returned 6: CADENCE_DEBUG_REG: CKSRE_F0:RW:16:8:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckeh tckckeh_minTck tckckeh_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckeh: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRX 0 --&gt; Returned 3: CADENCE_DEBUG_REG: CKSRX_F0:RW:24:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelck tckelck_minTck tckelck_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelck: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRE 1 --&gt; Returned 6: CADENCE_DEBUG_REG: CKSRE_F1:RW:0:8:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckeh tckckeh_minTck tckckeh_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckeh: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRX 1 --&gt; Returned 3: CADENCE_DEBUG_REG: CKSRX_F1:RW:8:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelck tckelck_minTck tckelck_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelck: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRE 2 --&gt; Returned 6: CADENCE_DEBUG_REG: CKSRE_F2:RW:16:8:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckeh tckckeh_minTck tckckeh_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckeh: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRX 2 --&gt; Returned 3: CADENCE_DEBUG_REG: CKSRX_F2:RW:24:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LOWPOWER_REFRESH_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LOWPOWER_REFRESH_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: LOWPOWER_REFRESH_ENABLE:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_CMD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_CMD --&gt; Returned 0: CADENCE_DEBUG_REG: LP_CMD:WR:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_IDLE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_IDLE_WAKEUP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_IDLE_WAKEUP_F0:RW:16:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_IDLE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_IDLE_WAKEUP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_CTRL_IDLE_WAKEUP_F0:RW:24:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_SHORT_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_SHORT_WAKEUP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_SR_SHORT_WAKEUP_F0:RW:0:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_WAKEUP 0 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SR_LONG_WAKEUP_F0:RW:8:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 0 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_WAKEUP_F0:RW:16:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 0 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0:RW:24:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 0 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F0:RW:0:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_PD_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_PD_WAKEUP 0 --&gt; Returned 1: CADENCE_DEBUG_REG: LPI_PD_WAKEUP_F0:RW:8:6:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_SHORT_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_SHORT_WAKEUP 0 --&gt; Returned 7: CADENCE_DEBUG_REG: LPI_SRPD_SHORT_WAKEUP_F0:RW:16:6:=0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_WAKEUP 0 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SRPD_LONG_WAKEUP_F0:RW:24:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 0 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_WAKEUP_F0:RW:0:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 0 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0:RW:8:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 0 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F0:RW:16:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_TIMER_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_TIMER_WAKEUP 0 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_TIMER_WAKEUP_F0:RW:24:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_TIMER_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_TIMER_WAKEUP 0 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_CTRL_TIMER_WAKEUP_F0:RW:0:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_IDLE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_IDLE_WAKEUP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_IDLE_WAKEUP_F1:RW:8:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_IDLE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_IDLE_WAKEUP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_CTRL_IDLE_WAKEUP_F1:RW:16:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_SHORT_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_SHORT_WAKEUP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_SR_SHORT_WAKEUP_F1:RW:24:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_WAKEUP 1 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SR_LONG_WAKEUP_F1:RW:0:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 1 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_WAKEUP_F1:RW:8:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 1 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1:RW:16:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 1 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F1:RW:24:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_PD_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_PD_WAKEUP 1 --&gt; Returned 1: CADENCE_DEBUG_REG: LPI_PD_WAKEUP_F1:RW:0:6:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_SHORT_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_SHORT_WAKEUP 1 --&gt; Returned 7: CADENCE_DEBUG_REG: LPI_SRPD_SHORT_WAKEUP_F1:RW:8:6:=0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_WAKEUP 1 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SRPD_LONG_WAKEUP_F1:RW:16:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 1 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_WAKEUP_F1:RW:24:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 1 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1:RW:0:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 1 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F1:RW:8:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_TIMER_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_TIMER_WAKEUP 1 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_TIMER_WAKEUP_F1:RW:16:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_TIMER_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_TIMER_WAKEUP 1 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_CTRL_TIMER_WAKEUP_F1:RW:24:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_IDLE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_IDLE_WAKEUP 2 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_IDLE_WAKEUP_F2:RW:0:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_IDLE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_IDLE_WAKEUP 2 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_CTRL_IDLE_WAKEUP_F2:RW:8:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_SHORT_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_SHORT_WAKEUP 2 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_SR_SHORT_WAKEUP_F2:RW:16:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_WAKEUP 2 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SR_LONG_WAKEUP_F2:RW:24:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 2 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_WAKEUP_F2:RW:0:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 2 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2:RW:8:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 2 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F2:RW:16:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_PD_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_PD_WAKEUP 2 --&gt; Returned 1: CADENCE_DEBUG_REG: LPI_PD_WAKEUP_F2:RW:24:6:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_SHORT_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_SHORT_WAKEUP 2 --&gt; Returned 7: CADENCE_DEBUG_REG: LPI_SRPD_SHORT_WAKEUP_F2:RW:0:6:=0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_WAKEUP 2 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SRPD_LONG_WAKEUP_F2:RW:8:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 2 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_WAKEUP_F2:RW:16:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 2 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2:RW:24:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 2 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F2:RW:0:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_TIMER_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_TIMER_WAKEUP 2 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_TIMER_WAKEUP_F2:RW:8:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_TIMER_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_TIMER_WAKEUP 2 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_CTRL_TIMER_WAKEUP_F2:RW:16:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_WAKEUP_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_WAKEUP_EN --&gt; Returned 47: CADENCE_DEBUG_REG: LPI_WAKEUP_EN:RW:24:6:=0x2f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_WAKEUP_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_WAKEUP_EN --&gt; Returned 45: CADENCE_DEBUG_REG: LPI_CTRL_WAKEUP_EN:RW:0:6:=0x2d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_REQ_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_REQ_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_CTRL_REQ_EN:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_TIMER_COUNT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_TIMER_COUNT --&gt; Returned 3: CADENCE_DEBUG_REG: LPI_TIMER_COUNT:RW:16:12:=0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_TIMER_COUNT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_TIMER_COUNT --&gt; Returned 3: CADENCE_DEBUG_REG: LPI_CTRL_TIMER_COUNT:RW:0:12:=0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_WAKEUP_TIMEOUT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_WAKEUP_TIMEOUT --&gt; Returned 4: CADENCE_DEBUG_REG: LPI_WAKEUP_TIMEOUT:RW:16:12:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_WAKEUP_TIMEOUT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_WAKEUP_TIMEOUT --&gt; Returned 4: CADENCE_DEBUG_REG: LPI_CTRL_WAKEUP_TIMEOUT:RW:0:12:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_LP_RESP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_LP_RESP --&gt; Returned 16: CADENCE_DEBUG_REG: TDFI_LP_RESP:RW:16:5:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__LP_STATE (LP_STATE RD {} ZERO LP_STATE_DEFAULT FULL CTL {{Low power state status parameter. Bits (5:0) indicate the current low power state and bit (6) set indicates that status bits are valid. READ-ONLY }} 9720 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_ENTRY_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_ENTRY_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_ENTRY_EN:RW:0:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_EXIT_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_EXIT_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_EXIT_EN:RW:8:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_MEM_GATE_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_MEM_GATE_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_MEM_GATE_EN:RW:16:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_PD_IDLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_PD_IDLE --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_PD_IDLE:RW:0:12:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_SR_SHORT_IDLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_SR_SHORT_IDLE --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_SR_SHORT_IDLE:RW:16:12:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_SR_LONG_IDLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_SR_LONG_IDLE --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_SR_LONG_IDLE:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_SR_LONG_MC_GATE_IDLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_SR_LONG_MC_GATE_IDLE --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_SR_LONG_MC_GATE_IDLE:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__HW_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__HW_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: HW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__HW_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__HW_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: HW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__HW_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__HW_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: HW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_SR_CTRLUPD_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_SR_CTRLUPD_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_SR_CTRLUPD_EN:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_SR_PHYUPD_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_SR_PHYUPD_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_SR_PHYUPD_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_SR_PHYMSTR_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_SR_PHYMSTR_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_SR_PHYMSTR_EN:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__LPC_SR_EXIT_CMD_EN will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_SR_ZQ_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_SR_ZQ_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_SR_ZQ_EN:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__PWRDN_SHIFT_DELAY will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFS_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFS_ENABLE --&gt; Returned 1: CADENCE_DEBUG_REG: DFS_ENABLE:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CURRENT_REG_COPY (CURRENT_REG_COPY RD {} ZERO ZERO FULL CTL {{Indicates the current copy of timing parameters that is in use by the controller. }} 9976 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CURRENT_FSP (CURRENT_FSP RD {} ZERO ZERO FULL CTL {{Indicates the active FSP within the DRAM.  If the connected DRAM device does not have FSPs, this will reflect zero. }} 9984 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INIT_FREQ" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INIT_FREQ --&gt; Returned 2: CADENCE_DEBUG_REG: INIT_FREQ:RW:8:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INIT_FSP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INIT_FSP --&gt; Returned 0: CADENCE_DEBUG_REG: INIT_FSP:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_START 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_START 0 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_INIT_START_F0:RW_D:0:24:=0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_COMPLETE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_COMPLETE 0 --&gt; Returned 4096: CADENCE_DEBUG_REG: TDFI_INIT_COMPLETE_F0:RW_D:0:24:=0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_START 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_START 1 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_INIT_START_F1:RW_D:0:24:=0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_COMPLETE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_COMPLETE 1 --&gt; Returned 4096: CADENCE_DEBUG_REG: TDFI_INIT_COMPLETE_F1:RW_D:0:24:=0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_START 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_START 2 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_INIT_START_F2:RW_D:0:24:=0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_COMPLETE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_COMPLETE 2 --&gt; Returned 4096: CADENCE_DEBUG_REG: TDFI_INIT_COMPLETE_F2:RW_D:0:24:=0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WRITE_MODEREG" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WRITE_MODEREG --&gt; Returned 0: CADENCE_DEBUG_REG: WRITE_MODEREG:RW+:0:27:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MRW_STATUS (MRW_STATUS RD {} ZERO ZERO FULL CTL {{Write memory mode register status. Bit (0) set indicates a WRITE_MODEREG parameter programming error. Bit (1) set indicates a PASR error. Bit (2) is Reserved. Bit (3) set indicates a self-refresh or deep power-down error. Bit (4) set indicates that a write to MR3 or MR11 was attempted (WRITE_MODEREG bit (25) was asserted with bit (17) set, or bit (23) was asserted with bits (7:0) defining MR3 or MR11) during tZQCAL after a ZQ calibration start command. READ-ONLY }} 10240 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__READ_MODEREG --&gt; FAKED 0: CADENCE_DEBUG_REG: READ_MODEREG:RW+:8:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PERIPHERAL_MRR_DATA (PERIPHERAL_MRR_DATA RD {} ZERO ZERO FULL CTL {{Data and chip returned from memory mode register read requested by the READ_MODEREG parameter. PERIPHERAL_MRR_DATA_WIDTH is the total width required to accomodate all attached DRAM Devices MRR data plus 8 bits for Chip select Info. Upper MSB 8 Bits of this register parameter indicates the targted chip from where this MRR data is read. Remaining PERIPHERAL_MRR_DATA_WIDTH-8 bits corresponds to attached DRAM device MRR Data. Example (7:0) for DRAM device0, (15:8) for DRAM device1, and so on to look for MRR data till total number of devices. READ-ONLY }} 10272 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AUTO_TEMPCHK_VAL_0 (AUTO_TEMPCHK_VAL_0 RD {} {ZERO 0} ZERO FULL CTL {{MR4 data for all devices accessed by automatic MRR commands. Bits (3:0) correlate to the device on the lower byte, bits (7:4) correlate to the devices on the 2nd byte etc. Value indicates the OP7, OP2, OP1 and OP0 bits. READ-ONLY. }} 10368 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AUTO_TEMPCHK_VAL_1 (AUTO_TEMPCHK_VAL_1 RD {} {ZERO 1} ZERO FULL CTL {{MR4 data for all devices accessed by automatic MRR commands. Bits (3:0) correlate to the device on the lower byte, bits (7:4) correlate to the devices on the 2nd byte etc. Value indicates the OP7, OP2, OP1 and OP0 bits. READ-ONLY. }} 10400 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRW_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRW_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRW_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRW_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRW_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRW_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DLL_RST" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DLL_RST --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DLL_RST:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__READ_MPR --&gt; FAKED 0: CADENCE_DEBUG_REG: READ_MPR:RW+:8:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MPRR_DATA_0 (MPRR_DATA_0 RD {} ZERO ZERO FULL CTL {{Data read from the multi-purpose register 0 read requested by the READ_MPR parameter. READ-ONLY MPR=0 }} 10560 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MPRR_DATA_1 (MPRR_DATA_1 RD {} ZERO ZERO FULL CTL {{Data read from the multi-purpose register 1 read requested by the READ_MPR parameter. READ-ONLY MPR=1 }} 10656 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MPRR_DATA_2 (MPRR_DATA_2 RD {} ZERO ZERO FULL CTL {{Data read from the multi-purpose register 2 read requested by the READ_MPR parameter. READ-ONLY MPR=2 }} 10752 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MPRR_DATA_3 (MPRR_DATA_3 RD {} ZERO ZERO FULL CTL {{Data read from the multi-purpose register 3 read requested by the READ_MPR parameter. READ-ONLY MPR=3 }} 10848 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F0_0:RW:8:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 0 0 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F0_0:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 0 0 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F0_0:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 0 1 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F1_0:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 0 1 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F1_0:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 0 2 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F2_0:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 0 2 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F2_0:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 1 0 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F0_1:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 1 0 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F0_1:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 1 1 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F1_1:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 1 1 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F1_1:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 1 2 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F2_1:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 1 2 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F2_1:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRSINGLE_DATA 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRSINGLE_DATA 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRSINGLE_DATA_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRSINGLE_DATA 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRSINGLE_DATA 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRSINGLE_DATA_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 0 0 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F0_0:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 0 1 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F1_0:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 0 2 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F2_0:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 1 0 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F0_1:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 1 1 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F1_1:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 1 2 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F2_1:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MR8_DATA_0 (MR8_DATA_0 RD {} {MR8_DATA 0} ZERO FULL CTL {{Data to program into memory mode register 8 for each chip select. READ-ONLY. }} 12312 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MR8_DATA_1 (MR8_DATA_1 RD {} {MR8_DATA 1} ZERO FULL CTL {{Data to program into memory mode register 8 for each chip select. READ-ONLY. }} 12320 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F0_0:RW:8:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 0 0 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F0_0:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 0 1 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F1_0:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 0 2 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F2_0:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 1 0 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F0_1:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 1 1 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F1_1:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 1 2 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F2_1:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 0 0 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F0_0:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 0 1 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F1_0:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 0 2 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F2_0:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 1 0 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F0_1:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 1 1 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F1_1:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 1 2 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F2_1:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR13_DATA 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of data_mask_en: Parameter value true</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR13_DATA 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR13_DATA_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR13_DATA 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of data_mask_en: Parameter value true</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR13_DATA 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR13_DATA_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 0 0 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F0_0:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 0 1 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F1_0:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 0 2 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F2_0:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 1 0 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F0_1:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 1 1 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F1_1:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 1 2 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F2_1:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR16_DATA 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR16_DATA 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR16_DATA_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR16_DATA 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR16_DATA 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR16_DATA_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 0 0 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F0_0:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 0 1 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F1_0:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 0 2 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F2_0:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 1 0 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F0_1:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 1 1 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F1_1:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 1 2 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F2_1:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR23_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR23_DATA --&gt; Returned 32: CADENCE_DEBUG_REG: MR23_DATA:RW:0:18:=0x000020</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR37_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ddr5: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR37_DATA --&gt; Returned 0: CADENCE_DEBUG_REG: MR37_DATA:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WCKI_OSC_TIMER_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WCKI_OSC_TIMER_DATA --&gt; Returned 0: CADENCE_DEBUG_REG: WCKI_OSC_TIMER_DATA:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WCKO_OSC_TIMER_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WCKO_OSC_TIMER_DATA --&gt; Returned 0: CADENCE_DEBUG_REG: WCKO_OSC_TIMER_DATA:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MPRR_SW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MPRR_SW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MPRR_SW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_MAP_0 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_MAP_0:RW+:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_VALID_0 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_VALID_0:RW+:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_MAP_1 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_MAP_1:RW+:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_VALID_1 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_VALID_1:RW+:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_MAP_2 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_MAP_2:RW+:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_VALID_2 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_VALID_2:RW+:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_GO" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_GO --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_GO:WR:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDR_SPACE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDR_SPACE --&gt; Returned 0: CADENCE_DEBUG_REG: ADDR_SPACE:RW:16:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_DATA_CHECK" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_DATA_CHECK --&gt; Returned 1: CADENCE_DEBUG_REG: BIST_DATA_CHECK:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_ECC_LANE_CHECK" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_ECC_LANE_CHECK --&gt; Returned 1: CADENCE_DEBUG_REG: BIST_ECC_LANE_CHECK:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_START_ADDRESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_START_ADDRESS --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_START_ADDRESS:RW:0:38:=0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_DATA_MASK" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_DATA_MASK --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_DATA_MASK:RW:0:144:=0x000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_TEST_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_TEST_MODE --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_TEST_MODE:RW:16:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_DATA_PATTERN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_DATA_PATTERN --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_DATA_PATTERN:RW:0:288:=0x000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_RET_STATE (BIST_RET_STATE RD {} ZERO ZERO FULL CTL {{Indicates if BIST is in a retention wait state, used when the BIST_TEST_MODE parameter is programmed to 2 or 3. Value of 1 indicates BIST is waiting. READ-ONLY }} 15552 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_ERR_STOP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_ERR_STOP --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_ERR_STOP:RW:8:12:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_ERR_COUNT (BIST_ERR_COUNT RD {} ZERO ZERO FULL CTL {{Indicates the number of BIST errors found when the BIST_TEST_MODE parameter is programmed to 1, 2 or 3. READ-ONLY }} 15584 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_RET_STATE_EXIT --&gt; FAKED 0: CADENCE_DEBUG_REG: BIST_RET_STATE_EXIT:WR:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_ENABLE:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FWC --&gt; FAKED 0: CADENCE_DEBUG_REG: FWC:RW+:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__XOR_CHECK_BITS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__XOR_CHECK_BITS --&gt; Returned 0: CADENCE_DEBUG_REG: XOR_CHECK_BITS:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_DISABLE_W_UC_ERR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_DISABLE_W_UC_ERR --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_DISABLE_W_UC_ERR:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_WRITEBACK_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_WRITEBACK_EN --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_WRITEBACK_EN:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_TYPE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_TYPE --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_TYPE:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INLINE_ECC_SAME_PAGE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INLINE_ECC_SAME_PAGE --&gt; Returned 0: CADENCE_DEBUG_REG: INLINE_ECC_SAME_PAGE:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INLINE_ECC_BANK_OFFSET" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INLINE_ECC_BANK_OFFSET --&gt; Returned 0: CADENCE_DEBUG_REG: INLINE_ECC_BANK_OFFSET:RW:0:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INLINE_ECC_BG_OFFSET" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INLINE_ECC_BG_OFFSET --&gt; Returned 0: CADENCE_DEBUG_REG: INLINE_ECC_BG_OFFSET:RW:8:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_READ_CACHING_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_READ_CACHING_EN --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_READ_CACHING_EN:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_WRITE_COMBINING_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_WRITE_COMBINING_EN --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_WRITE_COMBINING_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__MAX_WR_COMBINE will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DIRTY_TO_VALID_WRITES will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_U_ADDR (ECC_U_ADDR RD {} ZERO ZERO FULL CTL {{Address of uncorrectable ECC event. READ-ONLY }} 15776 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_U_SYND (ECC_U_SYND RD {} ZERO ZERO FULL CTL {{Syndrome for uncorrectable ECC event. READ-ONLY }} 15816 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_U_DATA (ECC_U_DATA RD {} ZERO ZERO FULL CTL {{Data associated with uncorrectable ECC event. READ-ONLY }} 15840 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_C_ADDR (ECC_C_ADDR RD {} ZERO ZERO FULL CTL {{Address of correctable ECC event. READ-ONLY }} 15904 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_C_SYND (ECC_C_SYND RD {} ZERO ZERO FULL CTL {{Syndrome for correctable ECC event. READ-ONLY }} 15944 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_C_DATA (ECC_C_DATA RD {} ZERO ZERO FULL CTL {{Data associated with correctable ECC event. READ-ONLY }} 15968 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_U_ID (ECC_U_ID RD {} ZERO ZERO FULL CTL {{Source ID associated with the uncorrectable ECC event. READ-ONLY }} 16032 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_C_ID (ECC_C_ID RD {} ZERO ZERO FULL CTL {{Source ID associated with correctable ECC event. READ-ONLY }} 16048 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_U_ADDR (RMODW_ECC_U_ADDR RD {} ZERO ZERO FULL CTL {{Address of uncorrectable rmodw ECC event. READ-ONLY }} 16064 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_U_SYND (RMODW_ECC_U_SYND RD {} ZERO ZERO FULL CTL {{Syndrome for uncorrectable rmodw ECC event. READ-ONLY }} 16104 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_U_DATA (RMODW_ECC_U_DATA RD {} ZERO ZERO FULL CTL {{Data associated with uncorrectable rmodw ECC event. READ-ONLY }} 16128 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_C_ADDR (RMODW_ECC_C_ADDR RD {} ZERO ZERO FULL CTL {{Address of correctable rmodw ECC event. READ-ONLY }} 16192 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_C_SYND (RMODW_ECC_C_SYND RD {} ZERO ZERO FULL CTL {{Syndrome for correctable rmodw ECC event. READ-ONLY }} 16232 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_C_DATA (RMODW_ECC_C_DATA RD {} ZERO ZERO FULL CTL {{Data associated with correctable rmodw ECC event. READ-ONLY }} 16256 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_U_ID (RMODW_ECC_U_ID RD {} ZERO ZERO FULL CTL {{Source ID associated with the uncorrectable rmodw ECC event. READ-ONLY }} 16320 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_C_ID (RMODW_ECC_C_ID RD {} ZERO ZERO FULL CTL {{Source ID associated with correctable ECC rmodw event. READ-ONLY }} 16336 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_0 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_0 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_1 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_1 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_2" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_2 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_2:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_2" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_2 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_2:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_3" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_3 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_3:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_3" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_3 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_3:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_4" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_4 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_4:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_4" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_4 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_4:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_5" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_5 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_5:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_5" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_5 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_5:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_6" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_6 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_6:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_6" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_6 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_6:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_7" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_7 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_7:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_7" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_7 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_7:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_ENABLE:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_START --&gt; FAKED 0: CADENCE_DEBUG_REG: ECC_SCRUB_START:WR:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_SCRUB_IN_PROGRESS (ECC_SCRUB_IN_PROGRESS RD {} ZERO ZERO FULL CTL {{Reports the scrubbing operation status. A value of 1 indicates that the controller is in the process of performing a scrubbing operation. READ-ONLY }} 16872 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_LEN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ddr5: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Controller_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Memory_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_LEN --&gt; Returned 16: CADENCE_DEBUG_REG: ECC_SCRUB_LEN:RW:16:13:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_MODE --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_SCRUB_MODE:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_INTERVAL" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_INTERVAL --&gt; Returned 1000: CADENCE_DEBUG_REG: ECC_SCRUB_INTERVAL:RW:8:16:=0x03e8</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_IDLE_CNT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_IDLE_CNT --&gt; Returned 100: CADENCE_DEBUG_REG: ECC_SCRUB_IDLE_CNT:RW:0:16:=0x0064</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_START_ADDR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_START_ADDR --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_SCRUB_START_ADDR:RW:0:38:=0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_END_ADDR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_END_ADDR --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_SCRUB_END_ADDR:RW:0:38:=0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CMD_BLK_SPLIT_SIZE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CMD_BLK_SPLIT_SIZE --&gt; Returned 0: CADENCE_DEBUG_REG: CMD_BLK_SPLIT_SIZE:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LONG_COUNT_MASK" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LONG_COUNT_MASK --&gt; Returned 0: CADENCE_DEBUG_REG: LONG_COUNT_MASK:RW:16:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_NORM_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Per_Bank_Refresh: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_NORM_THRESHOLD --&gt; Returned 20: CADENCE_DEBUG_REG: AREF_NORM_THRESHOLD:RW:24:5:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_HIGH_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Per_Bank_Refresh: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_HIGH_THRESHOLD --&gt; Returned 21: CADENCE_DEBUG_REG: AREF_HIGH_THRESHOLD:RW:0:5:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_MAX_DEFICIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_MAX_DEFICIT --&gt; Returned 24: CADENCE_DEBUG_REG: AREF_MAX_DEFICIT:RW:8:5:=0x18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_MAX_CREDIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_MAX_CREDIT --&gt; Returned 12: CADENCE_DEBUG_REG: AREF_MAX_CREDIT:RW:16:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_CMD_MAX_PER_TREFI" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_CMD_MAX_PER_TREFI --&gt; Returned 8: CADENCE_DEBUG_REG: AREF_CMD_MAX_PER_TREFI:RW:24:4:=0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_NULL_PEND_EXT_REQ" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Advanced_Low_Power_Control: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Advanced_Low_Power_Control: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_NULL_PEND_EXT_REQ --&gt; Returned 1: CADENCE_DEBUG_REG: AREF_NULL_PEND_EXT_REQ:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCS_OPT_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCS_OPT_THRESHOLD --&gt; Returned 3: CADENCE_DEBUG_REG: ZQCS_OPT_THRESHOLD:RW:8:3:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_NORM_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_HIGH_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_HIGH_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_NORM_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_NORM_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_NORM_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_HIGH_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_HIGH_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_TIMEOUT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_TIMEOUT_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_TIMEOUT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_TIMEOUT_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_TIMEOUT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_TIMEOUT_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_NORM_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_HIGH_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_HIGH_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_NORM_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_NORM_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_NORM_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_HIGH_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_HIGH_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_TIMEOUT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_TIMEOUT_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_TIMEOUT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_TIMEOUT_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_TIMEOUT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_TIMEOUT_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_NORM_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_HIGH_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_HIGH_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_NORM_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_NORM_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_NORM_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_HIGH_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_HIGH_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_TIMEOUT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_TIMEOUT_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_TIMEOUT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_TIMEOUT_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_TIMEOUT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_TIMEOUT_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__TIMEOUT_TIMER_LOG (TIMEOUT_TIMER_LOG RD {} ZERO ZERO FULL CTL {{Reflects which timers experienced a timeout error (or had an uncleared error) when the timeout interrupt fired.  Bit (0) correlates to a ZQ cal init, cs, cl, or reset FM timeout.  Bit (1) correlates to the ZQ calstart FM timeout.  Bit (2) correlates to the ZQ callatch FM timeout.  Bit (3) correlates to the MRR temperature check FM timeout.  Bit (4) correlates to the DQS oscillator FM timeout.  Bit (5) correlates to the DFI update FM timeout.  Bit (6) correlates to the low power interface wakeup timeout.  Bit (7) correlates to the low power interface wakeup timeout for LPI Control Interface.  Bit (9) correlates to the auto refresh max deficit timeout.  READ-ONLY }} 17568 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQINIT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqinit_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQINIT 0 --&gt; Returned 512: CADENCE_DEBUG_REG: ZQINIT_F0:RW_D:16:12:=0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcl_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCL 0 --&gt; Returned 256: CADENCE_DEBUG_REG: ZQCL_F0:RW:0:12:=0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCS 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCS 0 --&gt; Returned 64: CADENCE_DEBUG_REG: ZQCS_F0:RW:16:12:=0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCAL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcal tZQCAL}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcal: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcal: Parameter value {1.0 us}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.0 us}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQCAL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCAL 0 --&gt; Returned 1068: CADENCE_DEBUG_REG: TZQCAL_F0:RW:0:12:=0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQLAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqlat tZQLAT tZQLAT_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqlat: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqlat: Parameter value {30.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {30.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQLAT 0 --&gt; Returned 33: CADENCE_DEBUG_REG: TZQLAT_F0:RW:16:7:=0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQINIT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqinit_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQINIT 1 --&gt; Returned 512: CADENCE_DEBUG_REG: ZQINIT_F1:RW_D:0:12:=0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcl_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCL 1 --&gt; Returned 256: CADENCE_DEBUG_REG: ZQCL_F1:RW:16:12:=0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCS 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCS 1 --&gt; Returned 64: CADENCE_DEBUG_REG: ZQCS_F1:RW:0:12:=0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCAL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcal tZQCAL}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcal: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcal: Parameter value {1.0 us}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.0 us}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQCAL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCAL 1 --&gt; Returned 1068: CADENCE_DEBUG_REG: TZQCAL_F1:RW:16:12:=0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQLAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqlat tZQLAT tZQLAT_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqlat: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqlat: Parameter value {30.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {30.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQLAT 1 --&gt; Returned 33: CADENCE_DEBUG_REG: TZQLAT_F1:RW:0:7:=0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQINIT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqinit_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQINIT 2 --&gt; Returned 512: CADENCE_DEBUG_REG: ZQINIT_F2:RW_D:8:12:=0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcl_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCL 2 --&gt; Returned 256: CADENCE_DEBUG_REG: ZQCL_F2:RW:0:12:=0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCS 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCS 2 --&gt; Returned 64: CADENCE_DEBUG_REG: ZQCS_F2:RW:16:12:=0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCAL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcal tZQCAL}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcal: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcal: Parameter value {1.0 us}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.0 us}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQCAL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCAL 2 --&gt; Returned 1068: CADENCE_DEBUG_REG: TZQCAL_F2:RW:0:12:=0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQLAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqlat tZQLAT tZQLAT_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqlat: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqlat: Parameter value {30.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {30.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQLAT 2 --&gt; Returned 33: CADENCE_DEBUG_REG: TZQLAT_F2:RW:16:7:=0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_SW_REQ_START_LATCH_MAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_SW_REQ_START_LATCH_MAP --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_SW_REQ_START_LATCH_MAP:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_REQ --&gt; FAKED 0: CADENCE_DEBUG_REG: ZQ_REQ:WR:0:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ZQ_REQ_PENDING (ZQ_REQ_PENDING RD {} ZERO ZERO FULL CTL {{Indicates that a ZQ command is currently in progress or waiting to run. Value of 1 indicates command in progress or waiting to run. When this is asserted, no writes to ZQ_REQ should occur. READ-ONLY }} 17832 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQRESET 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqreset_minTck tZQRESET_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQRESET 0 --&gt; Returned 54: CADENCE_DEBUG_REG: ZQRESET_F0:RW:16:12:=0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQRESET 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqreset_minTck tZQRESET_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQRESET 1 --&gt; Returned 54: CADENCE_DEBUG_REG: ZQRESET_F1:RW:0:12:=0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQRESET 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqreset_minTck tZQRESET_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQRESET 2 --&gt; Returned 54: CADENCE_DEBUG_REG: ZQRESET_F2:RW:16:12:=0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCS_ROTATE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCS_ROTATE --&gt; Returned 1: CADENCE_DEBUG_REG: ZQCS_ROTATE:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CAL_START_MAP_0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CAL_START_MAP_0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CAL_START_MAP_0:RW_D:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CAL_LATCH_MAP_0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CAL_LATCH_MAP_0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CAL_LATCH_MAP_0:RW_D:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CAL_START_MAP_1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CAL_START_MAP_1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CAL_START_MAP_1:RW_D:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CAL_LATCH_MAP_1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CAL_LATCH_MAP_1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CAL_LATCH_MAP_1:RW_D:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_DIFF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_DIFF 0 --&gt; Returned 2: CADENCE_DEBUG_REG: BANK_DIFF_0:RW:8:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_DIFF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_DIFF 1 --&gt; Returned 2: CADENCE_DEBUG_REG: BANK_DIFF_1:RW:16:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ROW_DIFF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Rows_Supported: Parameter value 18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ROW_DIFF 0 --&gt; Returned 3: CADENCE_DEBUG_REG: ROW_DIFF_0:RW:24:3:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ROW_DIFF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Rows_Supported: Parameter value 18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ROW_DIFF 1 --&gt; Returned 3: CADENCE_DEBUG_REG: ROW_DIFF_1:RW:0:3:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__COL_DIFF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_Columns_Supported: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Columns_Supported: Parameter value 11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__COL_DIFF 0 --&gt; Returned 1: CADENCE_DEBUG_REG: COL_DIFF_0:RW:8:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__COL_DIFF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_Columns_Supported: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Columns_Supported: Parameter value 11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__COL_DIFF 1 --&gt; Returned 1: CADENCE_DEBUG_REG: COL_DIFF_1:RW:16:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CID_DIFF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of componentDdrSOMA: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CID_DIFF 0 --&gt; Returned 1: CADENCE_DEBUG_REG: CID_DIFF_0:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CID_DIFF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of componentDdrSOMA: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CID_DIFF 1 --&gt; Returned 1: CADENCE_DEBUG_REG: CID_DIFF_1:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BG_DIFF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BG_DIFF 0 --&gt; Returned 3: CADENCE_DEBUG_REG: BG_DIFF_0:RW:8:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BG_DIFF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BG_DIFF 1 --&gt; Returned 3: CADENCE_DEBUG_REG: BG_DIFF_1:RW:16:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_VAL_LOWER 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_VAL_LOWER 0 --&gt; Returned 0: CADENCE_DEBUG_REG: CS_VAL_LOWER_0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_VAL_UPPER 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_VAL_UPPER 0 --&gt; Returned 255: CADENCE_DEBUG_REG: CS_VAL_UPPER_0:RW:16:16:=0x00ff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ROW_START_VAL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ROW_START_VAL 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ROW_START_VAL_0:RW:0:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_MSK 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_MSK 0 --&gt; Returned 31: CADENCE_DEBUG_REG: CS_MSK_0:RW:8:16:=0x001f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_VAL_LOWER 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_VAL_LOWER 1 --&gt; Returned 0xFFFF: CADENCE_DEBUG_REG: CS_VAL_LOWER_1:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_VAL_UPPER 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_VAL_UPPER 1 --&gt; Returned 0xFFFF: CADENCE_DEBUG_REG: CS_VAL_UPPER_1:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ROW_START_VAL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ROW_START_VAL 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ROW_START_VAL_1:RW:0:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_MSK 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_MSK 1 --&gt; Returned 65535: CADENCE_DEBUG_REG: CS_MSK_1:RW:8:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PROGRAMMABLE_ADDRESS_ORDER" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_prog_addr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_prog_addr: Parameter value false</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PROGRAMMABLE_ADDRESS_ORDER --&gt; Returned 0: CADENCE_DEBUG_REG: PROGRAMMABLE_ADDRESS_ORDER:RW+:24:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__BANK_START_BIT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__APREBIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__APREBIT --&gt; Returned 11: CADENCE_DEBUG_REG: APREBIT:RW_D:8:5:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AGE_COUNT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AGE_COUNT --&gt; Returned 255: CADENCE_DEBUG_REG: AGE_COUNT:RW:16:8:=0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__COMMAND_AGE_COUNT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__COMMAND_AGE_COUNT --&gt; Returned 255: CADENCE_DEBUG_REG: COMMAND_AGE_COUNT:RW:24:8:=0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDR_CMP_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDR_CMP_EN --&gt; Returned 1: CADENCE_DEBUG_REG: ADDR_CMP_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDR_COLLISION_MPM_DIS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDR_COLLISION_MPM_DIS --&gt; Returned 0: CADENCE_DEBUG_REG: ADDR_COLLISION_MPM_DIS:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_SPLIT_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_SPLIT_EN --&gt; Returned 1: CADENCE_DEBUG_REG: BANK_SPLIT_EN:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PLACEMENT_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PLACEMENT_EN --&gt; Returned 1: CADENCE_DEBUG_REG: PLACEMENT_EN:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PRIORITY_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PRIORITY_EN --&gt; Returned 1: CADENCE_DEBUG_REG: PRIORITY_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RW_SAME_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RW_SAME_EN --&gt; Returned 1: CADENCE_DEBUG_REG: RW_SAME_EN:RW:8:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RW_SAME_PAGE_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RW_SAME_PAGE_EN --&gt; Returned 1: CADENCE_DEBUG_REG: RW_SAME_PAGE_EN:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_SAME_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_SAME_EN --&gt; Returned 1: CADENCE_DEBUG_REG: CS_SAME_EN:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2R_SPLIT_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2R_SPLIT_EN --&gt; Returned 1: CADENCE_DEBUG_REG: W2R_SPLIT_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DISABLE_RW_GROUP_W_BNK_CONFLICT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DISABLE_RW_GROUP_W_BNK_CONFLICT --&gt; Returned 1: CADENCE_DEBUG_REG: DISABLE_RW_GROUP_W_BNK_CONFLICT:RW:8:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NUM_Q_ENTRIES_ACT_DISABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NUM_Q_ENTRIES_ACT_DISABLE --&gt; Returned 16: CADENCE_DEBUG_REG: NUM_Q_ENTRIES_ACT_DISABLE:RW:16:5:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__SWAP_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__SWAP_EN --&gt; Returned 0: CADENCE_DEBUG_REG: SWAP_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DISABLE_RD_INTERLEAVE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DISABLE_RD_INTERLEAVE --&gt; Returned 1: CADENCE_DEBUG_REG: DISABLE_RD_INTERLEAVE:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INHIBIT_DRAM_CMD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INHIBIT_DRAM_CMD --&gt; Returned 0: CADENCE_DEBUG_REG: INHIBIT_DRAM_CMD:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_MAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_MAP --&gt; Returned 1: CADENCE_DEBUG_REG: CS_MAP:RW:16:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BURST_ON_FLY_BIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BURST_ON_FLY_BIT --&gt; Returned 0: CADENCE_DEBUG_REG: BURST_ON_FLY_BIT:RW:24:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MEM_DP_REDUCTION" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep_x40: Parameter value false</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of numChannels: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of HMC_Interface: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_enabled: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Memory_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: cadence_reg__MEM_DP_REDUCTION: is_lockstep_x40=false num_channels=1 dq_per_channel=32 hmc_interface=0 ecc_enabled=0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MEM_DP_REDUCTION --&gt; Returned 0: CADENCE_DEBUG_REG: MEM_DP_REDUCTION:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MEMDATA_RATIO 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ddr5: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Controller_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Memory_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MEMDATA_RATIO 0 --&gt; Returned 1: CADENCE_DEBUG_REG: MEMDATA_RATIO_0:RW:8:3:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MEMDATA_RATIO 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ddr5: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Controller_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Memory_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MEMDATA_RATIO 1 --&gt; Returned 1: CADENCE_DEBUG_REG: MEMDATA_RATIO_1:RW:16:3:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_0 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_0 0 0 --&gt; Returned 1: CADENCE_DEBUG_REG: DEVICE0_BYTE0_CS0:RW:0:9:=0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_1 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_1 0 1 --&gt; Returned 4: CADENCE_DEBUG_REG: DEVICE1_BYTE0_CS0:RW:16:9:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_2 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_2 0 2 --&gt; Returned 16: CADENCE_DEBUG_REG: DEVICE2_BYTE0_CS0:RW:0:9:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_3 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_3 0 3 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE3_BYTE0_CS0:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_4 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_4 0 4 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE4_BYTE0_CS0:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_5 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_5 0 5 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE5_BYTE0_CS0:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_6 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_6 0 6 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE6_BYTE0_CS0:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_7 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_7 0 7 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE7_BYTE0_CS0:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_8 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_8 0 8 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE8_BYTE0_CS0:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_0 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_0 1 0 --&gt; Returned 1: CADENCE_DEBUG_REG: DEVICE0_BYTE0_CS1:RW:16:9:=0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_1 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_1 1 1 --&gt; Returned 4: CADENCE_DEBUG_REG: DEVICE1_BYTE0_CS1:RW:0:9:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_2 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_2 1 2 --&gt; Returned 16: CADENCE_DEBUG_REG: DEVICE2_BYTE0_CS1:RW:16:9:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_3 1 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_3 1 3 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE3_BYTE0_CS1:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_4 1 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_4 1 4 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE4_BYTE0_CS1:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_5 1 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_5 1 5 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE5_BYTE0_CS1:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_6 1 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_6 1 6 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE6_BYTE0_CS1:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_7 1 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_7 1 7 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE7_BYTE0_CS1:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_8 1 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_8 1 8 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE8_BYTE0_CS1:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MDQS_MULT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MDQS_MULT --&gt; Returned 1: CADENCE_DEBUG_REG: MDQS_MULT:RW:0:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__Q_FULLNESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__Q_FULLNESS --&gt; Returned 0: CADENCE_DEBUG_REG: Q_FULLNESS:RW:8:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__IN_ORDER_ACCEPT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__IN_ORDER_ACCEPT --&gt; Returned 0: CADENCE_DEBUG_REG: IN_ORDER_ACCEPT:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_ORDER_REQ" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_ORDER_REQ --&gt; Returned 0: CADENCE_DEBUG_REG: WR_ORDER_REQ:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CONTROLLER_BUSY (CONTROLLER_BUSY RD {} ZERO ZERO FULL CTL {{Indicator that the controller is processing a command. Evaluates all ports for outstanding transactions. Value of 1 indicates controller busy. READ-ONLY }} 18656 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CTRLUPD_REQ --&gt; FAKED 0: CADENCE_DEBUG_REG: CTRLUPD_REQ:WR:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_PREAMBLE_LEN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_PREAMBLE_LEN 0 --&gt; Returned 1: CADENCE_DEBUG_REG: RD_PREAMBLE_LEN_F0:RW:0:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_PREAMBLE_LEN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_PREAMBLE_LEN 0 --&gt; Returned 1: CADENCE_DEBUG_REG: WR_PREAMBLE_LEN_F0:RW:8:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_PREAMBLE_LEN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_PREAMBLE_LEN 1 --&gt; Returned 1: CADENCE_DEBUG_REG: RD_PREAMBLE_LEN_F1:RW:16:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_PREAMBLE_LEN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_PREAMBLE_LEN 1 --&gt; Returned 1: CADENCE_DEBUG_REG: WR_PREAMBLE_LEN_F1:RW:24:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_PREAMBLE_LEN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_PREAMBLE_LEN 2 --&gt; Returned 1: CADENCE_DEBUG_REG: RD_PREAMBLE_LEN_F2:RW:0:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_PREAMBLE_LEN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_PREAMBLE_LEN 2 --&gt; Returned 1: CADENCE_DEBUG_REG: WR_PREAMBLE_LEN_F2:RW:8:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_PREAMBLE_TRAINING_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_PREAMBLE_TRAINING_EN --&gt; Returned 1: CADENCE_DEBUG_REG: RD_PREAMBLE_TRAINING_EN:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_DBI_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_DBI_EN --&gt; Returned 0: CADENCE_DEBUG_REG: WR_DBI_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_DBI_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_DBI_EN --&gt; Returned 1: CADENCE_DEBUG_REG: RD_DBI_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DFI_ERROR (DFI_ERROR RD {} ZERO ZERO FULL CTL {{Indicates that the DFI error flag has been asserted. READ-ONLY }} 18760 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DFI_ERROR_INFO (DFI_ERROR_INFO RD {} ZERO ZERO FULL CTL {{Holds the encoded DFI error type associated with the DFI_ERROR parameter assertion. READ-ONLY }} 18784 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BG_ROTATE_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of bg_rotation: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BG_ROTATE_EN --&gt; Returned 0: CADENCE_DEBUG_REG: BG_ROTATE_EN:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__GATHER_FIFO_RESYNC will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__POSTAMBLE_SUPPORT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__POSTAMBLE_SUPPORT --&gt; Returned 2: CADENCE_DEBUG_REG: POSTAMBLE_SUPPORT:RW:24:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_MASTER (INT_STATUS_MASTER RD {} ZERO ZERO FULL CTL {{Master status reporting register for interrupt status groups. READ-ONLY }} 18848 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_MASTER" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_MASTER --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_MASTER:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_TIMEOUT (INT_STATUS_TIMEOUT RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Timeout monitors. READ-ONLY }} 18912 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_ECC (INT_STATUS_ECC RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to ECC. READ-ONLY }} 18944 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_LOWPOWER (INT_STATUS_LOWPOWER RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Low Power. READ-ONLY }} 18976 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_STATUS_PORT_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_STATUS_RFIFO_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_TRAINING (INT_STATUS_TRAINING RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Training/Calibration. READ-ONLY }} 19040 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_USERIF (INT_STATUS_USERIF RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to ASIC to Controller Interface. READ-ONLY }} 19072 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_MISC (INT_STATUS_MISC RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Miscellaneous features. READ-ONLY }} 19104 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_BIST (INT_STATUS_BIST RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to BIST. READ-ONLY }} 19120 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_STATUS_CRC will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_DFI (INT_STATUS_DFI RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to DFI. READ-ONLY }} 19136 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_DIMM (INT_STATUS_DIMM RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to DIMM. READ-ONLY }} 19144 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_FREQ (INT_STATUS_FREQ RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Frequency Scaling. READ-ONLY }} 19152 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_INIT (INT_STATUS_INIT RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Initialization. READ-ONLY }} 19160 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_MODE (INT_STATUS_MODE RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Memory Mode Settings. READ-ONLY }} 19168 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_PARITY (INT_STATUS_PARITY RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Parity. READ-ONLY }} 19176 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_TIMEOUT --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_TIMEOUT:WR:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_ECC --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_ECC:WR:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_LOWPOWER --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_LOWPOWER:WR:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_ACK_PORT_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_ACK_RFIFO_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_TRAINING --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_TRAINING:WR:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_USERIF --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_USERIF:WR:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_MISC --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_MISC:WR:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_BIST --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_BIST:WR:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_ACK_CRC will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_DFI --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_DFI:WR:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_DIMM --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_DIMM:WR:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_FREQ --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_FREQ:WR:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_INIT --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_INIT:WR:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_MODE --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_MODE:WR:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_PARITY --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_PARITY:WR:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_TIMEOUT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_TIMEOUT --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_TIMEOUT:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_ECC" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_ECC --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_ECC:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_LOWPOWER" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_LOWPOWER --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_LOWPOWER:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_MASK_PORT_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_MASK_RFIFO_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_TRAINING" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_TRAINING --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_TRAINING:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_USERIF" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_USERIF --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_USERIF:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_MISC" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_MISC --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_MISC:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_BIST" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_BIST --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_BIST:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_MASK_CRC will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_DFI" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_DFI --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_DFI:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_DIMM" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_DIMM --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_DIMM:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_FREQ" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_FREQ --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_FREQ:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_INIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_INIT --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_INIT:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_MODE --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_MODE:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_PARITY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_PARITY --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_PARITY:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__OUT_OF_RANGE_ADDR (OUT_OF_RANGE_ADDR RD {} ZERO ZERO FULL CTL {{Address of command that caused an out-of-range interrupt. READ-ONLY }} 19776 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__OUT_OF_RANGE_LENGTH (OUT_OF_RANGE_LENGTH RD {} ZERO ZERO FULL CTL {{Length of command that caused an out-of-range interrupt. READ-ONLY }} 19816 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__OUT_OF_RANGE_TYPE (OUT_OF_RANGE_TYPE RD {} ZERO ZERO FULL CTL {{Type of command that caused an out-of-range interrupt. READ-ONLY }} 19832 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__OUT_OF_RANGE_SOURCE_ID (OUT_OF_RANGE_SOURCE_ID RD {} ZERO ZERO FULL CTL {{Source ID of command that caused an out-of-range interrupt. READ-ONLY }} 19840 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_EXP_DATA (BIST_EXP_DATA RD {} ZERO ZERO FULL CTL {{Expected data on BIST error. READ-ONLY }} 19872 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_FAIL_DATA (BIST_FAIL_DATA RD {} ZERO ZERO FULL CTL {{Actual data on BIST error. READ-ONLY }} 20160 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_FAIL_ADDR (BIST_FAIL_ADDR RD {} ZERO ZERO FULL CTL {{Address of BIST error. READ-ONLY }} 20448 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PORT_CMD_ERROR_ADDR (PORT_CMD_ERROR_ADDR RD {} ZERO ZERO FULL CTL {{Address of command that caused the PORT command error. READ-ONLY }} 20512 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PORT_CMD_ERROR_ID (PORT_CMD_ERROR_ID RD {} ZERO ZERO FULL CTL {{Source ID of command that caused the PORT command error. READ-ONLY }} 20552 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PORT_CMD_ERROR_TYPE (PORT_CMD_ERROR_TYPE RD {} ZERO ZERO FULL CTL {{Type of error and access type that caused the PORT command error. READ-ONLY }} 20568 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tODTUP}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTUP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTUP 0 --&gt; Returned 267: CADENCE_DEBUG_REG: TODTUP_F0:RW:0:16:=0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tODTUP}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTUP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTUP 1 --&gt; Returned 267: CADENCE_DEBUG_REG: TODTUP_F1:RW:16:16:=0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tODTUP}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTUP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTUP 2 --&gt; Returned 267: CADENCE_DEBUG_REG: TODTUP_F2:RW:0:16:=0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PD_NT_ODT_EN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PD_NT_ODT_EN 0 --&gt; Returned 0: CADENCE_DEBUG_REG: PD_NT_ODT_EN_F0:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PD_NT_ODT_EN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PD_NT_ODT_EN 1 --&gt; Returned 0: CADENCE_DEBUG_REG: PD_NT_ODT_EN_F1:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PD_NT_ODT_EN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PD_NT_ODT_EN 2 --&gt; Returned 0: CADENCE_DEBUG_REG: PD_NT_ODT_EN_F2:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTL_2CMD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTL_2CMD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TODTL_2CMD_F0:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_WR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_WR 0 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_WR_F0:RW:16:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_RD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_RD 0 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_RD_F0:RW:24:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTL_2CMD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTL_2CMD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TODTL_2CMD_F1:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_WR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_WR 1 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_WR_F1:RW:8:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_RD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_RD 1 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_RD_F1:RW:16:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTL_2CMD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTL_2CMD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TODTL_2CMD_F2:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_WR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_WR 2 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_WR_F2:RW:0:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_RD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_RD 2 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_RD_F2:RW:8:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_EN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_EN 0 --&gt; Returned 1: CADENCE_DEBUG_REG: ODT_EN_F0:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_EN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_EN 1 --&gt; Returned 1: CADENCE_DEBUG_REG: ODT_EN_F1:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_EN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_EN 2 --&gt; Returned 1: CADENCE_DEBUG_REG: ODT_EN_F2:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__EN_ODT_ASSERT_EXCEPT_RD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__EN_ODT_ASSERT_EXCEPT_RD --&gt; Returned 0: CADENCE_DEBUG_REG: EN_ODT_ASSERT_EXCEPT_RD:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_TO_ODTH 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_TO_ODTH 0 --&gt; Returned 16: CADENCE_DEBUG_REG: WR_TO_ODTH_F0:RW:16:7:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_TO_ODTH 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_TO_ODTH 1 --&gt; Returned 16: CADENCE_DEBUG_REG: WR_TO_ODTH_F1:RW:24:7:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_TO_ODTH 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_TO_ODTH 2 --&gt; Returned 16: CADENCE_DEBUG_REG: WR_TO_ODTH_F2:RW:0:7:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_RD_MAP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_RD_MAP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ODT_RD_MAP_CS0:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_WR_MAP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_WR_MAP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ODT_WR_MAP_CS0:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_RD_MAP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_RD_MAP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ODT_RD_MAP_CS1:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_WR_MAP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_WR_MAP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ODT_WR_MAP_CS1:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_TO_ODTH 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_TO_ODTH 0 --&gt; Returned 21: CADENCE_DEBUG_REG: RD_TO_ODTH_F0:RW:8:7:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_TO_ODTH 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_TO_ODTH 1 --&gt; Returned 21: CADENCE_DEBUG_REG: RD_TO_ODTH_F1:RW:16:7:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_TO_ODTH 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_TO_ODTH 2 --&gt; Returned 21: CADENCE_DEBUG_REG: RD_TO_ODTH_F2:RW:24:7:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RW2MRW_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RW2MRW_DLY 0 --&gt; Returned 9: CADENCE_DEBUG_REG: RW2MRW_DLY_F0:RW_D:0:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RW2MRW_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RW2MRW_DLY 1 --&gt; Returned 9: CADENCE_DEBUG_REG: RW2MRW_DLY_F1:RW_D:8:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RW2MRW_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RW2MRW_DLY 2 --&gt; Returned 9: CADENCE_DEBUG_REG: RW2MRW_DLY_F2:RW_D:16:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2R_DIFFCS_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2R_DIFFCS_DLY 0 --&gt; Returned 12: CADENCE_DEBUG_REG: R2R_DIFFCS_DLY_F0:RW_D:24:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_DIFFCS_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_DIFFCS_DLY 0 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_DIFFCS_DLY_F0:RW_D:0:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2R_DIFFCS_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2R_DIFFCS_DLY 0 --&gt; Returned 1: CADENCE_DEBUG_REG: W2R_DIFFCS_DLY_F0:RW_D:8:5:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2W_DIFFCS_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2W_DIFFCS_DLY 0 --&gt; Returned 12: CADENCE_DEBUG_REG: W2W_DIFFCS_DLY_F0:RW_D:16:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2R_DIFFCS_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2R_DIFFCS_DLY 1 --&gt; Returned 12: CADENCE_DEBUG_REG: R2R_DIFFCS_DLY_F1:RW_D:24:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_DIFFCS_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_DIFFCS_DLY 1 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_DIFFCS_DLY_F1:RW_D:0:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2R_DIFFCS_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2R_DIFFCS_DLY 1 --&gt; Returned 1: CADENCE_DEBUG_REG: W2R_DIFFCS_DLY_F1:RW_D:8:5:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2W_DIFFCS_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2W_DIFFCS_DLY 1 --&gt; Returned 12: CADENCE_DEBUG_REG: W2W_DIFFCS_DLY_F1:RW_D:16:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2R_DIFFCS_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2R_DIFFCS_DLY 2 --&gt; Returned 12: CADENCE_DEBUG_REG: R2R_DIFFCS_DLY_F2:RW_D:24:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_DIFFCS_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_DIFFCS_DLY 2 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_DIFFCS_DLY_F2:RW_D:0:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2R_DIFFCS_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2R_DIFFCS_DLY 2 --&gt; Returned 1: CADENCE_DEBUG_REG: W2R_DIFFCS_DLY_F2:RW_D:8:5:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2W_DIFFCS_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2W_DIFFCS_DLY 2 --&gt; Returned 12: CADENCE_DEBUG_REG: W2W_DIFFCS_DLY_F2:RW_D:16:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_SAMECS_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_SAMECS_DLY 0 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_SAMECS_DLY_F0:RW_D:24:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_SAMECS_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_SAMECS_DLY 1 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_SAMECS_DLY_F1:RW_D:0:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_SAMECS_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_SAMECS_DLY 2 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_SAMECS_DLY_F2:RW_D:8:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2R_SAMECS_DLY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2R_SAMECS_DLY --&gt; Returned 0: CADENCE_DEBUG_REG: R2R_SAMECS_DLY:RW:16:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2R_SAMECS_DLY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2R_SAMECS_DLY --&gt; Returned 0: CADENCE_DEBUG_REG: W2R_SAMECS_DLY:RW:24:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2W_SAMECS_DLY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2W_SAMECS_DLY --&gt; Returned 0: CADENCE_DEBUG_REG: W2W_SAMECS_DLY:RW:0:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MAX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MAX 0 --&gt; Returned 4: CADENCE_DEBUG_REG: TDQSCK_MAX_F0:RW:8:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MIN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MIN 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TDQSCK_MIN_F0:RW:16:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MAX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MAX 1 --&gt; Returned 4: CADENCE_DEBUG_REG: TDQSCK_MAX_F1:RW:24:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MIN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MIN 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TDQSCK_MIN_F1:RW:0:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MAX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MAX 2 --&gt; Returned 4: CADENCE_DEBUG_REG: TDQSCK_MAX_F2:RW:8:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MIN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MIN 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TDQSCK_MIN_F2:RW:16:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AXI0_ALL_STROBES_USED_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AXI0_ALL_STROBES_USED_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AXI0_FIXED_PORT_PRIORITY_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AXI0_FIXED_PORT_PRIORITY_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_FIXED_PORT_PRIORITY_ENABLE:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PORT_PRIORITY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PORT_PRIORITY 0 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_R_PRIORITY:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PORT_PRIORITY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PORT_PRIORITY 0 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_W_PRIORITY:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PORT_FIFO_TYPE_REG 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of fifo_type: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PORT_FIFO_TYPE_REG 0 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_FIFO_TYPE_REG:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PORT_ADDR_PROTECTION_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PORT_ADDR_PROTECTION_EN --&gt; Returned 0: CADENCE_DEBUG_REG: PORT_ADDR_PROTECTION_EN:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AXI0_ADDRESS_RANGE_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AXI0_ADDRESS_RANGE_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_ADDRESS_RANGE_ENABLE:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 0 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_0:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 0 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_0:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 0 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 0 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 0 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 0 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 1 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_1:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 1 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_1:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 1 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 1 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 1 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 1 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 2 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_2:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 2 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_2:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 2 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 2 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 2 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 2 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 3 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_3:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 3 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_3:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 3 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_3:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 3 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 3 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 3 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 3 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 4 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_4:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 4 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_4:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 4 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_4:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 4 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 4 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 4 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 4 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 5 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_5:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 5 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_5:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 5 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_5:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 5 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 5 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 5 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 5 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 6 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_6:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 6 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_6:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 6 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_6:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 6 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 6 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 6 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 6 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 7 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_7:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 7 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_7:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 7 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_7:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 7 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 7 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 7 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 7 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 8 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_8:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 8 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_8:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 8 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_8:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 8 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 8 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 8 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 8 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 9 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_9:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 9 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_9:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 9 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_9:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 9 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 9 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 9 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 9 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 10 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_10:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 10 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_10:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 10 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_10:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 10 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 10 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 10 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 10 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 11 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_11:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 11 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_11:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 11 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_11:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 11 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 11 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 11 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 11 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 12 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_12:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 12 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_12:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 12 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_12:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 12 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 12 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 12 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 12 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 13 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_13:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 13 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_13:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 13 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_13:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 13 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 13 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 13 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 13 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 14 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_14:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 14 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_14:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 14 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_14:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 14 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 14 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 14 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 14 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 15 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_15:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 15 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_15:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 15 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_15:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 15 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 15 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 15 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 15 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CKE_STATUS (CKE_STATUS RD {} ZERO ZERO FULL CTL {{Register access to cke_status signal. READ-ONLY }} 25288 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MEM_RST_VALID (MEM_RST_VALID RD {} ZERO ZERO FULL CTL {{Register access to mem_rst_valid signal. READ-ONLY }} 25296 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_RDLAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT: cas_latency = 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: mem_delay = 3.5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Base phy_internal_delay: 7. TDFI_PHY_WRDATA = 2, TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">1: phy_internal_delay-&gt; 8: TDFI_PHY_WRDATA = 2 TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">2: phy_internal_delay-&gt; 12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=17: delay_adder=0 phy_internal_delay=12 ie_delay_adder=0 lpddr_adder=4 dfi_adder=0 rd_preamble_len=1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=41: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=75: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT 0 --&gt; Returned 75: CADENCE_DEBUG_REG: TDFI_PHY_RDLAT_F0:RW_D:0:11:=0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_MAX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_MAX 0 --&gt; Returned 8324: CADENCE_DEBUG_REG: TDFI_CTRLUPD_MAX_F0:RW:0:21:=0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE0 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE0 0 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE0_F0:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE1 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE1 0 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE1_F0:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE2 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE2 0 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE2_F0:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE3 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE3 0 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE3_F0:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_RESP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_RESP 0 --&gt; Returned 12486: CADENCE_DEBUG_REG: TDFI_PHYUPD_RESP_F0:RW:0:23:=0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_INTERVAL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_INTERVAL 0 --&gt; Returned 83240: CADENCE_DEBUG_REG: TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRL_DELAY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRL_DELAY 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_CTRL_DELAY_F0:RW_D:0:4:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRDATA 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRDATA 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_PHY_WRDATA_F0:RW:8:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDCSLAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDCSLAT 0 --&gt; Returned 21: CADENCE_DEBUG_REG: TDFI_RDCSLAT_F0:RW:16:11:=0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDDATA_EN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDDATA_EN 0 --&gt; Returned 22: CADENCE_DEBUG_REG: TDFI_RDDATA_EN_F0:RW:0:11:=0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WRCSLAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WRCSLAT 0 --&gt; Returned 16: CADENCE_DEBUG_REG: TDFI_WRCSLAT_F0:RW:16:11:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRLAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Initial wrlat_adj=17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: New wrlat_adj=18 (lp4 4:1)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRLAT 0 --&gt; Returned 18: CADENCE_DEBUG_REG: TDFI_PHY_WRLAT_F0:RW:0:11:=0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLMSG_RESP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLMSG_RESP 0 --&gt; Returned 32: CADENCE_DEBUG_REG: TDFI_CTRLMSG_RESP_F0:RW:16:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_RDLAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT: cas_latency = 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: mem_delay = 3.5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Base phy_internal_delay: 7. TDFI_PHY_WRDATA = 2, TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">1: phy_internal_delay-&gt; 8: TDFI_PHY_WRDATA = 2 TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">2: phy_internal_delay-&gt; 12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=17: delay_adder=0 phy_internal_delay=12 ie_delay_adder=0 lpddr_adder=4 dfi_adder=0 rd_preamble_len=1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=41: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=75: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT 1 --&gt; Returned 75: CADENCE_DEBUG_REG: TDFI_PHY_RDLAT_F1:RW_D:0:11:=0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_MAX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_MAX 1 --&gt; Returned 8324: CADENCE_DEBUG_REG: TDFI_CTRLUPD_MAX_F1:RW:0:21:=0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE0 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE0 1 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE0_F1:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE1 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE1 1 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE1_F1:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE2 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE2 1 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE2_F1:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE3 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE3 1 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE3_F1:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_RESP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_RESP 1 --&gt; Returned 12486: CADENCE_DEBUG_REG: TDFI_PHYUPD_RESP_F1:RW:0:23:=0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_INTERVAL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_INTERVAL 1 --&gt; Returned 83240: CADENCE_DEBUG_REG: TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRL_DELAY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRL_DELAY 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_CTRL_DELAY_F1:RW_D:0:4:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRDATA 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRDATA 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_PHY_WRDATA_F1:RW:8:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDCSLAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDCSLAT 1 --&gt; Returned 21: CADENCE_DEBUG_REG: TDFI_RDCSLAT_F1:RW:16:11:=0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDDATA_EN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDDATA_EN 1 --&gt; Returned 22: CADENCE_DEBUG_REG: TDFI_RDDATA_EN_F1:RW:0:11:=0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WRCSLAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WRCSLAT 1 --&gt; Returned 16: CADENCE_DEBUG_REG: TDFI_WRCSLAT_F1:RW:16:11:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRLAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Initial wrlat_adj=17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: New wrlat_adj=18 (lp4 4:1)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRLAT 1 --&gt; Returned 18: CADENCE_DEBUG_REG: TDFI_PHY_WRLAT_F1:RW:0:11:=0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLMSG_RESP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLMSG_RESP 1 --&gt; Returned 32: CADENCE_DEBUG_REG: TDFI_CTRLMSG_RESP_F1:RW:16:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_RDLAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT: cas_latency = 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: mem_delay = 3.5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Base phy_internal_delay: 7. TDFI_PHY_WRDATA = 2, TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">1: phy_internal_delay-&gt; 8: TDFI_PHY_WRDATA = 2 TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">2: phy_internal_delay-&gt; 12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=17: delay_adder=0 phy_internal_delay=12 ie_delay_adder=0 lpddr_adder=4 dfi_adder=0 rd_preamble_len=1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=41: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=75: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT 2 --&gt; Returned 75: CADENCE_DEBUG_REG: TDFI_PHY_RDLAT_F2:RW_D:0:11:=0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_MAX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_MAX 2 --&gt; Returned 8324: CADENCE_DEBUG_REG: TDFI_CTRLUPD_MAX_F2:RW:0:21:=0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE0 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE0 2 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE0_F2:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE1 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE1 2 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE1_F2:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE2 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE2 2 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE2_F2:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE3 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE3 2 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE3_F2:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_RESP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_RESP 2 --&gt; Returned 12486: CADENCE_DEBUG_REG: TDFI_PHYUPD_RESP_F2:RW:0:23:=0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_INTERVAL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_INTERVAL 2 --&gt; Returned 83240: CADENCE_DEBUG_REG: TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRL_DELAY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRL_DELAY 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_CTRL_DELAY_F2:RW_D:0:4:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRDATA 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRDATA 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_PHY_WRDATA_F2:RW:8:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDCSLAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDCSLAT 2 --&gt; Returned 21: CADENCE_DEBUG_REG: TDFI_RDCSLAT_F2:RW:16:11:=0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDDATA_EN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDDATA_EN 2 --&gt; Returned 22: CADENCE_DEBUG_REG: TDFI_RDDATA_EN_F2:RW:0:11:=0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WRCSLAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WRCSLAT 2 --&gt; Returned 16: CADENCE_DEBUG_REG: TDFI_WRCSLAT_F2:RW:16:11:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRLAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Initial wrlat_adj=17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: New wrlat_adj=18 (lp4 4:1)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRLAT 2 --&gt; Returned 18: CADENCE_DEBUG_REG: TDFI_PHY_WRLAT_F2:RW:0:11:=0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLMSG_RESP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLMSG_RESP 2 --&gt; Returned 32: CADENCE_DEBUG_REG: TDFI_CTRLMSG_RESP_F2:RW:16:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DLL_RST_DELAY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DLL_RST_DELAY --&gt; Returned 0: CADENCE_DEBUG_REG: DLL_RST_DELAY:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DLL_RST_ADJ_DLY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DLL_RST_ADJ_DLY --&gt; Returned 0: CADENCE_DEBUG_REG: DLL_RST_ADJ_DLY:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__UPDATE_ERROR_STATUS (UPDATE_ERROR_STATUS RD {} ZERO ZERO FULL CTL {{Identifies the source of any DFI MC-initiated or PHY-initiated update errors. Value of 1 indicates a timing violation of the associated timing parameter. READ-ONLY }} 26392 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DRAM_CLK_DISABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DRAM_CLK_DISABLE --&gt; Returned 0: CADENCE_DEBUG_REG: DRAM_CLK_DISABLE:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_MIN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_MIN --&gt; Returned 21: CADENCE_DEBUG_REG: TDFI_CTRLUPD_MIN:RW:8:16:=0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_DRAM_CLK_DISABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_DRAM_CLK_DISABLE --&gt; Returned 6: CADENCE_DEBUG_REG: TDFI_DRAM_CLK_DISABLE:RW:24:4:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_DRAM_CLK_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_DRAM_CLK_ENABLE --&gt; Returned 5: CADENCE_DEBUG_REG: TDFI_DRAM_CLK_ENABLE:RW:0:4:=0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PARIN_LAT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PARIN_LAT --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_PARIN_LAT:RW:8:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WRDATA_DELAY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WRDATA_DELAY --&gt; Returned 5: CADENCE_DEBUG_REG: TDFI_WRDATA_DELAY:RW:16:8:=0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__EN_1T_TIMING 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of En_2T_Timing: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DDR5_1N_Mode: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DDR51NModeList: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__EN_1T_TIMING 0 --&gt; Returned 0: CADENCE_DEBUG_REG: EN_1T_TIMING_F0:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__EN_1T_TIMING 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of En_2T_Timing: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DDR5_1N_Mode: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DDR51NModeList: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__EN_1T_TIMING 1 --&gt; Returned 0: CADENCE_DEBUG_REG: EN_1T_TIMING_F1:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__EN_1T_TIMING 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of En_2T_Timing: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DDR5_1N_Mode: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DDR51NModeList: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__EN_1T_TIMING 2 --&gt; Returned 0: CADENCE_DEBUG_REG: EN_1T_TIMING_F2:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DISABLE_MEMORY_MASKED_WRITE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of data_mask_en: Parameter value true</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DISABLE_MEMORY_MASKED_WRITE --&gt; Returned 0: CADENCE_DEBUG_REG: DISABLE_MEMORY_MASKED_WRITE:RW_D:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_PHASE_2N" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_PHASE_2N --&gt; Returned 0: CADENCE_DEBUG_REG: CS_PHASE_2N:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__STRATEGY_2TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__BANK_ACTIVATE_2TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__PRE_2TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__STRATEGY_4TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__BANK_ACTIVATE_4TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__PRE_4TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_2X4_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_2X4_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_NXN_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_NXN_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__ODT_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__ODT_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRAS_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRAS_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRP_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRP_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TWR_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TWR_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_4X2_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_4X2_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRFC_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRFC_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__RL_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__RL_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WL_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WL_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMRD_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMRD_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TO_MRW_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TO_MRW_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TAAD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tAAD}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tAAD: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TAAD --&gt; Returned 8: CADENCE_DEBUG_REG: TAAD:RW:24:8:=0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ACT1_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ACT1_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: ACT1_ENABLE:RD:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__ACT1_EARLY will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NWR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NWR 0 --&gt; Returned 20: CADENCE_DEBUG_REG: NWR_F0:RW:16:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NWR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NWR 1 --&gt; Returned 20: CADENCE_DEBUG_REG: NWR_F1:RW:24:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NWR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NWR 2 --&gt; Returned 20: CADENCE_DEBUG_REG: NWR_F2:RW:0:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_PARITY_ERROR_INJECT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_PARITY_ERROR_INJECT --&gt; Returned 0: CADENCE_DEBUG_REG: CA_PARITY_ERROR_INJECT:RW:0:36:=0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD_PAR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD_PAR 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TMRD_PAR_F0:RW:8:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD_PAR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD_PAR 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TMRD_PAR_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD_PAR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD_PAR 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TMRD_PAR_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrw tmrw_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrw: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD 0 --&gt; Returned 11: CADENCE_DEBUG_REG: TMRD_F0:RW:0:16:=0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrw tmrw_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrw: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD 1 --&gt; Returned 11: CADENCE_DEBUG_REG: TMRD_F1:RW:16:16:=0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrw tmrw_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrw: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD 2 --&gt; Returned 11: CADENCE_DEBUG_REG: TMRD_F2:RW:0:16:=0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_RESULT (BIST_RESULT RD {} ZERO ZERO FULL CTL {{BIST operation status (pass/fail). Indicates data check status. Value of 1 is a passing result. READ-ONLY }} 26960 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_RD_FIFO_RESYNC_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_RD_FIFO_RESYNC_EN --&gt; Returned 0: CADENCE_DEBUG_REG: DFI_RD_FIFO_RESYNC_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_ADDRESS_RANGE_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_ALL_STROBES_USED_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_FIFO_TYPE_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_FIXED_PORT_PRIORITY_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_R_PRIORITY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_W_PRIORITY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_0 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_0 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_0 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_1 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_1 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_1 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_2 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_2 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_2 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_3 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_3 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_3 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_3 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_4 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_4 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_4 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_4 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_5 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_5 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_5 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_5 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_6 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_6 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_6 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_6 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_7 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_7 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_7 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_7 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_8 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_8 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_8 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_8 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_8 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_9 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_9 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_9 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_9 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_9 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_10 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_10 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_10 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_10 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_10 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_11 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_11 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_11 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_11 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_11 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_12 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_12 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_12 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_12 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_12 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_13 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_13 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_13 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_13 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_13 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_14 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_14 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_14 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_14 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_14 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_15 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_15 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_15 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_15 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_15 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AXI0_ADDRESS_RANGE_ENABLE : Assigning value 0x00 (idx=1) from 2/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AXI0_ALL_STROBES_USED_ENABLE : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_FIFO_TYPE_REG is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AXI0_FIXED_PORT_PRIORITY_ENABLE : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AXI0_R_PRIORITY : Assigning value 0x00 (idx=1) from 3/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AXI0_W_PRIORITY : Assigning value 0x00 (idx=1) from 5/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_SPACE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_DATA_CHECK = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_DATA_MASK = 0x000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_DATA_PATTERN = 0x000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_ECC_LANE_CHECK = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_START_ADDRESS = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_ERR_STOP = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_TEST_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_SPACE : Assigning value 0x00 (idx=1) from 0/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_DATA_CHECK : Assigning value 0x01 (idx=1) from 6/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_DATA_MASK : Assigning value 0x000000000000000000000000000000000000 (idx=1) from 349/144/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_DATA_PATTERN : Assigning value 0x000000000000000000000000000000000000000000000000000000000000000000000000 (idx=1) from 61/288/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_ECC_LANE_CHECK : Assigning value 0x01 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_START_ADDRESS : Assigning value 0x0000000000 (idx=1) from 23/38/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_ERR_STOP : Assigning value 0x0000 (idx=1) from 8/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_TEST_MODE : Assigning value 0x00 (idx=1) from 20/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_ERROR_INJECT = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_CS = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_NUM = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_VAL = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_MPC_CMD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_CS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_OPCODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_LSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_MSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NO_AUTO_MRR_INIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_INIT_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_TRAIN_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_INIT_SW_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_REGNUM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PWRUP_SREFRESH_EXIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_TRAINING_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MODEREG = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MPR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITE_MODEREG = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_MULTI_CYCLE_ENABLE_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.CA_PARITY_ERROR_INJECT is {CA_PARITY_ERROR_INJECT_0 CA_PARITY_ERROR_INJECT_1} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=1) from 0/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=4294967296) from 32/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_CS : Assigning value 0x01 (idx=1) from 36/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_NUM : Assigning value 0x0000 (idx=1) from 38/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_VAL : Assigning value 0x00 (idx=1) from 47/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_ENABLE : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_MPC_CMD : Assigning value 0x00000000 (idx=1) from 56/28/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 84/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TST : Assigning value 0x00 (idx=1) from 99/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_CS : Assigning value 0x00 (idx=1) from 100/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_OPCODE : Assigning value 0x00 (idx=1) from 103/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_LSB_REG : Assigning value 0x00 (idx=1) from 111/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_MSB_REG : Assigning value 0x00 (idx=1) from 119/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NO_AUTO_MRR_INIT : Assigning value 0x00 (idx=1) from 163/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_INIT_MODE : Assigning value 0x01 (idx=1) from 164/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_TRAIN_MODE : Assigning value 0x01 (idx=1) from 165/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_INIT_SW_MODE : Assigning value 0x00 (idx=1) from 166/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_DATA : Assigning value 0x000000 (idx=1) from 167/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_REGNUM : Assigning value 0x00 (idx=1) from 185/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PWRUP_SREFRESH_EXIT : Assigning value 0x00 (idx=1) from 193/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_TRAINING_EN : Assigning value 0x01 (idx=1) from 194/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MODEREG : Assigning value 0x000000 (idx=1) from 195/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MPR : Assigning value 0x00 (idx=1) from 213/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITE_MODEREG : Assigning value 0x00000000 (idx=1) from 217/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_0 : Assigning value 0x000000 (idx=1) from 127/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_1 : Assigning value 0x000000 (idx=1) from 145/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_MULTI_CYCLE_ENABLE_F0 : Assigning value 0x00 (idx=1) from 102/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000100000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000300000000000000000200000000000001000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_ERROR_INJECT = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_CS = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_NUM = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_VAL = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_MPC_CMD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_CS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_OPCODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_LSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_MSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NO_AUTO_MRR_INIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_INIT_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_TRAIN_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_INIT_SW_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_REGNUM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PWRUP_SREFRESH_EXIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_TRAINING_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MODEREG = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MPR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITE_MODEREG = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_MULTI_CYCLE_ENABLE_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.CA_PARITY_ERROR_INJECT is {CA_PARITY_ERROR_INJECT_0 CA_PARITY_ERROR_INJECT_1} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=1) from 0/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=4294967296) from 32/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_CS : Assigning value 0x01 (idx=1) from 36/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_NUM : Assigning value 0x0000 (idx=1) from 38/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_VAL : Assigning value 0x00 (idx=1) from 47/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_ENABLE : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_MPC_CMD : Assigning value 0x00000000 (idx=1) from 56/28/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 84/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TST : Assigning value 0x00 (idx=1) from 99/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_CS : Assigning value 0x00 (idx=1) from 100/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_OPCODE : Assigning value 0x00 (idx=1) from 103/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_LSB_REG : Assigning value 0x00 (idx=1) from 111/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_MSB_REG : Assigning value 0x00 (idx=1) from 119/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NO_AUTO_MRR_INIT : Assigning value 0x00 (idx=1) from 163/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_INIT_MODE : Assigning value 0x01 (idx=1) from 164/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_TRAIN_MODE : Assigning value 0x01 (idx=1) from 165/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_INIT_SW_MODE : Assigning value 0x00 (idx=1) from 166/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_DATA : Assigning value 0x000000 (idx=1) from 167/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_REGNUM : Assigning value 0x00 (idx=1) from 185/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PWRUP_SREFRESH_EXIT : Assigning value 0x00 (idx=1) from 193/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_TRAINING_EN : Assigning value 0x01 (idx=1) from 194/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MODEREG : Assigning value 0x000000 (idx=1) from 195/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MPR : Assigning value 0x00 (idx=1) from 213/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITE_MODEREG : Assigning value 0x00000000 (idx=1) from 217/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_0 : Assigning value 0x000000 (idx=1) from 127/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_1 : Assigning value 0x000000 (idx=1) from 145/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_MULTI_CYCLE_ENABLE_F1 : Assigning value 0x00 (idx=1) from 102/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000100000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000300000000000000000200000000000001000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_ERROR_INJECT = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_CS = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_NUM = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_VAL = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_MPC_CMD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_CS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_OPCODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_LSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_MSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NO_AUTO_MRR_INIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_INIT_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_TRAIN_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_INIT_SW_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_REGNUM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PWRUP_SREFRESH_EXIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_TRAINING_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MODEREG = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MPR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITE_MODEREG = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_MULTI_CYCLE_ENABLE_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.CA_PARITY_ERROR_INJECT is {CA_PARITY_ERROR_INJECT_0 CA_PARITY_ERROR_INJECT_1} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=1) from 0/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=4294967296) from 32/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_CS : Assigning value 0x01 (idx=1) from 36/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_NUM : Assigning value 0x0000 (idx=1) from 38/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_VAL : Assigning value 0x00 (idx=1) from 47/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_ENABLE : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_MPC_CMD : Assigning value 0x00000000 (idx=1) from 56/28/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 84/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TST : Assigning value 0x00 (idx=1) from 99/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_CS : Assigning value 0x00 (idx=1) from 100/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_OPCODE : Assigning value 0x00 (idx=1) from 103/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_LSB_REG : Assigning value 0x00 (idx=1) from 111/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_MSB_REG : Assigning value 0x00 (idx=1) from 119/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NO_AUTO_MRR_INIT : Assigning value 0x00 (idx=1) from 163/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_INIT_MODE : Assigning value 0x01 (idx=1) from 164/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_TRAIN_MODE : Assigning value 0x01 (idx=1) from 165/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_INIT_SW_MODE : Assigning value 0x00 (idx=1) from 166/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_DATA : Assigning value 0x000000 (idx=1) from 167/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_REGNUM : Assigning value 0x00 (idx=1) from 185/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PWRUP_SREFRESH_EXIT : Assigning value 0x00 (idx=1) from 193/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_TRAINING_EN : Assigning value 0x01 (idx=1) from 194/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MODEREG : Assigning value 0x000000 (idx=1) from 195/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MPR : Assigning value 0x00 (idx=1) from 213/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITE_MODEREG : Assigning value 0x00000000 (idx=1) from 217/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_0 : Assigning value 0x000000 (idx=1) from 127/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_1 : Assigning value 0x000000 (idx=1) from 145/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_MULTI_CYCLE_ENABLE_F2 : Assigning value 0x00 (idx=1) from 102/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000100000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000300000000000000000200000000000001000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_DISABLE_W_UC_ERR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_READ_CACHING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_TYPE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITEBACK_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITE_COMBINING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BANK_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BG_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_SAME_PAGE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key XOR_CHECK_BITS = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_LINK_ECC_EN_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_LINK_ECC_EN_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_DISABLE_W_UC_ERR : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_ENABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_READ_CACHING_EN : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_TYPE : Assigning value 0x00 (idx=1) from 6/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITEBACK_EN : Assigning value 0x00 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITE_COMBINING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BANK_OFFSET : Assigning value 0x00 (idx=1) from 9/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BG_OFFSET : Assigning value 0x00 (idx=1) from 14/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_SAME_PAGE : Assigning value 0x00 (idx=1) from 19/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_ENABLE : Assigning value 0x00 (idx=1) from 142/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_0 : Assigning value 0x000000 (idx=1) from 168/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_1 : Assigning value 0x000000 (idx=1) from 204/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_2 : Assigning value 0x000000 (idx=1) from 240/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_3 : Assigning value 0x000000 (idx=1) from 276/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_4 : Assigning value 0x000000 (idx=1) from 312/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_5 : Assigning value 0x000000 (idx=1) from 348/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_6 : Assigning value 0x000000 (idx=1) from 384/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_7 : Assigning value 0x000000 (idx=1) from 420/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_0 : Assigning value 0x000000 (idx=1) from 150/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_1 : Assigning value 0x000000 (idx=1) from 186/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_2 : Assigning value 0x000000 (idx=1) from 222/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_3 : Assigning value 0x000000 (idx=1) from 258/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_4 : Assigning value 0x000000 (idx=1) from 294/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_5 : Assigning value 0x000000 (idx=1) from 330/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_6 : Assigning value 0x000000 (idx=1) from 366/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_7 : Assigning value 0x000000 (idx=1) from 402/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.XOR_CHECK_BITS : Assigning value 0x00000000 (idx=1) from 438/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_LINK_ECC_EN_F0 : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_LINK_ECC_EN_F0 : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_DISABLE_W_UC_ERR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_READ_CACHING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_TYPE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITEBACK_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITE_COMBINING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BANK_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BG_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_SAME_PAGE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key XOR_CHECK_BITS = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_LINK_ECC_EN_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_LINK_ECC_EN_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_DISABLE_W_UC_ERR : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_ENABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_READ_CACHING_EN : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_TYPE : Assigning value 0x00 (idx=1) from 6/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITEBACK_EN : Assigning value 0x00 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITE_COMBINING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BANK_OFFSET : Assigning value 0x00 (idx=1) from 9/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BG_OFFSET : Assigning value 0x00 (idx=1) from 14/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_SAME_PAGE : Assigning value 0x00 (idx=1) from 19/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_ENABLE : Assigning value 0x00 (idx=1) from 142/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_0 : Assigning value 0x000000 (idx=1) from 168/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_1 : Assigning value 0x000000 (idx=1) from 204/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_2 : Assigning value 0x000000 (idx=1) from 240/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_3 : Assigning value 0x000000 (idx=1) from 276/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_4 : Assigning value 0x000000 (idx=1) from 312/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_5 : Assigning value 0x000000 (idx=1) from 348/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_6 : Assigning value 0x000000 (idx=1) from 384/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_7 : Assigning value 0x000000 (idx=1) from 420/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_0 : Assigning value 0x000000 (idx=1) from 150/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_1 : Assigning value 0x000000 (idx=1) from 186/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_2 : Assigning value 0x000000 (idx=1) from 222/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_3 : Assigning value 0x000000 (idx=1) from 258/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_4 : Assigning value 0x000000 (idx=1) from 294/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_5 : Assigning value 0x000000 (idx=1) from 330/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_6 : Assigning value 0x000000 (idx=1) from 366/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_7 : Assigning value 0x000000 (idx=1) from 402/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.XOR_CHECK_BITS : Assigning value 0x00000000 (idx=1) from 438/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_LINK_ECC_EN_F1 : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_LINK_ECC_EN_F1 : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_DISABLE_W_UC_ERR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_READ_CACHING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_TYPE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITEBACK_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITE_COMBINING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BANK_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BG_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_SAME_PAGE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key XOR_CHECK_BITS = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_LINK_ECC_EN_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_LINK_ECC_EN_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_DISABLE_W_UC_ERR : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_ENABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_READ_CACHING_EN : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_TYPE : Assigning value 0x00 (idx=1) from 6/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITEBACK_EN : Assigning value 0x00 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITE_COMBINING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BANK_OFFSET : Assigning value 0x00 (idx=1) from 9/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BG_OFFSET : Assigning value 0x00 (idx=1) from 14/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_SAME_PAGE : Assigning value 0x00 (idx=1) from 19/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_ENABLE : Assigning value 0x00 (idx=1) from 142/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_0 : Assigning value 0x000000 (idx=1) from 168/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_1 : Assigning value 0x000000 (idx=1) from 204/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_2 : Assigning value 0x000000 (idx=1) from 240/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_3 : Assigning value 0x000000 (idx=1) from 276/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_4 : Assigning value 0x000000 (idx=1) from 312/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_5 : Assigning value 0x000000 (idx=1) from 348/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_6 : Assigning value 0x000000 (idx=1) from 384/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_7 : Assigning value 0x000000 (idx=1) from 420/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_0 : Assigning value 0x000000 (idx=1) from 150/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_1 : Assigning value 0x000000 (idx=1) from 186/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_2 : Assigning value 0x000000 (idx=1) from 222/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_3 : Assigning value 0x000000 (idx=1) from 258/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_4 : Assigning value 0x000000 (idx=1) from 294/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_5 : Assigning value 0x000000 (idx=1) from 330/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_6 : Assigning value 0x000000 (idx=1) from 366/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_7 : Assigning value 0x000000 (idx=1) from 402/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.XOR_CHECK_BITS : Assigning value 0x00000000 (idx=1) from 438/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_LINK_ECC_EN_F2 : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_LINK_ECC_EN_F2 : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKE_DELAY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_BOOT_STATE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_CHANGE_STATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DRAM_CLK_DISABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FUNC_VALID_CYCLES = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI_VERSION_4P0V1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_TRAIN_AFTER_INIT_COMPLETE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MIN = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_DISABLE = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_ENABLE = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_LP_RESP = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PARIN_LAT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRDATA_DELAY = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFIBUS_FREQ_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_RATIO_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLMSG_RESP_F0 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_INTERVAL_F0 = 0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MAX_F0 = 0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRL_DELAY_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_COMPLETE_F0 = 0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_START_F0 = 0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_F0 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE0_F0 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE1_F0 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE2_F0 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE3_F0 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_RESP_F0 = 0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_RESP_F0 = 0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE0_F0 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE1_F0 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE2_F0 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE3_F0 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_RDLAT_F0 = 0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRDATA_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRLAT_F0 = 0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDCSLAT_F0 = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDDATA_EN_F0 = 0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_DIS_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_FS_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_RD_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_WR_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_FAST_TOGGLE_F0 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_TOGGLE_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRCSLAT_F0 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKE_DELAY : Assigning value 0x00 (idx=1) from 569/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_BOOT_STATE : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_CHANGE_STATE : Assigning value 0x01 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DRAM_CLK_DISABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FUNC_VALID_CYCLES : Assigning value 0x02 (idx=1) from 572/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI_VERSION_4P0V1 : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_TRAIN_AFTER_INIT_COMPLETE : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MIN : Assigning value 0x0015 (idx=1) from 576/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_DISABLE : Assigning value 0x06 (idx=1) from 70/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_ENABLE : Assigning value 0x05 (idx=1) from 74/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_LP_RESP : Assigning value 0x10 (idx=1) from 126/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PARIN_LAT : Assigning value 0x00 (idx=1) from 131/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRDATA_DELAY : Assigning value 0x05 (idx=1) from 561/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFIBUS_FREQ_F0 : Assigning value 0x00 (idx=1) from 595/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_RATIO_F0 : Assigning value 0x02 (idx=1) from 593/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLMSG_RESP_F0 : Assigning value 0x20 (idx=1) from 6/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_INTERVAL_F0 : Assigning value 0x00014528 (idx=1) from 13/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MAX_F0 : Assigning value 0x002084 (idx=1) from 45/21/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRL_DELAY_F0 : Assigning value 0x02 (idx=1) from 66/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_COMPLETE_F0 : Assigning value 0x001000 (idx=1) from 78/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_START_F0 : Assigning value 0x000200 (idx=1) from 102/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_F0 : Assigning value 0x00041080 (idx=1) from 134/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE0_F0 : Assigning value 0x00041080 (idx=1) from 166/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE1_F0 : Assigning value 0x00041080 (idx=1) from 198/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE2_F0 : Assigning value 0x00041080 (idx=1) from 230/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE3_F0 : Assigning value 0x00041080 (idx=1) from 262/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_RESP_F0 : Assigning value 0x0071ce (idx=1) from 294/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_RESP_F0 : Assigning value 0x0030c6 (idx=1) from 314/23/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE0_F0 : Assigning value 0x00000200 (idx=1) from 337/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE1_F0 : Assigning value 0x00000200 (idx=1) from 369/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE2_F0 : Assigning value 0x00000200 (idx=1) from 401/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE3_F0 : Assigning value 0x00000200 (idx=1) from 433/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_RDLAT_F0 : Assigning value 0x004b (idx=1) from 465/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRDATA_F0 : Assigning value 0x02 (idx=1) from 476/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRLAT_F0 : Assigning value 0x0012 (idx=1) from 479/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDCSLAT_F0 : Assigning value 0x0015 (idx=1) from 490/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDDATA_EN_F0 : Assigning value 0x0016 (idx=1) from 501/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_DIS_F0 : Assigning value 0x00 (idx=1) from 512/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_FS_F0 : Assigning value 0x00 (idx=1) from 518/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_RD_F0 : Assigning value 0x00 (idx=1) from 525/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_WR_F0 : Assigning value 0x00 (idx=1) from 532/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_FAST_TOGGLE_F0 : Assigning value 0x04 (idx=1) from 539/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_TOGGLE_F0 : Assigning value 0x00 (idx=1) from 543/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRCSLAT_F0 : Assigning value 0x0010 (idx=1) from 550/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000010x0000000000010101001000000000101000000100000000000010000000000000000000000000000000000010110000000101010000001001001000001001011000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000001100001100011000000111000111001110000000000000010000010000100000000000000000000100000100001000000000000000000001000001000010000000000000000000010000010000100000000000000000000100000100001000000000010000000000000000001000000000000000000001000000000000010101100010000000010000010000100000000000000000101000101001010000100000000010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040015200a04002000000002c0540920960000040000000400000004000000040000c3181c7380010420000104200001042000010420000104200400008000040015880410800028a50802</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKE_DELAY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_BOOT_STATE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_CHANGE_STATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DRAM_CLK_DISABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FUNC_VALID_CYCLES = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI_VERSION_4P0V1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_TRAIN_AFTER_INIT_COMPLETE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MIN = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_DISABLE = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_ENABLE = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_LP_RESP = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PARIN_LAT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRDATA_DELAY = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFIBUS_FREQ_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_RATIO_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLMSG_RESP_F1 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_INTERVAL_F1 = 0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MAX_F1 = 0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRL_DELAY_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_COMPLETE_F1 = 0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_START_F1 = 0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_F1 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE0_F1 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE1_F1 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE2_F1 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE3_F1 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_RESP_F1 = 0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_RESP_F1 = 0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE0_F1 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE1_F1 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE2_F1 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE3_F1 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_RDLAT_F1 = 0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRDATA_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRLAT_F1 = 0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDCSLAT_F1 = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDDATA_EN_F1 = 0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_DIS_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_FS_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_RD_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_WR_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_FAST_TOGGLE_F1 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_TOGGLE_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRCSLAT_F1 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKE_DELAY : Assigning value 0x00 (idx=1) from 569/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_BOOT_STATE : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_CHANGE_STATE : Assigning value 0x01 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DRAM_CLK_DISABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FUNC_VALID_CYCLES : Assigning value 0x02 (idx=1) from 572/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI_VERSION_4P0V1 : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_TRAIN_AFTER_INIT_COMPLETE : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MIN : Assigning value 0x0015 (idx=1) from 576/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_DISABLE : Assigning value 0x06 (idx=1) from 70/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_ENABLE : Assigning value 0x05 (idx=1) from 74/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_LP_RESP : Assigning value 0x10 (idx=1) from 126/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PARIN_LAT : Assigning value 0x00 (idx=1) from 131/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRDATA_DELAY : Assigning value 0x05 (idx=1) from 561/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFIBUS_FREQ_F1 : Assigning value 0x01 (idx=1) from 595/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_RATIO_F1 : Assigning value 0x02 (idx=1) from 593/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLMSG_RESP_F1 : Assigning value 0x20 (idx=1) from 6/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_INTERVAL_F1 : Assigning value 0x00014528 (idx=1) from 13/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MAX_F1 : Assigning value 0x002084 (idx=1) from 45/21/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRL_DELAY_F1 : Assigning value 0x02 (idx=1) from 66/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_COMPLETE_F1 : Assigning value 0x001000 (idx=1) from 78/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_START_F1 : Assigning value 0x000200 (idx=1) from 102/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_F1 : Assigning value 0x00041080 (idx=1) from 134/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE0_F1 : Assigning value 0x00041080 (idx=1) from 166/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE1_F1 : Assigning value 0x00041080 (idx=1) from 198/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE2_F1 : Assigning value 0x00041080 (idx=1) from 230/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE3_F1 : Assigning value 0x00041080 (idx=1) from 262/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_RESP_F1 : Assigning value 0x0071ce (idx=1) from 294/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_RESP_F1 : Assigning value 0x0030c6 (idx=1) from 314/23/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE0_F1 : Assigning value 0x00000200 (idx=1) from 337/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE1_F1 : Assigning value 0x00000200 (idx=1) from 369/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE2_F1 : Assigning value 0x00000200 (idx=1) from 401/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE3_F1 : Assigning value 0x00000200 (idx=1) from 433/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_RDLAT_F1 : Assigning value 0x004b (idx=1) from 465/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRDATA_F1 : Assigning value 0x02 (idx=1) from 476/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRLAT_F1 : Assigning value 0x0012 (idx=1) from 479/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDCSLAT_F1 : Assigning value 0x0015 (idx=1) from 490/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDDATA_EN_F1 : Assigning value 0x0016 (idx=1) from 501/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_DIS_F1 : Assigning value 0x00 (idx=1) from 512/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_FS_F1 : Assigning value 0x00 (idx=1) from 518/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_RD_F1 : Assigning value 0x00 (idx=1) from 525/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_WR_F1 : Assigning value 0x00 (idx=1) from 532/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_FAST_TOGGLE_F1 : Assigning value 0x04 (idx=1) from 539/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_TOGGLE_F1 : Assigning value 0x00 (idx=1) from 543/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRCSLAT_F1 : Assigning value 0x0010 (idx=1) from 550/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000110x0000000000010101001000000000101000000100000000000010000000000000000000000000000000000010110000000101010000001001001000001001011000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000001100001100011000000111000111001110000000000000010000010000100000000000000000000100000100001000000000000000000001000001000010000000000000000000010000010000100000000000000000000100000100001000000000010000000000000000001000000000000000000001000000000000010101100010000000010000010000100000000000000000101000101001010000100000000010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c0015200a04002000000002c0540920960000040000000400000004000000040000c3181c7380010420000104200001042000010420000104200400008000040015880410800028a50802</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKE_DELAY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_BOOT_STATE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_CHANGE_STATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DRAM_CLK_DISABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FUNC_VALID_CYCLES = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI_VERSION_4P0V1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_TRAIN_AFTER_INIT_COMPLETE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MIN = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_DISABLE = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_ENABLE = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_LP_RESP = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PARIN_LAT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRDATA_DELAY = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFIBUS_FREQ_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_RATIO_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLMSG_RESP_F2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_INTERVAL_F2 = 0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MAX_F2 = 0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRL_DELAY_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_COMPLETE_F2 = 0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_START_F2 = 0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_F2 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE0_F2 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE1_F2 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE2_F2 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE3_F2 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_RESP_F2 = 0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_RESP_F2 = 0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE0_F2 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE1_F2 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE2_F2 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE3_F2 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_RDLAT_F2 = 0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRDATA_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRLAT_F2 = 0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDCSLAT_F2 = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDDATA_EN_F2 = 0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_DIS_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_FS_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_RD_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_WR_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_FAST_TOGGLE_F2 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_TOGGLE_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRCSLAT_F2 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKE_DELAY : Assigning value 0x00 (idx=1) from 569/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_BOOT_STATE : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_CHANGE_STATE : Assigning value 0x01 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DRAM_CLK_DISABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FUNC_VALID_CYCLES : Assigning value 0x02 (idx=1) from 572/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI_VERSION_4P0V1 : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_TRAIN_AFTER_INIT_COMPLETE : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MIN : Assigning value 0x0015 (idx=1) from 576/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_DISABLE : Assigning value 0x06 (idx=1) from 70/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_ENABLE : Assigning value 0x05 (idx=1) from 74/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_LP_RESP : Assigning value 0x10 (idx=1) from 126/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PARIN_LAT : Assigning value 0x00 (idx=1) from 131/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRDATA_DELAY : Assigning value 0x05 (idx=1) from 561/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFIBUS_FREQ_F2 : Assigning value 0x02 (idx=1) from 595/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_RATIO_F2 : Assigning value 0x02 (idx=1) from 593/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLMSG_RESP_F2 : Assigning value 0x20 (idx=1) from 6/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_INTERVAL_F2 : Assigning value 0x00014528 (idx=1) from 13/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MAX_F2 : Assigning value 0x002084 (idx=1) from 45/21/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRL_DELAY_F2 : Assigning value 0x02 (idx=1) from 66/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_COMPLETE_F2 : Assigning value 0x001000 (idx=1) from 78/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_START_F2 : Assigning value 0x000200 (idx=1) from 102/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_F2 : Assigning value 0x00041080 (idx=1) from 134/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE0_F2 : Assigning value 0x00041080 (idx=1) from 166/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE1_F2 : Assigning value 0x00041080 (idx=1) from 198/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE2_F2 : Assigning value 0x00041080 (idx=1) from 230/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE3_F2 : Assigning value 0x00041080 (idx=1) from 262/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_RESP_F2 : Assigning value 0x0071ce (idx=1) from 294/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_RESP_F2 : Assigning value 0x0030c6 (idx=1) from 314/23/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE0_F2 : Assigning value 0x00000200 (idx=1) from 337/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE1_F2 : Assigning value 0x00000200 (idx=1) from 369/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE2_F2 : Assigning value 0x00000200 (idx=1) from 401/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE3_F2 : Assigning value 0x00000200 (idx=1) from 433/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_RDLAT_F2 : Assigning value 0x004b (idx=1) from 465/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRDATA_F2 : Assigning value 0x02 (idx=1) from 476/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRLAT_F2 : Assigning value 0x0012 (idx=1) from 479/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDCSLAT_F2 : Assigning value 0x0015 (idx=1) from 490/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDDATA_EN_F2 : Assigning value 0x0016 (idx=1) from 501/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_DIS_F2 : Assigning value 0x00 (idx=1) from 512/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_FS_F2 : Assigning value 0x00 (idx=1) from 518/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_RD_F2 : Assigning value 0x00 (idx=1) from 525/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_WR_F2 : Assigning value 0x00 (idx=1) from 532/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_FAST_TOGGLE_F2 : Assigning value 0x04 (idx=1) from 539/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_TOGGLE_F2 : Assigning value 0x00 (idx=1) from 543/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRCSLAT_F2 : Assigning value 0x0010 (idx=1) from 550/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0001010x0000000000010101001000000000101000000100000000000010000000000000000000000000000000000010110000000101010000001001001000001001011000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000001100001100011000000111000111001110000000000000010000010000100000000000000000000100000100001000000000000000000001000001000010000000000000000000010000010000100000000000000000000100000100001000000000010000000000000000001000000000000000000001000000000000010101100010000000010000010000100000000000000000101000101001010000100000000010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000140015200a04002000000002c0540920960000040000000400000004000000040000c3181c7380010420000104200001042000010420000104200400008000040015880410800028a50802</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_REQ_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_EN = 0x2d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_EN = 0x2f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_IDLE_WAKEUP_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_WAKEUP_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_WAKEUP_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_WAKEUP_F0 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_IDLE_WAKEUP_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_PD_WAKEUP_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_WAKEUP_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_SHORT_WAKEUP_F0 = 0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_WAKEUP_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_SHORT_WAKEUP_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_WAKEUP_F0 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_REQ_EN : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 49/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_EN : Assigning value 0x2d (idx=1) from 1/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 37/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 25/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_EN : Assigning value 0x2f (idx=1) from 7/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 13/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_IDLE_WAKEUP_F0 : Assigning value 0x00 (idx=1) from 61/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 : Assigning value 0x0a (idx=1) from 67/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_WAKEUP_F0 : Assigning value 0x09 (idx=1) from 73/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F0 : Assigning value 0x0a (idx=1) from 79/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_WAKEUP_F0 : Assigning value 0x09 (idx=1) from 85/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_WAKEUP_F0 : Assigning value 0x0e (idx=1) from 91/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_IDLE_WAKEUP_F0 : Assigning value 0x00 (idx=1) from 97/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_PD_WAKEUP_F0 : Assigning value 0x01 (idx=1) from 103/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 : Assigning value 0x0a (idx=1) from 109/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_WAKEUP_F0 : Assigning value 0x09 (idx=1) from 115/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_SHORT_WAKEUP_F0 : Assigning value 0x07 (idx=1) from 121/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0 : Assigning value 0x0a (idx=1) from 127/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_WAKEUP_F0 : Assigning value 0x09 (idx=1) from 133/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_SHORT_WAKEUP_F0 : Assigning value 0x00 (idx=1) from 139/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_WAKEUP_F0 : Assigning value 0x0e (idx=1) from 145/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0011100000000010010010100001110010010010100000010000000011100010010010100010010010100000000000000000110000000001000000000000110000000001001011111011010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c01250e4940807125125000060080060097da</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_REQ_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_EN = 0x2d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_EN = 0x2f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_IDLE_WAKEUP_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_WAKEUP_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_WAKEUP_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_WAKEUP_F1 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_IDLE_WAKEUP_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_PD_WAKEUP_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_WAKEUP_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_SHORT_WAKEUP_F1 = 0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_WAKEUP_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_SHORT_WAKEUP_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_WAKEUP_F1 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_REQ_EN : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 49/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_EN : Assigning value 0x2d (idx=1) from 1/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 37/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 25/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_EN : Assigning value 0x2f (idx=1) from 7/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 13/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_IDLE_WAKEUP_F1 : Assigning value 0x00 (idx=1) from 61/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 : Assigning value 0x0a (idx=1) from 67/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_WAKEUP_F1 : Assigning value 0x09 (idx=1) from 73/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F1 : Assigning value 0x0a (idx=1) from 79/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_WAKEUP_F1 : Assigning value 0x09 (idx=1) from 85/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_WAKEUP_F1 : Assigning value 0x0e (idx=1) from 91/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_IDLE_WAKEUP_F1 : Assigning value 0x00 (idx=1) from 97/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_PD_WAKEUP_F1 : Assigning value 0x01 (idx=1) from 103/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 : Assigning value 0x0a (idx=1) from 109/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_WAKEUP_F1 : Assigning value 0x09 (idx=1) from 115/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_SHORT_WAKEUP_F1 : Assigning value 0x07 (idx=1) from 121/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1 : Assigning value 0x0a (idx=1) from 127/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_WAKEUP_F1 : Assigning value 0x09 (idx=1) from 133/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_SHORT_WAKEUP_F1 : Assigning value 0x00 (idx=1) from 139/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_WAKEUP_F1 : Assigning value 0x0e (idx=1) from 145/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0011100000000010010010100001110010010010100000010000000011100010010010100010010010100000000000000000110000000001000000000000110000000001001011111011010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c01250e4940807125125000060080060097da</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_REQ_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_EN = 0x2d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_EN = 0x2f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_IDLE_WAKEUP_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_WAKEUP_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_WAKEUP_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_WAKEUP_F2 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_IDLE_WAKEUP_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_PD_WAKEUP_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_WAKEUP_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_SHORT_WAKEUP_F2 = 0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_WAKEUP_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_SHORT_WAKEUP_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_WAKEUP_F2 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_REQ_EN : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 49/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_EN : Assigning value 0x2d (idx=1) from 1/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 37/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 25/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_EN : Assigning value 0x2f (idx=1) from 7/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 13/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_IDLE_WAKEUP_F2 : Assigning value 0x00 (idx=1) from 61/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 : Assigning value 0x0a (idx=1) from 67/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_WAKEUP_F2 : Assigning value 0x09 (idx=1) from 73/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F2 : Assigning value 0x0a (idx=1) from 79/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_WAKEUP_F2 : Assigning value 0x09 (idx=1) from 85/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_WAKEUP_F2 : Assigning value 0x0e (idx=1) from 91/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_IDLE_WAKEUP_F2 : Assigning value 0x00 (idx=1) from 97/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_PD_WAKEUP_F2 : Assigning value 0x01 (idx=1) from 103/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 : Assigning value 0x0a (idx=1) from 109/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_WAKEUP_F2 : Assigning value 0x09 (idx=1) from 115/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_SHORT_WAKEUP_F2 : Assigning value 0x07 (idx=1) from 121/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2 : Assigning value 0x0a (idx=1) from 127/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_WAKEUP_F2 : Assigning value 0x09 (idx=1) from 133/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_SHORT_WAKEUP_F2 : Assigning value 0x00 (idx=1) from 139/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_WAKEUP_F2 : Assigning value 0x0e (idx=1) from 145/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0011100000000010010010100001110010010010100000010000000011100010010010100010010010100000000000000000110000000001000000000000110000000001001011111011010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c01250e4940807125125000060080060097da</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TSREF2PHYMSTR = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TSREF2PHYMSTR : Assigning value 0x10 (idx=1) from 0/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx010000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ENABLE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FREQ = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FSP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DVFSQ_MODE_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FREQ_CHANGE_TYPE_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_DFS_WAIT_TIME_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ENABLE : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_0 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_1 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_2 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_0 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_1 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_2 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FREQ : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FSP : Assigning value 0x00 (idx=1) from 3/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DVFSQ_MODE_F0 : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FREQ_CHANGE_TYPE_F0 : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_DFS_WAIT_TIME_F0 : Assigning value 0x0000 (idx=1) from 11/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000000000101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ENABLE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FREQ = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FSP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DVFSQ_MODE_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FREQ_CHANGE_TYPE_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_DFS_WAIT_TIME_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ENABLE : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_0 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_1 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_2 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_0 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_1 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_2 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FREQ : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FSP : Assigning value 0x00 (idx=1) from 3/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DVFSQ_MODE_F1 : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FREQ_CHANGE_TYPE_F1 : Assigning value 0x01 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_DFS_WAIT_TIME_F1 : Assigning value 0x0000 (idx=1) from 11/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000001000101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000045</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ENABLE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FREQ = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FSP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DVFSQ_MODE_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FREQ_CHANGE_TYPE_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_DFS_WAIT_TIME_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ENABLE : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_0 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_1 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_2 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_0 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_1 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_2 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FREQ : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FSP : Assigning value 0x00 (idx=1) from 3/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DVFSQ_MODE_F2 : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FREQ_CHANGE_TYPE_F2 : Assigning value 0x02 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_DFS_WAIT_TIME_F2 : Assigning value 0x0000 (idx=1) from 11/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000010000101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000085</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_IDLE_CNT = 0x0064</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_INTERVAL = 0x03e8</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_LEN = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_START_ADDR = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_END_ADDR = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_IDLE_CNT : Assigning value 0x0064 (idx=1) from 96/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_INTERVAL : Assigning value 0x03e8 (idx=1) from 112/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_LEN : Assigning value 0x0010 (idx=1) from 128/13/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_MODE : Assigning value 0x00 (idx=1) from 141/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_START_ADDR : Assigning value 0x0000000000 (idx=1) from 20/38/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_END_ADDR : Assigning value 0x0000000000 (idx=1) from 58/38/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000010000000000111110100000000000011001000000000000000000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxxxxxx;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001003e80064000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_BIST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_DFI = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_DIMM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_ECC = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_FREQ = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_INIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_LOWPOWER = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_MASTER = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_MISC = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_PARITY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_TIMEOUT = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_TRAINING = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_USERIF = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_BIST : Assigning value 0x00 (idx=1) from 192/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_DFI : Assigning value 0x00 (idx=1) from 200/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_DIMM : Assigning value 0x00 (idx=1) from 208/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_ECC : Assigning value 0x00000000 (idx=1) from 64/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_FREQ : Assigning value 0x00 (idx=1) from 216/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_INIT : Assigning value 0x00 (idx=1) from 224/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_LOWPOWER : Assigning value 0x0000 (idx=1) from 96/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_MASTER : Assigning value 0x00000000 (idx=1) from 0/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_MISC : Assigning value 0x0000 (idx=1) from 176/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_MODE : Assigning value 0x00 (idx=1) from 232/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_PARITY : Assigning value 0x00 (idx=1) from 240/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_TIMEOUT : Assigning value 0x00000000 (idx=1) from 32/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_TRAINING : Assigning value 0x00000000 (idx=1) from 112/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_USERIF : Assigning value 0x00000000 (idx=1) from 144/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LOWPOWER_REFRESH_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_SR_CTRLUPD_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_SR_PHYMSTR_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_SR_PHYUPD_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_SR_ZQ_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_ENTRY_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_EXIT_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_MEM_GATE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_PD_IDLE = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_SR_LONG_IDLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_SR_LONG_MC_GATE_IDLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_SR_SHORT_IDLE = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LOWPOWER_REFRESH_ENABLE : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_SR_CTRLUPD_EN : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_SR_PHYMSTR_EN : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_SR_PHYUPD_EN : Assigning value 0x00 (idx=1) from 2/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_SR_ZQ_EN : Assigning value 0x00 (idx=1) from 3/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_ENTRY_EN : Assigning value 0x00 (idx=1) from 6/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_EXIT_EN : Assigning value 0x00 (idx=1) from 10/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_MEM_GATE_EN : Assigning value 0x00 (idx=1) from 14/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_PD_IDLE : Assigning value 0x0000 (idx=1) from 17/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_SR_LONG_IDLE : Assigning value 0x00 (idx=1) from 29/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_SR_LONG_MC_GATE_IDLE : Assigning value 0x00 (idx=1) from 37/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_SR_SHORT_IDLE : Assigning value 0x0000 (idx=1) from 45/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000000000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_HIGH_THRESHOLD = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_NORM_THRESHOLD = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_HIGH_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_NORM_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TIMEOUT = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LONG_COUNT_MASK = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CWW_SW_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key HW_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPRR_SW_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_HIGH_THRESHOLD_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_NORM_THRESHOLD_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_TIMEOUT_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_HIGH_THRESHOLD_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_NORM_THRESHOLD_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_TIMEOUT_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRW_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_HIGH_THRESHOLD_F0 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_NORM_THRESHOLD_F0 = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_TIMEOUT_F0 = 0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_HIGH_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_TIMEOUT_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_HIGH_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_NORM_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_TIMEOUT_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_HIGH_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_NORM_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_TIMEOUT_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_HIGH_THRESHOLD : Assigning value 0x15 (idx=1) from 5/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_NORM_THRESHOLD : Assigning value 0x14 (idx=1) from 0/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_HIGH_THRESHOLD : Assigning value 0x00000000 (idx=1) from 42/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_NORM_THRESHOLD : Assigning value 0x00000000 (idx=1) from 10/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 458/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TIMEOUT : Assigning value 0x00000000 (idx=1) from 74/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LONG_COUNT_MASK : Assigning value 0x00 (idx=1) from 666/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 522/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CWW_SW_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 426/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 442/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.HW_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 490/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 506/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPRR_SW_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 554/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 570/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_HIGH_THRESHOLD_F0 : Assigning value 0x000000 (idx=1) from 130/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_NORM_THRESHOLD_F0 : Assigning value 0x000000 (idx=1) from 106/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_TIMEOUT_F0 : Assigning value 0x000000 (idx=1) from 154/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_HIGH_THRESHOLD_F0 : Assigning value 0x000000 (idx=1) from 202/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_NORM_THRESHOLD_F0 : Assigning value 0x000000 (idx=1) from 178/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_TIMEOUT_F0 : Assigning value 0x000000 (idx=1) from 226/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRW_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 586/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 602/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_HIGH_THRESHOLD_F0 : Assigning value 0x0004 (idx=1) from 266/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_NORM_THRESHOLD_F0 : Assigning value 0x0003 (idx=1) from 250/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0 : Assigning value 0x0004 (idx=1) from 618/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_TIMEOUT_F0 : Assigning value 0x0005 (idx=1) from 282/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 634/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_HIGH_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 298/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_TIMEOUT_F0 : Assigning value 0x0000 (idx=1) from 314/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_HIGH_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 346/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_NORM_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 330/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_TIMEOUT_F0 : Assigning value 0x0000 (idx=1) from 362/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_HIGH_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 394/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_NORM_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 378/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_TIMEOUT_F0 : Assigning value 0x0000 (idx=1) from 410/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 650/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000010000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010110100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000140010000c000000000000000000000000000000000000000000000000000000000002b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_HIGH_THRESHOLD = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_NORM_THRESHOLD = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_HIGH_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_NORM_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TIMEOUT = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LONG_COUNT_MASK = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CWW_SW_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key HW_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPRR_SW_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_HIGH_THRESHOLD_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_NORM_THRESHOLD_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_TIMEOUT_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_HIGH_THRESHOLD_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_NORM_THRESHOLD_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_TIMEOUT_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRW_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_HIGH_THRESHOLD_F1 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_NORM_THRESHOLD_F1 = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_TIMEOUT_F1 = 0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_HIGH_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_TIMEOUT_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_HIGH_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_NORM_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_TIMEOUT_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_HIGH_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_NORM_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_TIMEOUT_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_HIGH_THRESHOLD : Assigning value 0x15 (idx=1) from 5/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_NORM_THRESHOLD : Assigning value 0x14 (idx=1) from 0/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_HIGH_THRESHOLD : Assigning value 0x00000000 (idx=1) from 42/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_NORM_THRESHOLD : Assigning value 0x00000000 (idx=1) from 10/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 458/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TIMEOUT : Assigning value 0x00000000 (idx=1) from 74/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LONG_COUNT_MASK : Assigning value 0x00 (idx=1) from 666/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 522/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CWW_SW_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 426/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 442/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.HW_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 490/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 506/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPRR_SW_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 554/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 570/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_HIGH_THRESHOLD_F1 : Assigning value 0x000000 (idx=1) from 130/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_NORM_THRESHOLD_F1 : Assigning value 0x000000 (idx=1) from 106/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_TIMEOUT_F1 : Assigning value 0x000000 (idx=1) from 154/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_HIGH_THRESHOLD_F1 : Assigning value 0x000000 (idx=1) from 202/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_NORM_THRESHOLD_F1 : Assigning value 0x000000 (idx=1) from 178/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_TIMEOUT_F1 : Assigning value 0x000000 (idx=1) from 226/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRW_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 586/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 602/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_HIGH_THRESHOLD_F1 : Assigning value 0x0004 (idx=1) from 266/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_NORM_THRESHOLD_F1 : Assigning value 0x0003 (idx=1) from 250/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1 : Assigning value 0x0004 (idx=1) from 618/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_TIMEOUT_F1 : Assigning value 0x0005 (idx=1) from 282/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 634/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_HIGH_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 298/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_TIMEOUT_F1 : Assigning value 0x0000 (idx=1) from 314/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_HIGH_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 346/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_NORM_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 330/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_TIMEOUT_F1 : Assigning value 0x0000 (idx=1) from 362/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_HIGH_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 394/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_NORM_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 378/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_TIMEOUT_F1 : Assigning value 0x0000 (idx=1) from 410/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 650/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000010000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010110100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000140010000c000000000000000000000000000000000000000000000000000000000002b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_HIGH_THRESHOLD = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_NORM_THRESHOLD = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_HIGH_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_NORM_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TIMEOUT = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LONG_COUNT_MASK = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CWW_SW_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key HW_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPRR_SW_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_HIGH_THRESHOLD_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_NORM_THRESHOLD_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_TIMEOUT_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_HIGH_THRESHOLD_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_NORM_THRESHOLD_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_TIMEOUT_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRW_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_HIGH_THRESHOLD_F2 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_NORM_THRESHOLD_F2 = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_TIMEOUT_F2 = 0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_HIGH_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_TIMEOUT_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_HIGH_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_NORM_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_TIMEOUT_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_HIGH_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_NORM_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_TIMEOUT_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_HIGH_THRESHOLD : Assigning value 0x15 (idx=1) from 5/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_NORM_THRESHOLD : Assigning value 0x14 (idx=1) from 0/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_HIGH_THRESHOLD : Assigning value 0x00000000 (idx=1) from 42/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_NORM_THRESHOLD : Assigning value 0x00000000 (idx=1) from 10/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 458/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TIMEOUT : Assigning value 0x00000000 (idx=1) from 74/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LONG_COUNT_MASK : Assigning value 0x00 (idx=1) from 666/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 522/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CWW_SW_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 426/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 442/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.HW_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 490/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 506/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPRR_SW_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 554/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 570/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_HIGH_THRESHOLD_F2 : Assigning value 0x000000 (idx=1) from 130/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_NORM_THRESHOLD_F2 : Assigning value 0x000000 (idx=1) from 106/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_TIMEOUT_F2 : Assigning value 0x000000 (idx=1) from 154/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_HIGH_THRESHOLD_F2 : Assigning value 0x000000 (idx=1) from 202/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_NORM_THRESHOLD_F2 : Assigning value 0x000000 (idx=1) from 178/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_TIMEOUT_F2 : Assigning value 0x000000 (idx=1) from 226/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRW_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 586/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 602/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_HIGH_THRESHOLD_F2 : Assigning value 0x0004 (idx=1) from 266/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_NORM_THRESHOLD_F2 : Assigning value 0x0003 (idx=1) from 250/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2 : Assigning value 0x0004 (idx=1) from 618/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_TIMEOUT_F2 : Assigning value 0x0005 (idx=1) from 282/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 634/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_HIGH_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 298/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_TIMEOUT_F2 : Assigning value 0x0000 (idx=1) from 314/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_HIGH_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 346/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_NORM_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 330/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_TIMEOUT_F2 : Assigning value 0x0000 (idx=1) from 362/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_HIGH_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 394/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_NORM_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 378/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_TIMEOUT_F2 : Assigning value 0x0000 (idx=1) from 410/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 650/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000010000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010110100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000140010000c000000000000000000000000000000000000000000000000000000000002b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OSC_VARIANCE_LIMIT = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRECHARGE_DLR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SRX_NOP_CMDS = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TAAD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_DLR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_CS_LOW = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_HOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_SETUP = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPRR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_INTERVAL = 0x000005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDITIVE_LAT_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CASLAT_LIN_F0 = 0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_LAT_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRE_F0 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRX_F0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NWR_F0 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_LEN_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCACSH_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCDMW_F0 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR2_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR_F0 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKCKEL_F0 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCMD_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCS_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCMD_F0 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCS_F0 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELPD_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKESR_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKE_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKSTAB_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCMDCKE_F0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCPDED_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKEH_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKE_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSH_F0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSSR_F0 = 0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDAL_F0 = 0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TESCKE_F0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_DLR_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_F0 = 0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_F0 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_PAR_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_DELAY_F0 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_F0 = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_PAR_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRRI_F0 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRWCKEL_F0 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSCO_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSC_TRK_CALC_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPDEX_F0 = 0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPPD_F0 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MAX_F0 = 0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MIN_F0 = 0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRCD_F0 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRC_F0 = 0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_F0 = 0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_DLR_F0 = 0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_F0 = 0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_DLR_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_F0 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_DLR_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_F0 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_L_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_AP_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TSR_F0 = 0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWR_F0 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_AP_F0 = 0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_F0 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_AP_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSNR_F0 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSR_F0 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCAL_F0 = 0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCKE_F0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQLAT_F0 = 0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRLAT_F0 = 0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_PREAMBLE_LEN_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F0_0 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F0_0 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F0_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F0_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F0_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F0_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F0_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F0_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F0_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F0_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F0_0 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F0_1 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F0_1 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F0_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F0_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F0_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F0_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F0_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F0_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F0_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F0_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F0_1 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OSC_VARIANCE_LIMIT : Assigning value 0x0010 (idx=1) from 43/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRECHARGE_DLR : Assigning value 0x08 (idx=1) from 59/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SRX_NOP_CMDS : Assigning value 0x05 (idx=1) from 75/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TAAD : Assigning value 0x08 (idx=1) from 79/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD : Assigning value 0x08 (idx=1) from 95/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_DLR : Assigning value 0x00 (idx=1) from 106/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_CS_LOW : Assigning value 0x04 (idx=1) from 287/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_HOLD : Assigning value 0x03 (idx=1) from 299/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_SETUP : Assigning value 0x03 (idx=1) from 913/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPRR : Assigning value 0x00 (idx=1) from 917/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRR : Assigning value 0x08 (idx=1) from 335/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD1 : Assigning value 0x00 (idx=1) from 351/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD2 : Assigning value 0x00 (idx=1) from 357/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_INTERVAL : Assigning value 0x000005 (idx=1) from 552/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 592/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDITIVE_LAT_F0 : Assigning value 0x00 (idx=1) from 0/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CASLAT_LIN_F0 : Assigning value 0x2c (idx=1) from 7/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_LAT_F0 : Assigning value 0x00 (idx=1) from 15/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRE_F0 : Assigning value 0x06 (idx=1) from 19/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRX_F0 : Assigning value 0x03 (idx=1) from 27/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NWR_F0 : Assigning value 0x14 (idx=1) from 35/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_LEN_F0 : Assigning value 0x01 (idx=1) from 67/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCACSH_F0 : Assigning value 0x02 (idx=1) from 87/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCDMW_F0 : Assigning value 0x20 (idx=1) from 100/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_F0 : Assigning value 0x00 (idx=1) from 111/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR2_F0 : Assigning value 0x00 (idx=1) from 116/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR_F0 : Assigning value 0x20 (idx=1) from 123/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKCKEL_F0 : Assigning value 0x06 (idx=1) from 130/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCMD_F0 : Assigning value 0x09 (idx=1) from 135/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCS_F0 : Assigning value 0x09 (idx=1) from 140/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCMD_F0 : Assigning value 0x06 (idx=1) from 145/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCS_F0 : Assigning value 0x06 (idx=1) from 150/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELPD_F0 : Assigning value 0x09 (idx=1) from 155/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKESR_F0 : Assigning value 0x09 (idx=1) from 163/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKE_F0 : Assigning value 0x09 (idx=1) from 171/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKSTAB_F0 : Assigning value 0x0000 (idx=1) from 179/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCMDCKE_F0 : Assigning value 0x03 (idx=1) from 195/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCPDED_F0 : Assigning value 0x00 (idx=1) from 203/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKEH_F0 : Assigning value 0x02 (idx=1) from 211/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKE_F0 : Assigning value 0x02 (idx=1) from 216/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSH_F0 : Assigning value 0x03 (idx=1) from 221/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSSR_F0 : Assigning value 0x1e (idx=1) from 229/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDAL_F0 : Assigning value 0x29 (idx=1) from 237/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TESCKE_F0 : Assigning value 0x03 (idx=1) from 245/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_DLR_F0 : Assigning value 0x0000 (idx=1) from 253/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_F0 : Assigning value 0x002b (idx=1) from 262/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_F0 : Assigning value 0x0f (idx=1) from 271/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_PAR_F0 : Assigning value 0x00 (idx=1) from 279/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_DELAY_F0 : Assigning value 0x0b (idx=1) from 291/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_F0 : Assigning value 0x000b (idx=1) from 303/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_PAR_F0 : Assigning value 0x0000 (idx=1) from 319/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRRI_F0 : Assigning value 0x17 (idx=1) from 343/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRWCKEL_F0 : Assigning value 0x0f (idx=1) from 363/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSCO_F0 : Assigning value 0x00 (idx=1) from 371/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSC_TRK_CALC_F0 : Assigning value 0x0000 (idx=1) from 379/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPDEX_F0 : Assigning value 0x0009 (idx=1) from 467/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPPD_F0 : Assigning value 0x04 (idx=1) from 483/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MAX_F0 : Assigning value 0x00d903 (idx=1) from 486/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MIN_F0 : Assigning value 0x002d (idx=1) from 506/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRCD_F0 : Assigning value 0x14 (idx=1) from 515/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRC_F0 : Assigning value 0x0041 (idx=1) from 523/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_F0 : Assigning value 0x001042 (idx=1) from 532/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_DLR_F0 : Assigning value 0x0060 (idx=1) from 572/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_F0 : Assigning value 0x00c1 (idx=1) from 582/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_DLR_F0 : Assigning value 0x0000 (idx=1) from 667/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_F0 : Assigning value 0x0000 (idx=1) from 677/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_F0 : Assigning value 0x14 (idx=1) from 743/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_DLR_F0 : Assigning value 0x00 (idx=1) from 751/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_F0 : Assigning value 0x0b (idx=1) from 759/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_L_F0 : Assigning value 0x00 (idx=1) from 767/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_AP_F0 : Assigning value 0x00 (idx=1) from 775/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_F0 : Assigning value 0x09 (idx=1) from 783/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TSR_F0 : Assigning value 0x11 (idx=1) from 791/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWR_F0 : Assigning value 0x15 (idx=1) from 799/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_AP_F0 : Assigning value 0x000c (idx=1) from 807/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_F0 : Assigning value 0x0c (idx=1) from 816/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_AP_F0 : Assigning value 0x0000 (idx=1) from 823/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_F0 : Assigning value 0x00 (idx=1) from 832/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSNR_F0 : Assigning value 0x00c9 (idx=1) from 839/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSR_F0 : Assigning value 0x00c9 (idx=1) from 855/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCAL_F0 : Assigning value 0x042c (idx=1) from 871/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCKE_F0 : Assigning value 0x03 (idx=1) from 883/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQLAT_F0 : Assigning value 0x21 (idx=1) from 891/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRLAT_F0 : Assigning value 0x12 (idx=1) from 898/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_PREAMBLE_LEN_F0 : Assigning value 0x01 (idx=1) from 905/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F0_0 : Assigning value 0x10 (idx=1) from 395/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F0_0 : Assigning value 0x0b (idx=1) from 411/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F0_0 : Assigning value 0x0000 (idx=1) from 427/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F0_0 : Assigning value 0x0061 (idx=1) from 447/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F0_0 : Assigning value 0x0000 (idx=1) from 595/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F0_0 : Assigning value 0x0061 (idx=1) from 615/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F0_0 : Assigning value 0x00 (idx=1) from 635/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F0_0 : Assigning value 0x00 (idx=1) from 651/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F0_0 : Assigning value 0x0000 (idx=1) from 687/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F0_0 : Assigning value 0x0000 (idx=1) from 707/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F0_0 : Assigning value 0x17 (idx=1) from 727/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F0_1 : Assigning value 0x10 (idx=1) from 403/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F0_1 : Assigning value 0x0b (idx=1) from 419/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F0_1 : Assigning value 0x0000 (idx=1) from 437/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F0_1 : Assigning value 0x0061 (idx=1) from 457/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F0_1 : Assigning value 0x0000 (idx=1) from 605/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F0_1 : Assigning value 0x0061 (idx=1) from 625/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F0_1 : Assigning value 0x00 (idx=1) from 643/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F0_1 : Assigning value 0x00 (idx=1) from 659/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F0_1 : Assigning value 0x0000 (idx=1) from 697/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F0_1 : Assigning value 0x0000 (idx=1) from 717/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F0_1 : Assigning value 0x17 (idx=1) from 735/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110000000100100100100001000000110100001011000000000011001001000000001100100100000000000000000001100000001100000101010001000100001001000000000000000000001011000000000001010000010111000101110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000010001100001000000000000000000000110011000001000110000000000000000000000101000000010000010000100010000010001010000010110100001101100100000011100000000000000100100011000010001100001000000000000000000000000101100001011000100000001000000000000000000000000000000001111000000000000000101110000100000000000000000000000000000001011001100001011010000000000000011110001010110000000000000001100101001000111100000001100010000100000000000000011000000000000000000001001000010010000100100110001100100101001001100100000000000000000000001000000100000000010000010000101000000010000100000000000000100000001010000000011000001100000001011000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000060249081a160064806480000c060a8884800005800a0b8b800000000000000000000000c230800003304600000501042208a0b43640e00048c2308000005858808000000078000b8400000005985a00078ac0006523c06210001800004848498c94990000020401042808400080a018301600</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OSC_VARIANCE_LIMIT = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRECHARGE_DLR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SRX_NOP_CMDS = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TAAD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_DLR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_CS_LOW = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_HOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_SETUP = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPRR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_INTERVAL = 0x000005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDITIVE_LAT_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CASLAT_LIN_F1 = 0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_LAT_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRE_F1 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRX_F1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NWR_F1 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_LEN_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCACSH_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCDMW_F1 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR2_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR_F1 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKCKEL_F1 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCMD_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCS_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCMD_F1 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCS_F1 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELPD_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKESR_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKE_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKSTAB_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCMDCKE_F1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCPDED_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKEH_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKE_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSH_F1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSSR_F1 = 0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDAL_F1 = 0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TESCKE_F1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_DLR_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_F1 = 0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_F1 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_PAR_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_DELAY_F1 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_F1 = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_PAR_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRRI_F1 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRWCKEL_F1 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSCO_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSC_TRK_CALC_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPDEX_F1 = 0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPPD_F1 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MAX_F1 = 0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MIN_F1 = 0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRCD_F1 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRC_F1 = 0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_F1 = 0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_DLR_F1 = 0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_F1 = 0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_DLR_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_F1 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_DLR_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_F1 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_L_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_AP_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TSR_F1 = 0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWR_F1 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_AP_F1 = 0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_F1 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_AP_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSNR_F1 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSR_F1 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCAL_F1 = 0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCKE_F1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQLAT_F1 = 0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRLAT_F1 = 0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_PREAMBLE_LEN_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F1_0 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F1_0 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F1_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F1_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F1_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F1_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F1_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F1_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F1_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F1_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F1_0 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F1_1 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F1_1 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F1_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F1_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F1_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F1_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F1_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F1_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F1_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F1_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F1_1 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OSC_VARIANCE_LIMIT : Assigning value 0x0010 (idx=1) from 43/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRECHARGE_DLR : Assigning value 0x08 (idx=1) from 59/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SRX_NOP_CMDS : Assigning value 0x05 (idx=1) from 75/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TAAD : Assigning value 0x08 (idx=1) from 79/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD : Assigning value 0x08 (idx=1) from 95/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_DLR : Assigning value 0x00 (idx=1) from 106/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_CS_LOW : Assigning value 0x04 (idx=1) from 287/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_HOLD : Assigning value 0x03 (idx=1) from 299/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_SETUP : Assigning value 0x03 (idx=1) from 913/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPRR : Assigning value 0x00 (idx=1) from 917/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRR : Assigning value 0x08 (idx=1) from 335/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD1 : Assigning value 0x00 (idx=1) from 351/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD2 : Assigning value 0x00 (idx=1) from 357/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_INTERVAL : Assigning value 0x000005 (idx=1) from 552/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 592/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDITIVE_LAT_F1 : Assigning value 0x00 (idx=1) from 0/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CASLAT_LIN_F1 : Assigning value 0x2c (idx=1) from 7/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_LAT_F1 : Assigning value 0x00 (idx=1) from 15/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRE_F1 : Assigning value 0x06 (idx=1) from 19/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRX_F1 : Assigning value 0x03 (idx=1) from 27/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NWR_F1 : Assigning value 0x14 (idx=1) from 35/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_LEN_F1 : Assigning value 0x01 (idx=1) from 67/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCACSH_F1 : Assigning value 0x02 (idx=1) from 87/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCDMW_F1 : Assigning value 0x20 (idx=1) from 100/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_F1 : Assigning value 0x00 (idx=1) from 111/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR2_F1 : Assigning value 0x00 (idx=1) from 116/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR_F1 : Assigning value 0x20 (idx=1) from 123/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKCKEL_F1 : Assigning value 0x06 (idx=1) from 130/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCMD_F1 : Assigning value 0x09 (idx=1) from 135/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCS_F1 : Assigning value 0x09 (idx=1) from 140/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCMD_F1 : Assigning value 0x06 (idx=1) from 145/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCS_F1 : Assigning value 0x06 (idx=1) from 150/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELPD_F1 : Assigning value 0x09 (idx=1) from 155/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKESR_F1 : Assigning value 0x09 (idx=1) from 163/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKE_F1 : Assigning value 0x09 (idx=1) from 171/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKSTAB_F1 : Assigning value 0x0000 (idx=1) from 179/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCMDCKE_F1 : Assigning value 0x03 (idx=1) from 195/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCPDED_F1 : Assigning value 0x00 (idx=1) from 203/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKEH_F1 : Assigning value 0x02 (idx=1) from 211/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKE_F1 : Assigning value 0x02 (idx=1) from 216/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSH_F1 : Assigning value 0x03 (idx=1) from 221/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSSR_F1 : Assigning value 0x1e (idx=1) from 229/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDAL_F1 : Assigning value 0x29 (idx=1) from 237/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TESCKE_F1 : Assigning value 0x03 (idx=1) from 245/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_DLR_F1 : Assigning value 0x0000 (idx=1) from 253/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_F1 : Assigning value 0x002b (idx=1) from 262/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_F1 : Assigning value 0x0f (idx=1) from 271/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_PAR_F1 : Assigning value 0x00 (idx=1) from 279/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_DELAY_F1 : Assigning value 0x0b (idx=1) from 291/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_F1 : Assigning value 0x000b (idx=1) from 303/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_PAR_F1 : Assigning value 0x0000 (idx=1) from 319/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRRI_F1 : Assigning value 0x17 (idx=1) from 343/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRWCKEL_F1 : Assigning value 0x0f (idx=1) from 363/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSCO_F1 : Assigning value 0x00 (idx=1) from 371/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSC_TRK_CALC_F1 : Assigning value 0x0000 (idx=1) from 379/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPDEX_F1 : Assigning value 0x0009 (idx=1) from 467/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPPD_F1 : Assigning value 0x04 (idx=1) from 483/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MAX_F1 : Assigning value 0x00d903 (idx=1) from 486/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MIN_F1 : Assigning value 0x002d (idx=1) from 506/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRCD_F1 : Assigning value 0x14 (idx=1) from 515/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRC_F1 : Assigning value 0x0041 (idx=1) from 523/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_F1 : Assigning value 0x001042 (idx=1) from 532/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_DLR_F1 : Assigning value 0x0060 (idx=1) from 572/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_F1 : Assigning value 0x00c1 (idx=1) from 582/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_DLR_F1 : Assigning value 0x0000 (idx=1) from 667/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_F1 : Assigning value 0x0000 (idx=1) from 677/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_F1 : Assigning value 0x14 (idx=1) from 743/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_DLR_F1 : Assigning value 0x00 (idx=1) from 751/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_F1 : Assigning value 0x0b (idx=1) from 759/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_L_F1 : Assigning value 0x00 (idx=1) from 767/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_AP_F1 : Assigning value 0x00 (idx=1) from 775/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_F1 : Assigning value 0x09 (idx=1) from 783/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TSR_F1 : Assigning value 0x11 (idx=1) from 791/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWR_F1 : Assigning value 0x15 (idx=1) from 799/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_AP_F1 : Assigning value 0x000c (idx=1) from 807/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_F1 : Assigning value 0x0c (idx=1) from 816/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_AP_F1 : Assigning value 0x0000 (idx=1) from 823/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_F1 : Assigning value 0x00 (idx=1) from 832/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSNR_F1 : Assigning value 0x00c9 (idx=1) from 839/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSR_F1 : Assigning value 0x00c9 (idx=1) from 855/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCAL_F1 : Assigning value 0x042c (idx=1) from 871/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCKE_F1 : Assigning value 0x03 (idx=1) from 883/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQLAT_F1 : Assigning value 0x21 (idx=1) from 891/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRLAT_F1 : Assigning value 0x12 (idx=1) from 898/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_PREAMBLE_LEN_F1 : Assigning value 0x01 (idx=1) from 905/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F1_0 : Assigning value 0x10 (idx=1) from 395/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F1_0 : Assigning value 0x0b (idx=1) from 411/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F1_0 : Assigning value 0x0000 (idx=1) from 427/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F1_0 : Assigning value 0x0061 (idx=1) from 447/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F1_0 : Assigning value 0x0000 (idx=1) from 595/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F1_0 : Assigning value 0x0061 (idx=1) from 615/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F1_0 : Assigning value 0x00 (idx=1) from 635/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F1_0 : Assigning value 0x00 (idx=1) from 651/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F1_0 : Assigning value 0x0000 (idx=1) from 687/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F1_0 : Assigning value 0x0000 (idx=1) from 707/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F1_0 : Assigning value 0x17 (idx=1) from 727/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F1_1 : Assigning value 0x10 (idx=1) from 403/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F1_1 : Assigning value 0x0b (idx=1) from 419/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F1_1 : Assigning value 0x0000 (idx=1) from 437/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F1_1 : Assigning value 0x0061 (idx=1) from 457/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F1_1 : Assigning value 0x0000 (idx=1) from 605/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F1_1 : Assigning value 0x0061 (idx=1) from 625/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F1_1 : Assigning value 0x00 (idx=1) from 643/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F1_1 : Assigning value 0x00 (idx=1) from 659/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F1_1 : Assigning value 0x0000 (idx=1) from 697/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F1_1 : Assigning value 0x0000 (idx=1) from 717/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F1_1 : Assigning value 0x17 (idx=1) from 735/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110000000100100100100001000000110100001011000000000011001001000000001100100100000000000000000001100000001100000101010001000100001001000000000000000000001011000000000001010000010111000101110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000010001100001000000000000000000000110011000001000110000000000000000000000101000000010000010000100010000010001010000010110100001101100100000011100000000000000100100011000010001100001000000000000000000000000101100001011000100000001000000000000000000000000000000001111000000000000000101110000100000000000000000000000000000001011001100001011010000000000000011110001010110000000000000001100101001000111100000001100010000100000000000000011000000000000000000001001000010010000100100110001100100101001001100100000000000000000000001000000100000000010000010000101000000010000100000000000000100000001010000000011000001100000001011000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000060249081a160064806480000c060a8884800005800a0b8b800000000000000000000000c230800003304600000501042208a0b43640e00048c2308000005858808000000078000b8400000005985a00078ac0006523c06210001800004848498c94990000020401042808400080a018301600</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OSC_VARIANCE_LIMIT = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRECHARGE_DLR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SRX_NOP_CMDS = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TAAD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_DLR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_CS_LOW = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_HOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_SETUP = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPRR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_INTERVAL = 0x000005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDITIVE_LAT_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CASLAT_LIN_F2 = 0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_LAT_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRE_F2 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRX_F2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NWR_F2 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_LEN_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCACSH_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCDMW_F2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR2_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR_F2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKCKEL_F2 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCMD_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCS_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCMD_F2 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCS_F2 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELPD_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKESR_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKE_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKSTAB_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCMDCKE_F2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCPDED_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKEH_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKE_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSH_F2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSSR_F2 = 0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDAL_F2 = 0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TESCKE_F2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_DLR_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_F2 = 0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_F2 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_PAR_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_DELAY_F2 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_F2 = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_PAR_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRRI_F2 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRWCKEL_F2 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSCO_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSC_TRK_CALC_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPDEX_F2 = 0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPPD_F2 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MAX_F2 = 0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MIN_F2 = 0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRCD_F2 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRC_F2 = 0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_F2 = 0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_DLR_F2 = 0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_F2 = 0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_DLR_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_F2 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_DLR_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_F2 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_L_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_AP_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TSR_F2 = 0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWR_F2 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_AP_F2 = 0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_F2 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_AP_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSNR_F2 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSR_F2 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCAL_F2 = 0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCKE_F2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQLAT_F2 = 0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRLAT_F2 = 0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_PREAMBLE_LEN_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F2_0 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F2_0 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F2_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F2_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F2_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F2_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F2_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F2_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F2_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F2_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F2_0 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F2_1 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F2_1 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F2_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F2_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F2_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F2_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F2_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F2_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F2_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F2_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F2_1 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OSC_VARIANCE_LIMIT : Assigning value 0x0010 (idx=1) from 43/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRECHARGE_DLR : Assigning value 0x08 (idx=1) from 59/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SRX_NOP_CMDS : Assigning value 0x05 (idx=1) from 75/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TAAD : Assigning value 0x08 (idx=1) from 79/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD : Assigning value 0x08 (idx=1) from 95/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_DLR : Assigning value 0x00 (idx=1) from 106/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_CS_LOW : Assigning value 0x04 (idx=1) from 287/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_HOLD : Assigning value 0x03 (idx=1) from 299/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_SETUP : Assigning value 0x03 (idx=1) from 913/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPRR : Assigning value 0x00 (idx=1) from 917/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRR : Assigning value 0x08 (idx=1) from 335/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD1 : Assigning value 0x00 (idx=1) from 351/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD2 : Assigning value 0x00 (idx=1) from 357/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_INTERVAL : Assigning value 0x000005 (idx=1) from 552/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 592/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDITIVE_LAT_F2 : Assigning value 0x00 (idx=1) from 0/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CASLAT_LIN_F2 : Assigning value 0x2c (idx=1) from 7/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_LAT_F2 : Assigning value 0x00 (idx=1) from 15/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRE_F2 : Assigning value 0x06 (idx=1) from 19/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRX_F2 : Assigning value 0x03 (idx=1) from 27/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NWR_F2 : Assigning value 0x14 (idx=1) from 35/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_LEN_F2 : Assigning value 0x01 (idx=1) from 67/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCACSH_F2 : Assigning value 0x02 (idx=1) from 87/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCDMW_F2 : Assigning value 0x20 (idx=1) from 100/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_F2 : Assigning value 0x00 (idx=1) from 111/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR2_F2 : Assigning value 0x00 (idx=1) from 116/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR_F2 : Assigning value 0x20 (idx=1) from 123/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKCKEL_F2 : Assigning value 0x06 (idx=1) from 130/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCMD_F2 : Assigning value 0x09 (idx=1) from 135/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCS_F2 : Assigning value 0x09 (idx=1) from 140/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCMD_F2 : Assigning value 0x06 (idx=1) from 145/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCS_F2 : Assigning value 0x06 (idx=1) from 150/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELPD_F2 : Assigning value 0x09 (idx=1) from 155/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKESR_F2 : Assigning value 0x09 (idx=1) from 163/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKE_F2 : Assigning value 0x09 (idx=1) from 171/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKSTAB_F2 : Assigning value 0x0000 (idx=1) from 179/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCMDCKE_F2 : Assigning value 0x03 (idx=1) from 195/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCPDED_F2 : Assigning value 0x00 (idx=1) from 203/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKEH_F2 : Assigning value 0x02 (idx=1) from 211/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKE_F2 : Assigning value 0x02 (idx=1) from 216/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSH_F2 : Assigning value 0x03 (idx=1) from 221/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSSR_F2 : Assigning value 0x1e (idx=1) from 229/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDAL_F2 : Assigning value 0x29 (idx=1) from 237/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TESCKE_F2 : Assigning value 0x03 (idx=1) from 245/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_DLR_F2 : Assigning value 0x0000 (idx=1) from 253/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_F2 : Assigning value 0x002b (idx=1) from 262/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_F2 : Assigning value 0x0f (idx=1) from 271/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_PAR_F2 : Assigning value 0x00 (idx=1) from 279/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_DELAY_F2 : Assigning value 0x0b (idx=1) from 291/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_F2 : Assigning value 0x000b (idx=1) from 303/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_PAR_F2 : Assigning value 0x0000 (idx=1) from 319/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRRI_F2 : Assigning value 0x17 (idx=1) from 343/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRWCKEL_F2 : Assigning value 0x0f (idx=1) from 363/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSCO_F2 : Assigning value 0x00 (idx=1) from 371/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSC_TRK_CALC_F2 : Assigning value 0x0000 (idx=1) from 379/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPDEX_F2 : Assigning value 0x0009 (idx=1) from 467/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPPD_F2 : Assigning value 0x04 (idx=1) from 483/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MAX_F2 : Assigning value 0x00d903 (idx=1) from 486/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MIN_F2 : Assigning value 0x002d (idx=1) from 506/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRCD_F2 : Assigning value 0x14 (idx=1) from 515/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRC_F2 : Assigning value 0x0041 (idx=1) from 523/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_F2 : Assigning value 0x001042 (idx=1) from 532/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_DLR_F2 : Assigning value 0x0060 (idx=1) from 572/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_F2 : Assigning value 0x00c1 (idx=1) from 582/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_DLR_F2 : Assigning value 0x0000 (idx=1) from 667/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_F2 : Assigning value 0x0000 (idx=1) from 677/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_F2 : Assigning value 0x14 (idx=1) from 743/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_DLR_F2 : Assigning value 0x00 (idx=1) from 751/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_F2 : Assigning value 0x0b (idx=1) from 759/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_L_F2 : Assigning value 0x00 (idx=1) from 767/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_AP_F2 : Assigning value 0x00 (idx=1) from 775/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_F2 : Assigning value 0x09 (idx=1) from 783/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TSR_F2 : Assigning value 0x11 (idx=1) from 791/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWR_F2 : Assigning value 0x15 (idx=1) from 799/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_AP_F2 : Assigning value 0x000c (idx=1) from 807/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_F2 : Assigning value 0x0c (idx=1) from 816/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_AP_F2 : Assigning value 0x0000 (idx=1) from 823/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_F2 : Assigning value 0x00 (idx=1) from 832/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSNR_F2 : Assigning value 0x00c9 (idx=1) from 839/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSR_F2 : Assigning value 0x00c9 (idx=1) from 855/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCAL_F2 : Assigning value 0x042c (idx=1) from 871/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCKE_F2 : Assigning value 0x03 (idx=1) from 883/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQLAT_F2 : Assigning value 0x21 (idx=1) from 891/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRLAT_F2 : Assigning value 0x12 (idx=1) from 898/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_PREAMBLE_LEN_F2 : Assigning value 0x01 (idx=1) from 905/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F2_0 : Assigning value 0x10 (idx=1) from 395/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F2_0 : Assigning value 0x0b (idx=1) from 411/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F2_0 : Assigning value 0x0000 (idx=1) from 427/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F2_0 : Assigning value 0x0061 (idx=1) from 447/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F2_0 : Assigning value 0x0000 (idx=1) from 595/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F2_0 : Assigning value 0x0061 (idx=1) from 615/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F2_0 : Assigning value 0x00 (idx=1) from 635/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F2_0 : Assigning value 0x00 (idx=1) from 651/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F2_0 : Assigning value 0x0000 (idx=1) from 687/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F2_0 : Assigning value 0x0000 (idx=1) from 707/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F2_0 : Assigning value 0x17 (idx=1) from 727/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F2_1 : Assigning value 0x10 (idx=1) from 403/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F2_1 : Assigning value 0x0b (idx=1) from 419/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F2_1 : Assigning value 0x0000 (idx=1) from 437/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F2_1 : Assigning value 0x0061 (idx=1) from 457/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F2_1 : Assigning value 0x0000 (idx=1) from 605/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F2_1 : Assigning value 0x0061 (idx=1) from 625/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F2_1 : Assigning value 0x00 (idx=1) from 643/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F2_1 : Assigning value 0x00 (idx=1) from 659/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F2_1 : Assigning value 0x0000 (idx=1) from 697/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F2_1 : Assigning value 0x0000 (idx=1) from 717/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F2_1 : Assigning value 0x17 (idx=1) from 735/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110000000100100100100001000000110100001011000000000011001001000000001100100100000000000000000001100000001100000101010001000100001001000000000000000000001011000000000001010000010111000101110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000010001100001000000000000000000000110011000001000110000000000000000000000101000000010000010000100010000010001010000010110100001101100100000011100000000000000100100011000010001100001000000000000000000000000101100001011000100000001000000000000000000000000000000001111000000000000000101110000100000000000000000000000000000001011001100001011010000000000000011110001010110000000000000001100101001000111100000001100010000100000000000000011000000000000000000001001000010010000100100110001100100101001001100100000000000000000000001000000100000000010000010000101000000010000100000000000000100000001010000000011000001100000001011000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000060249081a160064806480000c060a8884800005800a0b8b800000000000000000000000c230800003304600000501042208a0b43640e00048c2308000005858808000000078000b8400000005985a00078ac0006523c06210001800004848498c94990000020401042808400080a018301600</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_INVERSION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_MIRRORING = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_3DS_PIN_MUXING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_CID0_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEM_DP_REDUCTION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_DBI_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCK_GROUP = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_DBI_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS0 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS0 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS0 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS1 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS1 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS1 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_DEFAULT_VAL_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_INVERSION : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_MIRRORING : Assigning value 0x00 (idx=1) from 16/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP : Assigning value 0x01 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_0 : Assigning value 0x03 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_3DS_PIN_MUXING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_CID0_MAP : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEM_DP_REDUCTION : Assigning value 0x00 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_0 : Assigning value 0x01 (idx=1) from 42/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 44/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_DBI_EN : Assigning value 0x01 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCK_GROUP : Assigning value 0x02 (idx=1) from 12/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_DBI_EN : Assigning value 0x00 (idx=1) from 11/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS0 : Assigning value 0x0001 (idx=1) from 46/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS0 : Assigning value 0x0004 (idx=1) from 64/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS0 : Assigning value 0x0010 (idx=1) from 82/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 100/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 118/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 136/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 154/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 172/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 190/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_0 : Assigning value 0x01 (idx=1) from 18/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS0 : Assigning value 0x00 (idx=1) from 24/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS0 : Assigning value 0x00 (idx=1) from 40/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS1 : Assigning value 0x0001 (idx=1) from 55/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS1 : Assigning value 0x0004 (idx=1) from 73/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS1 : Assigning value 0x0010 (idx=1) from 91/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 109/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 127/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 145/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 163/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 181/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 199/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_1 : Assigning value 0x01 (idx=1) from 21/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS1 : Assigning value 0x00 (idx=1) from 32/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS1 : Assigning value 0x00 (idx=1) from 41/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_DEFAULT_VAL_F0 : Assigning value 0x00 (idx=1) from 208/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000001000000001000000000010000000010001000000000000000000001001000010010000001101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080400804008044000024240d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_INVERSION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_MIRRORING = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_3DS_PIN_MUXING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_CID0_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEM_DP_REDUCTION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_DBI_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCK_GROUP = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_DBI_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS0 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS0 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS0 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS1 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS1 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS1 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_DEFAULT_VAL_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_INVERSION : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_MIRRORING : Assigning value 0x00 (idx=1) from 16/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP : Assigning value 0x01 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_0 : Assigning value 0x03 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_3DS_PIN_MUXING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_CID0_MAP : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEM_DP_REDUCTION : Assigning value 0x00 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_0 : Assigning value 0x01 (idx=1) from 42/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 44/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_DBI_EN : Assigning value 0x01 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCK_GROUP : Assigning value 0x02 (idx=1) from 12/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_DBI_EN : Assigning value 0x00 (idx=1) from 11/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS0 : Assigning value 0x0001 (idx=1) from 46/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS0 : Assigning value 0x0004 (idx=1) from 64/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS0 : Assigning value 0x0010 (idx=1) from 82/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 100/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 118/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 136/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 154/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 172/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 190/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_0 : Assigning value 0x01 (idx=1) from 18/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS0 : Assigning value 0x00 (idx=1) from 24/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS0 : Assigning value 0x00 (idx=1) from 40/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS1 : Assigning value 0x0001 (idx=1) from 55/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS1 : Assigning value 0x0004 (idx=1) from 73/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS1 : Assigning value 0x0010 (idx=1) from 91/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 109/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 127/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 145/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 163/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 181/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 199/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_1 : Assigning value 0x01 (idx=1) from 21/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS1 : Assigning value 0x00 (idx=1) from 32/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS1 : Assigning value 0x00 (idx=1) from 41/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_DEFAULT_VAL_F1 : Assigning value 0x00 (idx=1) from 208/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000001000000001000000000010000000010001000000000000000000001001000010010000001101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080400804008044000024240d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_INVERSION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_MIRRORING = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_3DS_PIN_MUXING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_CID0_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEM_DP_REDUCTION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_DBI_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCK_GROUP = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_DBI_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS0 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS0 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS0 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS1 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS1 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS1 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_DEFAULT_VAL_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_INVERSION : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_MIRRORING : Assigning value 0x00 (idx=1) from 16/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP : Assigning value 0x01 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_0 : Assigning value 0x03 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_3DS_PIN_MUXING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_CID0_MAP : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEM_DP_REDUCTION : Assigning value 0x00 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_0 : Assigning value 0x01 (idx=1) from 42/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 44/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_DBI_EN : Assigning value 0x01 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCK_GROUP : Assigning value 0x02 (idx=1) from 12/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_DBI_EN : Assigning value 0x00 (idx=1) from 11/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS0 : Assigning value 0x0001 (idx=1) from 46/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS0 : Assigning value 0x0004 (idx=1) from 64/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS0 : Assigning value 0x0010 (idx=1) from 82/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 100/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 118/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 136/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 154/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 172/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 190/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_0 : Assigning value 0x01 (idx=1) from 18/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS0 : Assigning value 0x00 (idx=1) from 24/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS0 : Assigning value 0x00 (idx=1) from 40/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS1 : Assigning value 0x0001 (idx=1) from 55/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS1 : Assigning value 0x0004 (idx=1) from 73/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS1 : Assigning value 0x0010 (idx=1) from 91/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 109/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 127/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 145/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 163/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 181/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 199/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_1 : Assigning value 0x01 (idx=1) from 21/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS1 : Assigning value 0x00 (idx=1) from 32/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS1 : Assigning value 0x00 (idx=1) from 41/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_DEFAULT_VAL_F2 : Assigning value 0x00 (idx=1) from 208/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000001000000001000000000010000000010001000000000000000000001001000010010000001101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080400804008044000024240d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DLL_RST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR23_DATA = 0x000020</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR37_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKI_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F0_0 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F0_0 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F0_0 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F0_0 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F0_0 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F0_0 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F0_0 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F0_1 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F0_1 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F0_1 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F0_1 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F0_1 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F0_1 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F0_1 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DLL_RST : Assigning value 0x00 (idx=1) from 180/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR23_DATA : Assigning value 0x000020 (idx=1) from 649/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR37_DATA : Assigning value 0x000000 (idx=1) from 775/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKI_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 793/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 811/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 826/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 0/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F0_0 : Assigning value 0x0000b4 (idx=1) from 36/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F0_0 : Assigning value 0x00005b (idx=1) from 72/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F0_0 : Assigning value 0x000073 (idx=1) from 108/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 144/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 181/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 217/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 253/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F0_0 : Assigning value 0x000035 (idx=1) from 289/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F0_0 : Assigning value 0x00004d (idx=1) from 325/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_0 : Assigning value 0x000000 (idx=1) from 361/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F0_0 : Assigning value 0x000014 (idx=1) from 397/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_0 : Assigning value 0x000000 (idx=1) from 433/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 469/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 505/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 541/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 577/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F0_0 : Assigning value 0x000018 (idx=1) from 613/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 667/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 703/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 739/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 18/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F0_1 : Assigning value 0x0000b4 (idx=1) from 54/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F0_1 : Assigning value 0x00005b (idx=1) from 90/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F0_1 : Assigning value 0x000073 (idx=1) from 126/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 162/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 199/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 235/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 271/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F0_1 : Assigning value 0x000035 (idx=1) from 307/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F0_1 : Assigning value 0x00004d (idx=1) from 343/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_1 : Assigning value 0x000000 (idx=1) from 379/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F0_1 : Assigning value 0x000014 (idx=1) from 415/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_1 : Assigning value 0x000000 (idx=1) from 451/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 487/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 523/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 559/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 595/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F0_1 : Assigning value 0x000018 (idx=1) from 631/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 685/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 721/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 757/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000110000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000000101000000000000000000000000000000000000000000000000010011010000000000010011010000000000001101010000000000001101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110011000000000001110011000000000001011011000000000001011011000000000010110100000000000010110100000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000040000c00030000000000000000000000000000000000000000000000000a0002800000000000268009a001a8006a000000000000000000000000000000000000001cc00730016c005b002d000b4000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DLL_RST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR23_DATA = 0x000020</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR37_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKI_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F1_0 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F1_0 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F1_0 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F1_0 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F1_0 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F1_0 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F1_0 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F1_1 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F1_1 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F1_1 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F1_1 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F1_1 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F1_1 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F1_1 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DLL_RST : Assigning value 0x00 (idx=1) from 180/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR23_DATA : Assigning value 0x000020 (idx=1) from 649/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR37_DATA : Assigning value 0x000000 (idx=1) from 775/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKI_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 793/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 811/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 826/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 0/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F1_0 : Assigning value 0x0000b4 (idx=1) from 36/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F1_0 : Assigning value 0x00005b (idx=1) from 72/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F1_0 : Assigning value 0x000073 (idx=1) from 108/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 144/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 181/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 217/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 253/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F1_0 : Assigning value 0x000035 (idx=1) from 289/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F1_0 : Assigning value 0x00004d (idx=1) from 325/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_0 : Assigning value 0x000000 (idx=1) from 361/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F1_0 : Assigning value 0x000014 (idx=1) from 397/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_0 : Assigning value 0x000000 (idx=1) from 433/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 469/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 505/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 541/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 577/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F1_0 : Assigning value 0x000018 (idx=1) from 613/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 667/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 703/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 739/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 18/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F1_1 : Assigning value 0x0000b4 (idx=1) from 54/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F1_1 : Assigning value 0x00005b (idx=1) from 90/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F1_1 : Assigning value 0x000073 (idx=1) from 126/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 162/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 199/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 235/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 271/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F1_1 : Assigning value 0x000035 (idx=1) from 307/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F1_1 : Assigning value 0x00004d (idx=1) from 343/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_1 : Assigning value 0x000000 (idx=1) from 379/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F1_1 : Assigning value 0x000014 (idx=1) from 415/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_1 : Assigning value 0x000000 (idx=1) from 451/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 487/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 523/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 559/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 595/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F1_1 : Assigning value 0x000018 (idx=1) from 631/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 685/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 721/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 757/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000110000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000000101000000000000000000000000000000000000000000000000010011010000000000010011010000000000001101010000000000001101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110011000000000001110011000000000001011011000000000001011011000000000010110100000000000010110100000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000040000c00030000000000000000000000000000000000000000000000000a0002800000000000268009a001a8006a000000000000000000000000000000000000001cc00730016c005b002d000b4000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DLL_RST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR23_DATA = 0x000020</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR37_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKI_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F2_0 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F2_0 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F2_0 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F2_0 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F2_0 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F2_0 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F2_0 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F2_1 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F2_1 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F2_1 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F2_1 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F2_1 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F2_1 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F2_1 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DLL_RST : Assigning value 0x00 (idx=1) from 180/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR23_DATA : Assigning value 0x000020 (idx=1) from 649/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR37_DATA : Assigning value 0x000000 (idx=1) from 775/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKI_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 793/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 811/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 826/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 0/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F2_0 : Assigning value 0x0000b4 (idx=1) from 36/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F2_0 : Assigning value 0x00005b (idx=1) from 72/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F2_0 : Assigning value 0x000073 (idx=1) from 108/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 144/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 181/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 217/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 253/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F2_0 : Assigning value 0x000035 (idx=1) from 289/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F2_0 : Assigning value 0x00004d (idx=1) from 325/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_0 : Assigning value 0x000000 (idx=1) from 361/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F2_0 : Assigning value 0x000014 (idx=1) from 397/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_0 : Assigning value 0x000000 (idx=1) from 433/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 469/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 505/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 541/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 577/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F2_0 : Assigning value 0x000018 (idx=1) from 613/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 667/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 703/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 739/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 18/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F2_1 : Assigning value 0x0000b4 (idx=1) from 54/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F2_1 : Assigning value 0x00005b (idx=1) from 90/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F2_1 : Assigning value 0x000073 (idx=1) from 126/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 162/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 199/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 235/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 271/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F2_1 : Assigning value 0x000035 (idx=1) from 307/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F2_1 : Assigning value 0x00004d (idx=1) from 343/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_1 : Assigning value 0x000000 (idx=1) from 379/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F2_1 : Assigning value 0x000014 (idx=1) from 415/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_1 : Assigning value 0x000000 (idx=1) from 451/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 487/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 523/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 559/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 595/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F2_1 : Assigning value 0x000018 (idx=1) from 631/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 685/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 721/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 757/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000110000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000000101000000000000000000000000000000000000000000000000010011010000000000010011010000000000001101010000000000001101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110011000000000001110011000000000001011011000000000001011011000000000010110100000000000010110100000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000040000c00030000000000000000000000000000000000000000000000000a0002800000000000268009a001a8006a000000000000000000000000000000000000001cc00730016c005b002d000b4000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key APREBIT = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BURST_ON_FLY_BIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DRAM_CLASS = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LOGICAL_CS_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LRDIMM_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MDQS_MULT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEM_3DS_SUPPORT_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NO_MEMORY_DM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key REG_DIMM_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_DIFF_0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BG_DIFF_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CID_DIFF_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key COL_DIFF_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ROW_DIFF_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_DIFF_1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BG_DIFF_1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CID_DIFF_1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key COL_DIFF_1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ROW_DIFF_1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.APREBIT : Assigning value 0x0b (idx=1) from 10/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BURST_ON_FLY_BIT : Assigning value 0x00 (idx=1) from 15/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.DRAM_CLASS is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LOGICAL_CS_MAP : Assigning value 0x00 (idx=1) from 0/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LRDIMM_ENABLE : Assigning value 0x00 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MDQS_MULT : Assigning value 0x01 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEM_3DS_SUPPORT_EN : Assigning value 0x00 (idx=1) from 6/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NO_MEMORY_DM : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.REG_DIMM_ENABLE : Assigning value 0x00 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_DIFF_0 : Assigning value 0x02 (idx=1) from 25/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BG_DIFF_0 : Assigning value 0x03 (idx=1) from 29/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CID_DIFF_0 : Assigning value 0x01 (idx=1) from 41/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.COL_DIFF_0 : Assigning value 0x01 (idx=1) from 33/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ROW_DIFF_0 : Assigning value 0x03 (idx=1) from 19/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_DIFF_1 : Assigning value 0x02 (idx=1) from 27/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BG_DIFF_1 : Assigning value 0x03 (idx=1) from 31/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CID_DIFF_1 : Assigning value 0x01 (idx=1) from 42/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.COL_DIFF_1 : Assigning value 0x01 (idx=1) from 37/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ROW_DIFF_1 : Assigning value 0x03 (idx=1) from 22/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1100010001111110100110110000010110000010000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000623f4d82c10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CA_PARITY_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_HOLD_CKE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_MAP = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRC = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_DFS_CW_MAP_F0 = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TSTAB_F0 = 0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F0_0 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F0_1 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CA_PARITY_EN : Assigning value 0x00 (idx=1) from 28/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_HOLD_CKE_EN : Assigning value 0x00 (idx=1) from 27/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_MAP : Assigning value 0x00000000 (idx=1) from 0/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRC : Assigning value 0x10 (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD : Assigning value 0x000b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L : Assigning value 0x10 (idx=1) from 50/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L2 : Assigning value 0x20 (idx=1) from 55/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_DFS_CW_MAP_F0 : Assigning value 0x00000000 (idx=1) from 389/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TSTAB_F0 : Assigning value 0x001904 (idx=1) from 365/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F0_0 is {RDIMM_CTL_F0_0_0 RDIMM_CTL_F0_0_1 RDIMM_CTL_F0_0_2 RDIMM_CTL_F0_0_3 RDIMM_CTL_F0_0_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 61/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 93/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 125/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 157/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 189/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F0_1 is {RDIMM_CTL_F0_1_0 RDIMM_CTL_F0_1_1 RDIMM_CTL_F0_1_2 RDIMM_CTL_F0_1_3 RDIMM_CTL_F0_1_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 213/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 245/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 277/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 309/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 341/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000110010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001000000000000000010111000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000032080000000000000000000000000000000000000000000000000000000000000000000000000001040002e00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CA_PARITY_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_HOLD_CKE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_MAP = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRC = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_DFS_CW_MAP_F1 = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TSTAB_F1 = 0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F1_0 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F1_1 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CA_PARITY_EN : Assigning value 0x00 (idx=1) from 28/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_HOLD_CKE_EN : Assigning value 0x00 (idx=1) from 27/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_MAP : Assigning value 0x00000000 (idx=1) from 0/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRC : Assigning value 0x10 (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD : Assigning value 0x000b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L : Assigning value 0x10 (idx=1) from 50/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L2 : Assigning value 0x20 (idx=1) from 55/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_DFS_CW_MAP_F1 : Assigning value 0x00000000 (idx=1) from 389/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TSTAB_F1 : Assigning value 0x001904 (idx=1) from 365/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F1_0 is {RDIMM_CTL_F1_0_0 RDIMM_CTL_F1_0_1 RDIMM_CTL_F1_0_2 RDIMM_CTL_F1_0_3 RDIMM_CTL_F1_0_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 61/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 93/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 125/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 157/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 189/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F1_1 is {RDIMM_CTL_F1_1_0 RDIMM_CTL_F1_1_1 RDIMM_CTL_F1_1_2 RDIMM_CTL_F1_1_3 RDIMM_CTL_F1_1_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 213/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 245/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 277/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 309/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 341/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000110010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001000000000000000010111000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000032080000000000000000000000000000000000000000000000000000000000000000000000000001040002e00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CA_PARITY_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_HOLD_CKE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_MAP = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRC = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_DFS_CW_MAP_F2 = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TSTAB_F2 = 0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F2_0 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F2_1 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CA_PARITY_EN : Assigning value 0x00 (idx=1) from 28/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_HOLD_CKE_EN : Assigning value 0x00 (idx=1) from 27/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_MAP : Assigning value 0x00000000 (idx=1) from 0/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRC : Assigning value 0x10 (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD : Assigning value 0x000b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L : Assigning value 0x10 (idx=1) from 50/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L2 : Assigning value 0x20 (idx=1) from 55/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_DFS_CW_MAP_F2 : Assigning value 0x00000000 (idx=1) from 389/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TSTAB_F2 : Assigning value 0x001904 (idx=1) from 365/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F2_0 is {RDIMM_CTL_F2_0_0 RDIMM_CTL_F2_0_1 RDIMM_CTL_F2_0_2 RDIMM_CTL_F2_0_3 RDIMM_CTL_F2_0_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 61/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 93/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 125/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 157/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 189/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F2_1 is {RDIMM_CTL_F2_1_0 RDIMM_CTL_F2_1_1 RDIMM_CTL_F2_1_2 RDIMM_CTL_F2_1_3 RDIMM_CTL_F2_1_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 213/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 245/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 277/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 309/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 341/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000110010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001000000000000000010111000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000032080000000000000000000000000000000000000000000000000000000000000000000000000001040002e00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Miscellaneous Parameter Configuration = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Miscellaneous Parameter Configuration = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_CMP_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_COLLISION_MPM_DIS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BG_ROTATE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BSTLEN = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CMD_BLK_SPLIT_SIZE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key COMMAND_AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CONCURRENTAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_MEMORY_MASKED_WRITE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RD_INTERLEAVE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RW_GROUP_W_BNK_CONFLICT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INHIBIT_DRAM_CMD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key IN_ORDER_ACCEPT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NUM_Q_ENTRIES_ACT_DISABLE = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OPTIMAL_RMODW_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PLACEMENT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRIORITY_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key Q_FULLNESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_PAGE_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SWAP_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_LOCKOUT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITEINTERP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_ORDER_REQ = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_ARCH_MODE_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_CMP_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_COLLISION_MPM_DIS : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AGE_COUNT : Assigning value 0xff (idx=1) from 2/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AP : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_SPLIT_EN : Assigning value 0x01 (idx=1) from 13/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BG_ROTATE_EN : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BSTLEN : Assigning value 0x04 (idx=1) from 16/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CMD_BLK_SPLIT_SIZE : Assigning value 0x00 (idx=1) from 22/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.COMMAND_AGE_COUNT : Assigning value 0xff (idx=1) from 23/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CONCURRENTAP : Assigning value 0x01 (idx=1) from 31/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_SAME_EN : Assigning value 0x01 (idx=1) from 32/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_MEMORY_MASKED_WRITE : Assigning value 0x00 (idx=1) from 33/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RD_INTERLEAVE : Assigning value 0x01 (idx=1) from 34/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RW_GROUP_W_BNK_CONFLICT : Assigning value 0x01 (idx=1) from 35/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INHIBIT_DRAM_CMD : Assigning value 0x00 (idx=1) from 37/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.IN_ORDER_ACCEPT : Assigning value 0x00 (idx=1) from 39/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NUM_Q_ENTRIES_ACT_DISABLE : Assigning value 0x10 (idx=1) from 40/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OPTIMAL_RMODW_EN : Assigning value 0x01 (idx=1) from 45/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PLACEMENT_EN : Assigning value 0x01 (idx=1) from 46/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRIORITY_EN : Assigning value 0x01 (idx=1) from 47/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.Q_FULLNESS : Assigning value 0x00 (idx=1) from 48/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_EN : Assigning value 0x01 (idx=1) from 53/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_PAGE_EN : Assigning value 0x01 (idx=1) from 54/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SWAP_EN : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_LOCKOUT : Assigning value 0x01 (idx=1) from 56/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SPLIT_EN : Assigning value 0x01 (idx=1) from 57/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITEINTERP : Assigning value 0x00 (idx=1) from 58/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_ORDER_REQ : Assigning value 0x00 (idx=1) from 59/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_ARCH_MODE_F0 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0001101100000111100000000110111111111100001000010001111111101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360f00dff8423fd</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_CMP_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_COLLISION_MPM_DIS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BG_ROTATE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BSTLEN = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CMD_BLK_SPLIT_SIZE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key COMMAND_AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CONCURRENTAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_MEMORY_MASKED_WRITE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RD_INTERLEAVE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RW_GROUP_W_BNK_CONFLICT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INHIBIT_DRAM_CMD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key IN_ORDER_ACCEPT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NUM_Q_ENTRIES_ACT_DISABLE = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OPTIMAL_RMODW_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PLACEMENT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRIORITY_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key Q_FULLNESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_PAGE_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SWAP_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_LOCKOUT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITEINTERP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_ORDER_REQ = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_ARCH_MODE_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_CMP_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_COLLISION_MPM_DIS : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AGE_COUNT : Assigning value 0xff (idx=1) from 2/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AP : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_SPLIT_EN : Assigning value 0x01 (idx=1) from 13/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BG_ROTATE_EN : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BSTLEN : Assigning value 0x04 (idx=1) from 16/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CMD_BLK_SPLIT_SIZE : Assigning value 0x00 (idx=1) from 22/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.COMMAND_AGE_COUNT : Assigning value 0xff (idx=1) from 23/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CONCURRENTAP : Assigning value 0x01 (idx=1) from 31/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_SAME_EN : Assigning value 0x01 (idx=1) from 32/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_MEMORY_MASKED_WRITE : Assigning value 0x00 (idx=1) from 33/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RD_INTERLEAVE : Assigning value 0x01 (idx=1) from 34/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RW_GROUP_W_BNK_CONFLICT : Assigning value 0x01 (idx=1) from 35/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INHIBIT_DRAM_CMD : Assigning value 0x00 (idx=1) from 37/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.IN_ORDER_ACCEPT : Assigning value 0x00 (idx=1) from 39/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NUM_Q_ENTRIES_ACT_DISABLE : Assigning value 0x10 (idx=1) from 40/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OPTIMAL_RMODW_EN : Assigning value 0x01 (idx=1) from 45/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PLACEMENT_EN : Assigning value 0x01 (idx=1) from 46/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRIORITY_EN : Assigning value 0x01 (idx=1) from 47/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.Q_FULLNESS : Assigning value 0x00 (idx=1) from 48/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_EN : Assigning value 0x01 (idx=1) from 53/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_PAGE_EN : Assigning value 0x01 (idx=1) from 54/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SWAP_EN : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_LOCKOUT : Assigning value 0x01 (idx=1) from 56/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SPLIT_EN : Assigning value 0x01 (idx=1) from 57/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITEINTERP : Assigning value 0x00 (idx=1) from 58/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_ORDER_REQ : Assigning value 0x00 (idx=1) from 59/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_ARCH_MODE_F1 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0001101100000111100000000110111111111100001000010001111111101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360f00dff8423fd</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_CMP_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_COLLISION_MPM_DIS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BG_ROTATE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BSTLEN = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CMD_BLK_SPLIT_SIZE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key COMMAND_AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CONCURRENTAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_MEMORY_MASKED_WRITE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RD_INTERLEAVE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RW_GROUP_W_BNK_CONFLICT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INHIBIT_DRAM_CMD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key IN_ORDER_ACCEPT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NUM_Q_ENTRIES_ACT_DISABLE = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OPTIMAL_RMODW_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PLACEMENT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRIORITY_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key Q_FULLNESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_PAGE_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SWAP_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_LOCKOUT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITEINTERP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_ORDER_REQ = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_ARCH_MODE_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_CMP_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_COLLISION_MPM_DIS : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AGE_COUNT : Assigning value 0xff (idx=1) from 2/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AP : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_SPLIT_EN : Assigning value 0x01 (idx=1) from 13/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BG_ROTATE_EN : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BSTLEN : Assigning value 0x04 (idx=1) from 16/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CMD_BLK_SPLIT_SIZE : Assigning value 0x00 (idx=1) from 22/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.COMMAND_AGE_COUNT : Assigning value 0xff (idx=1) from 23/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CONCURRENTAP : Assigning value 0x01 (idx=1) from 31/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_SAME_EN : Assigning value 0x01 (idx=1) from 32/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_MEMORY_MASKED_WRITE : Assigning value 0x00 (idx=1) from 33/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RD_INTERLEAVE : Assigning value 0x01 (idx=1) from 34/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RW_GROUP_W_BNK_CONFLICT : Assigning value 0x01 (idx=1) from 35/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INHIBIT_DRAM_CMD : Assigning value 0x00 (idx=1) from 37/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.IN_ORDER_ACCEPT : Assigning value 0x00 (idx=1) from 39/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NUM_Q_ENTRIES_ACT_DISABLE : Assigning value 0x10 (idx=1) from 40/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OPTIMAL_RMODW_EN : Assigning value 0x01 (idx=1) from 45/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PLACEMENT_EN : Assigning value 0x01 (idx=1) from 46/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRIORITY_EN : Assigning value 0x01 (idx=1) from 47/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.Q_FULLNESS : Assigning value 0x00 (idx=1) from 48/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_EN : Assigning value 0x01 (idx=1) from 53/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_PAGE_EN : Assigning value 0x01 (idx=1) from 54/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SWAP_EN : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_LOCKOUT : Assigning value 0x01 (idx=1) from 56/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SPLIT_EN : Assigning value 0x01 (idx=1) from 57/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITEINTERP : Assigning value 0x00 (idx=1) from 58/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_ORDER_REQ : Assigning value 0x00 (idx=1) from 59/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_ARCH_MODE_F2 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0001101100000111100000000110111111111100001000010001111111101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360f00dff8423fd</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DLL_RST_ADJ_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DLL_RST_DELAY = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DLL_RST_ADJ_DLY : Assigning value 0x00 (idx=1) from 16/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DLL_RST_DELAY : Assigning value 0x0000 (idx=1) from 0/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_BANK_ADDRESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_CID_ADDRESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRR_REGNUM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_CONTROL = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_CS_ADDRESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_ECC = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_ROW_ADDRESS = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_BANK_ADDRESS : Assigning value 0x00 (idx=1) from 10/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_CID_ADDRESS : Assigning value 0x00 (idx=1) from 15/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRR_REGNUM : Assigning value 0x00 (idx=1) from 2/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_CONTROL : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_CS_ADDRESS : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.PPR_DATA is {PPR_DATA_0 PPR_DATA_1 PPR_DATA_2 PPR_DATA_3 PPR_DATA_4 PPR_DATA_5 PPR_DATA_6 PPR_DATA_7} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=1) from 34/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=4294967296) from 66/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=18446744073709551616) from 98/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 130/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 162/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=1461501637330902918203684832716283019655932542976) from 194/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=6277101735386680763835789423207666416102355444464034512896) from 226/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=26959946667150639794667015087019630673637144422540572481103610249216) from 258/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_ECC : Assigning value 0x00000000 (idx=1) from 290/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_ROW_ADDRESS : Assigning value 0x000000 (idx=1) from 16/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_CMD_MAX_PER_TREFI = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_MAX_CREDIT = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_MAX_DEFICIT = 0x18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_PBR_CONT_EN_THRESHOLD = 0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_COMPARISON_FOR_REFRESH_DEPTH = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ENABLE_QUICK_SREFRESH = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PBR_CONT_REQ_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PBR_MODE_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PBR_NUMERIC_ORDER = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_NO_AREF = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RAAIMT = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RAAMMT = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RAA_CNT_DECR_PER_REF = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key REF_RFM_PRIO = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RFM_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RFM_HIGH_THRESHOLD = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RFM_NORM_THRESHOLD = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RFM_SB_CONT_EN_THRESHOLD = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SELECT_BANK_IN_Q = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SREFRESH_EXIT_NO_REFRESH = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_ENABLE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_CMD_MAX_PER_TREFI : Assigning value 0x08 (idx=1) from 10/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_MAX_CREDIT : Assigning value 0x0c (idx=1) from 14/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_MAX_DEFICIT : Assigning value 0x18 (idx=1) from 19/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_PBR_CONT_EN_THRESHOLD : Assigning value 0x12 (idx=1) from 24/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_COMPARISON_FOR_REFRESH_DEPTH : Assigning value 0x10 (idx=1) from 1/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ENABLE_QUICK_SREFRESH : Assigning value 0x01 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PBR_CONT_REQ_EN : Assigning value 0x01 (idx=1) from 29/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PBR_MODE_EN : Assigning value 0x01 (idx=1) from 30/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PBR_NUMERIC_ORDER : Assigning value 0x00 (idx=1) from 34/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_NO_AREF : Assigning value 0x00 (idx=1) from 35/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RAAIMT : Assigning value 0x0000 (idx=1) from 36/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RAAMMT : Assigning value 0x0000 (idx=1) from 46/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RAA_CNT_DECR_PER_REF : Assigning value 0x0000 (idx=1) from 56/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.REF_RFM_PRIO : Assigning value 0x01 (idx=1) from 67/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RFM_EN : Assigning value 0x00 (idx=1) from 66/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RFM_HIGH_THRESHOLD : Assigning value 0x0000 (idx=1) from 78/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RFM_NORM_THRESHOLD : Assigning value 0x0000 (idx=1) from 68/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RFM_SB_CONT_EN_THRESHOLD : Assigning value 0x0000 (idx=1) from 88/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SELECT_BANK_IN_Q : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SREFRESH_EXIT_NO_REFRESH : Assigning value 0x00 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_ENABLE : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000010000000000000000000000000000000000001110010110000110010000010100001;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000072c320a1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_PHASE_2N = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POSTAMBLE_SUPPORT = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_1T_TIMING_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_DIFFCS_DLY_F0 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_DIFFCS_DLY_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_SAMECS_DLY_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW2MRW_DLY_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MAX_F0 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MIN_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_DIFFCS_DLY_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_DIFFCS_DLY_F0 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_PHASE_2N : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POSTAMBLE_SUPPORT : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 3/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 8/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_SAMECS_DLY : Assigning value 0x00 (idx=1) from 13/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_1T_TIMING_F0 : Assigning value 0x00 (idx=1) from 18/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_DIFFCS_DLY_F0 : Assigning value 0x0c (idx=1) from 19/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_DIFFCS_DLY_F0 : Assigning value 0x0a (idx=1) from 24/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_SAMECS_DLY_F0 : Assigning value 0x0a (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW2MRW_DLY_F0 : Assigning value 0x09 (idx=1) from 34/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MAX_F0 : Assigning value 0x04 (idx=1) from 39/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MIN_F0 : Assigning value 0x02 (idx=1) from 43/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_DIFFCS_DLY_F0 : Assigning value 0x01 (idx=1) from 46/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_DIFFCS_DLY_F0 : Assigning value 0x0c (idx=1) from 51/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01100000010100100010010101001010011000000000000000000100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006052254a600004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_PHASE_2N = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POSTAMBLE_SUPPORT = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_1T_TIMING_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_DIFFCS_DLY_F1 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_DIFFCS_DLY_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_SAMECS_DLY_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW2MRW_DLY_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MAX_F1 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MIN_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_DIFFCS_DLY_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_DIFFCS_DLY_F1 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_PHASE_2N : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POSTAMBLE_SUPPORT : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 3/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 8/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_SAMECS_DLY : Assigning value 0x00 (idx=1) from 13/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_1T_TIMING_F1 : Assigning value 0x00 (idx=1) from 18/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_DIFFCS_DLY_F1 : Assigning value 0x0c (idx=1) from 19/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_DIFFCS_DLY_F1 : Assigning value 0x0a (idx=1) from 24/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_SAMECS_DLY_F1 : Assigning value 0x0a (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW2MRW_DLY_F1 : Assigning value 0x09 (idx=1) from 34/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MAX_F1 : Assigning value 0x04 (idx=1) from 39/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MIN_F1 : Assigning value 0x02 (idx=1) from 43/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_DIFFCS_DLY_F1 : Assigning value 0x01 (idx=1) from 46/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_DIFFCS_DLY_F1 : Assigning value 0x0c (idx=1) from 51/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01100000010100100010010101001010011000000000000000000100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006052254a600004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_PHASE_2N = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POSTAMBLE_SUPPORT = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_1T_TIMING_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_DIFFCS_DLY_F2 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_DIFFCS_DLY_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_SAMECS_DLY_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW2MRW_DLY_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MAX_F2 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MIN_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_DIFFCS_DLY_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_DIFFCS_DLY_F2 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_PHASE_2N : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POSTAMBLE_SUPPORT : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 3/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 8/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_SAMECS_DLY : Assigning value 0x00 (idx=1) from 13/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_1T_TIMING_F2 : Assigning value 0x00 (idx=1) from 18/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_DIFFCS_DLY_F2 : Assigning value 0x0c (idx=1) from 19/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_DIFFCS_DLY_F2 : Assigning value 0x0a (idx=1) from 24/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_SAMECS_DLY_F2 : Assigning value 0x0a (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW2MRW_DLY_F2 : Assigning value 0x09 (idx=1) from 34/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MAX_F2 : Assigning value 0x04 (idx=1) from 39/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MIN_F2 : Assigning value 0x02 (idx=1) from 43/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_DIFFCS_DLY_F2 : Assigning value 0x01 (idx=1) from 46/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_DIFFCS_DLY_F2 : Assigning value 0x0c (idx=1) from 51/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01100000010100100010010101001010011000000000000000000100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006052254a600004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_ODT_ASSERT_EXCEPT_RD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_VALUE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_EN_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PD_NT_ODT_EN_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_TO_ODTH_F0 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_RD_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_WR_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTL_2CMD_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTUP_F0 = 0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_TO_ODTH_F0 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_ODT_ASSERT_EXCEPT_RD : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_VALUE : Assigning value 0x01 (idx=1) from 57/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS0 : Assigning value 0x00 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS0 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS1 : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS1 : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_EN_F0 : Assigning value 0x01 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PD_NT_ODT_EN_F0 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_TO_ODTH_F0 : Assigning value 0x15 (idx=1) from 11/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_RD_F0 : Assigning value 0x01 (idx=1) from 18/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_WR_F0 : Assigning value 0x01 (idx=1) from 22/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTL_2CMD_F0 : Assigning value 0x00 (idx=1) from 26/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTUP_F0 : Assigning value 0x010b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_TO_ODTH_F0 : Assigning value 0x10 (idx=1) from 50/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01001000000000001000010110000000000010001001010101000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000240042c0044aa00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_ODT_ASSERT_EXCEPT_RD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_VALUE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_EN_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PD_NT_ODT_EN_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_TO_ODTH_F1 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_RD_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_WR_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTL_2CMD_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTUP_F1 = 0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_TO_ODTH_F1 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_ODT_ASSERT_EXCEPT_RD : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_VALUE : Assigning value 0x01 (idx=1) from 57/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS0 : Assigning value 0x00 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS0 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS1 : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS1 : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_EN_F1 : Assigning value 0x01 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PD_NT_ODT_EN_F1 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_TO_ODTH_F1 : Assigning value 0x15 (idx=1) from 11/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_RD_F1 : Assigning value 0x01 (idx=1) from 18/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_WR_F1 : Assigning value 0x01 (idx=1) from 22/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTL_2CMD_F1 : Assigning value 0x00 (idx=1) from 26/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTUP_F1 : Assigning value 0x010b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_TO_ODTH_F1 : Assigning value 0x10 (idx=1) from 50/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01001000000000001000010110000000000010001001010101000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000240042c0044aa00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_ODT_ASSERT_EXCEPT_RD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_VALUE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_EN_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PD_NT_ODT_EN_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_TO_ODTH_F2 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_RD_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_WR_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTL_2CMD_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTUP_F2 = 0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_TO_ODTH_F2 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_ODT_ASSERT_EXCEPT_RD : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_VALUE : Assigning value 0x01 (idx=1) from 57/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS0 : Assigning value 0x00 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS0 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS1 : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS1 : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_EN_F2 : Assigning value 0x01 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PD_NT_ODT_EN_F2 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_TO_ODTH_F2 : Assigning value 0x15 (idx=1) from 11/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_RD_F2 : Assigning value 0x01 (idx=1) from 18/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_WR_F2 : Assigning value 0x01 (idx=1) from 22/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTL_2CMD_F2 : Assigning value 0x00 (idx=1) from 26/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTUP_F2 : Assigning value 0x010b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_TO_ODTH_F2 : Assigning value 0x10 (idx=1) from 50/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01001000000000001000010110000000000010001001010101000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000240042c0044aa00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PORT_ADDR_PROTECTION_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PROGRAMMABLE_ADDRESS_ORDER = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MSK_0 = 0x001f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_VAL_LOWER_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_VAL_UPPER_0 = 0x00ff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ROW_START_VAL_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MSK_1 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_VAL_LOWER_1 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_VAL_UPPER_1 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ROW_START_VAL_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PORT_ADDR_PROTECTION_EN : Assigning value 0x00 (idx=1) from 106/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PROGRAMMABLE_ADDRESS_ORDER : Assigning value 0x00 (idx=1) from 96/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MSK_0 : Assigning value 0x001f (idx=1) from 0/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_VAL_LOWER_0 : Assigning value 0x0000 (idx=1) from 32/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_VAL_UPPER_0 : Assigning value 0x00ff (idx=1) from 64/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ROW_START_VAL_0 : Assigning value 0x00 (idx=1) from 100/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MSK_1 : Assigning value 0xffff (idx=1) from 16/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_VAL_LOWER_1 : Assigning value 0xffff (idx=1) from 48/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_VAL_UPPER_1 : Assigning value 0xffff (idx=1) from 80/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ROW_START_VAL_1 : Assigning value 0x00 (idx=1) from 103/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000111111111111111100000000111111111111111111111111000000000000000011111111111111110000000000011111;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffff00ffffff0000ffff001f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ZQ_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_ROTATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_SW_REQ_START_LATCH_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCL_F0 = 0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_F0 = 0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQINIT_F0 = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQRESET_F0 = 0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ZQ_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 1/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_ROTATE : Assigning value 0x01 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_SW_REQ_START_LATCH_MAP : Assigning value 0x00 (idx=1) from 13/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_0 : Assigning value 0x00 (idx=1) from 9/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_0 : Assigning value 0x00 (idx=1) from 5/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_1 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_1 : Assigning value 0x00 (idx=1) from 7/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCL_F0 : Assigning value 0x0100 (idx=1) from 15/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_F0 : Assigning value 0x0040 (idx=1) from 27/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQINIT_F0 : Assigning value 0x0200 (idx=1) from 39/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQRESET_F0 : Assigning value 0x0036 (idx=1) from 51/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110110001000000000000001000000000100000000000000000010111;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b1000200800017</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ZQ_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_ROTATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_SW_REQ_START_LATCH_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCL_F1 = 0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_F1 = 0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQINIT_F1 = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQRESET_F1 = 0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ZQ_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 1/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_ROTATE : Assigning value 0x01 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_SW_REQ_START_LATCH_MAP : Assigning value 0x00 (idx=1) from 13/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_0 : Assigning value 0x00 (idx=1) from 9/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_0 : Assigning value 0x00 (idx=1) from 5/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_1 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_1 : Assigning value 0x00 (idx=1) from 7/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCL_F1 : Assigning value 0x0100 (idx=1) from 15/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_F1 : Assigning value 0x0040 (idx=1) from 27/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQINIT_F1 : Assigning value 0x0200 (idx=1) from 39/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQRESET_F1 : Assigning value 0x0036 (idx=1) from 51/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110110001000000000000001000000000100000000000000000010111;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b1000200800017</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ZQ_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_ROTATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_SW_REQ_START_LATCH_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCL_F2 = 0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_F2 = 0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQINIT_F2 = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQRESET_F2 = 0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ZQ_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 1/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_ROTATE : Assigning value 0x01 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_SW_REQ_START_LATCH_MAP : Assigning value 0x00 (idx=1) from 13/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_0 : Assigning value 0x00 (idx=1) from 9/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_0 : Assigning value 0x00 (idx=1) from 5/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_1 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_1 : Assigning value 0x00 (idx=1) from 7/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCL_F2 : Assigning value 0x0100 (idx=1) from 15/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_F2 : Assigning value 0x0040 (idx=1) from 27/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQINIT_F2 : Assigning value 0x0200 (idx=1) from 39/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQRESET_F2 : Assigning value 0x0036 (idx=1) from 51/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110110001000000000000001000000000100000000000000000010111;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b1000200800017</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of data_mask_en: Parameter value true</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: HMC=1 (0: Wide/1: Slim) is_used=0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">quartus_synth fileset time: 717.63 ms</message>
   <message level="Info" culprit="cal_0">"Generating: cal_0"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_emif_io96b_cal_411_tsrqcha"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i"</message>
   <message level="Debug" culprit="cal_0">quartus_synth fileset time: 278.39 ms</message>
   <message level="Info" culprit="jamb">"Generating: jamb"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_jtag_interface"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_timing_adapter_1950_bbjt6kq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_altera_avalon_sc_fifo_1932_onpcouq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_bytes_to_packets"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_packets_to_bytes"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_packets_to_master"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_rd56ufy"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_5vp3d5a"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_reset_controller"</message>
  </messages>
 </entity>
 <entity
   kind="emif_io96b_lpddr4"
   version="4.1.1"
   name="EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry">
  <parameter name="PHY_CS_TX_EQUALIZATION" value="OFF" />
  <parameter name="MEM_DIE_DENSITY_GBITS" value="4" />
  <parameter name="SYSINFO_DEVICE_GROUP" value="B" />
  <parameter name="MEM_MINNUMREFSREQ" value="8192.0" />
  <parameter name="MEM_TREFI_NS" value="3904.0" />
  <parameter name="EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ" value="100" />
  <parameter name="TURNAROUND_R2W_SAMECS_CYC" value="0" />
  <parameter name="MEM_CHANNEL_CS_WIDTH" value="1" />
  <parameter name="SYSINFO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="PHY_TERM_X_R_S_CK_OUTPUT_OHM" value="SERIES_40_OHM_CAL" />
  <parameter name="INSTANCE_ID" value="0" />
  <parameter name="MEM_TCKEHCMD_NS" value="7.5" />
  <parameter name="MEM_TRPPB_NS" value="18.0" />
  <parameter name="PHY_TERM_X_R_S_DQ_OUTPUT_OHM" value="SERIES_40_OHM_CAL" />
  <parameter name="PHY_TERM_X_DQ_VREF" value="17.5" />
  <parameter name="MEM_NUM_IO96" value="1" />
  <parameter name="MEM_TRCD_NS" value="18.0" />
  <parameter name="AXI4_ADDR_WIDTH" value="30" />
  <parameter name="MEM_ODT_DQ_X_IDLE" value="off" />
  <parameter name="S2_AXID_WIDTH" value="7" />
  <parameter name="MEM_TRC_NS" value="63.0" />
  <parameter name="MEM_OPERATING_FREQ_MHZ" value="1066.667" />
  <parameter name="PLACEMENT_SCHEMES" value="LPDDR4_X32_BOT" />
  <parameter name="MEM_NUM_CHANNELS_PER_IO96" value="1" />
  <parameter name="PHY_AC_PLACEMENT" value="BOT" />
  <parameter name="MEM_CA_WIDTH" value="6" />
  <parameter name="CTRL_AUTO_PRECHARGE_EN" value="false" />
  <parameter name="PHY_REFCLK_FREQ_MHZ_AUTOSET_EN" value="false" />
  <parameter name="PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN" value="true" />
  <parameter name="MEM_DQ_VREF" value="20" />
  <parameter name="MEM_TCMDCKE_NS" value="2.81" />
  <parameter name="EX_DESIGN_GEN_SYNTH" value="true" />
  <parameter name="EX_DESIGN_PMON_CH2_EN" value="false" />
  <parameter name="MEM_NUM_CHANNELS" value="1" />
  <parameter name="MEM_TXSR_NS" value="187.5" />
  <parameter name="EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN" value="true" />
  <parameter name="TURNAROUND_W2W_SAMECS_CYC" value="0" />
  <parameter name="EX_DESIGN_PMON_INTERNAL_JAMB_EN" value="true" />
  <parameter name="PHY_TERM_X_GPIO_IO_STD_TYPE" value="LVCMOS" />
  <parameter name="MEM_TRAS_NS" value="42.0" />
  <parameter name="ADV_CAL_ENABLE_REQ" value="true" />
  <parameter name="MEM_CHANNEL_ADDR_NUM_BITS" value="33" />
  <parameter name="MEM_CS_WIDTH" value="1" />
  <parameter name="SYSINFO_DEVICE_IOBANK_REVISION" value="IO96B_REVB1" />
  <parameter name="ADV_CAL_ENABLE_MARGIN" value="true" />
  <parameter name="MEM_PER_BANK_REF_EN" value="1" />
  <parameter name="PHY_MAINBAND_ACCESS_MODE" value="ASYNC" />
  <parameter name="MEM_DQ_PER_DQS" value="8" />
  <parameter name="MEM_ROW_ADDR_WIDTH" value="15" />
  <parameter name="MEM_CWL_CYC" value="18" />
  <parameter
     name="JEDEC_OVERRIDE_TABLE_PARAM_NAME"
     value="MEM_TRFCAB_NS,MEM_TRFCPB_NS,MEM_TCCD_NS,MEM_RD_POSTAMBLE_CYC,MEM_WR_POSTAMBLE_CYC,MEM_TCMDCKE_NS,MEM_TCKCKEH_NS,MEM_TZQCKE_NS,MEM_TESCKE_NS" />
  <parameter name="EX_DESIGN_TG_PROGRAM" value="MEDIUM" />
  <parameter name="S3_AXID_WIDTH" value="6" />
  <parameter name="MEM_RD_PREAMBLE_CYC" value="0" />
  <parameter name="EX_DESIGN_HDL_FORMAT" value="VERILOG" />
  <parameter name="MEM_TRFCAB_NS" value="180.0" />
  <parameter name="MEM_TSR_NS" value="15.0" />
  <parameter name="CTRL_WR_DBI_EN" value="false" />
  <parameter name="MEM_TPPD_CYC" value="4.0" />
  <parameter name="PHY_TERM_X_DQS_IO_STD_TYPE" value="DF_LVSTL" />
  <parameter name="MEM_CA_VREF" value="13" />
  <parameter name="PHY_CK_TX_EQUALIZATION" value="OFF" />
  <parameter name="MEM_CHANNEL_CAPACITY_GBITS" value="8.0" />
  <parameter name="SYSINFO_DEVICE_SPEEDGRADE" value="4" />
  <parameter name="MEM_TWR_NS" value="18.0" />
  <parameter name="MEM_TESCKE_NS" value="2.81" />
  <parameter name="MEM_TXP_NS" value="7.5" />
  <parameter name="CTRL_DM_EN" value="true" />
  <parameter name="ANALOG_PARAM_DERIVATION_PARAM_NAME" value="" />
  <parameter name="CTRL_SCRAMBLER_EN" value="false" />
  <parameter name="MEM_TECH_IS_X" value="false" />
  <parameter name="MEM_ODT_CA_X_CA_ENABLE" value="true" />
  <parameter name="SYSINFO_BOARD_TRAIT" value="" />
  <parameter name="PHY_SIDEBAND_ACCESS_MODE" value="FABRIC" />
  <parameter name="MEM_TWTR_NS" value="10.0" />
  <parameter name="MEM_TDQSCK_MAX_NS" value="3.5" />
  <parameter name="DIAG_HMC_ADDR_SWAP_EN" value="false" />
  <parameter name="SYSINFO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="MEM_TRRD_NS" value="10.0" />
  <parameter name="MEM_TCSCKEH_NS" value="1.75" />
  <parameter name="MEM_TCKCKEH_NS" value="2.81" />
  <parameter name="MEM_VREF_CA_X_CA_RANGE" value="2" />
  <parameter name="MEM_VREF_CA_X_CA_VALUE" value="27.2" />
  <parameter name="EX_DESIGN_GEN_SIM" value="true" />
  <parameter name="TURNAROUND_W2W_DIFFCS_CYC" value="0" />
  <parameter name="MEM_TCKELCMD_NS" value="5.0" />
  <parameter name="EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ" value="100.0" />
  <parameter name="MEM_ODT_CA_X_CA_COMM" value="3" />
  <parameter name="MEM_TMRR_NS" value="7.5" />
  <parameter name="PHY_AC_TX_EQUALIZATION" value="OFF" />
  <parameter name="CTRL_ECC_INLINE_EN" value="false" />
  <parameter name="MEM_COL_ADDR_WIDTH" value="10" />
  <parameter name="EX_DESIGN_PMON_CH1_EN" value="false" />
  <parameter name="MEM_TCKELCK_NS" value="5.0" />
  <parameter name="PHY_TERM_X_R_S_AC_OUTPUT_OHM" value="SERIES_40_OHM_CAL" />
  <parameter name="MEM_CK_WIDTH" value="1" />
  <parameter name="MEM_TCCD_NS" value="8.0" />
  <parameter name="PHY_TERM_X_DQ_SLEW_RATE" value="FASTEST" />
  <parameter name="PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN" value="true" />
  <parameter name="MEM_TDQSCK_MIN_NS" value="1.5" />
  <parameter name="DIAG_FORCE_SLIM_EN" value="false" />
  <parameter name="EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ" value="310.0" />
  <parameter name="SYSINFO_DEVICE_DIE_REVISIONS" value="MAIN_SM4_REVB" />
  <parameter name="TURNAROUND_W2R_SAMECS_CYC" value="0" />
  <parameter name="CTRL_RD_DBI_EN" value="true" />
  <parameter name="TURNAROUND_R2R_DIFFCS_CYC" value="0" />
  <parameter name="PHY_REFCLK_ADVANCED_SELECT_EN" value="true" />
  <parameter name="TURNAROUND_R2R_SAMECS_CYC" value="0" />
  <parameter name="EX_DESIGN_TG_CSR_ACCESS_MODE" value="JTAG" />
  <parameter name="MEM_VREF_DQ_X_VALUE" value="18.0" />
  <parameter name="PHY_TERM_X_R_S_CS_OUTPUT_OHM" value="SERIES_40_OHM_CAL" />
  <parameter name="PHY_TERM_X_AC_OUTPUT_IO_STD_TYPE" value="LVSTL" />
  <parameter name="NUM_IO96_IN_CHIP" value="2" />
  <parameter name="MEM_ODT_DQ_X_RON" value="6" />
  <parameter name="MEM_VREF_DQ_X_RANGE" value="1" />
  <parameter name="S1_AXID_WIDTH" value="6" />
  <parameter name="EX_DESIGN_PMON_EN" value="true" />
  <parameter name="SYSINFO_SUPPORTS_VID" value="0" />
  <parameter name="ADV_CAL_ENABLE_WEQ" value="true" />
  <parameter name="PHY_TERM_X_R_T_DQ_INPUT_OHM" value="RT_50_OHM_CAL" />
  <parameter name="MEM_ODT_CA_X_CK_ENABLE" value="true" />
  <parameter name="S0_AXID_WIDTH" value="7" />
  <parameter name="MEM_TMRD_NS" value="14.0" />
  <parameter name="EX_DESIGN_GEN_CDC" value="false" />
  <parameter name="MEM_TFAW_NS" value="40.0" />
  <parameter name="MEM_TZQCKE_NS" value="2.81" />
  <parameter name="MEM_TMRW_NS" value="10.0" />
  <parameter name="MEM_RD_POSTAMBLE_CYC" value="1" />
  <parameter name="MEM_OPERATING_FREQ_MHZ_AUTOSET_EN" value="false" />
  <parameter name="SYSINFO_BOARD" value="default" />
  <parameter name="DIAG_EXTRA_PARAMETERS" value="" />
  <parameter name="MEM_TCSCKE_NS" value="1.75" />
  <parameter name="PHY_TERM_X_DQ_IO_STD_TYPE" value="LVSTL" />
  <parameter name="SYSINFO_DEVICE_BASE_DIE" value="SM4REVB" />
  <parameter name="TURNAROUND_W2R_DIFFCS_CYC" value="0" />
  <parameter name="MEM_TRTP_NS" value="7.5" />
  <parameter name="CTRL_PERFORMANCE_PROFILE" value="SEQ" />
  <parameter name="EX_DESIGN_PMON_CH3_EN" value="false" />
  <parameter name="PHY_REFCLK_FREQ_MHZ" value="166.6667" />
  <parameter name="MEM_ODT_DQ_X_TGT_WR" value="5" />
  <parameter name="MEM_BANK_ADDR_WIDTH" value="3" />
  <parameter name="MEM_CL_CYC" value="22" />
  <parameter name="MEM_TREFW_NS" value="3.2E7" />
  <parameter name="CTRL_ECC_AUTOCORRECT_EN" value="false" />
  <parameter name="MEM_WR_POSTAMBLE_CYC" value="1" />
  <parameter name="MEM_TCKE_NS" value="7.5" />
  <parameter name="PHY_TERM_X_CK_OUTPUT_IO_STD_TYPE" value="DF_LVSTL" />
  <parameter name="PHY_DQ_TX_EQUALIZATION" value="OFF" />
  <parameter name="MEM_TZQCAL_NS" value="1000.0" />
  <parameter name="MEM_CHANNEL_DATA_DQ_WIDTH" value="32" />
  <parameter name="MEM_TMRWCKEL_NS" value="14.0" />
  <parameter name="MEM_ODT_CA_X_CS_ENABLE" value="true" />
  <parameter name="SYSINFO_DEVICE_POWER_MODEL" value="STANDARD_POWER_FIXED" />
  <parameter
     name="PHY_SWIZZLE_MAP"
     value="PIN_SWIZZLE_CH0_DQS0=5,4,0,7,1,6,2,3;PIN_SWIZZLE_CH0_DQS1=15,8,14,9,12,13,11,10;PIN_SWIZZLE_CH0_DQS2=18,22,19,20,21,23,16,17;PIN_SWIZZLE_CH0_DQS3=27,29,28,26,24,25,31,30;" />
  <parameter name="MEM_WLS" value="1.0" />
  <parameter name="DEBUG_TOOLS_EN" value="true" />
  <parameter name="MEM_TRFCPB_NS" value="90.0" />
  <parameter name="PHY_TERM_X_CS_OUTPUT_IO_STD_TYPE" value="LVSTL" />
  <parameter name="PHY_TERM_X_REFCLK_IO_STD_TYPE" value="TRUE_DIFF" />
  <parameter name="PHY_TERM_X_R_T_REFCLK_INPUT_OHM" value="RT_DIFF" />
  <parameter name="MEM_CKE_WIDTH" value="1" />
  <parameter name="EMIF_INST_NAME" value="" />
  <parameter name="MEM_TCKCKEL_NS" value="5.0" />
  <parameter name="IS_HPS" value="false" />
  <parameter name="EX_DESIGN_PMON_CH0_EN" value="true" />
  <parameter name="TURNAROUND_R2W_DIFFCS_CYC" value="0" />
  <parameter name="SYSINFO_DEVICE_TEMPERATURE_GRADE" value="EXTENDED" />
  <parameter name="MEM_TRPAB_NS" value="21.0" />
  <parameter name="PHY_TERM_X_R_T_GPIO_INPUT_OHM" value="RT_OFF" />
  <parameter name="MEM_TZQLAT_NS" value="30.0" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_arch_top.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/altera_std_synchronizer_nocut.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/emif_io96b_interface.svh"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/emif_io96b_lib.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/emif_io96b_clk_div.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_jedec_params.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_timing_parameters.tcl"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry.sdc"
       attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_timing_pins.tcl"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_timing_utils.tcl"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_report_timing_core.tcl"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_report_timing.tcl"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_pin_locations.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_byte.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_byte_ctrl.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_cpa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_fa_c2p_hmc.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_fa_p2c_hmc.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_fa_c2p_lane.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_fa_p2c_lane.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_fa_noc.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_hmc_wide.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_hmc_slim.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_pa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_pll.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_bufs_mem.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_mc_wide_seq_pt_synth.hex"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_mc_wide_seq_pt_synth.txt"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_bufs_mem.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_byte.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_byte_ctrl.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_cpa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_fa_noc.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_hmc_wide.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_hmc_slim.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_pa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_pll.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_reftree.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_fa_hmc.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_fa_lane.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_fbr_axi_adapter_wide.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_fbr_axi_adapter_slim.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_io96b_top.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_arch_top.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/altera_std_synchronizer_nocut.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/emif_io96b_interface.svh"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/emif_io96b_lib.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/emif_io96b_clk_div.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_jedec_params.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_timing_parameters.tcl"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry.sdc"
       attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_timing_pins.tcl"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_timing_utils.tcl"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_report_timing_core.tcl"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_report_timing.tcl"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_pin_locations.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_byte.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_byte_ctrl.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_cpa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_fa_c2p_hmc.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_fa_p2c_hmc.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_fa_c2p_lane.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_fa_p2c_lane.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_fa_noc.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_hmc_wide.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_hmc_slim.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_pa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_pll.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_attr_bufs_mem.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_mc_wide_seq_pt_synth.hex"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_mc_wide_seq_pt_synth.txt"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_bufs_mem.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_byte.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_byte_ctrl.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_cpa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_fa_noc.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_hmc_wide.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_hmc_slim.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_pa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_pll.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_reftree.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_fa_hmc.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_atom_inst_fa_lane.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_fbr_axi_adapter_wide.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_fbr_axi_adapter_slim.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/io96b_0/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry_io96b_top.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
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       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/emif_io96b/ip_lpddr4/emif_io96b_lpddr4_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcmodel.components.hwtclvalidator.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcmodel.components.tclelement.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopc.generator.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.ddmwriter.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcdocument.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.hdlwriter.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcmodel.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.common.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.intel.quartus.ngpd.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.intel.shared.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jacl1.3.2a.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/commons-text-1.10.0.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/commons-lang3-3.12.0.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/guava-32.0.1-jre.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jfreechart-1.5.0.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/miglayout-swing-5.2.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/docking-frames-common-1.1.2_20c.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/bare-bones-browser-launch-3.2.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jaxb-api.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jaxb-jxc.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jaxb-runtime.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jaxb-xjc.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/codemodel.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/dtd-parser.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/FastInfoset.jar" />
   <file
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   <file
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   <file
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   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/relaxng-datatype.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/rngom.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/stax-ex.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/txw2.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/xsom.jar" />
   <file
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   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/listenablefuture-9999.0-empty-to-avoid-conflict-with-guava.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/jsr305-3.0.2.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/checker-qual-3.33.0.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/j2objc-annotations-2.8.jar" />
   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/miglayout-core-5.2.jar" />
   <file
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   <file path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/commons-io-2.13.0.jar" />
   <file
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   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.privateinterfaces.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.ipxact.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/antlr4-runtime-4.7.2.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopclibrary.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcmodel.atlantic.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.ipxact.module.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.intel.quartus.dni.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcreport.build.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.sopcreport.jar" />
   <file
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   <file
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   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.hypericonnect.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.qsys.cmsis.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.hdlcomponent.jar" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/qsys/lib/com.altera.tcl.interpreter.jar" />
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  <childSourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/emif_io96b/ip_cal/ip/emif_io96b_cal_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/alt_mem_if/alt_mem_if_jtag_master/alt_mem_if_jtag_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_avalon_st_jtag_interface_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_bytes_to_packets/altera_avalon_st_bytes_to_packets_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_packets_to_master/altera_avalon_packets_to_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
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  <instantiator instantiator="EMIF_Qsys_emif_io96b_lpddr4_0" as="emif_io96b_lpddr4_0" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry"</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: HMC=0 (0: Wide/1: Slim) is_used=1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tck_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcl_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcl_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tch_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tch_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tras to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trrd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trcd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tccdmw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsq to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trpre to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trpst to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqss_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqss_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twpre to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twpst to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twtr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trppb to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trpab to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtp to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdipw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdss to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdsh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsl to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tck_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tch_abs_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tch_abs_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcl_abs_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcl_abs_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting clkCyclesToAverageOver to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tjit_per_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tjit_per_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tjit_cc_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tjit_cc_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckdl to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckdlRollingWindowL to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckdm to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckdlRollingWindowM to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckds to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckdlRollingWindowS to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsl_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsh_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tras_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_start to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtp_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trcd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trppb_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trpab_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tras_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twr_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twtr_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trrd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trpste to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting txp to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting txp_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trfcab to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trfcpb to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trefw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting txsv to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting txsv_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckckel to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckckel_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting writeTL to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting readTL to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tsr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tsr_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tinit1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tinit2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tinit3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tinit4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tinit5 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqcal to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqlat to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tck_min_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tck_max_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tiscke_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tihcke_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_min_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_max_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsq_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tiscke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tihcke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting powerUpTime to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqreset to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqreset_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tadr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvreflong to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcaent to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrz to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tsdramDerating to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelcmd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckehcmd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelpd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tescke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcmdcke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckckeh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcsckeh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twlmrd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twldqsen to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twls to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twlh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twlo to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twlo_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelcmd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckehcmd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelpd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcke_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tODTon_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tODTon_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tODToff_min to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tODToff_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tfaw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tppd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcipw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twrwtr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twrwtr_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtrrd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtrrd_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtm to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtm_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcsvref to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tfc to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdstrain to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdhtrain to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tpw_reset to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckprecs to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckpstcs to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspe to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspx to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckprecs_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckpstcs_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspe_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspx_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckelck_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckprewl_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckpstwl_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrcg_enable to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrcg_disable to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqlat_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqscke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqscke_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckehdqs to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrw_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrefmed to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrefshort to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tfcmed to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tfcshort to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twtm to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twtm_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcscke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqcke to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tzqcke_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckckeh_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcmdcke_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tpgm to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tpgm_exit to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tpgmpst to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tescke_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrwckel to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tmrwckel_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tsdo to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tsdo_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting txsr_abort to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckprewl to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckpstwl to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tlat to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tosco to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tfaw_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspe_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tosco_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trtwcorrection to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tpbr2pbr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcmdtp to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tderate to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspe_se to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspx_se to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_random_ch_a to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_random_ch_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcacdm2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspe_se_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tckfspx_se_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcacdm2_minTck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trefrate to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trefrate_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq_variation to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq_variation_ch_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs2dq_variation_max to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsta to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrefweak to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrefca_long to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tvrefca_short to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting twdqstol to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trfmab to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting trfmpb to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsckj to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_drift to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqsck_drift_win to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcs_a to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcs_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcke_a to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tcke_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_a5 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tca_b5 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_a0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_a1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_b0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_b1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_a0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_a1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_b0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdmi_b1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_a0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_a1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_b0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_b1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_a0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_a1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_b0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_t_b1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_a0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_a1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_b0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_b1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_a0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_a1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_b0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdqs_c_b1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a5 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a6 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a7 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a8 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a9 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a10 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a11 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a12 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a13 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a14 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a15 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a2O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a3O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a4O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a5O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a6O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a7O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a8O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a9O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a10O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a11O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a12O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a13O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a14O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_a15O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b0 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b5 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b6 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b7 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b8 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b9 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b10 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b11 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b12 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b13 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b14 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b15 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b0O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b1O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b2O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b3O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b4O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b5O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b6O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b7O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b8O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b9O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b10O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b11O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b12O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b13O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b14O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: MEM_GLOBAL_DICT: Setting tdq_b15O to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegDeviceInfo to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegDevFt1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegDevFt2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegIoCfg1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegRefOrTemp to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegBasicCfg1 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegBasicCfg2 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegBasicCfg3 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegBasicCfg4 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegTestMode to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegIOCalib to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg11 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg12 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg13 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg14 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg15 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg16 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg17 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg18 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg19 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg20 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg21 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg22 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg23 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg32 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg40 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting minNumOfRefsReqd to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numRefsPostponedMax to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numRefsPulledInMax to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg24 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting validDataBeatDuringMRR to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numRefsWithin2trefi to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting autoRefreshAtSREntry to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting VrefCASetting to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting VrefCADelta to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting VrefDQSetting to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting VrefDQDelta to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting delayDeratingAfterMR4ReadCycles to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numCumulativeRefsPostponedMax to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numCumulativeRefsPulledInMax to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting macLimit to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg25 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg26 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numDqsPulsesInWriteLeveling to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg31 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numDqsPulsesInCATraining to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dqsJitterVariance to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg27 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg36 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeReg37 to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting autoRefreshAtSRExit to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting useTmrwInsteadOfTfc to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting isSRCountedForPullin to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting zqIgnoreCrossChannelErrors to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting zqLatchCheckPDClockStop to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dqsOscCheckPDClockStop to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting isTrefiFixedForMaxPullin to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting refPostponeInTrefw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting modeRegDef to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting refreshReq to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting refreshDebugInfo to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting noXOnDataLineDuringMRR to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting skipInitialization to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting corruptOnMissingRefresh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting startRefreshCountPostFirstWrite to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting vrefSettings to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting generalSettings to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting ckeAsync to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting trainingSettings to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting ignoreTrainingSetupHoldErrors to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting enhancedRefresh to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting fifoDuringTrfcTxsr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting checkCKPulsePostCATrain to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dbiDuringMRR to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting isRefreshAllowedPostMaxPullin to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting firstCycleViolations to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting delayAutoPrecharge to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting latchVrefcaOn2DqsPulse to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting ignoreRefabIntfaw to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting extraCyclesPriorClockStop to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting useIgnoredRefPostMaxPullin to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting violationsAtClockStopEntry to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting zqCalCheckPDClockStop to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting writePreAmble4tck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dqsValidRegionDuringWrite to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting lpddr4e to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting extraWritePambleViolation to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting discountRefreshPostSRExit to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting corruptWriteLevelingDataOnSetupHoldErr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting exploration to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting enableTdqsicycCheck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting prevDataOnSetupHoldErr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting updateDQSOscReg to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting lowerByteDevice to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting randomDqsJitter to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting randomDqsGlitch to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting bypassModel to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting enableClkErrors to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting randomDqsGlitch_ch_b to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dqsSharedBetweenChannels to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting isDiffValidInSEMode to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting randomInsteadOfXInWriteDataOnBurstErr to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting skipMissedBeatDuringWriteBurst to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting allowInvalidClkDuringtCKFSPESEMode to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting startInSelfRefreshState to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting trCallbackOnNop to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting clkStopChecks to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting isNopValid to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting lpddr4x to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting doNotAllowResetInInit to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting support64GbDensityPerDie to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CK_t_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CK_c_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CK_t_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CK_c_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CKE_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CKE_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CS_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CS_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CA_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting CA_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting ODT_CA_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting ODT_CA_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQ_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQ_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQS_t_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQS_c_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQS_t_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DQS_c_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DMI_A to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting DMI_B to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting RESET_n to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting dataCallbackForInvalidDataBeatDuringMRR to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting applyRefRateAfterMR4BackdoorWrite to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting disRAAUpdateWhenShorttREFI to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting lowInsteadOfXForInvalidCalibData to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting skipCkDiffCheckDuringSeToDiffSwitch to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting controlledRandDqsck to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting monitorMode to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting resetMemContentsAfterReset to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting memSizeMbits to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting numBanks to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: csMemParms: Setting columnAddrWidth to SOMA_UNASSIGNED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global dq_per_dqs</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0A</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0B</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0C</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0D</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0E</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC0F</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC1X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC2X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC3X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC4X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC5X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC6X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC7X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC8X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RC9X</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RCAX</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global DDR4_RCBX</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC DEBUG: deleting unwanted global Per_Bank_Refresh</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of numBanks: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter numBanks.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; numBanks = 8.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of rowWidth: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; rowWidth = 15.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of colWidth: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; colWidth = 10.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DQ_A: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter DQ_A.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; DQ_A = 16.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DQS_t_A: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter DQS_t_A.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; DQS_t_A = 2.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of memSizeMbits: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter memSizeMbits.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; memSizeMbits = 4096.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of minNumOfRefsReqd: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter minNumOfRefsReqd.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; minNumOfRefsReqd = 8192.0.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of data_mask_en: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; data_mask_en = true.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of modeRegBasicCfg4: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter modeRegBasicCfg4.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; modeRegBasicCfg4 = 0.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of dq_per_dqs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: LPDDR4 adding global parameter dq_per_dqs.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; dq_per_dqs = 8.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; Burst_Length = 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; CasLatencyList = 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; WR_CAS_Lat = 18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; SimMhzList = 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; AP_Sim = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; Additive_Lat = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; RDPREAMBLE_EN = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; BOF_EN = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; WLS_EN = 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; RDDBI_EN = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; WRDBI_EN = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; RDPSTMBLE_EN = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; WRPSTMBLE_EN = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; CRC_EN = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; CRC_Enable = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; BANKModeList = 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; RD_Link_ECC = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; WR_Link_ECC = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; X8_Device = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; CA_Parity_Lat = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; Fine_Granularity_Refresh = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; Per_Bank_Refresh = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; VDD_RANGE = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; DFI_Cmd_Ratio_4to1 = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; is_x4 = 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TSR_NS = 15.0: tsr = SOMA_UNASSIGNED --&gt; {15.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Global Parameter txsr does not exist</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TXP_NS = 7.5: txp = SOMA_UNASSIGNED --&gt; {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Global Parameter tccd does not exist</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRTP_NS = 7.5: trtp = SOMA_UNASSIGNED --&gt; {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRCD_NS = 18.0: trcd = SOMA_UNASSIGNED --&gt; {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRPPB_NS = 18.0: trppb = SOMA_UNASSIGNED --&gt; {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRPAB_NS = 21.0: trpab = SOMA_UNASSIGNED --&gt; {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRAS_NS = 42.0: tras = SOMA_UNASSIGNED --&gt; {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TWR_NS = 18.0: twr = SOMA_UNASSIGNED --&gt; {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TWTR_NS = 10.0: twtr = SOMA_UNASSIGNED --&gt; {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRRD_NS = 10.0: trrd = SOMA_UNASSIGNED --&gt; {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TPPD_CYC = 4.0: tppd = SOMA_UNASSIGNED --&gt; {4.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TFAW_NS = 40.0: tfaw = SOMA_UNASSIGNED --&gt; {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Global Parameter trc does not exist</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">converting from NS to ms (MEM_TREFW_NS=3.2E7)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TREFW_MS = 32.0: trefw = SOMA_UNASSIGNED --&gt; {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Global Parameter trefi does not exist</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRFCAB_NS = 180.0: trfcab = SOMA_UNASSIGNED --&gt; {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TRFCPB_NS = 90.0: trfcpb = SOMA_UNASSIGNED --&gt; {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKE_NS = 7.5: tcke = SOMA_UNASSIGNED --&gt; {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCMDCKE_NS = 2.81: tcmdcke = SOMA_UNASSIGNED --&gt; {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKELCK_NS = 5.0: tckelck = SOMA_UNASSIGNED --&gt; {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCSCKE_NS = 1.75: tcscke = SOMA_UNASSIGNED --&gt; {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKCKEH_NS = 2.81: tckckeh = SOMA_UNASSIGNED --&gt; {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCSCKEH_NS = 1.75: tcsckeh = SOMA_UNASSIGNED --&gt; {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TMRWCKEL_NS = 14.0: tmrwckel = SOMA_UNASSIGNED --&gt; {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TZQCKE_NS = 2.81: tzqcke = SOMA_UNASSIGNED --&gt; {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">converting from NS to cyc (MEM_TMRR_NS=7.5)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TMRR_CYC = 8.0: tmrr = SOMA_UNASSIGNED --&gt; {8.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TMRW_NS = 10.0: tmrw = SOMA_UNASSIGNED --&gt; {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TMRD_NS = 14.0: tmrd = SOMA_UNASSIGNED --&gt; {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TESCKE_NS = 2.81: tescke = SOMA_UNASSIGNED --&gt; {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">converting from NS to us (MEM_TZQCAL_NS=1000.0)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TZQCAL_US = 1.0: tzqcal = SOMA_UNASSIGNED --&gt; {1.0 us}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TZQLAT_NS = 30.0: tzqlat = SOMA_UNASSIGNED --&gt; {30.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">converting from NS to ps (MEM_TDQSCK_MAX_NS=3.5)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TDQSCK_MAX_PS = 3500.0: tdqsck_max = SOMA_UNASSIGNED --&gt; {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">converting from NS to ps (MEM_TDQSCK_MIN_NS=1.5)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TDQSCK_MIN_PS = 1500.0: tdqsck_min = SOMA_UNASSIGNED --&gt; {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKCKEL_NS = 5.0: tckckel = SOMA_UNASSIGNED --&gt; {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKELCMD_NS = 5.0: tckelcmd = SOMA_UNASSIGNED --&gt; {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite Timing Parameters: MEM_TCKEHCMD_NS = 7.5: tckehcmd = SOMA_UNASSIGNED --&gt; {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_drive_strength: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_drive_strength = 6.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_rtt_dq: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_rtt_dq = 5.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_rx_vref_dq: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_rx_vref_dq = 20.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_rx_vref_dq_range: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_rx_vref_dq_range = 0.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_ca_vref_range: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_ca_vref_range = 1.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_ca_vref_value: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_ca_vref_value = 13.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_ca_comm_odt: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_ca_comm_odt = 3.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_ck_odt_en: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_ck_odt_en = 1.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_cs_odt_en: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_cs_odt_en = 1.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lpddr4_ca_odt_dis: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Overwrite LPDDR4 Parameters --&gt; lpddr4_ca_odt_dis = 0.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of componentDdrSOMA: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Rows_Supported: Parameter value 18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_Columns_Supported: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Columns_Supported: Parameter value 11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep_x40: Parameter value false</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of numChannels: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of HMC_Interface: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_enabled: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Memory_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: cadence_reg__MEM_DP_REDUCTION: is_lockstep_x40=false num_channels=1 dq_per_channel=32 hmc_interface=0 ecc_enabled=0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__START" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__START --&gt; Returned 0: CADENCE_DEBUG_REG: START:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DRAM_CLASS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DRAM_CLASS --&gt; Returned 11: CADENCE_DEBUG_REG: DRAM_CLASS:RW:8:4:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CONTROLLER_ID" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CONTROLLER_ID --&gt; Returned 4166: CADENCE_DEBUG_REG: CONTROLLER_ID:RD:16:16:=0x1046</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CONTROLLER_VERSION (CONTROLLER_VERSION RD CONTROLLER_VERSION ZERO ZERO FULL CTL {{Holds the controller version id. READ-ONLY }} 32 OPEN WIRE WIRE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MAX_ROW_REG (MAX_ROW_REG RD ROW_WIDTH ZERO ROW_WIDTH ROW_WIDTH CTL {{Holds the maximum width of memory address bus. READ-ONLY }} 96 OPEN WIRE WIRE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MAX_COL_REG" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_Columns_Supported: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Columns_Supported: Parameter value 11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MAX_COL_REG --&gt; Returned 11: CADENCE_DEBUG_REG: MAX_COL_REG:RD:8:4:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MAX_CS_REG (MAX_CS_REG RD MAX_CS ZERO MAX_CS FULL CTL {{Holds the maximum number of chip selects available. READ-ONLY }} 112 OPEN WIRE WIRE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WRITE_DATA_FIFO_DEPTH (WRITE_DATA_FIFO_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the controller core write data latency queue. READ-ONLY }} 120 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WRITE_DATA_FIFO_PTR_WIDTH (WRITE_DATA_FIFO_PTR_WIDTH RD {} ZERO ZERO FULL CTL {{Reports the width of the controller core write data latency queue pointer. READ-ONLY }} 128 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MEMCD_RMODW_FIFO_DEPTH (MEMCD_RMODW_FIFO_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the controller core read/modify/write FIFO. READ-ONLY }} 136 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MEMCD_RMODW_FIFO_PTR_WIDTH (MEMCD_RMODW_FIFO_PTR_WIDTH RD {} ZERO ZERO FULL CTL {{Reports the width of the controller core read/modify/write FIFO pointer. READ-ONLY }} 152 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ASYNC_CDC_STAGES (ASYNC_CDC_STAGES RD {} ZERO ZERO FULL CTL {{Reports the number of synchronizer delays specified for the asynchronous boundary crossings. READ-ONLY }} 160 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AXI0_CMDFIFO_LOG2_DEPTH (AXI0_CMDFIFO_LOG2_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the AXI port 0 command FIFO. Value is the log2 value of the depth. READ-ONLY }} 168 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AXI0_RDFIFO_LOG2_DEPTH (AXI0_RDFIFO_LOG2_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the AXI port 0 read data FIFO. Value is the log2 value of the depth. READ-ONLY }} 176 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AXI0_WR_ARRAY_LOG2_DEPTH (AXI0_WR_ARRAY_LOG2_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the AXI port 0 write data array. Value is the log2 value of the depth. READ-ONLY }} 184 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AXI0_TRANS_WRFIFO_LOG2_DEPTH (AXI0_TRANS_WRFIFO_LOG2_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the AXI port 0 transition write data FIFO. Value is the log2 value of the depth. READ-ONLY }} 192 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH (AXI0_WRCMD_PROC_FIFO_LOG2_DEPTH RD {} ZERO ZERO FULL CTL {{Reports the depth of the AXI port 0 write command processing FIFO. Value is the log2 value of the depth. READ-ONLY }} 200 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NO_AUTO_MRR_INIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NO_AUTO_MRR_INIT --&gt; Returned 0: CADENCE_DEBUG_REG: NO_AUTO_MRR_INIT:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MRR_ERROR_STATUS (MRR_ERROR_STATUS RD {} ZERO ZERO FULL CTL {{Indicates that an MRR was issued while in self-refresh. Value of 1 indicates a violation. READ-ONLY }} 256 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_FREQ_RATIO 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_FREQ_RATIO 0 --&gt; Returned 2: CADENCE_DEBUG_REG: DFI_FREQ_RATIO_F0:RW:8:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_FREQ_RATIO 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_FREQ_RATIO 1 --&gt; Returned 2: CADENCE_DEBUG_REG: DFI_FREQ_RATIO_F1:RW:16:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_FREQ_RATIO 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_FREQ_RATIO 2 --&gt; Returned 2: CADENCE_DEBUG_REG: DFI_FREQ_RATIO_F2:RW:24:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_CMD_RATIO" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_CMD_RATIO --&gt; Returned 2: CADENCE_DEBUG_REG: DFI_CMD_RATIO:RD:0:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_VALUE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_VALUE --&gt; Returned 1: CADENCE_DEBUG_REG: ODT_VALUE:RW:8:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHY_INDEP_TRAIN_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHY_INDEP_TRAIN_MODE --&gt; Returned 1: CADENCE_DEBUG_REG: PHY_INDEP_TRAIN_MODE:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TSREF2PHYMSTR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TSREF2PHYMSTR --&gt; Returned 16: CADENCE_DEBUG_REG: TSREF2PHYMSTR:RW:24:6:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHY_INDEP_INIT_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHY_INDEP_INIT_MODE --&gt; Returned 1: CADENCE_DEBUG_REG: PHY_INDEP_INIT_MODE:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFIBUS_FREQ 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFIBUS_FREQ 0 --&gt; Returned 0: CADENCE_DEBUG_REG: DFIBUS_FREQ_F0:RW:8:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFIBUS_FREQ 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFIBUS_FREQ 1 --&gt; Returned 1: CADENCE_DEBUG_REG: DFIBUS_FREQ_F1:RW:16:5:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFIBUS_FREQ 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFIBUS_FREQ 2 --&gt; Returned 2: CADENCE_DEBUG_REG: DFIBUS_FREQ_F2:RW:24:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__FREQ_CHANGE_TYPE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FREQ_CHANGE_TYPE 0 --&gt; Returned 0: CADENCE_DEBUG_REG: FREQ_CHANGE_TYPE_F0:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__FREQ_CHANGE_TYPE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FREQ_CHANGE_TYPE 1 --&gt; Returned 1: CADENCE_DEBUG_REG: FREQ_CHANGE_TYPE_F1:RW:8:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__FREQ_CHANGE_TYPE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FREQ_CHANGE_TYPE 2 --&gt; Returned 2: CADENCE_DEBUG_REG: FREQ_CHANGE_TYPE_F2:RW:16:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS (LPC_SW_ENTER_DQS_OSC_IN_PROGRESS_ERR_STATUS RD {} ZERO ZERO FULL CTL {{Error response for Software issued Low power command while DQS Oscillator is in progress. READ-ONLY }} 376 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_PER_CS_OOV_TRAINING_STATUS (DQS_OSC_PER_CS_OOV_TRAINING_STATUS RD {} ZERO ZERO FULL CTL {{Set the CS information for which DQS oscillator is having out of variance value. READ-ONLY }} 384 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_TST" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_TST --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_TST:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_MPC_CMD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_MPC_CMD --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_MPC_CMD:RW:0:28:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_LSB_REG" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_LSB_REG --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_LSB_REG:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_MSB_REG" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_MSB_REG --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_MSB_REG:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_ENABLE:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_PERIOD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_PERIOD --&gt; Returned 512: CADENCE_DEBUG_REG: DQS_OSC_PERIOD:RW:0:15:=0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__FUNC_VALID_CYCLES" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FUNC_VALID_CYCLES --&gt; Returned 2: CADENCE_DEBUG_REG: FUNC_VALID_CYCLES:RW:16:4:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_NORM_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_NORM_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_NORM_THRESHOLD:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_HIGH_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_HIGH_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_HIGH_THRESHOLD:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_TIMEOUT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_TIMEOUT --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_TIMEOUT:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_PROMOTE_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_PROMOTE_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_PROMOTE_THRESHOLD:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__OSC_VARIANCE_LIMIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__OSC_VARIANCE_LIMIT --&gt; Returned 16: CADENCE_DEBUG_REG: OSC_VARIANCE_LIMIT:RW:0:16:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DQS_OSC_REQUEST" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DQS_OSC_REQUEST --&gt; Returned 0: CADENCE_DEBUG_REG: DQS_OSC_REQUEST:WR:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WCKO_OSC_PERIOD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WCKO_OSC_PERIOD --&gt; Returned 512: CADENCE_DEBUG_REG: WCKO_OSC_PERIOD:RW:0:15:=0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSCO 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tosco: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSCO 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSCO_F0:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSCO 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tosco: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSCO 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSCO_F1:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSCO 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tosco: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSCO 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSCO_F2:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSC_TRK_CALC 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {ttrkcalcinit ttrkcalccur}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalcinit: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalccur: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSC_TRK_CALC 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSC_TRK_CALC_F0:RW:8:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSC_TRK_CALC 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {ttrkcalcinit ttrkcalccur}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalcinit: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalccur: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSC_TRK_CALC 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSC_TRK_CALC_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TOSC_TRK_CALC 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {ttrkcalcinit ttrkcalccur}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalcinit: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ttrkcalccur: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TOSC_TRK_CALC 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TOSC_TRK_CALC_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_0_CS0 (DQS_OSC_BASE_VALUE_0_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 0 on chip 0. READ-ONLY DEV=0 }} 768 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_1_CS0 (DQS_OSC_BASE_VALUE_1_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 1 on chip 0. READ-ONLY DEV=1 }} 784 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_2_CS0 (DQS_OSC_BASE_VALUE_2_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 2 on chip 0. READ-ONLY DEV=2 }} 800 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_3_CS0 (DQS_OSC_BASE_VALUE_3_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 3 on chip 0. READ-ONLY DEV=3 }} 816 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_4_CS0 (DQS_OSC_BASE_VALUE_4_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 4 on chip 0. READ-ONLY DEV=4 }} 832 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_5_CS0 (DQS_OSC_BASE_VALUE_5_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 5 on chip 0. READ-ONLY DEV=5 }} 848 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_6_CS0 (DQS_OSC_BASE_VALUE_6_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 6 on chip 0. READ-ONLY DEV=6 }} 864 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_7_CS0 (DQS_OSC_BASE_VALUE_7_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 7 on chip 0. READ-ONLY DEV=7 }} 880 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_8_CS0 (DQS_OSC_BASE_VALUE_8_CS0 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 8 on chip 0. READ-ONLY DEV=8 }} 896 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_0_CS1 (DQS_OSC_BASE_VALUE_0_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 0 on chip 1. READ-ONLY DEV=0 }} 912 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_1_CS1 (DQS_OSC_BASE_VALUE_1_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 1 on chip 1. READ-ONLY DEV=1 }} 928 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_2_CS1 (DQS_OSC_BASE_VALUE_2_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 2 on chip 1. READ-ONLY DEV=2 }} 944 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_3_CS1 (DQS_OSC_BASE_VALUE_3_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 3 on chip 1. READ-ONLY DEV=3 }} 960 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_4_CS1 (DQS_OSC_BASE_VALUE_4_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 4 on chip 1. READ-ONLY DEV=4 }} 976 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_5_CS1 (DQS_OSC_BASE_VALUE_5_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 5 on chip 1. READ-ONLY DEV=5 }} 992 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_6_CS1 (DQS_OSC_BASE_VALUE_6_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 6 on chip 1. READ-ONLY DEV=6 }} 1008 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_7_CS1 (DQS_OSC_BASE_VALUE_7_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 7 on chip 1. READ-ONLY DEV=7 }} 1024 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_BASE_VALUE_8_CS1 (DQS_OSC_BASE_VALUE_8_CS1 RD {} DQS_OSC_BASE_VALUE ZERO FULL CTL {{Base value for device 8 on chip 1. READ-ONLY DEV=8 }} 1040 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_STATUS (DQS_OSC_STATUS RD {} ZERO ZERO FULL CTL {{Holds the overflow and out of variance status associated with the resp. interrupts. Bit (0) set indicates overflow of DQS oscillator,bit (1) set indicates overflow of WCKO oscillator,bit (2) set indicates oov of DQS oscillator,bit (3) set indicates oov of WCKO oscillator. READ-ONLY }} 1056 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_0_CS0 (WCKO_OSC_BASE_VALUE_0_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 0 on chip 0. READ-ONLY DEV=0 }} 1064 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_1_CS0 (WCKO_OSC_BASE_VALUE_1_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 1 on chip 0. READ-ONLY DEV=1 }} 1088 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_2_CS0 (WCKO_OSC_BASE_VALUE_2_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 2 on chip 0. READ-ONLY DEV=2 }} 1104 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_3_CS0 (WCKO_OSC_BASE_VALUE_3_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 3 on chip 0. READ-ONLY DEV=3 }} 1120 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_4_CS0 (WCKO_OSC_BASE_VALUE_4_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 4 on chip 0. READ-ONLY DEV=4 }} 1136 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_5_CS0 (WCKO_OSC_BASE_VALUE_5_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 5 on chip 0. READ-ONLY DEV=5 }} 1152 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_6_CS0 (WCKO_OSC_BASE_VALUE_6_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 6 on chip 0. READ-ONLY DEV=6 }} 1168 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_7_CS0 (WCKO_OSC_BASE_VALUE_7_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 7 on chip 0. READ-ONLY DEV=7 }} 1184 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_8_CS0 (WCKO_OSC_BASE_VALUE_8_CS0 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 8 on chip 0. READ-ONLY DEV=8 }} 1200 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_0_CS1 (WCKO_OSC_BASE_VALUE_0_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 0 on chip 1. READ-ONLY DEV=0 }} 1216 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_1_CS1 (WCKO_OSC_BASE_VALUE_1_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 1 on chip 1. READ-ONLY DEV=1 }} 1232 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_2_CS1 (WCKO_OSC_BASE_VALUE_2_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 2 on chip 1. READ-ONLY DEV=2 }} 1248 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_3_CS1 (WCKO_OSC_BASE_VALUE_3_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 3 on chip 1. READ-ONLY DEV=3 }} 1264 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_4_CS1 (WCKO_OSC_BASE_VALUE_4_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 4 on chip 1. READ-ONLY DEV=4 }} 1280 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_5_CS1 (WCKO_OSC_BASE_VALUE_5_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 5 on chip 1. READ-ONLY DEV=5 }} 1296 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_6_CS1 (WCKO_OSC_BASE_VALUE_6_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 6 on chip 1. READ-ONLY DEV=6 }} 1312 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_7_CS1 (WCKO_OSC_BASE_VALUE_7_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 7 on chip 1. READ-ONLY DEV=7 }} 1328 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCKO_OSC_BASE_VALUE_8_CS1 (WCKO_OSC_BASE_VALUE_8_CS1 RD {} WCKO_OSC_BASE_VALUE ZERO FULL CTL {{WCKO Oscillator Base value for device 8 on chip 1. READ-ONLY DEV=8 }} 1344 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DQS_OSC_IN_PROGRESS_STATUS (DQS_OSC_IN_PROGRESS_STATUS RD {} ZERO ZERO FULL CTL {{DQS Oscillator is in progress.Set '1' DQS OSC is in progress  READ-ONLY }} 1360 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CA_PARITY_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CA_PARITY_EN --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CA_PARITY_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CASLAT_LIN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CASLAT_LIN 0 --&gt; Returned 44: CADENCE_DEBUG_REG: CASLAT_LIN_F0:RW:0:8:=0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WRLAT_WITH_PL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Overriding HMC WRLAT with parity latency to 18.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WRLAT_WITH_PL 0 --&gt; Returned 18: CADENCE_DEBUG_REG: WRLAT_F0:RW:8:7:=0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDITIVE_LAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDITIVE_LAT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ADDITIVE_LAT_F0:RW:16:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_PARITY_LAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_PARITY_LAT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_PARITY_LAT_F0:RW:24:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSSR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSSR 0 --&gt; Returned 30: CADENCE_DEBUG_REG: TCSSR_F0:RW:0:8:=0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKSTAB 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKSTAB 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TCKSTAB_F0:RW:8:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD_PAR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD_PAR 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TMOD_PAR_F0:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CASLAT_LIN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CASLAT_LIN 1 --&gt; Returned 44: CADENCE_DEBUG_REG: CASLAT_LIN_F1:RW:8:8:=0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WRLAT_WITH_PL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Overriding HMC WRLAT with parity latency to 18.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WRLAT_WITH_PL 1 --&gt; Returned 18: CADENCE_DEBUG_REG: WRLAT_F1:RW:16:7:=0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDITIVE_LAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDITIVE_LAT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ADDITIVE_LAT_F1:RW:24:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_PARITY_LAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_PARITY_LAT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_PARITY_LAT_F1:RW:0:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSSR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSSR 1 --&gt; Returned 30: CADENCE_DEBUG_REG: TCSSR_F1:RW:8:8:=0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKSTAB 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKSTAB 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TCKSTAB_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD_PAR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD_PAR 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TMOD_PAR_F1:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CASLAT_LIN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CASLAT_LIN 2 --&gt; Returned 44: CADENCE_DEBUG_REG: CASLAT_LIN_F2:RW:16:8:=0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WRLAT_WITH_PL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Overriding HMC WRLAT with parity latency to 18.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WRLAT_WITH_PL 2 --&gt; Returned 18: CADENCE_DEBUG_REG: WRLAT_F2:RW:24:7:=0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDITIVE_LAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDITIVE_LAT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ADDITIVE_LAT_F2:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_PARITY_LAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_PARITY_LAT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_PARITY_LAT_F2:RW:8:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSSR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSSR 2 --&gt; Returned 30: CADENCE_DEBUG_REG: TCSSR_F2:RW:16:8:=0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKSTAB 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKSTAB 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TCKSTAB_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD_PAR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD_PAR 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TMOD_PAR_F2:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TBST_INT_INTERVAL" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_RMW: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_RMW: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TBST_INT_INTERVAL --&gt; Returned 4: CADENCE_DEBUG_REG: TBST_INT_INTERVAL:RW:0:3:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd tccd_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_s}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD --&gt; Returned 8: CADENCE_DEBUG_REG: TCCD:RW:8:5:=0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_F0:RW:16:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR 0 0 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCD_L_WR_F0:RW:24:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR2 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr2_time tccd_l_wr2_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_x4: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_x4: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR2 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_WR2_F0:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD 0 0 --&gt; Returned 11: CADENCE_DEBUG_REG: TRRD_F0:RW:8:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_L 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_l trrd_l_clk trrd_l_time tRRD_L tRRD_L_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_L 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_L_F0:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_dlr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_DLR_F0:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRC 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_135V_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trc trc_minTck tRC_time tRC_cycle}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRC 0 0 --&gt; Returned 65: CADENCE_DEBUG_REG: TRC_F0:RW:0:9:=0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MIN 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MIN 0 0 --&gt; Returned 45: CADENCE_DEBUG_REG: TRAS_MIN_F0:RW:16:9:=0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR 0 0 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_F0:RW:0:7:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_F0:RW:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_AP 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_AP 0 0 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_AP_F0:RW:16:9:=0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L_AP 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L_AP 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_AP_F0:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP 0 0 --&gt; Returned 20: CADENCE_DEBUG_REG: TRP_F0:RW:16:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW 0 0 --&gt; Returned 43: CADENCE_DEBUG_REG: TFAW_F0:RW:0:9:=0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw_dlr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TFAW_DLR_F0:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_F1:RW:0:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR 0 1 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCD_L_WR_F1:RW:8:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR2 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr2_time tccd_l_wr2_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_x4: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_x4: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR2 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_WR2_F1:RW:16:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 1 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD 0 1 --&gt; Returned 11: CADENCE_DEBUG_REG: TRRD_F1:RW:24:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_L 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_l trrd_l_clk trrd_l_time tRRD_L tRRD_L_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_L 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_L_F1:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_dlr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_DLR_F1:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRC 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_135V_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trc trc_minTck tRC_time tRC_cycle}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRC 0 1 --&gt; Returned 65: CADENCE_DEBUG_REG: TRC_F1:RW:16:9:=0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MIN 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MIN 0 1 --&gt; Returned 45: CADENCE_DEBUG_REG: TRAS_MIN_F1:RW:0:9:=0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR 0 1 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_F1:RW:16:7:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_F1:RW:24:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_AP 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_AP 0 1 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_AP_F1:RW:0:9:=0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L_AP 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L_AP 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_AP_F1:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP 0 1 --&gt; Returned 20: CADENCE_DEBUG_REG: TRP_F1:RW:0:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW 0 1 --&gt; Returned 43: CADENCE_DEBUG_REG: TFAW_F1:RW:8:9:=0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw_dlr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TFAW_DLR_F1:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_F2:RW:16:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR 0 2 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCD_L_WR_F2:RW:24:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_L_WR2 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr_time tccd_l_wr_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tccd_l_wr2_time tccd_l_wr2_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_wr2_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_x4: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_x4: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_L_WR2 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_L_WR2_F2:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 2 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD 0 2 --&gt; Returned 11: CADENCE_DEBUG_REG: TRRD_F2:RW:8:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_L 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_l trrd_l_clk trrd_l_time tRRD_L tRRD_L_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_L_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_L 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_L_F2:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRRD_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd_dlr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRRD_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRRD_DLR_F2:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRC 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_135V_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trc trc_minTck tRC_time tRC_cycle}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trc_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRC_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRC 0 2 --&gt; Returned 65: CADENCE_DEBUG_REG: TRC_F2:RW:0:9:=0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MIN 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tras tras_minTck tRAS_minTck tras_min_clk tRAS_min_cycle}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tras: Parameter value {42.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {42.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_min_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRAS_min_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MIN 0 2 --&gt; Returned 45: CADENCE_DEBUG_REG: TRAS_MIN_F2:RW:16:9:=0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR 0 2 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_F2:RW:0:7:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_F2:RW:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_AP 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr twtr_clk twtr_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twtr: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twtr_s_crc_dm twtr_s_crc_dm_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twtr_s_crc_dm_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_AP 0 2 --&gt; Returned 12: CADENCE_DEBUG_REG: TWTR_AP_F2:RW:16:9:=0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWTR_L_AP 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWTR_L_AP 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TWTR_L_AP_F2:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP 0 2 --&gt; Returned 20: CADENCE_DEBUG_REG: TRP_F2:RW:16:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw tfaw_minTck tfaw_clk tfaw_time}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tfaw: Parameter value {40.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {40.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW 0 2 --&gt; Returned 43: CADENCE_DEBUG_REG: TFAW_F2:RW:0:9:=0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TFAW_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tfaw_dlr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tfaw_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TFAW_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TFAW_DLR_F2:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCD_DLR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCD_DLR --&gt; Returned 0: CADENCE_DEBUG_REG: TCCD_DLR:RW:0:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trtp trtp_minTck trtp_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trtp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TRTP_F0:RW:8:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP_AP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP_AP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRTP_AP_F0:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_DELAY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd_time tmrd_clk tmpc_delay_time tmpc_delay_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_DELAY 0 --&gt; Returned 11: CADENCE_DEBUG_REG: TMPC_DELAY_F0:RW:24:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod tmod_clk tmod_time tMOD_time tMOD_cycle}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod_max}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_max: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd tmrd_minTck tmrw_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrd: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD 0 --&gt; Returned 15: CADENCE_DEBUG_REG: TMOD_F0:RW:8:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MAX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MAX 0 --&gt; Returned 55555: CADENCE_DEBUG_REG: TRAS_MAX_F0:RW:0:20:=0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKE 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKE_F0:RW:24:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKESR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckesr tckesr_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsrfc}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsrfc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKESR 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKESR_F0:RW:0:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCDMW 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccdmw: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCCDMW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCDMW 0 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCDMW_F0:RW:8:6:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSH 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tCSH}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCSH: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSH 0 --&gt; Returned 3: CADENCE_DEBUG_REG: TCSH_F0:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCACSH 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCACSH 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TCACSH_F0:RW:24:8:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trtp trtp_minTck trtp_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trtp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TRTP_F1:RW:0:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP_AP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP_AP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRTP_AP_F1:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_DELAY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd_time tmrd_clk tmpc_delay_time tmpc_delay_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_DELAY 1 --&gt; Returned 11: CADENCE_DEBUG_REG: TMPC_DELAY_F1:RW:16:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod tmod_clk tmod_time tMOD_time tMOD_cycle}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod_max}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_max: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd tmrd_minTck tmrw_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrd: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD 1 --&gt; Returned 15: CADENCE_DEBUG_REG: TMOD_F1:RW:0:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MAX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MAX 1 --&gt; Returned 55555: CADENCE_DEBUG_REG: TRAS_MAX_F1:RW:8:20:=0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKE 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKE_F1:RW:0:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKESR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckesr tckesr_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsrfc}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsrfc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKESR 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKESR_F1:RW:8:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCDMW 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccdmw: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCCDMW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCDMW 1 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCDMW_F1:RW:16:6:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSH 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tCSH}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCSH: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSH 1 --&gt; Returned 3: CADENCE_DEBUG_REG: TCSH_F1:RW:24:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCACSH 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCACSH 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TCACSH_F1:RW:0:8:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trtp trtp_minTck trtp_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trtp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trtp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TRTP_F2:RW:8:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRTP_AP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRTP_AP 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRTP_AP_F2:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_DELAY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd_time tmrd_clk tmpc_delay_time tmpc_delay_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmpc_delay_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_DELAY 2 --&gt; Returned 11: CADENCE_DEBUG_REG: TMPC_DELAY_F2:RW:24:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMOD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod tmod_clk tmod_time tMOD_time tMOD_cycle}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tMOD_cycle: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmod_max}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmod_max: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrd tmrd_minTck tmrw_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrd: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMOD 2 --&gt; Returned 15: CADENCE_DEBUG_REG: TMOD_F2:RW:8:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_MAX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tras_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_MAX 2 --&gt; Returned 55555: CADENCE_DEBUG_REG: TRAS_MAX_F2:RW:0:20:=0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKE 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKE_F2:RW:24:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKESR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckesr tckesr_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckesr_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsrfc}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsrfc: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKESR 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKESR_F2:RW:0:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCCDMW 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccdmw: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCCDMW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCCDMW 2 --&gt; Returned 32: CADENCE_DEBUG_REG: TCCDMW_F2:RW:8:6:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSH 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tCSH}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCSH: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSH 2 --&gt; Returned 3: CADENCE_DEBUG_REG: TCSH_F2:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCACSH 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCACSH 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TCACSH_F2:RW:24:8:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPPD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tppd}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tppd: Parameter value {4.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {4.0 clk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPPD 0 --&gt; Returned 4: CADENCE_DEBUG_REG: TPPD_F0:RW_D:0:3:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPPD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tppd}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tppd: Parameter value {4.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {4.0 clk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPPD 1 --&gt; Returned 4: CADENCE_DEBUG_REG: TPPD_F1:RW_D:8:3:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPPD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tppd}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tppd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tppd: Parameter value {4.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {4.0 clk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPPD 2 --&gt; Returned 4: CADENCE_DEBUG_REG: TPPD_F2:RW_D:16:3:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMOD_OPT_THRESHOLD will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMRD_OPT_THRESHOLD will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WRITEINTERP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WRITEINTERP --&gt; Returned 0: CADENCE_DEBUG_REG: WRITEINTERP:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_MULTI_CYCLE_ENABLE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_MULTI_CYCLE_ENABLE 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_MULTI_CYCLE_ENABLE_F0:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_MULTI_CYCLE_ENABLE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_MULTI_CYCLE_ENABLE 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_MULTI_CYCLE_ENABLE_F1:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_MULTI_CYCLE_ENABLE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_MULTI_CYCLE_ENABLE 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_MULTI_CYCLE_ENABLE_F2:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_CS_LOW" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_CS_LOW --&gt; Returned 4: CADENCE_DEBUG_REG: TMPC_CS_LOW:RW:8:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_SETUP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_SETUP --&gt; Returned 3: CADENCE_DEBUG_REG: TMPC_SETUP:RW:16:4:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPC_HOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPC_HOLD --&gt; Returned 3: CADENCE_DEBUG_REG: TMPC_HOLD:RW:24:4:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_REQ --&gt; FAKED 3: CADENCE_DEBUG_REG: MPC_REQ:WR:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_CS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_CS --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_CS:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_OPCODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_OPCODE --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_OPCODE:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPC_PROMOTE_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPC_PROMOTE_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: MPC_PROMOTE_THRESHOLD:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MPC_ERROR_STATUS (MPC_ERROR_STATUS RD {} ZERO ZERO FULL CTL {{Indicates if a MPC request was attempted when the Controller was in Self-Refresh Long or Self-Refresh Short with Memory Clock Gating state. READ-ONLY }} 2656 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRCD 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRCD 0 0 --&gt; Returned 20: CADENCE_DEBUG_REG: TRCD_F0:RW:8:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWR 0 0 --&gt; Returned 21: CADENCE_DEBUG_REG: TWR_F0:RW:16:8:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRCD 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRCD 0 1 --&gt; Returned 20: CADENCE_DEBUG_REG: TRCD_F1:RW:24:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWR 0 1 --&gt; Returned 21: CADENCE_DEBUG_REG: TWR_F1:RW:0:8:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRCD 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRCD 0 2 --&gt; Returned 20: CADENCE_DEBUG_REG: TRCD_F2:RW:8:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TWR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TWR 0 2 --&gt; Returned 21: CADENCE_DEBUG_REG: TWR_F2:RW:16:8:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrr tmrr_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrr: Parameter value {8.0 clk}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {8.0 clk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrr_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRR --&gt; Returned 8: CADENCE_DEBUG_REG: TMRR:RW:24:8:=0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMPRR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmprr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMPRR --&gt; Returned 0: CADENCE_DEBUG_REG: TMPRR:RW:0:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of AP_Sim: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AP --&gt; Returned 0: CADENCE_DEBUG_REG: AP:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CONCURRENTAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CONCURRENTAP --&gt; Returned 1: CADENCE_DEBUG_REG: CONCURRENTAP:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRAS_LOCKOUT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRAS_LOCKOUT --&gt; Returned 1: CADENCE_DEBUG_REG: TRAS_LOCKOUT:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDAL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdal: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDAL 0 --&gt; Returned 41: CADENCE_DEBUG_REG: TDAL_F0:RW:0:8:=0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDAL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdal: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDAL 1 --&gt; Returned 41: CADENCE_DEBUG_REG: TDAL_F1:RW:8:8:=0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDAL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trppb trppb_minTck trp trp_minTck tRPpb tRPpb_minTck tRP}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trppb: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trppb_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trp_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPpb_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdal: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDAL 2 --&gt; Returned 41: CADENCE_DEBUG_REG: TDAL_F2:RW:16:8:=0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BSTLEN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BSTLEN --&gt; Returned 4: CADENCE_DEBUG_REG: BSTLEN:RW_D:24:6:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 0 0 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F0_0:RW:0:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 0 1 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F1_0:RW:8:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 0 2 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F2_0:RW:16:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 1 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 1 0 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F0_1:RW:24:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 1 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 1 1 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F1_1:RW:0:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRP_AB 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trpab trpab_minTck tRPab tRPab_minTck}, 1 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trpab: Parameter value {21.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {21.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trpab_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRPab_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRP_AB 1 2 --&gt; Returned 23: CADENCE_DEBUG_REG: TRP_AB_F2_1:RW:8:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MEM_3DS_SUPPORT_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MEM_3DS_SUPPORT_EN --&gt; Returned 0: CADENCE_DEBUG_REG: MEM_3DS_SUPPORT_EN:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LOGICAL_CS_MAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of componentDdrSOMA: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LOGICAL_CS_MAP --&gt; Returned 0: CADENCE_DEBUG_REG: LOGICAL_CS_MAP:RW:24:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PRECHARGE_DLR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PRECHARGE_DLR --&gt; Returned 8: CADENCE_DEBUG_REG: PRECHARGE_DLR:RW:0:8:=0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__REG_DIMM_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__REG_DIMM_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: REG_DIMM_ENABLE:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDRESS_MIRRORING" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter is_addr_mirror_en does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDRESS_MIRRORING --&gt; Returned 0: CADENCE_DEBUG_REG: ADDRESS_MIRRORING:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDRESS_INVERSION" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDRESS_INVERSION --&gt; Returned 0: CADENCE_DEBUG_REG: ADDRESS_INVERSION:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PDA_INVERT_DEV_CS0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PDA_INVERT_DEV_CS0 --&gt; Returned 0: CADENCE_DEBUG_REG: PDA_INVERT_DEV_CS0:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PDA_INVERT_DEV_CS1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PDA_INVERT_DEV_CS1 --&gt; Returned 0: CADENCE_DEBUG_REG: PDA_INVERT_DEV_CS1:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PDA_INVERT_ECC_DEV_CS0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PDA_INVERT_ECC_DEV_CS0 --&gt; Returned 0: CADENCE_DEBUG_REG: PDA_INVERT_ECC_DEV_CS0:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PDA_INVERT_ECC_DEV_CS1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PDA_INVERT_ECC_DEV_CS1 --&gt; Returned 0: CADENCE_DEBUG_REG: PDA_INVERT_ECC_DEV_CS1:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__OPTIMAL_RMODW_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Burst_RMW_Optimize: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_RMW: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_RMW: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__OPTIMAL_RMODW_EN --&gt; Returned 1: CADENCE_DEBUG_REG: OPTIMAL_RMODW_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__OPTIMAL_RMODW_WRITE_REDUC_EN will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NO_MEMORY_DM" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of data_mask_en: Parameter value true</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NO_MEMORY_DM --&gt; Returned 0: CADENCE_DEBUG_REG: NO_MEMORY_DM:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CW_REQ --&gt; FAKED 0: CADENCE_DEBUG_REG: CW_REQ:WR:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CWW_SW_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CWW_SW_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: CWW_SW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CWW_SW_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CWW_SW_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: CWW_SW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CWW_SW_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CWW_SW_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: CWW_SW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RDIMM_CWW_ERROR_STATUS (RDIMM_CWW_ERROR_STATUS RD {} ZERO ZERO FULL CTL {{Indicates if a RDIMM CWW request was attempted when the Controller was in Self-Refresh Long or Self-Refresh Short with Memory Clock Gating state. READ-ONLY }} 2992 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TMRD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrw tmrw_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrw: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrw tmrw_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrw: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TMRD --&gt; Returned 11: CADENCE_DEBUG_REG: RDIMM_TMRD:RW:0:16:=0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F0_0:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F1_0:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F2_0:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F0_1:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F1_1:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CTL 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CTL 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CTL_F2_1:RW:0:152:=0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_DFS_CW_MAP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_DFS_CW_MAP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_DFS_CW_MAP_F0:RW:0:27:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_DFS_CW_MAP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_DFS_CW_MAP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_DFS_CW_MAP_F1:RW:0:27:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_DFS_CW_MAP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_DFS_CW_MAP 2 --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_DFS_CW_MAP_F2:RW:0:27:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CW_MAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CW_MAP --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CW_MAP:RW:0:27:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_CW_HOLD_CKE_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_CW_HOLD_CKE_EN --&gt; Returned 0: CADENCE_DEBUG_REG: RDIMM_CW_HOLD_CKE_EN:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TSTAB 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {6 us}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TSTAB 0 --&gt; Returned 6404: CADENCE_DEBUG_REG: RDIMM_TSTAB_F0:RW:8:24:=0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TSTAB 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {6 us}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TSTAB 1 --&gt; Returned 6404: CADENCE_DEBUG_REG: RDIMM_TSTAB_F1:RW:0:24:=0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TSTAB 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {6 us}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TSTAB 2 --&gt; Returned 6404: CADENCE_DEBUG_REG: RDIMM_TSTAB_F2:RW:0:24:=0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_MAP_DIMM 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_MAP_DIMM 0 --&gt; Returned 3: CADENCE_DEBUG_REG: CS_MAP_DIMM_0:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_MAP_DIMM 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_MAP_DIMM 1 --&gt; Returned 0: CADENCE_DEBUG_REG: CS_MAP_DIMM_1:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DDR4_DIMM_3DS_PIN_MUXING_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DDR4_DIMM_3DS_PIN_MUXING_EN --&gt; Returned 0: CADENCE_DEBUG_REG: DDR4_DIMM_3DS_PIN_MUXING_EN:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DDR4_DIMM_CID0_MAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DDR4_DIMM_CID0_MAP --&gt; Returned 0: CADENCE_DEBUG_REG: DDR4_DIMM_CID0_MAP:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANK0_MAP_DIMM 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANK0_MAP_DIMM 0 --&gt; Returned 1: CADENCE_DEBUG_REG: RANK0_MAP_DIMM_0:RW:24:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANK0_MAP_DIMM 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANK0_MAP_DIMM 1 --&gt; Returned 0: CADENCE_DEBUG_REG: RANK0_MAP_DIMM_1:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TMRD_L" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TMRD_L --&gt; Returned 16: CADENCE_DEBUG_REG: RDIMM_TMRD_L:RW:8:5:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TMRD_L2" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TMRD_L2 --&gt; Returned 32: CADENCE_DEBUG_REG: RDIMM_TMRD_L2:RW:16:6:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RDIMM_TMRC" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RDIMM_TMRC --&gt; Returned 16: CADENCE_DEBUG_REG: RDIMM_TMRC:RW:24:5:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LRDIMM_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Load_Reduced_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LRDIMM_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: LRDIMM_ENABLE:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRROD1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRROD1 --&gt; Returned 0: CADENCE_DEBUG_REG: TMRROD1:RW:8:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRROD2" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRROD2 --&gt; Returned 0: CADENCE_DEBUG_REG: TMRROD2:RW:16:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CW_VAL" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CW_VAL --&gt; Returned 0: CADENCE_DEBUG_REG: CW_VAL:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CW_NUM" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CW_NUM --&gt; Returned 0: CADENCE_DEBUG_REG: CW_NUM:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CW_CS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CW_CS --&gt; Returned 1: CADENCE_DEBUG_REG: CW_CS:RW:16:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CA_PARITY_ERROR (CA_PARITY_ERROR RD {} ZERO ZERO FULL CTL {{Contains one hot indication of registered DIMM parity errors. Value of 1 indicates an error on that DIMM. READ-ONLY }} 4384 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREFRESH --&gt; FAKED 1: CADENCE_DEBUG_REG: AREFRESH:WR:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AREF_STATUS (AREF_STATUS RD {} ZERO ZERO FULL CTL {{Indicates a SR error associated with the AREF interrupt. Value of 1 indicates a violation. READ-ONLY }} 4400 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AREF_SW_ACK (AREF_SW_ACK RD {} ZERO ZERO FULL CTL {{Indicates a aref request is done corresponding to SW aref request. Value of 1 indicates sw aref req done . READ-ONLY }} 4408 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TREF_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TREF_ENABLE --&gt; Returned 1: CADENCE_DEBUG_REG: TREF_ENABLE:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_OPT_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_OPT_THRESHOLD --&gt; Returned 3: CADENCE_DEBUG_REG: TRFC_OPT_THRESHOLD:RW:8:3:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_COMPARISON_FOR_REFRESH_DEPTH" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_COMPARISON_FOR_REFRESH_DEPTH --&gt; Returned 16: CADENCE_DEBUG_REG: CS_COMPARISON_FOR_REFRESH_DEPTH:RW:16:6:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC 0 --&gt; Returned 193: CADENCE_DEBUG_REG: TRFC_F0:RW:0:10:=0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TREF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TREF 0 --&gt; Returned 4162: CADENCE_DEBUG_REG: TREF_F0:RW:0:20:=0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_DLR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfc_dlr1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_DLR 0 --&gt; Returned 96: CADENCE_DEBUG_REG: TRFC_DLR_F0:RW:0:10:=0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC 1 --&gt; Returned 193: CADENCE_DEBUG_REG: TRFC_F1:RW:16:10:=0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TREF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TREF 1 --&gt; Returned 4162: CADENCE_DEBUG_REG: TREF_F1:RW:0:20:=0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_DLR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfc_dlr1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_DLR 1 --&gt; Returned 96: CADENCE_DEBUG_REG: TRFC_DLR_F1:RW:0:10:=0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC 2 --&gt; Returned 193: CADENCE_DEBUG_REG: TRFC_F2:RW:16:10:=0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TREF 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TREF 2 --&gt; Returned 4162: CADENCE_DEBUG_REG: TREF_F2:RW:0:20:=0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_DLR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfc_dlr1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab tRFCab}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCab: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_DLR 2 --&gt; Returned 96: CADENCE_DEBUG_REG: TRFC_DLR_F2:RW:0:10:=0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TREF_INTERVAL" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TREF_INTERVAL --&gt; Returned 5: CADENCE_DEBUG_REG: TREF_INTERVAL:RW:0:20:=0x000005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_F0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_DLR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_DLR 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_DLR_F0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_F1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_DLR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_DLR 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_DLR_F1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_F2:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_DLR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_DLR 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_DLR_F2:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F0_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F0_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F0_0:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F0_0:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F1_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F1_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F1_0:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F1_0:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F2_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F2_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F2_0:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F2_0:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F0_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F0_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F0_1:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F0_1:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F1_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F1_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F1_1:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F1_1:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_F2_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM_SB_DLR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM_SB_DLR 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM_SB_DLR_F2_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_F2_1:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFM2ACT_DLR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFM2ACT_DLR 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFM2ACT_DLR_F2_1:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RFM_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RFM_EN --&gt; Returned 0: CADENCE_DEBUG_REG: RFM_EN:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__REF_RFM_PRIO" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__REF_RFM_PRIO --&gt; Returned 1: CADENCE_DEBUG_REG: REF_RFM_PRIO:RW:8:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RAA_CNT_DECR_PER_REF" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RAA_CNT_DECR_PER_REF --&gt; Returned 0: CADENCE_DEBUG_REG: RAA_CNT_DECR_PER_REF:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RAAIMT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RAAIMT --&gt; Returned 0: CADENCE_DEBUG_REG: RAAIMT:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RAAMMT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RAAMMT --&gt; Returned 0: CADENCE_DEBUG_REG: RAAMMT:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RFM_SB_CONT_EN_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RFM_SB_CONT_EN_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: RFM_SB_CONT_EN_THRESHOLD:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RFM_NORM_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RFM_NORM_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: RFM_NORM_THRESHOLD:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RFM_HIGH_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RFM_HIGH_THRESHOLD --&gt; Returned 0: CADENCE_DEBUG_REG: RFM_HIGH_THRESHOLD:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 0 0 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F0_0:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F0_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 0 0 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F0_0:RW:0:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 0 0 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F0_0:RW:8:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 0 0 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F0_0:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F0_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 0 1 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F1_0:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F1_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 1 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 0 1 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F1_0:RW:16:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 0 1 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F1_0:RW:24:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 0 1 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F1_0:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F1_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 0 2 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F2_0:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F2_0:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 0 2 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 0 2 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F2_0:RW:0:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 0 2 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F2_0:RW:8:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 0 2 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F2_0:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F2_0:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 1 0 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F0_1:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F0_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 1 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 1 0 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F0_1:RW:16:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 1 0 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F0_1:RW:24:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 1 0 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F0_1:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F0_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 1 1 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F1_1:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F1_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 1 1 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 1 1 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F1_1:RW:0:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 1 1 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F1_1:RW:8:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 1 1 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F1_1:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F1_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB 1 2 --&gt; Returned 97: CADENCE_DEBUG_REG: TRFC_PB_F2_1:RW:16:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TRFC_PB_DLR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TRFC_PB_DLR 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TRFC_PB_DLR_F2_1:RW:0:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trrd trrd_s trrd_clk trrd_s_clk trrd_minTck tRRD_S tRRD_S_minTck}, 1 2 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trrd: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_s_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trrd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRRD_S_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT 1 2 --&gt; Returned 11: CADENCE_DEBUG_REG: TPBR2ACT_F2_1:RW:16:8:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2ACT_DLR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefsbrd_dlr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2ACT_DLR 1 2 --&gt; Returned 16: CADENCE_DEBUG_REG: TPBR2ACT_DLR_F2_1:RW:24:8:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcpb tRFCpb}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcpb: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcpb: Parameter value {90.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {90.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tRFCpb: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR 1 2 --&gt; Returned 97: CADENCE_DEBUG_REG: TPBR2PBR_F2_1:RW:0:10:=0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPBR2PBR_DLR 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPBR2PBR_DLR 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TPBR2PBR_DLR_F2_1:RW:16:10:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PBR_MODE_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Per_Bank_Refresh: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PBR_MODE_EN --&gt; Returned 1: CADENCE_DEBUG_REG: PBR_MODE_EN:RW:0:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__SELECT_BANK_IN_Q" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__SELECT_BANK_IN_Q --&gt; Returned 0: CADENCE_DEBUG_REG: SELECT_BANK_IN_Q:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PBR_NUMERIC_ORDER" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PBR_NUMERIC_ORDER --&gt; Returned 0: CADENCE_DEBUG_REG: PBR_NUMERIC_ORDER:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PBR_CONT_REQ_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PBR_CONT_REQ_EN --&gt; Returned 1: CADENCE_DEBUG_REG: PBR_CONT_REQ_EN:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_PBR_CONT_EN_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_PBR_CONT_EN_THRESHOLD --&gt; Returned 18: CADENCE_DEBUG_REG: AREF_PBR_CONT_EN_THRESHOLD:RW:0:5:=0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPDEX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txp txp_minTck txp_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of txp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPDEX 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TPDEX_F0:RW:8:16:=0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPDEX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txp txp_minTck txp_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of txp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPDEX 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TPDEX_F1:RW:0:16:=0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TPDEX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txp txp_minTck txp_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of txp: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txp_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TPDEX 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TPDEX_F2:RW:16:16:=0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRRI 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrri: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRRI 0 --&gt; Returned 23: CADENCE_DEBUG_REG: TMRRI_F0:RW:0:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRRI 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrri: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRRI 1 --&gt; Returned 23: CADENCE_DEBUG_REG: TMRRI_F1:RW:8:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRRI 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrri: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of useSeparateTRCDforRW: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trcd trcd_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trcd: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trcd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DVFSCList: Parameter value 0 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRRI 2 --&gt; Returned 23: CADENCE_DEBUG_REG: TMRRI_F2:RW:16:8:=0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCS 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCS 0 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCS_F0:RW:24:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCS 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCS 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCS_F0:RW:0:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRWCKEL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrwckel tmrwckel_minTck tmrwckel_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrwckel: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRWCKEL 0 --&gt; Returned 15: CADENCE_DEBUG_REG: TMRWCKEL_F0:RW:8:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCKE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcke tzqcke_minTck tzqcke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCKE 0 --&gt; Returned 3: CADENCE_DEBUG_REG: TZQCKE_F0:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCS 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCS 1 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCS_F1:RW:24:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCS 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCS 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCS_F1:RW:0:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRWCKEL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrwckel tmrwckel_minTck tmrwckel_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrwckel: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRWCKEL 1 --&gt; Returned 15: CADENCE_DEBUG_REG: TMRWCKEL_F1:RW:8:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCKE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcke tzqcke_minTck tzqcke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCKE 1 --&gt; Returned 3: CADENCE_DEBUG_REG: TZQCKE_F1:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCS 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCS 2 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCS_F2:RW:24:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCS 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCS 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCS_F2:RW:0:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRWCKEL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrwckel tmrwckel_minTck tmrwckel_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrwckel: Parameter value {14.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {14.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrwckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRWCKEL 2 --&gt; Returned 15: CADENCE_DEBUG_REG: TMRWCKEL_F2:RW:8:8:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCKE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcke tzqcke_minTck tzqcke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCKE 2 --&gt; Returned 3: CADENCE_DEBUG_REG: TZQCKE_F2:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcscke tcscke_minTck tcscke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcscke: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKE 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKE_F0:RW:24:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_DEFAULT_VAL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_DEFAULT_VAL 0 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_DEFAULT_VAL_F0:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcscke tcscke_minTck tcscke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcscke: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKE 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKE_F1:RW:8:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_DEFAULT_VAL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_DEFAULT_VAL 1 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_DEFAULT_VAL_F1:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcscke tcscke_minTck tcscke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcscke: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcscke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKE 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKE_F2:RW:24:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_DEFAULT_VAL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_DEFAULT_VAL 2 --&gt; Returned 0: CADENCE_DEBUG_REG: CA_DEFAULT_VAL_F2:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsrd}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsrd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsdll}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsdll: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lowPower: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSR 0 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSR_F0:RW:8:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSNR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsnr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsnr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txs}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSNR 0 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSNR_F0:RW:0:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCPDED 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCPDED 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TCPDED_F0:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsrd}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsrd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsdll}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsdll: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lowPower: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSR 1 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSR_F1:RW:0:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSNR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsnr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsnr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txs}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSNR 1 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSNR_F1:RW:16:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCPDED 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCPDED 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TCPDED_F1:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsrd}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsrd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsdll}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsdll: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of lowPower: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSR 2 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSR_F2:RW:8:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TXSNR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txsnr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txsnr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {txs}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of txs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trfcab}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trfcab: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trfcab: Parameter value {180.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {180.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TXSNR 2 --&gt; Returned 201: CADENCE_DEBUG_REG: TXSNR_F2:RW:0:16:=0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCPDED 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcpded_clk tcpded tCPDED}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcpded: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCPDED: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCPDED 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TCPDED_F2:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__SRX_NOP_CMDS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__SRX_NOP_CMDS --&gt; Returned 5: CADENCE_DEBUG_REG: SRX_NOP_CMDS:RW:24:4:=0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TSR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsr tsr_minTck tSR tSR_minTck tsr_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tsr: Parameter value {15.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TSR 0 --&gt; Returned 17: CADENCE_DEBUG_REG: TSR_F0:RW:0:8:=0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TESCKE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tescke tescke_minTck tescke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tescke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TESCKE 0 --&gt; Returned 3: CADENCE_DEBUG_REG: TESCKE_F0:RW:8:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKEH 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcsckeh tcsckeh_minTck tcsckeh_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcsckeh: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKEH 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKEH_F0:RW:16:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCMD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCMD 0 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCMD_F0:RW:24:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCMD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCMD 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCMD_F0:RW:0:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKCKEL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckel tckckel_minTck tckckel_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckel: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKCKEL 0 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKCKEL_F0:RW:8:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELPD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELPD 0 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKELPD_F0:RW:16:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TSR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsr tsr_minTck tSR tSR_minTck tsr_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tsr: Parameter value {15.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TSR 1 --&gt; Returned 17: CADENCE_DEBUG_REG: TSR_F1:RW:24:8:=0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TESCKE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tescke tescke_minTck tescke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tescke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TESCKE 1 --&gt; Returned 3: CADENCE_DEBUG_REG: TESCKE_F1:RW:0:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKEH 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcsckeh tcsckeh_minTck tcsckeh_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcsckeh: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKEH 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKEH_F1:RW:8:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCMD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCMD 1 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCMD_F1:RW:16:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCMD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCMD 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCMD_F1:RW:24:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKCKEL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckel tckckel_minTck tckckel_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckel: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKCKEL 1 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKCKEL_F1:RW:0:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELPD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELPD 1 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKELPD_F1:RW:8:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TSR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tsr tsr_minTck tSR tSR_minTck tsr_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tsr: Parameter value {15.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {15.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tSR_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tsr_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TSR 2 --&gt; Returned 17: CADENCE_DEBUG_REG: TSR_F2:RW:16:8:=0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TESCKE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tescke tescke_minTck tescke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tescke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tescke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TESCKE 2 --&gt; Returned 3: CADENCE_DEBUG_REG: TESCKE_F2:RW:24:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCSCKEH 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcsckeh tcsckeh_minTck tcsckeh_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcsckeh: Parameter value {1.75 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.75 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcsckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCSCKEH 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TCSCKEH_F2:RW:0:5:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELCMD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelcmd tckelcmd_minTck tckelcmd_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelcmd: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELCMD 2 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKELCMD_F2:RW:8:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKEHCMD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckehcmd tckehcmd_minTck tckehcmd_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckehcmd: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckehcmd_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKEHCMD 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKEHCMD_F2:RW:16:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKCKEL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckel tckckel_minTck tckckel_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckel: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckel_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKCKEL 2 --&gt; Returned 6: CADENCE_DEBUG_REG: TCKCKEL_F2:RW:24:5:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCKELPD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcke tcke_minTck tcke_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcke: Parameter value {7.5 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {7.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCKELPD 2 --&gt; Returned 9: CADENCE_DEBUG_REG: TCKELPD_F2:RW:0:8:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCMDCKE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcmdcke tcmdcke_minTck tcmdcke_clk tactpden tprpden trefpden tCMDPD tCMDPD_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcmdcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tactpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tprpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCMDCKE 0 --&gt; Returned 3: CADENCE_DEBUG_REG: TCMDCKE_F0:RW:8:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCMDCKE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcmdcke tcmdcke_minTck tcmdcke_clk tactpden tprpden trefpden tCMDPD tCMDPD_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcmdcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tactpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tprpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCMDCKE 1 --&gt; Returned 3: CADENCE_DEBUG_REG: TCMDCKE_F1:RW:16:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TCMDCKE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tcmdcke tcmdcke_minTck tcmdcke_clk tactpden tprpden trefpden tCMDPD tCMDPD_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tcmdcke: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tcmdcke_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tactpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tprpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefpden: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tCMDPD_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TCMDCKE 2 --&gt; Returned 3: CADENCE_DEBUG_REG: TCMDCKE_F2:RW:24:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PWRUP_SREFRESH_EXIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PWRUP_SREFRESH_EXIT --&gt; Returned 0: CADENCE_DEBUG_REG: PWRUP_SREFRESH_EXIT:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__SREFRESH_EXIT_NO_REFRESH" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__SREFRESH_EXIT_NO_REFRESH --&gt; Returned 0: CADENCE_DEBUG_REG: SREFRESH_EXIT_NO_REFRESH:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ENABLE_QUICK_SREFRESH" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ENABLE_QUICK_SREFRESH --&gt; Returned 1: CADENCE_DEBUG_REG: ENABLE_QUICK_SREFRESH:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKE_DELAY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKE_DELAY --&gt; Returned 0: CADENCE_DEBUG_REG: CKE_DELAY:RW:24:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DFS_CMD will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DFS_STATUS will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_FREQ_CHANGE_STATE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_FREQ_CHANGE_STATE --&gt; Returned 1: CADENCE_DEBUG_REG: DFI_FREQ_CHANGE_STATE:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WAIT_FOR_SW_AFTER_DFS will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFS_ZQ_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFS_ZQ_EN --&gt; Returned 1: CADENCE_DEBUG_REG: DFS_ZQ_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFS_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFS_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: DFS_PROMOTE_THRESHOLD_F0:RW:8:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 0 --&gt; Returned 0: CADENCE_DEBUG_REG: POST_DFS_WAIT_TIME_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFS_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFS_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: DFS_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 1 --&gt; Returned 0: CADENCE_DEBUG_REG: POST_DFS_WAIT_TIME_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFS_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFS_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: DFS_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 2 --&gt; Returned 0: CADENCE_DEBUG_REG: POST_DFS_WAIT_TIME_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ZQ_STATUS_LOG (ZQ_STATUS_LOG RD {} ZERO ZERO FULL CTL {{Indicates what kind of ZQ command was terminated without execution that caused the ZQ status interrupt to assert. Bit (0) correlates to a ZQ cal init, reset, short or long command. Bit (1) correlates to a ZQ cal start command. Bit (2) correlates to a ZQ cal latch command. Value of 1 indicates that that type of command was received, but terminated without execution. READ-ONLY }} 6480 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRP_OPT_THRESHOLD will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRAS_OPT_THRESHOLD will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__FM_NORM_CQ_DISCONNECT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__FM_HIGH_CQ_DISCONNECT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__FM_DISCONNECT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 0 --&gt; Returned 3: CADENCE_DEBUG_REG: UPD_CTRLUPD_NORM_THRESHOLD_F0:RW:0:16:=0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 0 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_HIGH_THRESHOLD_F0:RW:16:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_TIMEOUT 0 --&gt; Returned 5: CADENCE_DEBUG_REG: UPD_CTRLUPD_TIMEOUT_F0:RW:0:16:=0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 0 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 1 --&gt; Returned 3: CADENCE_DEBUG_REG: UPD_CTRLUPD_NORM_THRESHOLD_F1:RW:16:16:=0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 1 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_HIGH_THRESHOLD_F1:RW:0:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_TIMEOUT 1 --&gt; Returned 5: CADENCE_DEBUG_REG: UPD_CTRLUPD_TIMEOUT_F1:RW:16:16:=0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 1 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_NORM_THRESHOLD 2 --&gt; Returned 3: CADENCE_DEBUG_REG: UPD_CTRLUPD_NORM_THRESHOLD_F2:RW:0:16:=0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_HIGH_THRESHOLD 2 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_HIGH_THRESHOLD_F2:RW:16:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_TIMEOUT 2 --&gt; Returned 5: CADENCE_DEBUG_REG: UPD_CTRLUPD_TIMEOUT_F2:RW:0:16:=0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_CTRLUPD_SW_PROMOTE_THRESHOLD 2 --&gt; Returned 4: CADENCE_DEBUG_REG: UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__UPD_PHYUPD_DFI_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_RD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_RD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_RD_F0:RW:16:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_WR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_WR 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_WR_F0:RW:24:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_FS 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_FS 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_FS_F0:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_TOGGLE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_TOGGLE 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_TOGGLE_F0:RW:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_FAST_TOGGLE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_FAST_TOGGLE 0 --&gt; Returned 4: CADENCE_DEBUG_REG: TDFI_WCK_FAST_TOGGLE_F0:RW:16:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_DIS 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_DIS 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_DIS_F0:RW:24:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_RD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_RD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_RD_F1:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_WR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_WR 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_WR_F1:RW:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_FS 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_FS 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_FS_F1:RW:16:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_TOGGLE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_TOGGLE 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_TOGGLE_F1:RW:24:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_FAST_TOGGLE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_FAST_TOGGLE 1 --&gt; Returned 4: CADENCE_DEBUG_REG: TDFI_WCK_FAST_TOGGLE_F1:RW:0:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_DIS 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_DIS 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_DIS_F1:RW:8:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_RD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_rd: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_RD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_RD_F2:RW:16:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_WR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_wr: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_WR 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_WR_F2:RW:24:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_EN_FS 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckenl_fs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_EN_FS 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_EN_FS_F2:RW:0:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_TOGGLE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twckpre_static: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_TOGGLE 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_TOGGLE_F2:RW:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_FAST_TOGGLE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_FAST_TOGGLE 2 --&gt; Returned 4: CADENCE_DEBUG_REG: TDFI_WCK_FAST_TOGGLE_F2:RW:16:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WCK_DIS 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WCK_DIS 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_WCK_DIS_F2:RW:24:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WCK_ON will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WCK_OFF will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WCK_GROUP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WCK_GROUP --&gt; Returned 2: CADENCE_DEBUG_REG: WCK_GROUP:RW:16:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WCK_WR_FREERUN will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WCK_MODE will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WCK_SYNCED (WCK_SYNCED RD {} ZERO ZERO FULL CTL {{Indicates the WCK is synced for each chip select. Bit (0) correlates to cs0, bit (1) correlates to cs1, etc. A value of 1 indicates that a CAS WCK2CK Sync command has been issued to that chip select and the WCK2CK is still synced. READ-ONLY }} 6960 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__CAS_TO_CAS_WS_OFF_VAL will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX 0 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_F0:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 0 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE0_F0:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 0 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE1_F0:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 0 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE2_F0:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 0 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE3_F0:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_RESP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_RESP 0 --&gt; Returned 29134: CADENCE_DEBUG_REG: TDFI_PHYMSTR_RESP_F0:RW:0:20:=0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX 1 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_F1:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 1 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE0_F1:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 1 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE1_F1:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 1 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE2_F1:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 1 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE3_F1:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_RESP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_RESP 1 --&gt; Returned 29134: CADENCE_DEBUG_REG: TDFI_PHYMSTR_RESP_F1:RW:0:20:=0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX 2 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_F2:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE0 2 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE0_F2:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE1 2 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE1_F2:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE2 2 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE2_F2:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_MAX_TYPE3 2 --&gt; Returned 266368: CADENCE_DEBUG_REG: TDFI_PHYMSTR_MAX_TYPE3_F2:RW:0:32:=0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_DFI4_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYMSTR_RESP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYMSTR_RESP 2 --&gt; Returned 29134: CADENCE_DEBUG_REG: TDFI_PHYMSTR_RESP_F2:RW:0:20:=0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_NO_AREF" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_NO_AREF --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_NO_AREF:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PHYMSTR_ERROR_STATUS (PHYMSTR_ERROR_STATUS RD {} ZERO ZERO FULL CTL {{Identifies the source of any DFI PHY Master Interface errors. Value of 1 indicates a timing violation of the associated timing parameter. Bit (0) set indicates a TDFI_PHYMSTR_MAX or TDFI_PHYMSTR_TYPEn_MAX parmaeter violation and bit (1) set indicates a TDFI_PHYMSTR_RESP parameter violation. READ-ONLY }} 7744 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_DFI_VERSION_4P0V1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_DFI_VERSION_4P0V1 --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_DFI_VERSION_4P0V1:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PHYMSTR_TRAIN_AFTER_INIT_COMPLETE --&gt; Returned 0: CADENCE_DEBUG_REG: PHYMSTR_TRAIN_AFTER_INIT_COMPLETE:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_NORM_THRESHOLD_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_HIGH_THRESHOLD_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_TIMEOUT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_TIMEOUT_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_NORM_THRESHOLD_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_HIGH_THRESHOLD_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_TIMEOUT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_TIMEOUT_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_NORM_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_NORM_THRESHOLD_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_HIGH_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_HIGH_THRESHOLD_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_TEMPCHK_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_TEMPCHK_TIMEOUT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_TEMPCHK_TIMEOUT_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_COMMAND_MRR_REGNUM" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_COMMAND_MRR_REGNUM --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_COMMAND_MRR_REGNUM:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_CONTROL" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_CONTROL --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_CONTROL:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_COMMAND --&gt; FAKED 0: CADENCE_DEBUG_REG: PPR_COMMAND:WR:8:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_COMMAND_MRW_REGNUM" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_COMMAND_MRW_REGNUM --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_COMMAND_MRW_REGNUM:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_COMMAND_MRW_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_COMMAND_MRW_DATA --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_COMMAND_MRW_DATA:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_ROW_ADDRESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_ROW_ADDRESS --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_ROW_ADDRESS:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_BANK_ADDRESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_BANK_ADDRESS --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_BANK_ADDRESS:RW:24:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_CS_ADDRESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_CS_ADDRESS --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_CS_ADDRESS:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_CID_ADDRESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_CID_ADDRESS --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_CID_ADDRESS:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_DATA --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_DATA:RW:0:256:=0x0000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PPR_ECC" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PPR_ECC --&gt; Returned 0: CADENCE_DEBUG_REG: PPR_ECC:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PPR_STATUS (PPR_STATUS RD {} PPR_STATUS_INIT ZERO FULL CTL {{Reports the status of the PPR operation. Bit (0) set indicates that PPR operations are now allowed and bit (1) set indicates if the last PPR command is complete. READ-ONLY }} 8480 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__POST_INIT_SW_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__POST_INIT_SW_MODE --&gt; Returned 0: CADENCE_DEBUG_REG: POST_INIT_SW_MODE:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_BOOT_STATE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_BOOT_STATE --&gt; Returned 0: CADENCE_DEBUG_REG: DFI_BOOT_STATE:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__X8_DEVICE_EN will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DATA2CMD_RATIO 0 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_ARCH_MODE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_ARCH_MODE 0 --&gt; Returned 0: CADENCE_DEBUG_REG: BANK_ARCH_MODE_F0:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DVFSC_MODE 0 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_LINK_ECC_EN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RD_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_LINK_ECC_EN 0 --&gt; Returned 0: CADENCE_DEBUG_REG: RD_LINK_ECC_EN_F0:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_LINK_ECC_EN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WR_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_LINK_ECC_EN 0 --&gt; Returned 0: CADENCE_DEBUG_REG: WR_LINK_ECC_EN_F0:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DATA2CMD_RATIO 1 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_ARCH_MODE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_ARCH_MODE 1 --&gt; Returned 0: CADENCE_DEBUG_REG: BANK_ARCH_MODE_F1:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DVFSC_MODE 1 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_LINK_ECC_EN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RD_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_LINK_ECC_EN 1 --&gt; Returned 0: CADENCE_DEBUG_REG: RD_LINK_ECC_EN_F1:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_LINK_ECC_EN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WR_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_LINK_ECC_EN 1 --&gt; Returned 0: CADENCE_DEBUG_REG: WR_LINK_ECC_EN_F1:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DATA2CMD_RATIO 2 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_ARCH_MODE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_ARCH_MODE 2 --&gt; Returned 0: CADENCE_DEBUG_REG: BANK_ARCH_MODE_F2:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DVFSC_MODE 2 will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_LINK_ECC_EN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RD_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_LINK_ECC_EN 2 --&gt; Returned 0: CADENCE_DEBUG_REG: RD_LINK_ECC_EN_F2:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_LINK_ECC_EN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WR_Link_ECC: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_LINK_ECC_EN 2 --&gt; Returned 0: CADENCE_DEBUG_REG: WR_LINK_ECC_EN_F2:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 0 --&gt; Returned 0: CADENCE_DEBUG_REG: DVFSQ_MODE_F0:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 1 --&gt; Returned 0: CADENCE_DEBUG_REG: DVFSQ_MODE_F1:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZERO 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZERO 2 --&gt; Returned 0: CADENCE_DEBUG_REG: DVFSQ_MODE_F2:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_NORM_THRESHOLD_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_HIGH_THRESHOLD_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_TIMEOUT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_TIMEOUT_F0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_NORM_THRESHOLD_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_HIGH_THRESHOLD_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_TIMEOUT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_TIMEOUT_F1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_NORM_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_NORM_THRESHOLD_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_HIGH_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_HIGH_THRESHOLD_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_WR_LECC_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_WR_LECC_TIMEOUT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_WR_LECC_TIMEOUT_F2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WR_LINK_ECC_SBE_MR_VAL_0 (WR_LINK_ECC_SBE_MR_VAL_0 RD {} {ZERO 0} ZERO FULL CTL {{MR43 single-bit error data (bits 6:0) for all devices accessed by periodic Write Link ECC MRR commands. READ-ONLY. }} 8960 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WR_LINK_ECC_DBE_MR_VAL_0 (WR_LINK_ECC_DBE_MR_VAL_0 RD {} {ZERO 0} ZERO FULL CTL {{MR43 double-bit error data (bit 7) for all devices accessed by periodic Write Link ECC MRR commands. READ-ONLY. }} 8992 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WR_LINK_ECC_SBE_MR_VAL_1 (WR_LINK_ECC_SBE_MR_VAL_1 RD {} {ZERO 1} ZERO FULL CTL {{MR43 single-bit error data (bits 6:0) for all devices accessed by periodic Write Link ECC MRR commands. READ-ONLY. }} 9024 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__WR_LINK_ECC_DBE_MR_VAL_1 (WR_LINK_ECC_DBE_MR_VAL_1 RD {} {ZERO 1} ZERO FULL CTL {{MR43 double-bit error data (bit 7) for all devices accessed by periodic Write Link ECC MRR commands. READ-ONLY. }} 9056 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_DOUBLE_BIT_ERROR (RD_LINK_ECC_DOUBLE_BIT_ERROR RD {} ZERO ZERO FULL CTL {{A double bit error was detected on READ LINK ECC for a Port Read, Bit 0 is LSB of memory data bus (DQ) }} 9064 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMW_RD_LINK_ECC_DOUBLE_BIT_ERROR (RMW_RD_LINK_ECC_DOUBLE_BIT_ERROR RD {} ZERO ZERO FULL CTL {{A double bit error was detected on READ LINK ECC for a RMW-Read, Bit 0 is LSB of memory data bus (DQ) }} 9072 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_COUNT_0 (RD_LINK_ECC_SBE_COUNT_0 RD {} ZERO ZERO FULL CTL {{Number of times single bit errors have occurred. 0 is byte position  from least significant byte of  memory data bus (DQ). Counter will be cleared  on RD LINK ECC SBE Interrupt read   }} 9080 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_SYNDROME_0 (RD_LINK_ECC_SBE_SYNDROME_0 RD {} ZERO ZERO FULL CTL {{Syndrome for most recent error, 0 is byte position  from least significant byte of  memory data bus (DQ). Syndrome will be cleared  on RD LINK ECC SBE Interrupt read   }} 9088 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_COUNT_1 (RD_LINK_ECC_SBE_COUNT_1 RD {} ZERO ZERO FULL CTL {{Number of times single bit errors have occurred. 1 is byte position  from least significant byte of  memory data bus (DQ). Counter will be cleared  on RD LINK ECC SBE Interrupt read   }} 9104 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_SYNDROME_1 (RD_LINK_ECC_SBE_SYNDROME_1 RD {} ZERO ZERO FULL CTL {{Syndrome for most recent error, 1 is byte position  from least significant byte of  memory data bus (DQ). Syndrome will be cleared  on RD LINK ECC SBE Interrupt read   }} 9120 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_COUNT_2 (RD_LINK_ECC_SBE_COUNT_2 RD {} ZERO ZERO FULL CTL {{Number of times single bit errors have occurred. 2 is byte position  from least significant byte of  memory data bus (DQ). Counter will be cleared  on RD LINK ECC SBE Interrupt read   }} 9136 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_SYNDROME_2 (RD_LINK_ECC_SBE_SYNDROME_2 RD {} ZERO ZERO FULL CTL {{Syndrome for most recent error, 2 is byte position  from least significant byte of  memory data bus (DQ). Syndrome will be cleared  on RD LINK ECC SBE Interrupt read   }} 9152 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_COUNT_3 (RD_LINK_ECC_SBE_COUNT_3 RD {} ZERO ZERO FULL CTL {{Number of times single bit errors have occurred. 3 is byte position  from least significant byte of  memory data bus (DQ). Counter will be cleared  on RD LINK ECC SBE Interrupt read   }} 9168 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RD_LINK_ECC_SBE_SYNDROME_3 (RD_LINK_ECC_SBE_SYNDROME_3 RD {} ZERO ZERO FULL CTL {{Syndrome for most recent error, 3 is byte position  from least significant byte of  memory data bus (DQ). Syndrome will be cleared  on RD LINK ECC SBE Interrupt read   }} 9184 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelck tckelck_minTck tckelck_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelck: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRE 0 --&gt; Returned 6: CADENCE_DEBUG_REG: CKSRE_F0:RW:16:8:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckeh tckckeh_minTck tckckeh_clk}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckeh: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRX 0 --&gt; Returned 3: CADENCE_DEBUG_REG: CKSRX_F0:RW:24:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelck tckelck_minTck tckelck_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelck: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRE 1 --&gt; Returned 6: CADENCE_DEBUG_REG: CKSRE_F1:RW:0:8:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckeh tckckeh_minTck tckckeh_clk}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckeh: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRX 1 --&gt; Returned 3: CADENCE_DEBUG_REG: CKSRX_F1:RW:8:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckelck tckelck_minTck tckelck_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckelck: Parameter value {5.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {5.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckelck_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRE 2 --&gt; Returned 6: CADENCE_DEBUG_REG: CKSRE_F2:RW:16:8:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CKSRX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tckckeh tckckeh_minTck tckckeh_clk}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tckckeh: Parameter value {2.81 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {2.81 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckckeh_clk: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CKSRX 2 --&gt; Returned 3: CADENCE_DEBUG_REG: CKSRX_F2:RW:24:8:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LOWPOWER_REFRESH_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LOWPOWER_REFRESH_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: LOWPOWER_REFRESH_ENABLE:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_CMD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_CMD --&gt; Returned 0: CADENCE_DEBUG_REG: LP_CMD:WR:8:7:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_IDLE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_IDLE_WAKEUP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_IDLE_WAKEUP_F0:RW:16:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_IDLE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_IDLE_WAKEUP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_CTRL_IDLE_WAKEUP_F0:RW:24:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_SHORT_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_SHORT_WAKEUP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_SR_SHORT_WAKEUP_F0:RW:0:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_WAKEUP 0 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SR_LONG_WAKEUP_F0:RW:8:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 0 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_WAKEUP_F0:RW:16:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 0 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0:RW:24:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 0 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F0:RW:0:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_PD_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_PD_WAKEUP 0 --&gt; Returned 1: CADENCE_DEBUG_REG: LPI_PD_WAKEUP_F0:RW:8:6:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_SHORT_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_SHORT_WAKEUP 0 --&gt; Returned 7: CADENCE_DEBUG_REG: LPI_SRPD_SHORT_WAKEUP_F0:RW:16:6:=0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_WAKEUP 0 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SRPD_LONG_WAKEUP_F0:RW:24:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 0 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_WAKEUP_F0:RW:0:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 0 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0:RW:8:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 0 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F0:RW:16:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_TIMER_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_TIMER_WAKEUP 0 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_TIMER_WAKEUP_F0:RW:24:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_TIMER_WAKEUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_TIMER_WAKEUP 0 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_CTRL_TIMER_WAKEUP_F0:RW:0:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_IDLE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_IDLE_WAKEUP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_IDLE_WAKEUP_F1:RW:8:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_IDLE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_IDLE_WAKEUP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_CTRL_IDLE_WAKEUP_F1:RW:16:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_SHORT_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_SHORT_WAKEUP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_SR_SHORT_WAKEUP_F1:RW:24:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_WAKEUP 1 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SR_LONG_WAKEUP_F1:RW:0:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 1 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_WAKEUP_F1:RW:8:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 1 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1:RW:16:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 1 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F1:RW:24:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_PD_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_PD_WAKEUP 1 --&gt; Returned 1: CADENCE_DEBUG_REG: LPI_PD_WAKEUP_F1:RW:0:6:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_SHORT_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_SHORT_WAKEUP 1 --&gt; Returned 7: CADENCE_DEBUG_REG: LPI_SRPD_SHORT_WAKEUP_F1:RW:8:6:=0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_WAKEUP 1 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SRPD_LONG_WAKEUP_F1:RW:16:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 1 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_WAKEUP_F1:RW:24:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 1 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1:RW:0:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 1 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F1:RW:8:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_TIMER_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_TIMER_WAKEUP 1 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_TIMER_WAKEUP_F1:RW:16:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_TIMER_WAKEUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_TIMER_WAKEUP 1 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_CTRL_TIMER_WAKEUP_F1:RW:24:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_IDLE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_IDLE_WAKEUP 2 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_IDLE_WAKEUP_F2:RW:0:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_IDLE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_IDLE_WAKEUP 2 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_CTRL_IDLE_WAKEUP_F2:RW:8:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_SHORT_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_SHORT_WAKEUP 2 --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_SR_SHORT_WAKEUP_F2:RW:16:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_WAKEUP 2 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SR_LONG_WAKEUP_F2:RW:24:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_WAKEUP 2 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_WAKEUP_F2:RW:0:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SR_LONG_MCCLK_GATE_WAKEUP 2 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2:RW:8:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP 2 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F2:RW:16:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_PD_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_PD_WAKEUP 2 --&gt; Returned 1: CADENCE_DEBUG_REG: LPI_PD_WAKEUP_F2:RW:24:6:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_SHORT_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_SHORT_WAKEUP 2 --&gt; Returned 7: CADENCE_DEBUG_REG: LPI_SRPD_SHORT_WAKEUP_F2:RW:0:6:=0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_WAKEUP 2 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_SRPD_LONG_WAKEUP_F2:RW:8:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_WAKEUP 2 --&gt; Returned 9: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_WAKEUP_F2:RW:16:6:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_SRPD_LONG_MCCLK_GATE_WAKEUP 2 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2:RW:24:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP 2 --&gt; Returned 10: CADENCE_DEBUG_REG: LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F2:RW:0:6:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_TIMER_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_TIMER_WAKEUP 2 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_TIMER_WAKEUP_F2:RW:8:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_TIMER_WAKEUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_TIMER_WAKEUP 2 --&gt; Returned 14: CADENCE_DEBUG_REG: LPI_CTRL_TIMER_WAKEUP_F2:RW:16:6:=0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_WAKEUP_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_WAKEUP_EN --&gt; Returned 47: CADENCE_DEBUG_REG: LPI_WAKEUP_EN:RW:24:6:=0x2f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_WAKEUP_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_WAKEUP_EN --&gt; Returned 45: CADENCE_DEBUG_REG: LPI_CTRL_WAKEUP_EN:RW:0:6:=0x2d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_REQ_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_REQ_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LPI_CTRL_REQ_EN:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_TIMER_COUNT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_TIMER_COUNT --&gt; Returned 3: CADENCE_DEBUG_REG: LPI_TIMER_COUNT:RW:16:12:=0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_TIMER_COUNT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_TIMER_COUNT --&gt; Returned 3: CADENCE_DEBUG_REG: LPI_CTRL_TIMER_COUNT:RW:0:12:=0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_WAKEUP_TIMEOUT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_WAKEUP_TIMEOUT --&gt; Returned 4: CADENCE_DEBUG_REG: LPI_WAKEUP_TIMEOUT:RW:16:12:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPI_CTRL_WAKEUP_TIMEOUT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPI_CTRL_WAKEUP_TIMEOUT --&gt; Returned 4: CADENCE_DEBUG_REG: LPI_CTRL_WAKEUP_TIMEOUT:RW:0:12:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_LP_RESP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_LP_RESP --&gt; Returned 16: CADENCE_DEBUG_REG: TDFI_LP_RESP:RW:16:5:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__LP_STATE (LP_STATE RD {} ZERO LP_STATE_DEFAULT FULL CTL {{Low power state status parameter. Bits (5:0) indicate the current low power state and bit (6) set indicates that status bits are valid. READ-ONLY }} 9720 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_ENTRY_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_ENTRY_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_ENTRY_EN:RW:0:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_EXIT_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_EXIT_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_EXIT_EN:RW:8:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_MEM_GATE_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_MEM_GATE_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_MEM_GATE_EN:RW:16:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_PD_IDLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_PD_IDLE --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_PD_IDLE:RW:0:12:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_SR_SHORT_IDLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_SR_SHORT_IDLE --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_SR_SHORT_IDLE:RW:16:12:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_SR_LONG_IDLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_SR_LONG_IDLE --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_SR_LONG_IDLE:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LP_AUTO_SR_LONG_MC_GATE_IDLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LP_AUTO_SR_LONG_MC_GATE_IDLE --&gt; Returned 0: CADENCE_DEBUG_REG: LP_AUTO_SR_LONG_MC_GATE_IDLE:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__HW_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__HW_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: HW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__HW_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__HW_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: HW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__HW_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__HW_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: HW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_SR_CTRLUPD_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_SR_CTRLUPD_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_SR_CTRLUPD_EN:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_SR_PHYUPD_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_SR_PHYUPD_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_SR_PHYUPD_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_SR_PHYMSTR_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_SR_PHYMSTR_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_SR_PHYMSTR_EN:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__LPC_SR_EXIT_CMD_EN will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LPC_SR_ZQ_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LPC_SR_ZQ_EN --&gt; Returned 0: CADENCE_DEBUG_REG: LPC_SR_ZQ_EN:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__PWRDN_SHIFT_DELAY will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFS_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFS_ENABLE --&gt; Returned 1: CADENCE_DEBUG_REG: DFS_ENABLE:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CURRENT_REG_COPY (CURRENT_REG_COPY RD {} ZERO ZERO FULL CTL {{Indicates the current copy of timing parameters that is in use by the controller. }} 9976 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CURRENT_FSP (CURRENT_FSP RD {} ZERO ZERO FULL CTL {{Indicates the active FSP within the DRAM.  If the connected DRAM device does not have FSPs, this will reflect zero. }} 9984 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INIT_FREQ" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INIT_FREQ --&gt; Returned 2: CADENCE_DEBUG_REG: INIT_FREQ:RW:8:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INIT_FSP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INIT_FSP --&gt; Returned 0: CADENCE_DEBUG_REG: INIT_FSP:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_START 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_START 0 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_INIT_START_F0:RW_D:0:24:=0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_COMPLETE 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_COMPLETE 0 --&gt; Returned 4096: CADENCE_DEBUG_REG: TDFI_INIT_COMPLETE_F0:RW_D:0:24:=0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_START 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_START 1 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_INIT_START_F1:RW_D:0:24:=0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_COMPLETE 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_COMPLETE 1 --&gt; Returned 4096: CADENCE_DEBUG_REG: TDFI_INIT_COMPLETE_F1:RW_D:0:24:=0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_START 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_START 2 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_INIT_START_F2:RW_D:0:24:=0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_INIT_COMPLETE 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_INIT_COMPLETE 2 --&gt; Returned 4096: CADENCE_DEBUG_REG: TDFI_INIT_COMPLETE_F2:RW_D:0:24:=0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WRITE_MODEREG" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WRITE_MODEREG --&gt; Returned 0: CADENCE_DEBUG_REG: WRITE_MODEREG:RW+:0:27:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MRW_STATUS (MRW_STATUS RD {} ZERO ZERO FULL CTL {{Write memory mode register status. Bit (0) set indicates a WRITE_MODEREG parameter programming error. Bit (1) set indicates a PASR error. Bit (2) is Reserved. Bit (3) set indicates a self-refresh or deep power-down error. Bit (4) set indicates that a write to MR3 or MR11 was attempted (WRITE_MODEREG bit (25) was asserted with bit (17) set, or bit (23) was asserted with bits (7:0) defining MR3 or MR11) during tZQCAL after a ZQ calibration start command. READ-ONLY }} 10240 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__READ_MODEREG --&gt; FAKED 0: CADENCE_DEBUG_REG: READ_MODEREG:RW+:8:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PERIPHERAL_MRR_DATA (PERIPHERAL_MRR_DATA RD {} ZERO ZERO FULL CTL {{Data and chip returned from memory mode register read requested by the READ_MODEREG parameter. PERIPHERAL_MRR_DATA_WIDTH is the total width required to accomodate all attached DRAM Devices MRR data plus 8 bits for Chip select Info. Upper MSB 8 Bits of this register parameter indicates the targted chip from where this MRR data is read. Remaining PERIPHERAL_MRR_DATA_WIDTH-8 bits corresponds to attached DRAM device MRR Data. Example (7:0) for DRAM device0, (15:8) for DRAM device1, and so on to look for MRR data till total number of devices. READ-ONLY }} 10272 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AUTO_TEMPCHK_VAL_0 (AUTO_TEMPCHK_VAL_0 RD {} {ZERO 0} ZERO FULL CTL {{MR4 data for all devices accessed by automatic MRR commands. Bits (3:0) correlate to the device on the lower byte, bits (7:4) correlate to the devices on the 2nd byte etc. Value indicates the OP7, OP2, OP1 and OP0 bits. READ-ONLY. }} 10368 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__AUTO_TEMPCHK_VAL_1 (AUTO_TEMPCHK_VAL_1 RD {} {ZERO 1} ZERO FULL CTL {{MR4 data for all devices accessed by automatic MRR commands. Bits (3:0) correlate to the device on the lower byte, bits (7:4) correlate to the devices on the 2nd byte etc. Value indicates the OP7, OP2, OP1 and OP0 bits. READ-ONLY. }} 10400 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRR_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRR_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRR_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRW_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRW_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRW_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRW_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRW_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRW_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRW_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRW_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MRW_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DLL_RST" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DLL_RST --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DLL_RST:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__READ_MPR --&gt; FAKED 0: CADENCE_DEBUG_REG: READ_MPR:RW+:8:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MPRR_DATA_0 (MPRR_DATA_0 RD {} ZERO ZERO FULL CTL {{Data read from the multi-purpose register 0 read requested by the READ_MPR parameter. READ-ONLY MPR=0 }} 10560 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MPRR_DATA_1 (MPRR_DATA_1 RD {} ZERO ZERO FULL CTL {{Data read from the multi-purpose register 1 read requested by the READ_MPR parameter. READ-ONLY MPR=1 }} 10656 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MPRR_DATA_2 (MPRR_DATA_2 RD {} ZERO ZERO FULL CTL {{Data read from the multi-purpose register 2 read requested by the READ_MPR parameter. READ-ONLY MPR=2 }} 10752 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MPRR_DATA_3 (MPRR_DATA_3 RD {} ZERO ZERO FULL CTL {{Data read from the multi-purpose register 3 read requested by the READ_MPR parameter. READ-ONLY MPR=3 }} 10848 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F0_0:RW:8:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 0 0 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F0_0:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 0 0 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F0_0:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 0 1 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F1_0:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 0 1 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F1_0:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 0 2 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F2_0:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 0 2 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F2_0:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 1 0 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F0_1:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 1 0 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F0_1:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 1 1 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F1_1:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 1 1 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F1_1:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR0_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR0_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR0_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR1_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR1_DATA 1 2 --&gt; Returned 180: CADENCE_DEBUG_REG: MR1_DATA_F2_1:RW:0:18:=0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR2_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR2_DATA 1 2 --&gt; Returned 91: CADENCE_DEBUG_REG: MR2_DATA_F2_1:RW:0:18:=0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRSINGLE_DATA 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRSINGLE_DATA 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MRSINGLE_DATA_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MRSINGLE_DATA 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MRSINGLE_DATA 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MRSINGLE_DATA_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 0 0 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F0_0:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 0 1 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F1_0:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 0 2 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F2_0:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 1 0 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F0_1:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 1 1 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F1_1:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR3_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR3_DATA 1 2 --&gt; Returned 115: CADENCE_DEBUG_REG: MR3_DATA_F2_1:RW:0:18:=0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR4_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Fine_Granularity_Refresh: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Fine_Granularity_Refresh: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR4_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR4_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR5_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR5_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR5_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR6_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tccd_l_time: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ccdlMap: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR6_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR6_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MR8_DATA_0 (MR8_DATA_0 RD {} {MR8_DATA 0} ZERO FULL CTL {{Data to program into memory mode register 8 for each chip select. READ-ONLY. }} 12312 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MR8_DATA_1 (MR8_DATA_1 RD {} {MR8_DATA 1} ZERO FULL CTL {{Data to program into memory mode register 8 for each chip select. READ-ONLY. }} 12320 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F0_0:RW:8:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR10_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR10_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR10_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 0 0 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F0_0:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 0 1 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F1_0:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 0 2 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F2_0:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 1 0 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F0_1:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 1 1 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F1_1:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR11_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR11_DATA 1 2 --&gt; Returned 53: CADENCE_DEBUG_REG: MR11_DATA_F2_1:RW:0:18:=0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 0 0 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F0_0:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 0 1 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F1_0:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 0 2 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F2_0:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 1 0 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F0_1:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 1 1 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F1_1:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR12_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR12_DATA 1 2 --&gt; Returned 77: CADENCE_DEBUG_REG: MR12_DATA_F2_1:RW:0:18:=0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR13_DATA 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of data_mask_en: Parameter value true</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR13_DATA 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR13_DATA_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR13_DATA 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of data_mask_en: Parameter value true</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR13_DATA 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR13_DATA_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 0 0 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F0_0:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 0 1 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F1_0:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 0 2 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F2_0:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 1 0 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F0_1:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 1 1 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F1_1:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR14_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR14_DATA 1 2 --&gt; Returned 20: CADENCE_DEBUG_REG: MR14_DATA_F2_1:RW:0:18:=0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR16_DATA 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR16_DATA 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR16_DATA_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR16_DATA 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR16_DATA 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR16_DATA_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR17_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR17_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR17_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR18_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR18_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR18_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR19_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR19_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR19_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR20_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR20_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR20_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 0 0 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F0_0:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 0 1 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F1_0:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 0 2 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F2_0:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 1 0 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F0_1:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 1 1 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F1_1:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR22_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR22_DATA 1 2 --&gt; Returned 24: CADENCE_DEBUG_REG: MR22_DATA_F2_1:RW:0:18:=0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR23_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR23_DATA --&gt; Returned 32: CADENCE_DEBUG_REG: MR23_DATA:RW:0:18:=0x000020</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR33_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR33_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR33_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR34_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR34_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR34_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F0_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F1_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F2_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 1 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F0_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 1 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F1_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR35_DATA 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR35_DATA 1 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MR35_DATA_F2_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MR37_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ddr5: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MR37_DATA --&gt; Returned 0: CADENCE_DEBUG_REG: MR37_DATA:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WCKI_OSC_TIMER_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WCKI_OSC_TIMER_DATA --&gt; Returned 0: CADENCE_DEBUG_REG: WCKI_OSC_TIMER_DATA:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WCKO_OSC_TIMER_DATA" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WCKO_OSC_TIMER_DATA --&gt; Returned 0: CADENCE_DEBUG_REG: WCKO_OSC_TIMER_DATA:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: MPRR_SW_PROMOTE_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: MPRR_SW_PROMOTE_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MPRR_SW_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: MPRR_SW_PROMOTE_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_MAP_0 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_MAP_0:RW+:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_VALID_0 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_VALID_0:RW+:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_MAP_1 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_MAP_1:RW+:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_VALID_1 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_VALID_1:RW+:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_MAP_2 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_MAP_2:RW+:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FSP_VALID_2 --&gt; FAKED 0: CADENCE_DEBUG_REG: FSP_VALID_2:RW+:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_GO" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_GO --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_GO:WR:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDR_SPACE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDR_SPACE --&gt; Returned 0: CADENCE_DEBUG_REG: ADDR_SPACE:RW:16:6:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_DATA_CHECK" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_DATA_CHECK --&gt; Returned 1: CADENCE_DEBUG_REG: BIST_DATA_CHECK:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_ECC_LANE_CHECK" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_ECC_LANE_CHECK --&gt; Returned 1: CADENCE_DEBUG_REG: BIST_ECC_LANE_CHECK:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_START_ADDRESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_START_ADDRESS --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_START_ADDRESS:RW:0:38:=0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_DATA_MASK" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_DATA_MASK --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_DATA_MASK:RW:0:144:=0x000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_TEST_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_TEST_MODE --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_TEST_MODE:RW:16:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_DATA_PATTERN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_DATA_PATTERN --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_DATA_PATTERN:RW:0:288:=0x000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_RET_STATE (BIST_RET_STATE RD {} ZERO ZERO FULL CTL {{Indicates if BIST is in a retention wait state, used when the BIST_TEST_MODE parameter is programmed to 2 or 3. Value of 1 indicates BIST is waiting. READ-ONLY }} 15552 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BIST_ERR_STOP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_ERR_STOP --&gt; Returned 0: CADENCE_DEBUG_REG: BIST_ERR_STOP:RW:8:12:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_ERR_COUNT (BIST_ERR_COUNT RD {} ZERO ZERO FULL CTL {{Indicates the number of BIST errors found when the BIST_TEST_MODE parameter is programmed to 1, 2 or 3. READ-ONLY }} 15584 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BIST_RET_STATE_EXIT --&gt; FAKED 0: CADENCE_DEBUG_REG: BIST_RET_STATE_EXIT:WR:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_ENABLE:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__FWC --&gt; FAKED 0: CADENCE_DEBUG_REG: FWC:RW+:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__XOR_CHECK_BITS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__XOR_CHECK_BITS --&gt; Returned 0: CADENCE_DEBUG_REG: XOR_CHECK_BITS:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_DISABLE_W_UC_ERR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_DISABLE_W_UC_ERR --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_DISABLE_W_UC_ERR:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_WRITEBACK_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_WRITEBACK_EN --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_WRITEBACK_EN:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_TYPE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_TYPE --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_TYPE:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INLINE_ECC_SAME_PAGE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INLINE_ECC_SAME_PAGE --&gt; Returned 0: CADENCE_DEBUG_REG: INLINE_ECC_SAME_PAGE:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INLINE_ECC_BANK_OFFSET" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INLINE_ECC_BANK_OFFSET --&gt; Returned 0: CADENCE_DEBUG_REG: INLINE_ECC_BANK_OFFSET:RW:0:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INLINE_ECC_BG_OFFSET" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INLINE_ECC_BG_OFFSET --&gt; Returned 0: CADENCE_DEBUG_REG: INLINE_ECC_BG_OFFSET:RW:8:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_READ_CACHING_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_READ_CACHING_EN --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_READ_CACHING_EN:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_WRITE_COMBINING_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_WRITE_COMBINING_EN --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_WRITE_COMBINING_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__MAX_WR_COMBINE will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__DIRTY_TO_VALID_WRITES will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_U_ADDR (ECC_U_ADDR RD {} ZERO ZERO FULL CTL {{Address of uncorrectable ECC event. READ-ONLY }} 15776 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_U_SYND (ECC_U_SYND RD {} ZERO ZERO FULL CTL {{Syndrome for uncorrectable ECC event. READ-ONLY }} 15816 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_U_DATA (ECC_U_DATA RD {} ZERO ZERO FULL CTL {{Data associated with uncorrectable ECC event. READ-ONLY }} 15840 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_C_ADDR (ECC_C_ADDR RD {} ZERO ZERO FULL CTL {{Address of correctable ECC event. READ-ONLY }} 15904 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_C_SYND (ECC_C_SYND RD {} ZERO ZERO FULL CTL {{Syndrome for correctable ECC event. READ-ONLY }} 15944 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_C_DATA (ECC_C_DATA RD {} ZERO ZERO FULL CTL {{Data associated with correctable ECC event. READ-ONLY }} 15968 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_U_ID (ECC_U_ID RD {} ZERO ZERO FULL CTL {{Source ID associated with the uncorrectable ECC event. READ-ONLY }} 16032 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_C_ID (ECC_C_ID RD {} ZERO ZERO FULL CTL {{Source ID associated with correctable ECC event. READ-ONLY }} 16048 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_U_ADDR (RMODW_ECC_U_ADDR RD {} ZERO ZERO FULL CTL {{Address of uncorrectable rmodw ECC event. READ-ONLY }} 16064 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_U_SYND (RMODW_ECC_U_SYND RD {} ZERO ZERO FULL CTL {{Syndrome for uncorrectable rmodw ECC event. READ-ONLY }} 16104 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_U_DATA (RMODW_ECC_U_DATA RD {} ZERO ZERO FULL CTL {{Data associated with uncorrectable rmodw ECC event. READ-ONLY }} 16128 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_C_ADDR (RMODW_ECC_C_ADDR RD {} ZERO ZERO FULL CTL {{Address of correctable rmodw ECC event. READ-ONLY }} 16192 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_C_SYND (RMODW_ECC_C_SYND RD {} ZERO ZERO FULL CTL {{Syndrome for correctable rmodw ECC event. READ-ONLY }} 16232 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_C_DATA (RMODW_ECC_C_DATA RD {} ZERO ZERO FULL CTL {{Data associated with correctable rmodw ECC event. READ-ONLY }} 16256 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_U_ID (RMODW_ECC_U_ID RD {} ZERO ZERO FULL CTL {{Source ID associated with the uncorrectable rmodw ECC event. READ-ONLY }} 16320 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__RMODW_ECC_C_ID (RMODW_ECC_C_ID RD {} ZERO ZERO FULL CTL {{Source ID associated with correctable ECC rmodw event. READ-ONLY }} 16336 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_0 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_0 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_0:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_1 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_1 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_1:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_2" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_2 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_2:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_2" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_2 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_2:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_3" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_3 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_3:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_3" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_3 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_3:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_4" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_4 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_4:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_4" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_4 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_4:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_5" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_5 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_5:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_5" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_5 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_5:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_6" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_6 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_6:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_6" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_6 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_6:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_START_ADDR_7" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_START_ADDR_7 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_START_ADDR_7:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_END_ADDR_7" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_END_ADDR_7 --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_END_ADDR_7:RW:0:18:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NON_ECC_REGION_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NON_ECC_REGION_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: NON_ECC_REGION_ENABLE:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_START --&gt; FAKED 0: CADENCE_DEBUG_REG: ECC_SCRUB_START:WR:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ECC_SCRUB_IN_PROGRESS (ECC_SCRUB_IN_PROGRESS RD {} ZERO ZERO FULL CTL {{Reports the scrubbing operation status. A value of 1 indicates that the controller is in the process of performing a scrubbing operation. READ-ONLY }} 16872 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_LEN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ddr5: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Controller_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Memory_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_LEN --&gt; Returned 16: CADENCE_DEBUG_REG: ECC_SCRUB_LEN:RW:16:13:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_MODE --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_SCRUB_MODE:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_INTERVAL" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_INTERVAL --&gt; Returned 1000: CADENCE_DEBUG_REG: ECC_SCRUB_INTERVAL:RW:8:16:=0x03e8</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_IDLE_CNT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_IDLE_CNT --&gt; Returned 100: CADENCE_DEBUG_REG: ECC_SCRUB_IDLE_CNT:RW:0:16:=0x0064</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_START_ADDR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_START_ADDR --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_SCRUB_START_ADDR:RW:0:38:=0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ECC_SCRUB_END_ADDR" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ECC_SCRUB_END_ADDR --&gt; Returned 0: CADENCE_DEBUG_REG: ECC_SCRUB_END_ADDR:RW:0:38:=0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CMD_BLK_SPLIT_SIZE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CMD_BLK_SPLIT_SIZE --&gt; Returned 0: CADENCE_DEBUG_REG: CMD_BLK_SPLIT_SIZE:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__LONG_COUNT_MASK" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__LONG_COUNT_MASK --&gt; Returned 0: CADENCE_DEBUG_REG: LONG_COUNT_MASK:RW:16:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_NORM_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Per_Bank_Refresh: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_NORM_THRESHOLD --&gt; Returned 20: CADENCE_DEBUG_REG: AREF_NORM_THRESHOLD:RW:24:5:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_HIGH_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Per_Bank_Refresh: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_HIGH_THRESHOLD --&gt; Returned 21: CADENCE_DEBUG_REG: AREF_HIGH_THRESHOLD:RW:0:5:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_MAX_DEFICIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_MAX_DEFICIT --&gt; Returned 24: CADENCE_DEBUG_REG: AREF_MAX_DEFICIT:RW:8:5:=0x18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_MAX_CREDIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_MAX_CREDIT --&gt; Returned 12: CADENCE_DEBUG_REG: AREF_MAX_CREDIT:RW:16:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_CMD_MAX_PER_TREFI" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_CMD_MAX_PER_TREFI --&gt; Returned 8: CADENCE_DEBUG_REG: AREF_CMD_MAX_PER_TREFI:RW:24:4:=0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AREF_NULL_PEND_EXT_REQ" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Advanced_Low_Power_Control: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Advanced_Low_Power_Control: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AREF_NULL_PEND_EXT_REQ --&gt; Returned 1: CADENCE_DEBUG_REG: AREF_NULL_PEND_EXT_REQ:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCS_OPT_THRESHOLD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCS_OPT_THRESHOLD --&gt; Returned 3: CADENCE_DEBUG_REG: ZQCS_OPT_THRESHOLD:RW:8:3:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_NORM_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_HIGH_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_HIGH_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_NORM_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_NORM_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_NORM_THRESHOLD_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_HIGH_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_HIGH_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_HIGH_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_TIMEOUT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_TIMEOUT_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_TIMEOUT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_TIMEOUT_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_TIMEOUT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_TIMEOUT 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_TIMEOUT_F0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_PROMOTE_THRESHOLD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_PROMOTE_THRESHOLD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_PROMOTE_THRESHOLD_F0:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_NORM_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_HIGH_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_HIGH_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_NORM_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_NORM_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_NORM_THRESHOLD_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_HIGH_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_HIGH_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_HIGH_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_TIMEOUT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_TIMEOUT_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_TIMEOUT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_TIMEOUT_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_TIMEOUT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_TIMEOUT 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_TIMEOUT_F1:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_PROMOTE_THRESHOLD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_PROMOTE_THRESHOLD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_PROMOTE_THRESHOLD_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_NORM_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_NORM_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_HIGH_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_HIGH_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_HIGH_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_HIGH_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_NORM_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_NORM_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_NORM_THRESHOLD_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_HIGH_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_HIGH_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_HIGH_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALSTART_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALSTART_TIMEOUT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALSTART_TIMEOUT_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CALLATCH_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CALLATCH_TIMEOUT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CALLATCH_TIMEOUT_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CS_TIMEOUT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CS_TIMEOUT 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CS_TIMEOUT_F2:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_PROMOTE_THRESHOLD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_PROMOTE_THRESHOLD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_PROMOTE_THRESHOLD_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__TIMEOUT_TIMER_LOG (TIMEOUT_TIMER_LOG RD {} ZERO ZERO FULL CTL {{Reflects which timers experienced a timeout error (or had an uncleared error) when the timeout interrupt fired.  Bit (0) correlates to a ZQ cal init, cs, cl, or reset FM timeout.  Bit (1) correlates to the ZQ calstart FM timeout.  Bit (2) correlates to the ZQ callatch FM timeout.  Bit (3) correlates to the MRR temperature check FM timeout.  Bit (4) correlates to the DQS oscillator FM timeout.  Bit (5) correlates to the DFI update FM timeout.  Bit (6) correlates to the low power interface wakeup timeout.  Bit (7) correlates to the low power interface wakeup timeout for LPI Control Interface.  Bit (9) correlates to the auto refresh max deficit timeout.  READ-ONLY }} 17568 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQINIT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqinit_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQINIT 0 --&gt; Returned 512: CADENCE_DEBUG_REG: ZQINIT_F0:RW_D:16:12:=0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcl_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCL 0 --&gt; Returned 256: CADENCE_DEBUG_REG: ZQCL_F0:RW:0:12:=0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCS 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCS 0 --&gt; Returned 64: CADENCE_DEBUG_REG: ZQCS_F0:RW:16:12:=0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCAL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcal tZQCAL}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcal: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcal: Parameter value {1.0 us}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.0 us}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQCAL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCAL 0 --&gt; Returned 1068: CADENCE_DEBUG_REG: TZQCAL_F0:RW:0:12:=0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQLAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqlat tZQLAT tZQLAT_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqlat: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqlat: Parameter value {30.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {30.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQLAT 0 --&gt; Returned 33: CADENCE_DEBUG_REG: TZQLAT_F0:RW:16:7:=0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQINIT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqinit_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQINIT 1 --&gt; Returned 512: CADENCE_DEBUG_REG: ZQINIT_F1:RW_D:0:12:=0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcl_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCL 1 --&gt; Returned 256: CADENCE_DEBUG_REG: ZQCL_F1:RW:16:12:=0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCS 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCS 1 --&gt; Returned 64: CADENCE_DEBUG_REG: ZQCS_F1:RW:0:12:=0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCAL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcal tZQCAL}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcal: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcal: Parameter value {1.0 us}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.0 us}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQCAL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCAL 1 --&gt; Returned 1068: CADENCE_DEBUG_REG: TZQCAL_F1:RW:16:12:=0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQLAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqlat tZQLAT tZQLAT_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqlat: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqlat: Parameter value {30.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {30.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQLAT 1 --&gt; Returned 33: CADENCE_DEBUG_REG: TZQLAT_F1:RW:0:7:=0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQINIT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqinit_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQINIT 2 --&gt; Returned 512: CADENCE_DEBUG_REG: ZQINIT_F2:RW_D:8:12:=0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqoper_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcl_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCL 2 --&gt; Returned 256: CADENCE_DEBUG_REG: ZQCL_F2:RW:0:12:=0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCS 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcs_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCS 2 --&gt; Returned 64: CADENCE_DEBUG_REG: ZQCS_F2:RW:16:12:=0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQCAL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqcal tZQCAL}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqcal: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqcal: Parameter value {1.0 us}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.0 us}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQCAL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQCAL 2 --&gt; Returned 1068: CADENCE_DEBUG_REG: TZQCAL_F2:RW:0:12:=0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TZQLAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tzqlat tZQLAT tZQLAT_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqlat: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tzqlat: Parameter value {30.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {30.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tZQLAT_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TZQLAT 2 --&gt; Returned 33: CADENCE_DEBUG_REG: TZQLAT_F2:RW:16:7:=0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_SW_REQ_START_LATCH_MAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_SW_REQ_START_LATCH_MAP --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_SW_REQ_START_LATCH_MAP:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_REQ --&gt; FAKED 0: CADENCE_DEBUG_REG: ZQ_REQ:WR:0:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__ZQ_REQ_PENDING (ZQ_REQ_PENDING RD {} ZERO ZERO FULL CTL {{Indicates that a ZQ command is currently in progress or waiting to run. Value of 1 indicates command in progress or waiting to run. When this is asserted, no writes to ZQ_REQ should occur. READ-ONLY }} 17832 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQRESET 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqreset_minTck tZQRESET_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQRESET 0 --&gt; Returned 54: CADENCE_DEBUG_REG: ZQRESET_F0:RW:16:12:=0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQRESET 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqreset_minTck tZQRESET_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQRESET 1 --&gt; Returned 54: CADENCE_DEBUG_REG: ZQRESET_F1:RW:0:12:=0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQRESET 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tzqreset_minTck tZQRESET_minTck: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQRESET 2 --&gt; Returned 54: CADENCE_DEBUG_REG: ZQRESET_F2:RW:16:12:=0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQCS_ROTATE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQCS_ROTATE --&gt; Returned 1: CADENCE_DEBUG_REG: ZQCS_ROTATE:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CAL_START_MAP_0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CAL_START_MAP_0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CAL_START_MAP_0:RW_D:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CAL_LATCH_MAP_0" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CAL_LATCH_MAP_0 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CAL_LATCH_MAP_0:RW_D:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CAL_START_MAP_1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CAL_START_MAP_1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CAL_START_MAP_1:RW_D:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ZQ_CAL_LATCH_MAP_1" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ZQ_CAL_LATCH_MAP_1 --&gt; Returned 0: CADENCE_DEBUG_REG: ZQ_CAL_LATCH_MAP_1:RW_D:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_DIFF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_DIFF 0 --&gt; Returned 2: CADENCE_DEBUG_REG: BANK_DIFF_0:RW:8:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_DIFF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_DIFF 1 --&gt; Returned 2: CADENCE_DEBUG_REG: BANK_DIFF_1:RW:16:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ROW_DIFF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Rows_Supported: Parameter value 18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ROW_DIFF 0 --&gt; Returned 3: CADENCE_DEBUG_REG: ROW_DIFF_0:RW:24:3:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ROW_DIFF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Rows_Supported: Parameter value 18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ROW_DIFF 1 --&gt; Returned 3: CADENCE_DEBUG_REG: ROW_DIFF_1:RW:0:3:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__COL_DIFF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_Columns_Supported: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Columns_Supported: Parameter value 11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__COL_DIFF 0 --&gt; Returned 1: CADENCE_DEBUG_REG: COL_DIFF_0:RW:8:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__COL_DIFF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_Columns_Supported: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_Columns_Supported: Parameter value 11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__COL_DIFF 1 --&gt; Returned 1: CADENCE_DEBUG_REG: COL_DIFF_1:RW:16:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CID_DIFF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of componentDdrSOMA: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CID_DIFF 0 --&gt; Returned 1: CADENCE_DEBUG_REG: CID_DIFF_0:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CID_DIFF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of 3DS_Support_Max_Logical_CS: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of 3DS_Support_Max_Logical_CS: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of componentDdrSOMA: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CID_DIFF 1 --&gt; Returned 1: CADENCE_DEBUG_REG: CID_DIFF_1:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BG_DIFF 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BG_DIFF 0 --&gt; Returned 3: CADENCE_DEBUG_REG: BG_DIFF_0:RW:8:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BG_DIFF 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Thirtytwo_Bank_Mode_Support: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Sixteen_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Sixteen_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Eight_Bank_Mode_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Eight_Bank_Mode_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BG_DIFF 1 --&gt; Returned 3: CADENCE_DEBUG_REG: BG_DIFF_1:RW:16:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_VAL_LOWER 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_VAL_LOWER 0 --&gt; Returned 0: CADENCE_DEBUG_REG: CS_VAL_LOWER_0:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_VAL_UPPER 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_VAL_UPPER 0 --&gt; Returned 255: CADENCE_DEBUG_REG: CS_VAL_UPPER_0:RW:16:16:=0x00ff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ROW_START_VAL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ROW_START_VAL 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ROW_START_VAL_0:RW:0:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_MSK 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_MSK 0 --&gt; Returned 31: CADENCE_DEBUG_REG: CS_MSK_0:RW:8:16:=0x001f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_VAL_LOWER 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_VAL_LOWER 1 --&gt; Returned 0xFFFF: CADENCE_DEBUG_REG: CS_VAL_LOWER_1:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_VAL_UPPER 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_VAL_UPPER 1 --&gt; Returned 0xFFFF: CADENCE_DEBUG_REG: CS_VAL_UPPER_1:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ROW_START_VAL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ROW_START_VAL 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ROW_START_VAL_1:RW:0:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_MSK 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of list_csmsk_csval: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of list_csmsk_csval: Parameter value {0 31 0 0 255} {1 65535 0 65535 65535}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_MSK 1 --&gt; Returned 65535: CADENCE_DEBUG_REG: CS_MSK_1:RW:8:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PROGRAMMABLE_ADDRESS_ORDER" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_prog_addr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_prog_addr: Parameter value false</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PROGRAMMABLE_ADDRESS_ORDER --&gt; Returned 0: CADENCE_DEBUG_REG: PROGRAMMABLE_ADDRESS_ORDER:RW+:24:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__BANK_START_BIT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__APREBIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__APREBIT --&gt; Returned 11: CADENCE_DEBUG_REG: APREBIT:RW_D:8:5:=0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AGE_COUNT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AGE_COUNT --&gt; Returned 255: CADENCE_DEBUG_REG: AGE_COUNT:RW:16:8:=0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__COMMAND_AGE_COUNT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__COMMAND_AGE_COUNT --&gt; Returned 255: CADENCE_DEBUG_REG: COMMAND_AGE_COUNT:RW:24:8:=0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDR_CMP_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDR_CMP_EN --&gt; Returned 1: CADENCE_DEBUG_REG: ADDR_CMP_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ADDR_COLLISION_MPM_DIS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ADDR_COLLISION_MPM_DIS --&gt; Returned 0: CADENCE_DEBUG_REG: ADDR_COLLISION_MPM_DIS:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BANK_SPLIT_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BANK_SPLIT_EN --&gt; Returned 1: CADENCE_DEBUG_REG: BANK_SPLIT_EN:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PLACEMENT_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PLACEMENT_EN --&gt; Returned 1: CADENCE_DEBUG_REG: PLACEMENT_EN:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PRIORITY_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PRIORITY_EN --&gt; Returned 1: CADENCE_DEBUG_REG: PRIORITY_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RW_SAME_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RW_SAME_EN --&gt; Returned 1: CADENCE_DEBUG_REG: RW_SAME_EN:RW:8:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RW_SAME_PAGE_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RW_SAME_PAGE_EN --&gt; Returned 1: CADENCE_DEBUG_REG: RW_SAME_PAGE_EN:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_SAME_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_SAME_EN --&gt; Returned 1: CADENCE_DEBUG_REG: CS_SAME_EN:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2R_SPLIT_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2R_SPLIT_EN --&gt; Returned 1: CADENCE_DEBUG_REG: W2R_SPLIT_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DISABLE_RW_GROUP_W_BNK_CONFLICT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DISABLE_RW_GROUP_W_BNK_CONFLICT --&gt; Returned 1: CADENCE_DEBUG_REG: DISABLE_RW_GROUP_W_BNK_CONFLICT:RW:8:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NUM_Q_ENTRIES_ACT_DISABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NUM_Q_ENTRIES_ACT_DISABLE --&gt; Returned 16: CADENCE_DEBUG_REG: NUM_Q_ENTRIES_ACT_DISABLE:RW:16:5:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__SWAP_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__SWAP_EN --&gt; Returned 0: CADENCE_DEBUG_REG: SWAP_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DISABLE_RD_INTERLEAVE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of is_ecc_inline: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_inline: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DISABLE_RD_INTERLEAVE --&gt; Returned 1: CADENCE_DEBUG_REG: DISABLE_RD_INTERLEAVE:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INHIBIT_DRAM_CMD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INHIBIT_DRAM_CMD --&gt; Returned 0: CADENCE_DEBUG_REG: INHIBIT_DRAM_CMD:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_MAP" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Maximum_PHY_Ranks: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Maximum_PHY_Ranks: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Dual_Chn_40bit_DDR5_72bit_DDR4_Combo_PHY: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_MAP --&gt; Returned 1: CADENCE_DEBUG_REG: CS_MAP:RW:16:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BURST_ON_FLY_BIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BURST_ON_FLY_BIT --&gt; Returned 0: CADENCE_DEBUG_REG: BURST_ON_FLY_BIT:RW:24:4:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MEM_DP_REDUCTION" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep_x40: Parameter value false</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of numChannels: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of HMC_Interface: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ecc_enabled: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Memory_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: cadence_reg__MEM_DP_REDUCTION: is_lockstep_x40=false num_channels=1 dq_per_channel=32 hmc_interface=0 ecc_enabled=0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MEM_DP_REDUCTION --&gt; Returned 0: CADENCE_DEBUG_REG: MEM_DP_REDUCTION:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MEMDATA_RATIO 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ddr5: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Controller_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Memory_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MEMDATA_RATIO 0 --&gt; Returned 1: CADENCE_DEBUG_REG: MEMDATA_RATIO_0:RW:8:3:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MEMDATA_RATIO 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_ddr5: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Controller_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Memory_Data_Width: Parameter value 32</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MEMDATA_RATIO 1 --&gt; Returned 1: CADENCE_DEBUG_REG: MEMDATA_RATIO_1:RW:16:3:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_0 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_0 0 0 --&gt; Returned 1: CADENCE_DEBUG_REG: DEVICE0_BYTE0_CS0:RW:0:9:=0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_1 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_1 0 1 --&gt; Returned 4: CADENCE_DEBUG_REG: DEVICE1_BYTE0_CS0:RW:16:9:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_2 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_2 0 2 --&gt; Returned 16: CADENCE_DEBUG_REG: DEVICE2_BYTE0_CS0:RW:0:9:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_3 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_3 0 3 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE3_BYTE0_CS0:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_4 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_4 0 4 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE4_BYTE0_CS0:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_5 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_5 0 5 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE5_BYTE0_CS0:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_6 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_6 0 6 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE6_BYTE0_CS0:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_7 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_7 0 7 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE7_BYTE0_CS0:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_8 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_8 0 8 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE8_BYTE0_CS0:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_0 1 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_0 1 0 --&gt; Returned 1: CADENCE_DEBUG_REG: DEVICE0_BYTE0_CS1:RW:16:9:=0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_1 1 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_1 1 1 --&gt; Returned 4: CADENCE_DEBUG_REG: DEVICE1_BYTE0_CS1:RW:0:9:=0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_2 1 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_2 1 2 --&gt; Returned 16: CADENCE_DEBUG_REG: DEVICE2_BYTE0_CS1:RW:16:9:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_3 1 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_3 1 3 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE3_BYTE0_CS1:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_4 1 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_4 1 4 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE4_BYTE0_CS1:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_5 1 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_5 1 5 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE5_BYTE0_CS1:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_6 1 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_6 1 6 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE6_BYTE0_CS1:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_7 1 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_7 1 7 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE7_BYTE0_CS1:RW:0:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DEVICE_BYTE0_8 1 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of byte0_pos: Parameter value </message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of ECC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of ECC_Enable: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DEVICE_BYTE0_8 1 8 --&gt; Returned 0: CADENCE_DEBUG_REG: DEVICE8_BYTE0_CS1:RW:16:9:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__MDQS_MULT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__MDQS_MULT --&gt; Returned 1: CADENCE_DEBUG_REG: MDQS_MULT:RW:0:2:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__Q_FULLNESS" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__Q_FULLNESS --&gt; Returned 0: CADENCE_DEBUG_REG: Q_FULLNESS:RW:8:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__IN_ORDER_ACCEPT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__IN_ORDER_ACCEPT --&gt; Returned 0: CADENCE_DEBUG_REG: IN_ORDER_ACCEPT:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_ORDER_REQ" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_ORDER_REQ --&gt; Returned 0: CADENCE_DEBUG_REG: WR_ORDER_REQ:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CONTROLLER_BUSY (CONTROLLER_BUSY RD {} ZERO ZERO FULL CTL {{Indicator that the controller is processing a command. Evaluates all ports for outstanding transactions. Value of 1 indicates controller busy. READ-ONLY }} 18656 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CTRLUPD_REQ --&gt; FAKED 0: CADENCE_DEBUG_REG: CTRLUPD_REQ:WR:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_PREAMBLE_LEN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_PREAMBLE_LEN 0 --&gt; Returned 1: CADENCE_DEBUG_REG: RD_PREAMBLE_LEN_F0:RW:0:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_PREAMBLE_LEN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_PREAMBLE_LEN 0 --&gt; Returned 1: CADENCE_DEBUG_REG: WR_PREAMBLE_LEN_F0:RW:8:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_PREAMBLE_LEN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_PREAMBLE_LEN 1 --&gt; Returned 1: CADENCE_DEBUG_REG: RD_PREAMBLE_LEN_F1:RW:16:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_PREAMBLE_LEN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_PREAMBLE_LEN 1 --&gt; Returned 1: CADENCE_DEBUG_REG: WR_PREAMBLE_LEN_F1:RW:24:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_PREAMBLE_LEN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_PREAMBLE_LEN 2 --&gt; Returned 1: CADENCE_DEBUG_REG: RD_PREAMBLE_LEN_F2:RW:0:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_PREAMBLE_LEN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_PREAMBLE_LEN 2 --&gt; Returned 1: CADENCE_DEBUG_REG: WR_PREAMBLE_LEN_F2:RW:8:8:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_PREAMBLE_TRAINING_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_PREAMBLE_TRAINING_EN --&gt; Returned 1: CADENCE_DEBUG_REG: RD_PREAMBLE_TRAINING_EN:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_DBI_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_DBI_EN --&gt; Returned 0: CADENCE_DEBUG_REG: WR_DBI_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_DBI_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_DBI_EN --&gt; Returned 1: CADENCE_DEBUG_REG: RD_DBI_EN:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DFI_ERROR (DFI_ERROR RD {} ZERO ZERO FULL CTL {{Indicates that the DFI error flag has been asserted. READ-ONLY }} 18760 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__DFI_ERROR_INFO (DFI_ERROR_INFO RD {} ZERO ZERO FULL CTL {{Holds the encoded DFI error type associated with the DFI_ERROR parameter assertion. READ-ONLY }} 18784 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__BG_ROTATE_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of bg_rotation: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__BG_ROTATE_EN --&gt; Returned 0: CADENCE_DEBUG_REG: BG_ROTATE_EN:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__GATHER_FIFO_RESYNC will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__POSTAMBLE_SUPPORT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__POSTAMBLE_SUPPORT --&gt; Returned 2: CADENCE_DEBUG_REG: POSTAMBLE_SUPPORT:RW:24:2:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_MASTER (INT_STATUS_MASTER RD {} ZERO ZERO FULL CTL {{Master status reporting register for interrupt status groups. READ-ONLY }} 18848 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_MASTER" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_MASTER --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_MASTER:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_TIMEOUT (INT_STATUS_TIMEOUT RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Timeout monitors. READ-ONLY }} 18912 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_ECC (INT_STATUS_ECC RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to ECC. READ-ONLY }} 18944 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_LOWPOWER (INT_STATUS_LOWPOWER RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Low Power. READ-ONLY }} 18976 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_STATUS_PORT_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_STATUS_RFIFO_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_TRAINING (INT_STATUS_TRAINING RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Training/Calibration. READ-ONLY }} 19040 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_USERIF (INT_STATUS_USERIF RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to ASIC to Controller Interface. READ-ONLY }} 19072 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_MISC (INT_STATUS_MISC RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Miscellaneous features. READ-ONLY }} 19104 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_BIST (INT_STATUS_BIST RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to BIST. READ-ONLY }} 19120 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_STATUS_CRC will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_DFI (INT_STATUS_DFI RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to DFI. READ-ONLY }} 19136 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_DIMM (INT_STATUS_DIMM RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to DIMM. READ-ONLY }} 19144 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_FREQ (INT_STATUS_FREQ RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Frequency Scaling. READ-ONLY }} 19152 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_INIT (INT_STATUS_INIT RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Initialization. READ-ONLY }} 19160 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_MODE (INT_STATUS_MODE RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Memory Mode Settings. READ-ONLY }} 19168 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__INT_STATUS_PARITY (INT_STATUS_PARITY RD {} ZERO ZERO FULL CTL {{Status of interrupts in the controller related to Parity. READ-ONLY }} 19176 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_TIMEOUT --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_TIMEOUT:WR:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_ECC --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_ECC:WR:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_LOWPOWER --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_LOWPOWER:WR:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_ACK_PORT_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_ACK_RFIFO_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_TRAINING --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_TRAINING:WR:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_USERIF --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_USERIF:WR:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_MISC --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_MISC:WR:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_BIST --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_BIST:WR:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_ACK_CRC will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_DFI --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_DFI:WR:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_DIMM --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_DIMM:WR:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_FREQ --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_FREQ:WR:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_INIT --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_INIT:WR:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_MODE --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_MODE:WR:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_ACK_PARITY --&gt; FAKED 0: CADENCE_DEBUG_REG: INT_ACK_PARITY:WR:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_TIMEOUT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_TIMEOUT --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_TIMEOUT:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_ECC" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_ECC --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_ECC:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_LOWPOWER" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_LOWPOWER --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_LOWPOWER:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_MASK_PORT_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_MASK_RFIFO_TIMEOUT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_TRAINING" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_TRAINING --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_TRAINING:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_USERIF" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_USERIF --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_USERIF:RW:0:32:=0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_MISC" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_MISC --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_MISC:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_BIST" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_BIST --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_BIST:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__INT_MASK_CRC will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_DFI" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_DFI --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_DFI:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_DIMM" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_DIMM --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_DIMM:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_FREQ" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_FREQ --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_FREQ:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_INIT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_INIT --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_INIT:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_MODE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_MODE --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_MODE:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__INT_MASK_PARITY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__INT_MASK_PARITY --&gt; Returned 0: CADENCE_DEBUG_REG: INT_MASK_PARITY:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__OUT_OF_RANGE_ADDR (OUT_OF_RANGE_ADDR RD {} ZERO ZERO FULL CTL {{Address of command that caused an out-of-range interrupt. READ-ONLY }} 19776 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__OUT_OF_RANGE_LENGTH (OUT_OF_RANGE_LENGTH RD {} ZERO ZERO FULL CTL {{Length of command that caused an out-of-range interrupt. READ-ONLY }} 19816 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__OUT_OF_RANGE_TYPE (OUT_OF_RANGE_TYPE RD {} ZERO ZERO FULL CTL {{Type of command that caused an out-of-range interrupt. READ-ONLY }} 19832 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__OUT_OF_RANGE_SOURCE_ID (OUT_OF_RANGE_SOURCE_ID RD {} ZERO ZERO FULL CTL {{Source ID of command that caused an out-of-range interrupt. READ-ONLY }} 19840 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_EXP_DATA (BIST_EXP_DATA RD {} ZERO ZERO FULL CTL {{Expected data on BIST error. READ-ONLY }} 19872 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_FAIL_DATA (BIST_FAIL_DATA RD {} ZERO ZERO FULL CTL {{Actual data on BIST error. READ-ONLY }} 20160 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_FAIL_ADDR (BIST_FAIL_ADDR RD {} ZERO ZERO FULL CTL {{Address of BIST error. READ-ONLY }} 20448 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PORT_CMD_ERROR_ADDR (PORT_CMD_ERROR_ADDR RD {} ZERO ZERO FULL CTL {{Address of command that caused the PORT command error. READ-ONLY }} 20512 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PORT_CMD_ERROR_ID (PORT_CMD_ERROR_ID RD {} ZERO ZERO FULL CTL {{Source ID of command that caused the PORT command error. READ-ONLY }} 20552 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__PORT_CMD_ERROR_TYPE (PORT_CMD_ERROR_TYPE RD {} ZERO ZERO FULL CTL {{Type of error and access type that caused the PORT command error. READ-ONLY }} 20568 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTUP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tODTUP}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTUP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTUP 0 --&gt; Returned 267: CADENCE_DEBUG_REG: TODTUP_F0:RW:0:16:=0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTUP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tODTUP}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTUP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTUP 1 --&gt; Returned 267: CADENCE_DEBUG_REG: TODTUP_F1:RW:16:16:=0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTUP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tODTUP}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTUP: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTUP 2 --&gt; Returned 267: CADENCE_DEBUG_REG: TODTUP_F2:RW:0:16:=0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PD_NT_ODT_EN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PD_NT_ODT_EN 0 --&gt; Returned 0: CADENCE_DEBUG_REG: PD_NT_ODT_EN_F0:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PD_NT_ODT_EN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PD_NT_ODT_EN 1 --&gt; Returned 0: CADENCE_DEBUG_REG: PD_NT_ODT_EN_F1:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PD_NT_ODT_EN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PD_NT_ODT_EN 2 --&gt; Returned 0: CADENCE_DEBUG_REG: PD_NT_ODT_EN_F2:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTL_2CMD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTL_2CMD 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TODTL_2CMD_F0:RW:8:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_WR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_WR 0 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_WR_F0:RW:16:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_RD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_RD 0 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_RD_F0:RW:24:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTL_2CMD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTL_2CMD 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TODTL_2CMD_F1:RW:0:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_WR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_WR 1 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_WR_F1:RW:8:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_RD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_RD 1 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_RD_F1:RW:16:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTL_2CMD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTL_2CMD 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TODTL_2CMD_F2:RW:24:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_WR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_WR 2 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_WR_F2:RW:0:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TODTH_RD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of CRC_Enable: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CRC_Enable: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TODTH_RD 2 --&gt; Returned 1: CADENCE_DEBUG_REG: TODTH_RD_F2:RW:8:4:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_EN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_EN 0 --&gt; Returned 1: CADENCE_DEBUG_REG: ODT_EN_F0:RW:16:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_EN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_EN 1 --&gt; Returned 1: CADENCE_DEBUG_REG: ODT_EN_F1:RW:24:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_EN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_EN 2 --&gt; Returned 1: CADENCE_DEBUG_REG: ODT_EN_F2:RW:0:1:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__EN_ODT_ASSERT_EXCEPT_RD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__EN_ODT_ASSERT_EXCEPT_RD --&gt; Returned 0: CADENCE_DEBUG_REG: EN_ODT_ASSERT_EXCEPT_RD:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_TO_ODTH 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_TO_ODTH 0 --&gt; Returned 16: CADENCE_DEBUG_REG: WR_TO_ODTH_F0:RW:16:7:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_TO_ODTH 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_TO_ODTH 1 --&gt; Returned 16: CADENCE_DEBUG_REG: WR_TO_ODTH_F1:RW:24:7:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__WR_TO_ODTH 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__WR_TO_ODTH 2 --&gt; Returned 16: CADENCE_DEBUG_REG: WR_TO_ODTH_F2:RW:0:7:=0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_RD_MAP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_RD_MAP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ODT_RD_MAP_CS0:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_WR_MAP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_WR_MAP 0 --&gt; Returned 0: CADENCE_DEBUG_REG: ODT_WR_MAP_CS0:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_RD_MAP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_RD_MAP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ODT_RD_MAP_CS1:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ODT_WR_MAP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ODT_WR_MAP 1 --&gt; Returned 0: CADENCE_DEBUG_REG: ODT_WR_MAP_CS1:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_TO_ODTH 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_TO_ODTH 0 --&gt; Returned 21: CADENCE_DEBUG_REG: RD_TO_ODTH_F0:RW:8:7:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_TO_ODTH 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_TO_ODTH 1 --&gt; Returned 21: CADENCE_DEBUG_REG: RD_TO_ODTH_F1:RW:16:7:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RD_TO_ODTH 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RD_TO_ODTH 2 --&gt; Returned 21: CADENCE_DEBUG_REG: RD_TO_ODTH_F2:RW:24:7:=0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RW2MRW_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RW2MRW_DLY 0 --&gt; Returned 9: CADENCE_DEBUG_REG: RW2MRW_DLY_F0:RW_D:0:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RW2MRW_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RW2MRW_DLY 1 --&gt; Returned 9: CADENCE_DEBUG_REG: RW2MRW_DLY_F1:RW_D:8:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RW2MRW_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RW2MRW_DLY 2 --&gt; Returned 9: CADENCE_DEBUG_REG: RW2MRW_DLY_F2:RW_D:16:5:=0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2R_DIFFCS_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2R_DIFFCS_DLY 0 --&gt; Returned 12: CADENCE_DEBUG_REG: R2R_DIFFCS_DLY_F0:RW_D:24:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_DIFFCS_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_DIFFCS_DLY 0 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_DIFFCS_DLY_F0:RW_D:0:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2R_DIFFCS_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2R_DIFFCS_DLY 0 --&gt; Returned 1: CADENCE_DEBUG_REG: W2R_DIFFCS_DLY_F0:RW_D:8:5:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2W_DIFFCS_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2W_DIFFCS_DLY 0 --&gt; Returned 12: CADENCE_DEBUG_REG: W2W_DIFFCS_DLY_F0:RW_D:16:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2R_DIFFCS_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2R_DIFFCS_DLY 1 --&gt; Returned 12: CADENCE_DEBUG_REG: R2R_DIFFCS_DLY_F1:RW_D:24:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_DIFFCS_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_DIFFCS_DLY 1 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_DIFFCS_DLY_F1:RW_D:0:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2R_DIFFCS_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2R_DIFFCS_DLY 1 --&gt; Returned 1: CADENCE_DEBUG_REG: W2R_DIFFCS_DLY_F1:RW_D:8:5:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2W_DIFFCS_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2W_DIFFCS_DLY 1 --&gt; Returned 12: CADENCE_DEBUG_REG: W2W_DIFFCS_DLY_F1:RW_D:16:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2R_DIFFCS_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2R_DIFFCS_DLY 2 --&gt; Returned 12: CADENCE_DEBUG_REG: R2R_DIFFCS_DLY_F2:RW_D:24:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_DIFFCS_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_DIFFCS_DLY 2 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_DIFFCS_DLY_F2:RW_D:0:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2R_DIFFCS_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2R_DIFFCS_DLY 2 --&gt; Returned 1: CADENCE_DEBUG_REG: W2R_DIFFCS_DLY_F2:RW_D:8:5:=0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2W_DIFFCS_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLoff: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODToff_max: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2W_DIFFCS_DLY 2 --&gt; Returned 12: CADENCE_DEBUG_REG: W2W_DIFFCS_DLY_F2:RW_D:16:5:=0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_SAMECS_DLY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_SAMECS_DLY 0 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_SAMECS_DLY_F0:RW_D:24:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_SAMECS_DLY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_SAMECS_DLY 1 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_SAMECS_DLY_F1:RW_D:0:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2W_SAMECS_DLY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTLon: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTon_min: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tODTON_MIN: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1.5 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2W_SAMECS_DLY 2 --&gt; Returned 10: CADENCE_DEBUG_REG: R2W_SAMECS_DLY_F2:RW_D:8:5:=0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__R2R_SAMECS_DLY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__R2R_SAMECS_DLY --&gt; Returned 0: CADENCE_DEBUG_REG: R2R_SAMECS_DLY:RW:16:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2R_SAMECS_DLY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2R_SAMECS_DLY --&gt; Returned 0: CADENCE_DEBUG_REG: W2R_SAMECS_DLY:RW:24:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__W2W_SAMECS_DLY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__W2W_SAMECS_DLY --&gt; Returned 0: CADENCE_DEBUG_REG: W2W_SAMECS_DLY:RW:0:5:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MAX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MAX 0 --&gt; Returned 4: CADENCE_DEBUG_REG: TDQSCK_MAX_F0:RW:8:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MIN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MIN 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TDQSCK_MIN_F0:RW:16:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MAX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MAX 1 --&gt; Returned 4: CADENCE_DEBUG_REG: TDQSCK_MAX_F1:RW:24:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MIN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MIN 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TDQSCK_MIN_F1:RW:0:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MAX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MAX 2 --&gt; Returned 4: CADENCE_DEBUG_REG: TDQSCK_MAX_F2:RW:8:4:=0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDQSCK_MIN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_min}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_min: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_min: Parameter value {1500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDQSCK_MIN 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TDQSCK_MIN_F2:RW:16:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AXI0_ALL_STROBES_USED_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AXI0_ALL_STROBES_USED_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_ALL_STROBES_USED_ENABLE:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AXI0_FIXED_PORT_PRIORITY_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AXI0_FIXED_PORT_PRIORITY_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_FIXED_PORT_PRIORITY_ENABLE:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PORT_PRIORITY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PORT_PRIORITY 0 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_R_PRIORITY:RW:8:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PORT_PRIORITY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PORT_PRIORITY 0 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_W_PRIORITY:RW:16:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PORT_FIFO_TYPE_REG 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of fifo_type: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PORT_FIFO_TYPE_REG 0 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_FIFO_TYPE_REG:RW:24:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__PORT_ADDR_PROTECTION_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__PORT_ADDR_PROTECTION_EN --&gt; Returned 0: CADENCE_DEBUG_REG: PORT_ADDR_PROTECTION_EN:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__AXI0_ADDRESS_RANGE_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__AXI0_ADDRESS_RANGE_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_ADDRESS_RANGE_ENABLE:RW:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 0 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_0:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 0 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_0:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 0 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_0:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 0 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_0:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 0 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_0:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 0 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 0" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 0 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 1 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_1:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 1 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_1:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 1 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_1:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 1 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_1:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 1 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_1:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 1 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 1" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 1 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 2 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_2:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 2 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_2:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 2 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_2:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 2 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_2:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 2 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_2:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 2 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 2" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 2 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 3 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_3:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 3 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_3:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 3 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_3:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 3 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_3:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 3 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_3:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 3 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 3" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 3 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 4 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_4:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 4 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_4:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 4 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_4:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 4 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_4:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 4 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_4:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 4 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 4" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 4 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 5 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_5:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 5 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_5:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 5 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_5:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 5 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_5:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 5 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_5:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 5 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 5" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 5 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 6 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_6:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 6 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_6:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 6 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_6:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 6 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_6:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 6 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_6:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 6 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 6" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 6 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 7 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_7:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 7 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_7:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 7 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_7:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 7 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_7:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 7 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_7:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 7 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 7" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 7 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 8 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_8:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 8 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_8:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 8 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_8:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 8 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_8:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 8 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_8:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 8 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 8" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 8 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 9 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_9:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 9 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_9:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 9 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_9:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 9 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_9:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 9 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_9:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 9 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 9" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 9 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 10 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_10:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 10 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_10:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 10 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_10:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 10 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_10:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 10 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_10:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 10 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 10" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 10 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 11 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_11:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 11 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_11:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 11 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_11:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 11 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_11:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 11 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_11:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 11 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 11" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 11 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 12 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_12:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 12 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_12:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 12 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_12:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 12 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_12:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 12 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_12:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 12 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 12" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 12 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 13 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_13:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 13 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_13:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 13 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_13:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 13 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_13:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 13 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_13:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 13 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 13" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 13 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 14 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_14:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 14 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_14:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 14 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_14:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 14 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_14:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 14 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_14:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 14 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 14" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 14 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_START_ADDR 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_START_ADDR 0 15 --&gt; Returned 0: CADENCE_DEBUG_REG: AXI0_START_ADDR_15:RW:0:24:=0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_END_ADDR 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_END_ADDR 0 15 --&gt; Returned 274877906943: CADENCE_DEBUG_REG: AXI0_END_ADDR_15:RW:0:24:=0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_PROT_BITS 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_PROT_BITS 0 15 --&gt; Returned 3: CADENCE_DEBUG_REG: AXI0_RANGE_PROT_BITS_15:RW:24:2:=0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 15 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_15:RW:0:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS 0 15 --&gt; Returned 65535: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_15:RW:16:16:=0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 15 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15:RW:0:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 15" with 2 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__RANGE_ID_CHECK_BITS_ID_LOOKUP 0 15 --&gt; Returned 15: CADENCE_DEBUG_REG: AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15:RW:8:7:=0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__CKE_STATUS (CKE_STATUS RD {} ZERO ZERO FULL CTL {{Register access to cke_status signal. READ-ONLY }} 25288 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__MEM_RST_VALID (MEM_RST_VALID RD {} ZERO ZERO FULL CTL {{Register access to mem_rst_valid signal. READ-ONLY }} 25296 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_RDLAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT: cas_latency = 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: mem_delay = 3.5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Base phy_internal_delay: 7. TDFI_PHY_WRDATA = 2, TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">1: phy_internal_delay-&gt; 8: TDFI_PHY_WRDATA = 2 TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">2: phy_internal_delay-&gt; 12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=17: delay_adder=0 phy_internal_delay=12 ie_delay_adder=0 lpddr_adder=4 dfi_adder=0 rd_preamble_len=1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=41: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=75: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT 0 --&gt; Returned 75: CADENCE_DEBUG_REG: TDFI_PHY_RDLAT_F0:RW_D:0:11:=0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_MAX 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_MAX 0 --&gt; Returned 8324: CADENCE_DEBUG_REG: TDFI_CTRLUPD_MAX_F0:RW:0:21:=0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE0 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE0 0 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE0_F0:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE1 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE1 0 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE1_F0:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE2 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE2 0 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE2_F0:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE3 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE3 0 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE3_F0:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_RESP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_RESP 0 --&gt; Returned 12486: CADENCE_DEBUG_REG: TDFI_PHYUPD_RESP_F0:RW:0:23:=0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_INTERVAL 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_INTERVAL 0 --&gt; Returned 83240: CADENCE_DEBUG_REG: TDFI_CTRLUPD_INTERVAL_F0:RW:0:32:=0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRL_DELAY 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRL_DELAY 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_CTRL_DELAY_F0:RW_D:0:4:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRDATA 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRDATA 0 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_PHY_WRDATA_F0:RW:8:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDCSLAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDCSLAT 0 --&gt; Returned 21: CADENCE_DEBUG_REG: TDFI_RDCSLAT_F0:RW:16:11:=0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDDATA_EN 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDDATA_EN 0 --&gt; Returned 22: CADENCE_DEBUG_REG: TDFI_RDDATA_EN_F0:RW:0:11:=0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WRCSLAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WRCSLAT 0 --&gt; Returned 16: CADENCE_DEBUG_REG: TDFI_WRCSLAT_F0:RW:16:11:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRLAT 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Initial wrlat_adj=17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: New wrlat_adj=18 (lp4 4:1)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRLAT 0 --&gt; Returned 18: CADENCE_DEBUG_REG: TDFI_PHY_WRLAT_F0:RW:0:11:=0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLMSG_RESP 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLMSG_RESP 0 --&gt; Returned 32: CADENCE_DEBUG_REG: TDFI_CTRLMSG_RESP_F0:RW:16:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_RDLAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT: cas_latency = 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: mem_delay = 3.5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Base phy_internal_delay: 7. TDFI_PHY_WRDATA = 2, TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">1: phy_internal_delay-&gt; 8: TDFI_PHY_WRDATA = 2 TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">2: phy_internal_delay-&gt; 12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=17: delay_adder=0 phy_internal_delay=12 ie_delay_adder=0 lpddr_adder=4 dfi_adder=0 rd_preamble_len=1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=41: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=75: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT 1 --&gt; Returned 75: CADENCE_DEBUG_REG: TDFI_PHY_RDLAT_F1:RW_D:0:11:=0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_MAX 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_MAX 1 --&gt; Returned 8324: CADENCE_DEBUG_REG: TDFI_CTRLUPD_MAX_F1:RW:0:21:=0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE0 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE0 1 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE0_F1:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE1 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE1 1 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE1_F1:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE2 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE2 1 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE2_F1:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE3 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE3 1 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE3_F1:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_RESP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_RESP 1 --&gt; Returned 12486: CADENCE_DEBUG_REG: TDFI_PHYUPD_RESP_F1:RW:0:23:=0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_INTERVAL 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_INTERVAL 1 --&gt; Returned 83240: CADENCE_DEBUG_REG: TDFI_CTRLUPD_INTERVAL_F1:RW:0:32:=0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRL_DELAY 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRL_DELAY 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_CTRL_DELAY_F1:RW_D:0:4:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRDATA 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRDATA 1 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_PHY_WRDATA_F1:RW:8:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDCSLAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDCSLAT 1 --&gt; Returned 21: CADENCE_DEBUG_REG: TDFI_RDCSLAT_F1:RW:16:11:=0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDDATA_EN 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDDATA_EN 1 --&gt; Returned 22: CADENCE_DEBUG_REG: TDFI_RDDATA_EN_F1:RW:0:11:=0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WRCSLAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WRCSLAT 1 --&gt; Returned 16: CADENCE_DEBUG_REG: TDFI_WRCSLAT_F1:RW:16:11:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRLAT 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Initial wrlat_adj=17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: New wrlat_adj=18 (lp4 4:1)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRLAT 1 --&gt; Returned 18: CADENCE_DEBUG_REG: TDFI_PHY_WRLAT_F1:RW:0:11:=0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLMSG_RESP 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLMSG_RESP 1 --&gt; Returned 32: CADENCE_DEBUG_REG: TDFI_CTRLMSG_RESP_F1:RW:16:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_RDLAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT: cas_latency = 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: mem_delay = 3.5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">Base phy_internal_delay: 7. TDFI_PHY_WRDATA = 2, TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">1: phy_internal_delay-&gt; 8: TDFI_PHY_WRDATA = 2 TDFI_PHY_WRDATA_DEFAULT = 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">2: phy_internal_delay-&gt; 12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tdqsck_max}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tdqsck_max: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tdqsck_max: Parameter value {3500.0 ps}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {3500.0 ps}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=17: delay_adder=0 phy_internal_delay=12 ie_delay_adder=0 lpddr_adder=4 dfi_adder=0 rd_preamble_len=1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=41: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">rdlat_delay=75: overwrite rdlat_delay with an empirical value that is known to guarantee RMW correctness.</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_RDLAT 2 --&gt; Returned 75: CADENCE_DEBUG_REG: TDFI_PHY_RDLAT_F2:RW_D:0:11:=0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_MAX 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_MAX 2 --&gt; Returned 8324: CADENCE_DEBUG_REG: TDFI_CTRLUPD_MAX_F2:RW:0:21:=0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE0 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE0 2 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE0_F2:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE1 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE1 2 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE1_F2:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE2 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE2 2 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE2_F2:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_TYPE3 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_TYPE3 2 --&gt; Returned 512: CADENCE_DEBUG_REG: TDFI_PHYUPD_TYPE3_F2:RW:0:32:=0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHYUPD_RESP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHYUPD_RESP 2 --&gt; Returned 12486: CADENCE_DEBUG_REG: TDFI_PHYUPD_RESP_F2:RW:0:23:=0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_INTERVAL 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {trefw}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of trefw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of trefw: Parameter value {32.0 ms}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {32.0 ms}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of minNumOfRefsReqd: Parameter value 8192.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_INTERVAL 2 --&gt; Returned 83240: CADENCE_DEBUG_REG: TDFI_CTRLUPD_INTERVAL_F2:RW:0:32:=0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRL_DELAY 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRL_DELAY 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_CTRL_DELAY_F2:RW_D:0:4:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRDATA 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of LPDDR5_Support: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of LPDDR5_Support: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRDATA 2 --&gt; Returned 2: CADENCE_DEBUG_REG: TDFI_PHY_WRDATA_F2:RW:8:3:=0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDCSLAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDCSLAT 2 --&gt; Returned 21: CADENCE_DEBUG_REG: TDFI_RDCSLAT_F2:RW:16:11:=0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_RDDATA_EN 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_RDDATA_EN 2 --&gt; Returned 22: CADENCE_DEBUG_REG: TDFI_RDDATA_EN_F2:RW:0:11:=0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WRCSLAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WRCSLAT 2 --&gt; Returned 16: CADENCE_DEBUG_REG: TDFI_WRCSLAT_F2:RW:16:11:=0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PHY_WRLAT 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_type_is_NONE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_type_is_NONE: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DLL_Structure_is_sim2: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DLL_Structure_is_sim2: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Inside _cadence_info__WRLAT_ADJ: PHY_TYPE= SIM_PHY DLLSTRUCTURE = DLL_IS_SIM DLLSUBTYPE2 = STD_DENALI_HIP2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RCD_Command_Lat_Adder: Parameter value 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Additive_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CA_Parity_Lat: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ (initial) = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_info__WRLAT_ADJ = 17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Initial wrlat_adj=17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Reg_Dimm: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DFI_Cmd_Ratio_4to1: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DFI_Cmd_Ratio_4to1: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Max_DFI_Cmd_Freq_Ratio: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Max_DFI_Cmd_Freq_Ratio: Parameter value 4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: New wrlat_adj=18 (lp4 4:1)</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PHY_WRLAT 2 --&gt; Returned 18: CADENCE_DEBUG_REG: TDFI_PHY_WRLAT_F2:RW:0:11:=0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLMSG_RESP 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLMSG_RESP 2 --&gt; Returned 32: CADENCE_DEBUG_REG: TDFI_CTRLMSG_RESP_F2:RW:16:7:=0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DLL_RST_DELAY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DLL_RST_DELAY --&gt; Returned 0: CADENCE_DEBUG_REG: DLL_RST_DELAY:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DLL_RST_ADJ_DLY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DLL_RST_ADJ_DLY --&gt; Returned 0: CADENCE_DEBUG_REG: DLL_RST_ADJ_DLY:RW:16:8:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__UPDATE_ERROR_STATUS (UPDATE_ERROR_STATUS RD {} ZERO ZERO FULL CTL {{Identifies the source of any DFI MC-initiated or PHY-initiated update errors. Value of 1 indicates a timing violation of the associated timing parameter. READ-ONLY }} 26392 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DRAM_CLK_DISABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DRAM_CLK_DISABLE --&gt; Returned 0: CADENCE_DEBUG_REG: DRAM_CLK_DISABLE:RW:0:2:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_CTRLUPD_MIN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Framework_Management: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_CTRLUPD_MIN --&gt; Returned 21: CADENCE_DEBUG_REG: TDFI_CTRLUPD_MIN:RW:8:16:=0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_DRAM_CLK_DISABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_DRAM_CLK_DISABLE --&gt; Returned 6: CADENCE_DEBUG_REG: TDFI_DRAM_CLK_DISABLE:RW:24:4:=0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_DRAM_CLK_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_DRAM_CLK_ENABLE --&gt; Returned 5: CADENCE_DEBUG_REG: TDFI_DRAM_CLK_ENABLE:RW:0:4:=0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_PARIN_LAT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_PARIN_LAT --&gt; Returned 0: CADENCE_DEBUG_REG: TDFI_PARIN_LAT:RW:8:3:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TDFI_WRDATA_DELAY" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TDFI_WRDATA_DELAY --&gt; Returned 5: CADENCE_DEBUG_REG: TDFI_WRDATA_DELAY:RW:16:8:=0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__EN_1T_TIMING 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of En_2T_Timing: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DDR5_1N_Mode: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DDR51NModeList: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__EN_1T_TIMING 0 --&gt; Returned 0: CADENCE_DEBUG_REG: EN_1T_TIMING_F0:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__EN_1T_TIMING 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of En_2T_Timing: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DDR5_1N_Mode: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DDR51NModeList: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__EN_1T_TIMING 1 --&gt; Returned 0: CADENCE_DEBUG_REG: EN_1T_TIMING_F1:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__EN_1T_TIMING 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of En_2T_Timing: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of DDR5_1N_Mode: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of DDR51NModeList: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__EN_1T_TIMING 2 --&gt; Returned 0: CADENCE_DEBUG_REG: EN_1T_TIMING_F2:RW:8:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DISABLE_MEMORY_MASKED_WRITE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of data_mask_en: Parameter value true</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DISABLE_MEMORY_MASKED_WRITE --&gt; Returned 0: CADENCE_DEBUG_REG: DISABLE_MEMORY_MASKED_WRITE:RW_D:16:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CS_PHASE_2N" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CS_PHASE_2N --&gt; Returned 0: CADENCE_DEBUG_REG: CS_PHASE_2N:RW:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__STRATEGY_2TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__BANK_ACTIVATE_2TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__PRE_2TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__STRATEGY_4TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__BANK_ACTIVATE_4TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__PRE_4TICK_COUNT will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_2X4_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_2X4_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_NXN_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_NXN_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__ODT_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__ODT_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRAS_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRAS_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRP_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRP_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TWR_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TWR_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_4X2_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMP_4X2_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRFC_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TRFC_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__RL_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__RL_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WL_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__WL_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMRD_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TMRD_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TO_MRW_TICK_PLUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__TO_MRW_TICK_MINUS_ADJ will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TAAD" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tAAD}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tAAD: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TAAD --&gt; Returned 8: CADENCE_DEBUG_REG: TAAD:RW:24:8:=0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__ACT1_ENABLE" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__ACT1_ENABLE --&gt; Returned 0: CADENCE_DEBUG_REG: ACT1_ENABLE:RD:0:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Reserved register _cadence_reg__ACT1_EARLY will be skipped</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NWR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NWR 0 --&gt; Returned 20: CADENCE_DEBUG_REG: NWR_F0:RW:16:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NWR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NWR 1 --&gt; Returned 20: CADENCE_DEBUG_REG: NWR_F1:RW:24:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__NWR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__NWR 2 --&gt; Returned 20: CADENCE_DEBUG_REG: NWR_F2:RW:0:8:=0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__CA_PARITY_ERROR_INJECT" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__CA_PARITY_ERROR_INJECT --&gt; Returned 0: CADENCE_DEBUG_REG: CA_PARITY_ERROR_INJECT:RW:0:36:=0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD_PAR 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD_PAR 0 --&gt; Returned 0: CADENCE_DEBUG_REG: TMRD_PAR_F0:RW:8:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD_PAR 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD_PAR 1 --&gt; Returned 0: CADENCE_DEBUG_REG: TMRD_PAR_F1:RW:0:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD_PAR 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD_PAR 2 --&gt; Returned 0: CADENCE_DEBUG_REG: TMRD_PAR_F2:RW:16:16:=0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD 0" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrw tmrw_minTck}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrw: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD 0 --&gt; Returned 11: CADENCE_DEBUG_REG: TMRD_F0:RW:0:16:=0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD 1" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrw tmrw_minTck}, 0 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrw: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD 1 --&gt; Returned 11: CADENCE_DEBUG_REG: TMRD_F1:RW:16:16:=0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__TMRD 2" with 1 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {tmrw tmrw_minTck}, 0 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of tmrw: Parameter value {10.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {10.0 ns}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tmrw_minTck: unassigned</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 2</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__TMRD 2 --&gt; Returned 11: CADENCE_DEBUG_REG: TMRD_F2:RW:0:16:=0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Skipping _cadence_reg__BIST_RESULT (BIST_RESULT RD {} ZERO ZERO FULL CTL {{BIST operation status (pass/fail). Indicates data check status. Value of 1 is a passing result. READ-ONLY }} 26960 OPEN ONECYCLE ONECYCLE {})</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Will Call "_cadence_reg__DFI_RD_FIFO_RESYNC_EN" with 0 arguments</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of is_lockstep: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: _cadence_reg__DFI_RD_FIFO_RESYNC_EN --&gt; Returned 0: CADENCE_DEBUG_REG: DFI_RD_FIFO_RESYNC_EN:RW:24:1:=0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_ADDRESS_RANGE_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_ALL_STROBES_USED_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_FIFO_TYPE_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_FIXED_PORT_PRIORITY_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_R_PRIORITY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_W_PRIORITY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_0 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_0 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_0 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_1 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_1 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_1 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_2 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_2 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_2 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_3 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_3 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_3 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_3 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_4 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_4 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_4 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_4 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_5 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_5 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_5 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_5 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_6 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_6 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_6 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_6 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_7 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_7 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_7 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_7 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_8 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_8 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_8 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_8 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_8 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_9 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_9 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_9 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_9 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_9 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_10 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_10 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_10 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_10 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_10 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_11 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_11 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_11 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_11 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_11 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_12 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_12 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_12 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_12 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_12 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_13 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_13 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_13 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_13 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_13 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_14 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_14 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_14 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_14 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_14 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_START_ADDR_15 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_END_ADDR_15 = 0x3fffffffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_PROT_BITS_15 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_15 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_15 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AXI0_ADDRESS_RANGE_ENABLE : Assigning value 0x00 (idx=1) from 2/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AXI0_ALL_STROBES_USED_ENABLE : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_FIFO_TYPE_REG is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AXI0_FIXED_PORT_PRIORITY_ENABLE : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AXI0_R_PRIORITY : Assigning value 0x00 (idx=1) from 3/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AXI0_W_PRIORITY : Assigning value 0x00 (idx=1) from 5/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_0 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_1 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_2 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_3 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_4 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_5 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_6 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_7 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_8 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_9 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_10 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_11 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_12 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_13 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_14 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_START_ADDR_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_END_ADDR_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_PROT_BITS_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_RID_CHECK_BITS_ID_LOOKUP_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.AXI0_RANGE_WID_CHECK_BITS_ID_LOOKUP_15 is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_SPACE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_DATA_CHECK = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_DATA_MASK = 0x000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_DATA_PATTERN = 0x000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_ECC_LANE_CHECK = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_START_ADDRESS = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_ERR_STOP = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BIST_TEST_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_SPACE : Assigning value 0x00 (idx=1) from 0/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_DATA_CHECK : Assigning value 0x01 (idx=1) from 6/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_DATA_MASK : Assigning value 0x000000000000000000000000000000000000 (idx=1) from 349/144/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_DATA_PATTERN : Assigning value 0x000000000000000000000000000000000000000000000000000000000000000000000000 (idx=1) from 61/288/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_ECC_LANE_CHECK : Assigning value 0x01 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_START_ADDRESS : Assigning value 0x0000000000 (idx=1) from 23/38/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_ERR_STOP : Assigning value 0x0000 (idx=1) from 8/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BIST_TEST_MODE : Assigning value 0x00 (idx=1) from 20/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_ERROR_INJECT = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_CS = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_NUM = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_VAL = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_MPC_CMD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_CS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_OPCODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_LSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_MSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NO_AUTO_MRR_INIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_INIT_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_TRAIN_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_INIT_SW_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_REGNUM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PWRUP_SREFRESH_EXIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_TRAINING_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MODEREG = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MPR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITE_MODEREG = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_MULTI_CYCLE_ENABLE_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.CA_PARITY_ERROR_INJECT is {CA_PARITY_ERROR_INJECT_0 CA_PARITY_ERROR_INJECT_1} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=1) from 0/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=4294967296) from 32/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_CS : Assigning value 0x01 (idx=1) from 36/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_NUM : Assigning value 0x0000 (idx=1) from 38/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_VAL : Assigning value 0x00 (idx=1) from 47/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_ENABLE : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_MPC_CMD : Assigning value 0x00000000 (idx=1) from 56/28/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 84/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TST : Assigning value 0x00 (idx=1) from 99/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_CS : Assigning value 0x00 (idx=1) from 100/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_OPCODE : Assigning value 0x00 (idx=1) from 103/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_LSB_REG : Assigning value 0x00 (idx=1) from 111/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_MSB_REG : Assigning value 0x00 (idx=1) from 119/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NO_AUTO_MRR_INIT : Assigning value 0x00 (idx=1) from 163/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_INIT_MODE : Assigning value 0x01 (idx=1) from 164/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_TRAIN_MODE : Assigning value 0x01 (idx=1) from 165/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_INIT_SW_MODE : Assigning value 0x00 (idx=1) from 166/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_DATA : Assigning value 0x000000 (idx=1) from 167/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_REGNUM : Assigning value 0x00 (idx=1) from 185/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PWRUP_SREFRESH_EXIT : Assigning value 0x00 (idx=1) from 193/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_TRAINING_EN : Assigning value 0x01 (idx=1) from 194/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MODEREG : Assigning value 0x000000 (idx=1) from 195/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MPR : Assigning value 0x00 (idx=1) from 213/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITE_MODEREG : Assigning value 0x00000000 (idx=1) from 217/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_0 : Assigning value 0x000000 (idx=1) from 127/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_1 : Assigning value 0x000000 (idx=1) from 145/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_MULTI_CYCLE_ENABLE_F0 : Assigning value 0x00 (idx=1) from 102/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000100000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000300000000000000000200000000000001000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_ERROR_INJECT = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_CS = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_NUM = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_VAL = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_MPC_CMD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_CS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_OPCODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_LSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_MSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NO_AUTO_MRR_INIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_INIT_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_TRAIN_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_INIT_SW_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_REGNUM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PWRUP_SREFRESH_EXIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_TRAINING_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MODEREG = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MPR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITE_MODEREG = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_MULTI_CYCLE_ENABLE_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.CA_PARITY_ERROR_INJECT is {CA_PARITY_ERROR_INJECT_0 CA_PARITY_ERROR_INJECT_1} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=1) from 0/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=4294967296) from 32/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_CS : Assigning value 0x01 (idx=1) from 36/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_NUM : Assigning value 0x0000 (idx=1) from 38/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_VAL : Assigning value 0x00 (idx=1) from 47/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_ENABLE : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_MPC_CMD : Assigning value 0x00000000 (idx=1) from 56/28/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 84/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TST : Assigning value 0x00 (idx=1) from 99/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_CS : Assigning value 0x00 (idx=1) from 100/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_OPCODE : Assigning value 0x00 (idx=1) from 103/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_LSB_REG : Assigning value 0x00 (idx=1) from 111/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_MSB_REG : Assigning value 0x00 (idx=1) from 119/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NO_AUTO_MRR_INIT : Assigning value 0x00 (idx=1) from 163/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_INIT_MODE : Assigning value 0x01 (idx=1) from 164/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_TRAIN_MODE : Assigning value 0x01 (idx=1) from 165/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_INIT_SW_MODE : Assigning value 0x00 (idx=1) from 166/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_DATA : Assigning value 0x000000 (idx=1) from 167/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_REGNUM : Assigning value 0x00 (idx=1) from 185/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PWRUP_SREFRESH_EXIT : Assigning value 0x00 (idx=1) from 193/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_TRAINING_EN : Assigning value 0x01 (idx=1) from 194/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MODEREG : Assigning value 0x000000 (idx=1) from 195/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MPR : Assigning value 0x00 (idx=1) from 213/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITE_MODEREG : Assigning value 0x00000000 (idx=1) from 217/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_0 : Assigning value 0x000000 (idx=1) from 127/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_1 : Assigning value 0x000000 (idx=1) from 145/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_MULTI_CYCLE_ENABLE_F1 : Assigning value 0x00 (idx=1) from 102/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000100000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000300000000000000000200000000000001000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_ERROR_INJECT = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_CS = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_NUM = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CW_VAL = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_MPC_CMD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_CS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_OPCODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_LSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_MSB_REG = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NO_AUTO_MRR_INIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_INIT_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHY_INDEP_TRAIN_MODE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_INIT_SW_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRW_REGNUM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PWRUP_SREFRESH_EXIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_TRAINING_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MODEREG = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key READ_MPR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITE_MODEREG = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRSINGLE_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_MULTI_CYCLE_ENABLE_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.CA_PARITY_ERROR_INJECT is {CA_PARITY_ERROR_INJECT_0 CA_PARITY_ERROR_INJECT_1} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=1) from 0/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_ERROR_INJECT : Assigning value 0x0000000000 (idx=4294967296) from 32/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_CS : Assigning value 0x01 (idx=1) from 36/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_NUM : Assigning value 0x0000 (idx=1) from 38/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CW_VAL : Assigning value 0x00 (idx=1) from 47/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_ENABLE : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_MPC_CMD : Assigning value 0x00000000 (idx=1) from 56/28/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 84/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TST : Assigning value 0x00 (idx=1) from 99/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_CS : Assigning value 0x00 (idx=1) from 100/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_OPCODE : Assigning value 0x00 (idx=1) from 103/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_LSB_REG : Assigning value 0x00 (idx=1) from 111/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_MSB_REG : Assigning value 0x00 (idx=1) from 119/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NO_AUTO_MRR_INIT : Assigning value 0x00 (idx=1) from 163/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_INIT_MODE : Assigning value 0x01 (idx=1) from 164/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHY_INDEP_TRAIN_MODE : Assigning value 0x01 (idx=1) from 165/1/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_INIT_SW_MODE : Assigning value 0x00 (idx=1) from 166/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_DATA : Assigning value 0x000000 (idx=1) from 167/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRW_REGNUM : Assigning value 0x00 (idx=1) from 185/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PWRUP_SREFRESH_EXIT : Assigning value 0x00 (idx=1) from 193/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_TRAINING_EN : Assigning value 0x01 (idx=1) from 194/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MODEREG : Assigning value 0x000000 (idx=1) from 195/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.READ_MPR : Assigning value 0x00 (idx=1) from 213/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITE_MODEREG : Assigning value 0x00000000 (idx=1) from 217/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_0 : Assigning value 0x000000 (idx=1) from 127/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRSINGLE_DATA_1 : Assigning value 0x000000 (idx=1) from 145/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_MULTI_CYCLE_ENABLE_F2 : Assigning value 0x00 (idx=1) from 102/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000100000000000000000000000000001100000000000000000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000000000000000000000001000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000004000000300000000000000000200000000000001000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_DISABLE_W_UC_ERR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_READ_CACHING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_TYPE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITEBACK_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITE_COMBINING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BANK_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BG_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_SAME_PAGE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key XOR_CHECK_BITS = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_LINK_ECC_EN_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_LINK_ECC_EN_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_DISABLE_W_UC_ERR : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_ENABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_READ_CACHING_EN : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_TYPE : Assigning value 0x00 (idx=1) from 6/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITEBACK_EN : Assigning value 0x00 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITE_COMBINING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BANK_OFFSET : Assigning value 0x00 (idx=1) from 9/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BG_OFFSET : Assigning value 0x00 (idx=1) from 14/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_SAME_PAGE : Assigning value 0x00 (idx=1) from 19/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_ENABLE : Assigning value 0x00 (idx=1) from 142/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_0 : Assigning value 0x000000 (idx=1) from 168/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_1 : Assigning value 0x000000 (idx=1) from 204/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_2 : Assigning value 0x000000 (idx=1) from 240/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_3 : Assigning value 0x000000 (idx=1) from 276/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_4 : Assigning value 0x000000 (idx=1) from 312/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_5 : Assigning value 0x000000 (idx=1) from 348/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_6 : Assigning value 0x000000 (idx=1) from 384/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_7 : Assigning value 0x000000 (idx=1) from 420/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_0 : Assigning value 0x000000 (idx=1) from 150/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_1 : Assigning value 0x000000 (idx=1) from 186/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_2 : Assigning value 0x000000 (idx=1) from 222/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_3 : Assigning value 0x000000 (idx=1) from 258/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_4 : Assigning value 0x000000 (idx=1) from 294/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_5 : Assigning value 0x000000 (idx=1) from 330/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_6 : Assigning value 0x000000 (idx=1) from 366/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_7 : Assigning value 0x000000 (idx=1) from 402/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.XOR_CHECK_BITS : Assigning value 0x00000000 (idx=1) from 438/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_LINK_ECC_EN_F0 : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_LINK_ECC_EN_F0 : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_DISABLE_W_UC_ERR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_READ_CACHING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_TYPE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITEBACK_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITE_COMBINING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BANK_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BG_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_SAME_PAGE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key XOR_CHECK_BITS = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_LINK_ECC_EN_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_LINK_ECC_EN_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_DISABLE_W_UC_ERR : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_ENABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_READ_CACHING_EN : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_TYPE : Assigning value 0x00 (idx=1) from 6/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITEBACK_EN : Assigning value 0x00 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITE_COMBINING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BANK_OFFSET : Assigning value 0x00 (idx=1) from 9/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BG_OFFSET : Assigning value 0x00 (idx=1) from 14/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_SAME_PAGE : Assigning value 0x00 (idx=1) from 19/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_ENABLE : Assigning value 0x00 (idx=1) from 142/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_0 : Assigning value 0x000000 (idx=1) from 168/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_1 : Assigning value 0x000000 (idx=1) from 204/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_2 : Assigning value 0x000000 (idx=1) from 240/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_3 : Assigning value 0x000000 (idx=1) from 276/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_4 : Assigning value 0x000000 (idx=1) from 312/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_5 : Assigning value 0x000000 (idx=1) from 348/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_6 : Assigning value 0x000000 (idx=1) from 384/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_7 : Assigning value 0x000000 (idx=1) from 420/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_0 : Assigning value 0x000000 (idx=1) from 150/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_1 : Assigning value 0x000000 (idx=1) from 186/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_2 : Assigning value 0x000000 (idx=1) from 222/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_3 : Assigning value 0x000000 (idx=1) from 258/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_4 : Assigning value 0x000000 (idx=1) from 294/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_5 : Assigning value 0x000000 (idx=1) from 330/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_6 : Assigning value 0x000000 (idx=1) from 366/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_7 : Assigning value 0x000000 (idx=1) from 402/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.XOR_CHECK_BITS : Assigning value 0x00000000 (idx=1) from 438/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_LINK_ECC_EN_F1 : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_LINK_ECC_EN_F1 : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_DISABLE_W_UC_ERR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_READ_CACHING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_TYPE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITEBACK_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_WRITE_COMBINING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BANK_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_BG_OFFSET = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INLINE_ECC_SAME_PAGE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_END_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_3 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_4 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_5 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_6 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NON_ECC_REGION_START_ADDR_7 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key XOR_CHECK_BITS = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_LINK_ECC_EN_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_LINK_ECC_EN_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_DISABLE_W_UC_ERR : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_ENABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_READ_CACHING_EN : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_TYPE : Assigning value 0x00 (idx=1) from 6/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITEBACK_EN : Assigning value 0x00 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_WRITE_COMBINING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BANK_OFFSET : Assigning value 0x00 (idx=1) from 9/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_BG_OFFSET : Assigning value 0x00 (idx=1) from 14/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INLINE_ECC_SAME_PAGE : Assigning value 0x00 (idx=1) from 19/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_ENABLE : Assigning value 0x00 (idx=1) from 142/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_0 : Assigning value 0x000000 (idx=1) from 168/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_1 : Assigning value 0x000000 (idx=1) from 204/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_2 : Assigning value 0x000000 (idx=1) from 240/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_3 : Assigning value 0x000000 (idx=1) from 276/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_4 : Assigning value 0x000000 (idx=1) from 312/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_5 : Assigning value 0x000000 (idx=1) from 348/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_6 : Assigning value 0x000000 (idx=1) from 384/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_END_ADDR_7 : Assigning value 0x000000 (idx=1) from 420/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_0 : Assigning value 0x000000 (idx=1) from 150/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_1 : Assigning value 0x000000 (idx=1) from 186/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_2 : Assigning value 0x000000 (idx=1) from 222/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_3 : Assigning value 0x000000 (idx=1) from 258/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_4 : Assigning value 0x000000 (idx=1) from 294/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_5 : Assigning value 0x000000 (idx=1) from 330/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_6 : Assigning value 0x000000 (idx=1) from 366/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NON_ECC_REGION_START_ADDR_7 : Assigning value 0x000000 (idx=1) from 402/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.XOR_CHECK_BITS : Assigning value 0x00000000 (idx=1) from 438/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_LINK_ECC_EN_F2 : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_LINK_ECC_EN_F2 : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKE_DELAY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_BOOT_STATE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_CHANGE_STATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DRAM_CLK_DISABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FUNC_VALID_CYCLES = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI_VERSION_4P0V1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_TRAIN_AFTER_INIT_COMPLETE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MIN = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_DISABLE = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_ENABLE = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_LP_RESP = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PARIN_LAT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRDATA_DELAY = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFIBUS_FREQ_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_RATIO_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLMSG_RESP_F0 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_INTERVAL_F0 = 0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MAX_F0 = 0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRL_DELAY_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_COMPLETE_F0 = 0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_START_F0 = 0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_F0 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE0_F0 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE1_F0 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE2_F0 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE3_F0 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_RESP_F0 = 0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_RESP_F0 = 0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE0_F0 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE1_F0 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE2_F0 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE3_F0 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_RDLAT_F0 = 0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRDATA_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRLAT_F0 = 0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDCSLAT_F0 = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDDATA_EN_F0 = 0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_DIS_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_FS_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_RD_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_WR_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_FAST_TOGGLE_F0 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_TOGGLE_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRCSLAT_F0 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKE_DELAY : Assigning value 0x00 (idx=1) from 569/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_BOOT_STATE : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_CHANGE_STATE : Assigning value 0x01 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DRAM_CLK_DISABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FUNC_VALID_CYCLES : Assigning value 0x02 (idx=1) from 572/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI_VERSION_4P0V1 : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_TRAIN_AFTER_INIT_COMPLETE : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MIN : Assigning value 0x0015 (idx=1) from 576/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_DISABLE : Assigning value 0x06 (idx=1) from 70/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_ENABLE : Assigning value 0x05 (idx=1) from 74/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_LP_RESP : Assigning value 0x10 (idx=1) from 126/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PARIN_LAT : Assigning value 0x00 (idx=1) from 131/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRDATA_DELAY : Assigning value 0x05 (idx=1) from 561/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFIBUS_FREQ_F0 : Assigning value 0x00 (idx=1) from 595/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_RATIO_F0 : Assigning value 0x02 (idx=1) from 593/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLMSG_RESP_F0 : Assigning value 0x20 (idx=1) from 6/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_INTERVAL_F0 : Assigning value 0x00014528 (idx=1) from 13/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MAX_F0 : Assigning value 0x002084 (idx=1) from 45/21/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRL_DELAY_F0 : Assigning value 0x02 (idx=1) from 66/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_COMPLETE_F0 : Assigning value 0x001000 (idx=1) from 78/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_START_F0 : Assigning value 0x000200 (idx=1) from 102/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_F0 : Assigning value 0x00041080 (idx=1) from 134/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE0_F0 : Assigning value 0x00041080 (idx=1) from 166/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE1_F0 : Assigning value 0x00041080 (idx=1) from 198/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE2_F0 : Assigning value 0x00041080 (idx=1) from 230/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE3_F0 : Assigning value 0x00041080 (idx=1) from 262/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_RESP_F0 : Assigning value 0x0071ce (idx=1) from 294/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_RESP_F0 : Assigning value 0x0030c6 (idx=1) from 314/23/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE0_F0 : Assigning value 0x00000200 (idx=1) from 337/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE1_F0 : Assigning value 0x00000200 (idx=1) from 369/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE2_F0 : Assigning value 0x00000200 (idx=1) from 401/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE3_F0 : Assigning value 0x00000200 (idx=1) from 433/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_RDLAT_F0 : Assigning value 0x004b (idx=1) from 465/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRDATA_F0 : Assigning value 0x02 (idx=1) from 476/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRLAT_F0 : Assigning value 0x0012 (idx=1) from 479/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDCSLAT_F0 : Assigning value 0x0015 (idx=1) from 490/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDDATA_EN_F0 : Assigning value 0x0016 (idx=1) from 501/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_DIS_F0 : Assigning value 0x00 (idx=1) from 512/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_FS_F0 : Assigning value 0x00 (idx=1) from 518/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_RD_F0 : Assigning value 0x00 (idx=1) from 525/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_WR_F0 : Assigning value 0x00 (idx=1) from 532/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_FAST_TOGGLE_F0 : Assigning value 0x04 (idx=1) from 539/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_TOGGLE_F0 : Assigning value 0x00 (idx=1) from 543/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRCSLAT_F0 : Assigning value 0x0010 (idx=1) from 550/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000010x0000000000010101001000000000101000000100000000000010000000000000000000000000000000000010110000000101010000001001001000001001011000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000001100001100011000000111000111001110000000000000010000010000100000000000000000000100000100001000000000000000000001000001000010000000000000000000010000010000100000000000000000000100000100001000000000010000000000000000001000000000000000000001000000000000010101100010000000010000010000100000000000000000101000101001010000100000000010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000040015200a04002000000002c0540920960000040000000400000004000000040000c3181c7380010420000104200001042000010420000104200400008000040015880410800028a50802</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKE_DELAY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_BOOT_STATE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_CHANGE_STATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DRAM_CLK_DISABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FUNC_VALID_CYCLES = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI_VERSION_4P0V1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_TRAIN_AFTER_INIT_COMPLETE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MIN = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_DISABLE = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_ENABLE = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_LP_RESP = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PARIN_LAT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRDATA_DELAY = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFIBUS_FREQ_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_RATIO_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLMSG_RESP_F1 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_INTERVAL_F1 = 0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MAX_F1 = 0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRL_DELAY_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_COMPLETE_F1 = 0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_START_F1 = 0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_F1 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE0_F1 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE1_F1 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE2_F1 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE3_F1 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_RESP_F1 = 0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_RESP_F1 = 0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE0_F1 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE1_F1 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE2_F1 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE3_F1 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_RDLAT_F1 = 0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRDATA_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRLAT_F1 = 0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDCSLAT_F1 = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDDATA_EN_F1 = 0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_DIS_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_FS_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_RD_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_WR_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_FAST_TOGGLE_F1 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_TOGGLE_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRCSLAT_F1 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKE_DELAY : Assigning value 0x00 (idx=1) from 569/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_BOOT_STATE : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_CHANGE_STATE : Assigning value 0x01 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DRAM_CLK_DISABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FUNC_VALID_CYCLES : Assigning value 0x02 (idx=1) from 572/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI_VERSION_4P0V1 : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_TRAIN_AFTER_INIT_COMPLETE : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MIN : Assigning value 0x0015 (idx=1) from 576/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_DISABLE : Assigning value 0x06 (idx=1) from 70/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_ENABLE : Assigning value 0x05 (idx=1) from 74/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_LP_RESP : Assigning value 0x10 (idx=1) from 126/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PARIN_LAT : Assigning value 0x00 (idx=1) from 131/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRDATA_DELAY : Assigning value 0x05 (idx=1) from 561/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFIBUS_FREQ_F1 : Assigning value 0x01 (idx=1) from 595/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_RATIO_F1 : Assigning value 0x02 (idx=1) from 593/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLMSG_RESP_F1 : Assigning value 0x20 (idx=1) from 6/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_INTERVAL_F1 : Assigning value 0x00014528 (idx=1) from 13/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MAX_F1 : Assigning value 0x002084 (idx=1) from 45/21/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRL_DELAY_F1 : Assigning value 0x02 (idx=1) from 66/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_COMPLETE_F1 : Assigning value 0x001000 (idx=1) from 78/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_START_F1 : Assigning value 0x000200 (idx=1) from 102/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_F1 : Assigning value 0x00041080 (idx=1) from 134/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE0_F1 : Assigning value 0x00041080 (idx=1) from 166/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE1_F1 : Assigning value 0x00041080 (idx=1) from 198/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE2_F1 : Assigning value 0x00041080 (idx=1) from 230/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE3_F1 : Assigning value 0x00041080 (idx=1) from 262/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_RESP_F1 : Assigning value 0x0071ce (idx=1) from 294/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_RESP_F1 : Assigning value 0x0030c6 (idx=1) from 314/23/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE0_F1 : Assigning value 0x00000200 (idx=1) from 337/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE1_F1 : Assigning value 0x00000200 (idx=1) from 369/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE2_F1 : Assigning value 0x00000200 (idx=1) from 401/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE3_F1 : Assigning value 0x00000200 (idx=1) from 433/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_RDLAT_F1 : Assigning value 0x004b (idx=1) from 465/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRDATA_F1 : Assigning value 0x02 (idx=1) from 476/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRLAT_F1 : Assigning value 0x0012 (idx=1) from 479/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDCSLAT_F1 : Assigning value 0x0015 (idx=1) from 490/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDDATA_EN_F1 : Assigning value 0x0016 (idx=1) from 501/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_DIS_F1 : Assigning value 0x00 (idx=1) from 512/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_FS_F1 : Assigning value 0x00 (idx=1) from 518/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_RD_F1 : Assigning value 0x00 (idx=1) from 525/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_WR_F1 : Assigning value 0x00 (idx=1) from 532/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_FAST_TOGGLE_F1 : Assigning value 0x04 (idx=1) from 539/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_TOGGLE_F1 : Assigning value 0x00 (idx=1) from 543/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRCSLAT_F1 : Assigning value 0x0010 (idx=1) from 550/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000110x0000000000010101001000000000101000000100000000000010000000000000000000000000000000000010110000000101010000001001001000001001011000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000001100001100011000000111000111001110000000000000010000010000100000000000000000000100000100001000000000000000000001000001000010000000000000000000010000010000100000000000000000000100000100001000000000010000000000000000001000000000000000000001000000000000010101100010000000010000010000100000000000000000101000101001010000100000000010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000c0015200a04002000000002c0540920960000040000000400000004000000040000c3181c7380010420000104200001042000010420000104200400008000040015880410800028a50802</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKE_DELAY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_BOOT_STATE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_CHANGE_STATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DRAM_CLK_DISABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FUNC_VALID_CYCLES = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI_VERSION_4P0V1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_TRAIN_AFTER_INIT_COMPLETE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MIN = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_DISABLE = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_DRAM_CLK_ENABLE = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_LP_RESP = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PARIN_LAT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRDATA_DELAY = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFIBUS_FREQ_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFI_FREQ_RATIO_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLMSG_RESP_F2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_INTERVAL_F2 = 0x00014528</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRLUPD_MAX_F2 = 0x002084</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_CTRL_DELAY_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_COMPLETE_F2 = 0x001000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_INIT_START_F2 = 0x000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_F2 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE0_F2 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE1_F2 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE2_F2 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_MAX_TYPE3_F2 = 0x00041080</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYMSTR_RESP_F2 = 0x0071ce</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_RESP_F2 = 0x0030c6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE0_F2 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE1_F2 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE2_F2 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHYUPD_TYPE3_F2 = 0x00000200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_RDLAT_F2 = 0x004b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRDATA_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_PHY_WRLAT_F2 = 0x0012</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDCSLAT_F2 = 0x0015</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_RDDATA_EN_F2 = 0x0016</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_DIS_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_FS_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_RD_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_EN_WR_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_FAST_TOGGLE_F2 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WCK_TOGGLE_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDFI_WRCSLAT_F2 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKE_DELAY : Assigning value 0x00 (idx=1) from 569/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_BOOT_STATE : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_CHANGE_STATE : Assigning value 0x01 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DRAM_CLK_DISABLE : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FUNC_VALID_CYCLES : Assigning value 0x02 (idx=1) from 572/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI_VERSION_4P0V1 : Assigning value 0x00 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_TRAIN_AFTER_INIT_COMPLETE : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MIN : Assigning value 0x0015 (idx=1) from 576/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_DISABLE : Assigning value 0x06 (idx=1) from 70/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_DRAM_CLK_ENABLE : Assigning value 0x05 (idx=1) from 74/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_LP_RESP : Assigning value 0x10 (idx=1) from 126/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PARIN_LAT : Assigning value 0x00 (idx=1) from 131/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRDATA_DELAY : Assigning value 0x05 (idx=1) from 561/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFIBUS_FREQ_F2 : Assigning value 0x02 (idx=1) from 595/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFI_FREQ_RATIO_F2 : Assigning value 0x02 (idx=1) from 593/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLMSG_RESP_F2 : Assigning value 0x20 (idx=1) from 6/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_INTERVAL_F2 : Assigning value 0x00014528 (idx=1) from 13/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRLUPD_MAX_F2 : Assigning value 0x002084 (idx=1) from 45/21/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_CTRL_DELAY_F2 : Assigning value 0x02 (idx=1) from 66/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_COMPLETE_F2 : Assigning value 0x001000 (idx=1) from 78/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_INIT_START_F2 : Assigning value 0x000200 (idx=1) from 102/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_F2 : Assigning value 0x00041080 (idx=1) from 134/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE0_F2 : Assigning value 0x00041080 (idx=1) from 166/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE1_F2 : Assigning value 0x00041080 (idx=1) from 198/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE2_F2 : Assigning value 0x00041080 (idx=1) from 230/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_MAX_TYPE3_F2 : Assigning value 0x00041080 (idx=1) from 262/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYMSTR_RESP_F2 : Assigning value 0x0071ce (idx=1) from 294/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_RESP_F2 : Assigning value 0x0030c6 (idx=1) from 314/23/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE0_F2 : Assigning value 0x00000200 (idx=1) from 337/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE1_F2 : Assigning value 0x00000200 (idx=1) from 369/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE2_F2 : Assigning value 0x00000200 (idx=1) from 401/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHYUPD_TYPE3_F2 : Assigning value 0x00000200 (idx=1) from 433/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_RDLAT_F2 : Assigning value 0x004b (idx=1) from 465/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRDATA_F2 : Assigning value 0x02 (idx=1) from 476/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_PHY_WRLAT_F2 : Assigning value 0x0012 (idx=1) from 479/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDCSLAT_F2 : Assigning value 0x0015 (idx=1) from 490/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_RDDATA_EN_F2 : Assigning value 0x0016 (idx=1) from 501/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_DIS_F2 : Assigning value 0x00 (idx=1) from 512/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_FS_F2 : Assigning value 0x00 (idx=1) from 518/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_RD_F2 : Assigning value 0x00 (idx=1) from 525/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_EN_WR_F2 : Assigning value 0x00 (idx=1) from 532/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_FAST_TOGGLE_F2 : Assigning value 0x04 (idx=1) from 539/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WCK_TOGGLE_F2 : Assigning value 0x00 (idx=1) from 543/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDFI_WRCSLAT_F2 : Assigning value 0x0010 (idx=1) from 550/11/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0001010x0000000000010101001000000000101000000100000000000010000000000000000000000000000000000010110000000101010000001001001000001001011000000000000000000000010000000000000000000000000000000100000000000000000000000000000001000000000000000000000000000000010000000000000000001100001100011000000111000111001110000000000000010000010000100000000000000000000100000100001000000000000000000001000001000010000000000000000000010000010000100000000000000000000100000100001000000000010000000000000000001000000000000000000001000000000000010101100010000000010000010000100000000000000000101000101001010000100000000010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000140015200a04002000000002c0540920960000040000000400000004000000040000c3181c7380010420000104200001042000010420000104200400008000040015880410800028a50802</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_REQ_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_EN = 0x2d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_EN = 0x2f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_IDLE_WAKEUP_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_WAKEUP_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_WAKEUP_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_WAKEUP_F0 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_IDLE_WAKEUP_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_PD_WAKEUP_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_WAKEUP_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_SHORT_WAKEUP_F0 = 0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_WAKEUP_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_SHORT_WAKEUP_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_WAKEUP_F0 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_REQ_EN : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 49/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_EN : Assigning value 0x2d (idx=1) from 1/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 37/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 25/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_EN : Assigning value 0x2f (idx=1) from 7/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 13/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_IDLE_WAKEUP_F0 : Assigning value 0x00 (idx=1) from 61/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 : Assigning value 0x0a (idx=1) from 67/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_WAKEUP_F0 : Assigning value 0x09 (idx=1) from 73/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F0 : Assigning value 0x0a (idx=1) from 79/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_WAKEUP_F0 : Assigning value 0x09 (idx=1) from 85/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_WAKEUP_F0 : Assigning value 0x0e (idx=1) from 91/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_IDLE_WAKEUP_F0 : Assigning value 0x00 (idx=1) from 97/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_PD_WAKEUP_F0 : Assigning value 0x01 (idx=1) from 103/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F0 : Assigning value 0x0a (idx=1) from 109/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_WAKEUP_F0 : Assigning value 0x09 (idx=1) from 115/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_SHORT_WAKEUP_F0 : Assigning value 0x07 (idx=1) from 121/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_MCCLK_GATE_WAKEUP_F0 : Assigning value 0x0a (idx=1) from 127/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_WAKEUP_F0 : Assigning value 0x09 (idx=1) from 133/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_SHORT_WAKEUP_F0 : Assigning value 0x00 (idx=1) from 139/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_WAKEUP_F0 : Assigning value 0x0e (idx=1) from 145/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0011100000000010010010100001110010010010100000010000000011100010010010100010010010100000000000000000110000000001000000000000110000000001001011111011010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c01250e4940807125125000060080060097da</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_REQ_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_EN = 0x2d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_EN = 0x2f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_IDLE_WAKEUP_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_WAKEUP_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_WAKEUP_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_WAKEUP_F1 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_IDLE_WAKEUP_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_PD_WAKEUP_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_WAKEUP_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_SHORT_WAKEUP_F1 = 0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_WAKEUP_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_SHORT_WAKEUP_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_WAKEUP_F1 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_REQ_EN : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 49/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_EN : Assigning value 0x2d (idx=1) from 1/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 37/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 25/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_EN : Assigning value 0x2f (idx=1) from 7/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 13/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_IDLE_WAKEUP_F1 : Assigning value 0x00 (idx=1) from 61/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 : Assigning value 0x0a (idx=1) from 67/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_WAKEUP_F1 : Assigning value 0x09 (idx=1) from 73/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F1 : Assigning value 0x0a (idx=1) from 79/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_WAKEUP_F1 : Assigning value 0x09 (idx=1) from 85/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_WAKEUP_F1 : Assigning value 0x0e (idx=1) from 91/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_IDLE_WAKEUP_F1 : Assigning value 0x00 (idx=1) from 97/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_PD_WAKEUP_F1 : Assigning value 0x01 (idx=1) from 103/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F1 : Assigning value 0x0a (idx=1) from 109/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_WAKEUP_F1 : Assigning value 0x09 (idx=1) from 115/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_SHORT_WAKEUP_F1 : Assigning value 0x07 (idx=1) from 121/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_MCCLK_GATE_WAKEUP_F1 : Assigning value 0x0a (idx=1) from 127/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_WAKEUP_F1 : Assigning value 0x09 (idx=1) from 133/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_SHORT_WAKEUP_F1 : Assigning value 0x00 (idx=1) from 139/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_WAKEUP_F1 : Assigning value 0x0e (idx=1) from 145/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0011100000000010010010100001110010010010100000010000000011100010010010100010010010100000000000000000110000000001000000000000110000000001001011111011010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c01250e4940807125125000060080060097da</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_REQ_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_EN = 0x2d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_COUNT = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_EN = 0x2f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_WAKEUP_TIMEOUT = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_IDLE_WAKEUP_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SRPD_LONG_WAKEUP_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_SR_LONG_WAKEUP_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_CTRL_TIMER_WAKEUP_F2 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_IDLE_WAKEUP_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_PD_WAKEUP_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_LONG_WAKEUP_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SRPD_SHORT_WAKEUP_F2 = 0x07</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_LONG_WAKEUP_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_SR_SHORT_WAKEUP_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPI_TIMER_WAKEUP_F2 = 0x0e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_REQ_EN : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 49/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_EN : Assigning value 0x2d (idx=1) from 1/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 37/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_COUNT : Assigning value 0x0003 (idx=1) from 25/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_EN : Assigning value 0x2f (idx=1) from 7/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_WAKEUP_TIMEOUT : Assigning value 0x0004 (idx=1) from 13/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_IDLE_WAKEUP_F2 : Assigning value 0x00 (idx=1) from 61/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 : Assigning value 0x0a (idx=1) from 67/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SRPD_LONG_WAKEUP_F2 : Assigning value 0x09 (idx=1) from 73/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_MCCLK_GATE_WAKEUP_F2 : Assigning value 0x0a (idx=1) from 79/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_SR_LONG_WAKEUP_F2 : Assigning value 0x09 (idx=1) from 85/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_CTRL_TIMER_WAKEUP_F2 : Assigning value 0x0e (idx=1) from 91/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_IDLE_WAKEUP_F2 : Assigning value 0x00 (idx=1) from 97/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_PD_WAKEUP_F2 : Assigning value 0x01 (idx=1) from 103/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_MCCLK_GATE_WAKEUP_F2 : Assigning value 0x0a (idx=1) from 109/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_LONG_WAKEUP_F2 : Assigning value 0x09 (idx=1) from 115/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SRPD_SHORT_WAKEUP_F2 : Assigning value 0x07 (idx=1) from 121/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_MCCLK_GATE_WAKEUP_F2 : Assigning value 0x0a (idx=1) from 127/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_LONG_WAKEUP_F2 : Assigning value 0x09 (idx=1) from 133/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_SR_SHORT_WAKEUP_F2 : Assigning value 0x00 (idx=1) from 139/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPI_TIMER_WAKEUP_F2 : Assigning value 0x0e (idx=1) from 145/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0011100000000010010010100001110010010010100000010000000011100010010010100010010010100000000000000000110000000001000000000000110000000001001011111011010;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001c01250e4940807125125000060080060097da</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TSREF2PHYMSTR = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TSREF2PHYMSTR : Assigning value 0x10 (idx=1) from 0/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx010000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ENABLE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FREQ = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FSP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DVFSQ_MODE_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FREQ_CHANGE_TYPE_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_DFS_WAIT_TIME_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ENABLE : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_0 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_1 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_2 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_0 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_1 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_2 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FREQ : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FSP : Assigning value 0x00 (idx=1) from 3/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DVFSQ_MODE_F0 : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FREQ_CHANGE_TYPE_F0 : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_DFS_WAIT_TIME_F0 : Assigning value 0x0000 (idx=1) from 11/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000000000101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ENABLE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FREQ = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FSP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DVFSQ_MODE_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FREQ_CHANGE_TYPE_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_DFS_WAIT_TIME_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ENABLE : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_0 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_1 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_2 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_0 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_1 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_2 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FREQ : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FSP : Assigning value 0x00 (idx=1) from 3/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DVFSQ_MODE_F1 : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FREQ_CHANGE_TYPE_F1 : Assigning value 0x01 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_DFS_WAIT_TIME_F1 : Assigning value 0x0000 (idx=1) from 11/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000001000101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000045</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ENABLE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_MAP_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FSP_VALID_2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FREQ = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INIT_FSP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DVFSQ_MODE_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key FREQ_CHANGE_TYPE_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POST_DFS_WAIT_TIME_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ENABLE : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_0 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_1 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_MAP_2 : Assigning value 0x00 (idx=1) from 8/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_0 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_1 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FSP_VALID_2 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FREQ : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INIT_FSP : Assigning value 0x00 (idx=1) from 3/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DVFSQ_MODE_F2 : Assigning value 0x00 (idx=1) from 5/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.FREQ_CHANGE_TYPE_F2 : Assigning value 0x02 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POST_DFS_WAIT_TIME_F2 : Assigning value 0x0000 (idx=1) from 11/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000010000101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000085</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_IDLE_CNT = 0x0064</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_INTERVAL = 0x03e8</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_LEN = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_START_ADDR = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ECC_SCRUB_END_ADDR = 0x0000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_IDLE_CNT : Assigning value 0x0064 (idx=1) from 96/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_INTERVAL : Assigning value 0x03e8 (idx=1) from 112/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_LEN : Assigning value 0x0010 (idx=1) from 128/13/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_MODE : Assigning value 0x00 (idx=1) from 141/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_START_ADDR : Assigning value 0x0000000000 (idx=1) from 20/38/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ECC_SCRUB_END_ADDR : Assigning value 0x0000000000 (idx=1) from 58/38/0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000010000000000111110100000000000011001000000000000000000000000000000000000000000000000000000000000000000000000000000xxxxxxxxxxxxxxxxxxxx;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001003e80064000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_BIST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_DFI = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_DIMM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_ECC = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_FREQ = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_INIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_LOWPOWER = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_MASTER = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_MISC = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_MODE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_PARITY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_TIMEOUT = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_TRAINING = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INT_MASK_USERIF = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_BIST : Assigning value 0x00 (idx=1) from 192/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_DFI : Assigning value 0x00 (idx=1) from 200/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_DIMM : Assigning value 0x00 (idx=1) from 208/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_ECC : Assigning value 0x00000000 (idx=1) from 64/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_FREQ : Assigning value 0x00 (idx=1) from 216/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_INIT : Assigning value 0x00 (idx=1) from 224/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_LOWPOWER : Assigning value 0x0000 (idx=1) from 96/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_MASTER : Assigning value 0x00000000 (idx=1) from 0/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_MISC : Assigning value 0x0000 (idx=1) from 176/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_MODE : Assigning value 0x00 (idx=1) from 232/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_PARITY : Assigning value 0x00 (idx=1) from 240/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_TIMEOUT : Assigning value 0x00000000 (idx=1) from 32/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_TRAINING : Assigning value 0x00000000 (idx=1) from 112/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INT_MASK_USERIF : Assigning value 0x00000000 (idx=1) from 144/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LOWPOWER_REFRESH_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_SR_CTRLUPD_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_SR_PHYMSTR_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_SR_PHYUPD_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_SR_ZQ_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_ENTRY_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_EXIT_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_MEM_GATE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_PD_IDLE = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_SR_LONG_IDLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_SR_LONG_MC_GATE_IDLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LP_AUTO_SR_SHORT_IDLE = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LOWPOWER_REFRESH_ENABLE : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_SR_CTRLUPD_EN : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_SR_PHYMSTR_EN : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_SR_PHYUPD_EN : Assigning value 0x00 (idx=1) from 2/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_SR_ZQ_EN : Assigning value 0x00 (idx=1) from 3/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_ENTRY_EN : Assigning value 0x00 (idx=1) from 6/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_EXIT_EN : Assigning value 0x00 (idx=1) from 10/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_MEM_GATE_EN : Assigning value 0x00 (idx=1) from 14/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_PD_IDLE : Assigning value 0x0000 (idx=1) from 17/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_SR_LONG_IDLE : Assigning value 0x00 (idx=1) from 29/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_SR_LONG_MC_GATE_IDLE : Assigning value 0x00 (idx=1) from 37/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LP_AUTO_SR_SHORT_IDLE : Assigning value 0x0000 (idx=1) from 45/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000000000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_HIGH_THRESHOLD = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_NORM_THRESHOLD = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_HIGH_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_NORM_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TIMEOUT = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LONG_COUNT_MASK = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CWW_SW_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key HW_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPRR_SW_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_HIGH_THRESHOLD_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_NORM_THRESHOLD_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_TIMEOUT_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_HIGH_THRESHOLD_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_NORM_THRESHOLD_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_TIMEOUT_F0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRW_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_HIGH_THRESHOLD_F0 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_NORM_THRESHOLD_F0 = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_TIMEOUT_F0 = 0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_HIGH_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_TIMEOUT_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_HIGH_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_NORM_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_TIMEOUT_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_HIGH_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_NORM_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_TIMEOUT_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_PROMOTE_THRESHOLD_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_HIGH_THRESHOLD : Assigning value 0x15 (idx=1) from 5/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_NORM_THRESHOLD : Assigning value 0x14 (idx=1) from 0/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_HIGH_THRESHOLD : Assigning value 0x00000000 (idx=1) from 42/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_NORM_THRESHOLD : Assigning value 0x00000000 (idx=1) from 10/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 458/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TIMEOUT : Assigning value 0x00000000 (idx=1) from 74/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LONG_COUNT_MASK : Assigning value 0x00 (idx=1) from 666/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 522/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CWW_SW_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 426/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 442/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.HW_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 490/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 506/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPRR_SW_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 554/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 570/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_HIGH_THRESHOLD_F0 : Assigning value 0x000000 (idx=1) from 130/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_NORM_THRESHOLD_F0 : Assigning value 0x000000 (idx=1) from 106/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_TIMEOUT_F0 : Assigning value 0x000000 (idx=1) from 154/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_HIGH_THRESHOLD_F0 : Assigning value 0x000000 (idx=1) from 202/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_NORM_THRESHOLD_F0 : Assigning value 0x000000 (idx=1) from 178/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_TIMEOUT_F0 : Assigning value 0x000000 (idx=1) from 226/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRW_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 586/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI4_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 602/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_HIGH_THRESHOLD_F0 : Assigning value 0x0004 (idx=1) from 266/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_NORM_THRESHOLD_F0 : Assigning value 0x0003 (idx=1) from 250/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F0 : Assigning value 0x0004 (idx=1) from 618/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_TIMEOUT_F0 : Assigning value 0x0005 (idx=1) from 282/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 634/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_HIGH_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 298/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_TIMEOUT_F0 : Assigning value 0x0000 (idx=1) from 314/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_HIGH_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 346/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_NORM_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 330/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_TIMEOUT_F0 : Assigning value 0x0000 (idx=1) from 362/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_HIGH_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 394/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_NORM_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 378/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_TIMEOUT_F0 : Assigning value 0x0000 (idx=1) from 410/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_PROMOTE_THRESHOLD_F0 : Assigning value 0x0000 (idx=1) from 650/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000010000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010110100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000140010000c000000000000000000000000000000000000000000000000000000000002b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_HIGH_THRESHOLD = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_NORM_THRESHOLD = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_HIGH_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_NORM_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TIMEOUT = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LONG_COUNT_MASK = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CWW_SW_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key HW_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPRR_SW_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_HIGH_THRESHOLD_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_NORM_THRESHOLD_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_TIMEOUT_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_HIGH_THRESHOLD_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_NORM_THRESHOLD_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_TIMEOUT_F1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRW_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_HIGH_THRESHOLD_F1 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_NORM_THRESHOLD_F1 = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_TIMEOUT_F1 = 0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_HIGH_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_TIMEOUT_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_HIGH_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_NORM_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_TIMEOUT_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_HIGH_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_NORM_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_TIMEOUT_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_PROMOTE_THRESHOLD_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_HIGH_THRESHOLD : Assigning value 0x15 (idx=1) from 5/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_NORM_THRESHOLD : Assigning value 0x14 (idx=1) from 0/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_HIGH_THRESHOLD : Assigning value 0x00000000 (idx=1) from 42/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_NORM_THRESHOLD : Assigning value 0x00000000 (idx=1) from 10/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 458/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TIMEOUT : Assigning value 0x00000000 (idx=1) from 74/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LONG_COUNT_MASK : Assigning value 0x00 (idx=1) from 666/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 522/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CWW_SW_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 426/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 442/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.HW_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 490/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 506/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPRR_SW_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 554/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 570/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_HIGH_THRESHOLD_F1 : Assigning value 0x000000 (idx=1) from 130/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_NORM_THRESHOLD_F1 : Assigning value 0x000000 (idx=1) from 106/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_TIMEOUT_F1 : Assigning value 0x000000 (idx=1) from 154/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_HIGH_THRESHOLD_F1 : Assigning value 0x000000 (idx=1) from 202/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_NORM_THRESHOLD_F1 : Assigning value 0x000000 (idx=1) from 178/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_TIMEOUT_F1 : Assigning value 0x000000 (idx=1) from 226/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRW_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 586/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI4_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 602/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_HIGH_THRESHOLD_F1 : Assigning value 0x0004 (idx=1) from 266/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_NORM_THRESHOLD_F1 : Assigning value 0x0003 (idx=1) from 250/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F1 : Assigning value 0x0004 (idx=1) from 618/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_TIMEOUT_F1 : Assigning value 0x0005 (idx=1) from 282/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 634/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_HIGH_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 298/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_TIMEOUT_F1 : Assigning value 0x0000 (idx=1) from 314/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_HIGH_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 346/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_NORM_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 330/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_TIMEOUT_F1 : Assigning value 0x0000 (idx=1) from 362/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_HIGH_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 394/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_NORM_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 378/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_TIMEOUT_F1 : Assigning value 0x0000 (idx=1) from 410/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_PROMOTE_THRESHOLD_F1 : Assigning value 0x0000 (idx=1) from 650/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000010000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010110100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000140010000c000000000000000000000000000000000000000000000000000000000002b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_HIGH_THRESHOLD = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_NORM_THRESHOLD = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_HIGH_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_NORM_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DQS_OSC_TIMEOUT = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LONG_COUNT_MASK = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPC_PROMOTE_THRESHOLD = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CWW_SW_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key HW_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LPC_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MPRR_SW_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_HIGH_THRESHOLD_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_NORM_THRESHOLD_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_TEMPCHK_TIMEOUT_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_HIGH_THRESHOLD_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_NORM_THRESHOLD_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRR_WR_LECC_TIMEOUT_F2 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MRW_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_HIGH_THRESHOLD_F2 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_NORM_THRESHOLD_F2 = 0x0003</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_CTRLUPD_TIMEOUT_F2 = 0x0005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_HIGH_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALLATCH_TIMEOUT_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_HIGH_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_NORM_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CALSTART_TIMEOUT_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_HIGH_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_NORM_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CS_TIMEOUT_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_PROMOTE_THRESHOLD_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_HIGH_THRESHOLD : Assigning value 0x15 (idx=1) from 5/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_NORM_THRESHOLD : Assigning value 0x14 (idx=1) from 0/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_HIGH_THRESHOLD : Assigning value 0x00000000 (idx=1) from 42/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_NORM_THRESHOLD : Assigning value 0x00000000 (idx=1) from 10/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 458/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DQS_OSC_TIMEOUT : Assigning value 0x00000000 (idx=1) from 74/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LONG_COUNT_MASK : Assigning value 0x00 (idx=1) from 666/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPC_PROMOTE_THRESHOLD : Assigning value 0x00000000 (idx=1) from 522/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CWW_SW_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 426/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 442/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.HW_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 490/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LPC_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 506/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MPRR_SW_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 554/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 570/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_HIGH_THRESHOLD_F2 : Assigning value 0x000000 (idx=1) from 130/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_NORM_THRESHOLD_F2 : Assigning value 0x000000 (idx=1) from 106/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_TEMPCHK_TIMEOUT_F2 : Assigning value 0x000000 (idx=1) from 154/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_HIGH_THRESHOLD_F2 : Assigning value 0x000000 (idx=1) from 202/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_NORM_THRESHOLD_F2 : Assigning value 0x000000 (idx=1) from 178/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRR_WR_LECC_TIMEOUT_F2 : Assigning value 0x000000 (idx=1) from 226/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MRW_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 586/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_DFI4_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 602/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_HIGH_THRESHOLD_F2 : Assigning value 0x0004 (idx=1) from 266/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_NORM_THRESHOLD_F2 : Assigning value 0x0003 (idx=1) from 250/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_SW_PROMOTE_THRESHOLD_F2 : Assigning value 0x0004 (idx=1) from 618/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_CTRLUPD_TIMEOUT_F2 : Assigning value 0x0005 (idx=1) from 282/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.UPD_PHYUPD_DFI_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 634/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_HIGH_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 298/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALLATCH_TIMEOUT_F2 : Assigning value 0x0000 (idx=1) from 314/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_HIGH_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 346/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_NORM_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 330/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CALSTART_TIMEOUT_F2 : Assigning value 0x0000 (idx=1) from 362/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_HIGH_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 394/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_NORM_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 378/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CS_TIMEOUT_F2 : Assigning value 0x0000 (idx=1) from 410/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_PROMOTE_THRESHOLD_F2 : Assigning value 0x0000 (idx=1) from 650/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000010000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001010110100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000000000000000000000000000000000000000000000000000000000000000000000000000000140010000c000000000000000000000000000000000000000000000000000000000002b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OSC_VARIANCE_LIMIT = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRECHARGE_DLR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SRX_NOP_CMDS = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TAAD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_DLR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_CS_LOW = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_HOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_SETUP = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPRR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_INTERVAL = 0x000005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDITIVE_LAT_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CASLAT_LIN_F0 = 0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_LAT_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRE_F0 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRX_F0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NWR_F0 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_LEN_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCACSH_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCDMW_F0 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR2_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR_F0 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKCKEL_F0 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCMD_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCS_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCMD_F0 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCS_F0 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELPD_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKESR_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKE_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKSTAB_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCMDCKE_F0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCPDED_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKEH_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKE_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSH_F0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSSR_F0 = 0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDAL_F0 = 0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TESCKE_F0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_DLR_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_F0 = 0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_F0 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_PAR_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_DELAY_F0 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_F0 = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_PAR_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRRI_F0 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRWCKEL_F0 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSCO_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSC_TRK_CALC_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPDEX_F0 = 0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPPD_F0 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MAX_F0 = 0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MIN_F0 = 0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRCD_F0 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRC_F0 = 0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_F0 = 0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_DLR_F0 = 0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_F0 = 0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_DLR_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_F0 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_DLR_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_F0 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_L_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_AP_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TSR_F0 = 0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWR_F0 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_AP_F0 = 0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_F0 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_AP_F0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSNR_F0 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSR_F0 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCAL_F0 = 0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCKE_F0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQLAT_F0 = 0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRLAT_F0 = 0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_PREAMBLE_LEN_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F0_0 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F0_0 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F0_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F0_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F0_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F0_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F0_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F0_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F0_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F0_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F0_0 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F0_1 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F0_1 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F0_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F0_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F0_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F0_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F0_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F0_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F0_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F0_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F0_1 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OSC_VARIANCE_LIMIT : Assigning value 0x0010 (idx=1) from 43/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRECHARGE_DLR : Assigning value 0x08 (idx=1) from 59/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SRX_NOP_CMDS : Assigning value 0x05 (idx=1) from 75/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TAAD : Assigning value 0x08 (idx=1) from 79/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD : Assigning value 0x08 (idx=1) from 95/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_DLR : Assigning value 0x00 (idx=1) from 106/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_CS_LOW : Assigning value 0x04 (idx=1) from 287/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_HOLD : Assigning value 0x03 (idx=1) from 299/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_SETUP : Assigning value 0x03 (idx=1) from 913/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPRR : Assigning value 0x00 (idx=1) from 917/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRR : Assigning value 0x08 (idx=1) from 335/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD1 : Assigning value 0x00 (idx=1) from 351/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD2 : Assigning value 0x00 (idx=1) from 357/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_INTERVAL : Assigning value 0x000005 (idx=1) from 552/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 592/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDITIVE_LAT_F0 : Assigning value 0x00 (idx=1) from 0/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CASLAT_LIN_F0 : Assigning value 0x2c (idx=1) from 7/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_LAT_F0 : Assigning value 0x00 (idx=1) from 15/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRE_F0 : Assigning value 0x06 (idx=1) from 19/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRX_F0 : Assigning value 0x03 (idx=1) from 27/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NWR_F0 : Assigning value 0x14 (idx=1) from 35/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_LEN_F0 : Assigning value 0x01 (idx=1) from 67/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCACSH_F0 : Assigning value 0x02 (idx=1) from 87/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCDMW_F0 : Assigning value 0x20 (idx=1) from 100/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_F0 : Assigning value 0x00 (idx=1) from 111/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR2_F0 : Assigning value 0x00 (idx=1) from 116/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR_F0 : Assigning value 0x20 (idx=1) from 123/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKCKEL_F0 : Assigning value 0x06 (idx=1) from 130/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCMD_F0 : Assigning value 0x09 (idx=1) from 135/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCS_F0 : Assigning value 0x09 (idx=1) from 140/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCMD_F0 : Assigning value 0x06 (idx=1) from 145/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCS_F0 : Assigning value 0x06 (idx=1) from 150/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELPD_F0 : Assigning value 0x09 (idx=1) from 155/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKESR_F0 : Assigning value 0x09 (idx=1) from 163/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKE_F0 : Assigning value 0x09 (idx=1) from 171/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKSTAB_F0 : Assigning value 0x0000 (idx=1) from 179/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCMDCKE_F0 : Assigning value 0x03 (idx=1) from 195/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCPDED_F0 : Assigning value 0x00 (idx=1) from 203/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKEH_F0 : Assigning value 0x02 (idx=1) from 211/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKE_F0 : Assigning value 0x02 (idx=1) from 216/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSH_F0 : Assigning value 0x03 (idx=1) from 221/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSSR_F0 : Assigning value 0x1e (idx=1) from 229/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDAL_F0 : Assigning value 0x29 (idx=1) from 237/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TESCKE_F0 : Assigning value 0x03 (idx=1) from 245/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_DLR_F0 : Assigning value 0x0000 (idx=1) from 253/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_F0 : Assigning value 0x002b (idx=1) from 262/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_F0 : Assigning value 0x0f (idx=1) from 271/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_PAR_F0 : Assigning value 0x00 (idx=1) from 279/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_DELAY_F0 : Assigning value 0x0b (idx=1) from 291/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_F0 : Assigning value 0x000b (idx=1) from 303/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_PAR_F0 : Assigning value 0x0000 (idx=1) from 319/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRRI_F0 : Assigning value 0x17 (idx=1) from 343/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRWCKEL_F0 : Assigning value 0x0f (idx=1) from 363/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSCO_F0 : Assigning value 0x00 (idx=1) from 371/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSC_TRK_CALC_F0 : Assigning value 0x0000 (idx=1) from 379/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPDEX_F0 : Assigning value 0x0009 (idx=1) from 467/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPPD_F0 : Assigning value 0x04 (idx=1) from 483/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MAX_F0 : Assigning value 0x00d903 (idx=1) from 486/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MIN_F0 : Assigning value 0x002d (idx=1) from 506/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRCD_F0 : Assigning value 0x14 (idx=1) from 515/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRC_F0 : Assigning value 0x0041 (idx=1) from 523/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_F0 : Assigning value 0x001042 (idx=1) from 532/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_DLR_F0 : Assigning value 0x0060 (idx=1) from 572/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_F0 : Assigning value 0x00c1 (idx=1) from 582/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_DLR_F0 : Assigning value 0x0000 (idx=1) from 667/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_F0 : Assigning value 0x0000 (idx=1) from 677/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_F0 : Assigning value 0x14 (idx=1) from 743/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_DLR_F0 : Assigning value 0x00 (idx=1) from 751/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_F0 : Assigning value 0x0b (idx=1) from 759/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_L_F0 : Assigning value 0x00 (idx=1) from 767/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_AP_F0 : Assigning value 0x00 (idx=1) from 775/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_F0 : Assigning value 0x09 (idx=1) from 783/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TSR_F0 : Assigning value 0x11 (idx=1) from 791/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWR_F0 : Assigning value 0x15 (idx=1) from 799/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_AP_F0 : Assigning value 0x000c (idx=1) from 807/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_F0 : Assigning value 0x0c (idx=1) from 816/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_AP_F0 : Assigning value 0x0000 (idx=1) from 823/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_F0 : Assigning value 0x00 (idx=1) from 832/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSNR_F0 : Assigning value 0x00c9 (idx=1) from 839/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSR_F0 : Assigning value 0x00c9 (idx=1) from 855/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCAL_F0 : Assigning value 0x042c (idx=1) from 871/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCKE_F0 : Assigning value 0x03 (idx=1) from 883/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQLAT_F0 : Assigning value 0x21 (idx=1) from 891/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRLAT_F0 : Assigning value 0x12 (idx=1) from 898/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_PREAMBLE_LEN_F0 : Assigning value 0x01 (idx=1) from 905/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F0_0 : Assigning value 0x10 (idx=1) from 395/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F0_0 : Assigning value 0x0b (idx=1) from 411/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F0_0 : Assigning value 0x0000 (idx=1) from 427/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F0_0 : Assigning value 0x0061 (idx=1) from 447/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F0_0 : Assigning value 0x0000 (idx=1) from 595/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F0_0 : Assigning value 0x0061 (idx=1) from 615/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F0_0 : Assigning value 0x00 (idx=1) from 635/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F0_0 : Assigning value 0x00 (idx=1) from 651/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F0_0 : Assigning value 0x0000 (idx=1) from 687/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F0_0 : Assigning value 0x0000 (idx=1) from 707/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F0_0 : Assigning value 0x17 (idx=1) from 727/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F0_1 : Assigning value 0x10 (idx=1) from 403/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F0_1 : Assigning value 0x0b (idx=1) from 419/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F0_1 : Assigning value 0x0000 (idx=1) from 437/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F0_1 : Assigning value 0x0061 (idx=1) from 457/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F0_1 : Assigning value 0x0000 (idx=1) from 605/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F0_1 : Assigning value 0x0061 (idx=1) from 625/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F0_1 : Assigning value 0x00 (idx=1) from 643/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F0_1 : Assigning value 0x00 (idx=1) from 659/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F0_1 : Assigning value 0x0000 (idx=1) from 697/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F0_1 : Assigning value 0x0000 (idx=1) from 717/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F0_1 : Assigning value 0x17 (idx=1) from 735/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110000000100100100100001000000110100001011000000000011001001000000001100100100000000000000000001100000001100000101010001000100001001000000000000000000001011000000000001010000010111000101110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000010001100001000000000000000000000110011000001000110000000000000000000000101000000010000010000100010000010001010000010110100001101100100000011100000000000000100100011000010001100001000000000000000000000000101100001011000100000001000000000000000000000000000000001111000000000000000101110000100000000000000000000000000000001011001100001011010000000000000011110001010110000000000000001100101001000111100000001100010000100000000000000011000000000000000000001001000010010000100100110001100100101001001100100000000000000000000001000000100000000010000010000101000000010000100000000000000100000001010000000011000001100000001011000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000060249081a160064806480000c060a8884800005800a0b8b800000000000000000000000c230800003304600000501042208a0b43640e00048c2308000005858808000000078000b8400000005985a00078ac0006523c06210001800004848498c94990000020401042808400080a018301600</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OSC_VARIANCE_LIMIT = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRECHARGE_DLR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SRX_NOP_CMDS = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TAAD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_DLR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_CS_LOW = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_HOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_SETUP = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPRR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_INTERVAL = 0x000005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDITIVE_LAT_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CASLAT_LIN_F1 = 0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_LAT_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRE_F1 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRX_F1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NWR_F1 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_LEN_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCACSH_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCDMW_F1 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR2_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR_F1 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKCKEL_F1 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCMD_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCS_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCMD_F1 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCS_F1 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELPD_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKESR_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKE_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKSTAB_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCMDCKE_F1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCPDED_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKEH_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKE_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSH_F1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSSR_F1 = 0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDAL_F1 = 0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TESCKE_F1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_DLR_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_F1 = 0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_F1 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_PAR_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_DELAY_F1 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_F1 = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_PAR_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRRI_F1 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRWCKEL_F1 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSCO_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSC_TRK_CALC_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPDEX_F1 = 0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPPD_F1 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MAX_F1 = 0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MIN_F1 = 0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRCD_F1 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRC_F1 = 0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_F1 = 0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_DLR_F1 = 0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_F1 = 0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_DLR_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_F1 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_DLR_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_F1 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_L_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_AP_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TSR_F1 = 0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWR_F1 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_AP_F1 = 0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_F1 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_AP_F1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSNR_F1 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSR_F1 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCAL_F1 = 0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCKE_F1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQLAT_F1 = 0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRLAT_F1 = 0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_PREAMBLE_LEN_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F1_0 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F1_0 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F1_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F1_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F1_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F1_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F1_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F1_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F1_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F1_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F1_0 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F1_1 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F1_1 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F1_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F1_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F1_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F1_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F1_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F1_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F1_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F1_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F1_1 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OSC_VARIANCE_LIMIT : Assigning value 0x0010 (idx=1) from 43/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRECHARGE_DLR : Assigning value 0x08 (idx=1) from 59/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SRX_NOP_CMDS : Assigning value 0x05 (idx=1) from 75/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TAAD : Assigning value 0x08 (idx=1) from 79/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD : Assigning value 0x08 (idx=1) from 95/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_DLR : Assigning value 0x00 (idx=1) from 106/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_CS_LOW : Assigning value 0x04 (idx=1) from 287/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_HOLD : Assigning value 0x03 (idx=1) from 299/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_SETUP : Assigning value 0x03 (idx=1) from 913/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPRR : Assigning value 0x00 (idx=1) from 917/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRR : Assigning value 0x08 (idx=1) from 335/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD1 : Assigning value 0x00 (idx=1) from 351/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD2 : Assigning value 0x00 (idx=1) from 357/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_INTERVAL : Assigning value 0x000005 (idx=1) from 552/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 592/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDITIVE_LAT_F1 : Assigning value 0x00 (idx=1) from 0/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CASLAT_LIN_F1 : Assigning value 0x2c (idx=1) from 7/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_LAT_F1 : Assigning value 0x00 (idx=1) from 15/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRE_F1 : Assigning value 0x06 (idx=1) from 19/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRX_F1 : Assigning value 0x03 (idx=1) from 27/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NWR_F1 : Assigning value 0x14 (idx=1) from 35/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_LEN_F1 : Assigning value 0x01 (idx=1) from 67/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCACSH_F1 : Assigning value 0x02 (idx=1) from 87/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCDMW_F1 : Assigning value 0x20 (idx=1) from 100/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_F1 : Assigning value 0x00 (idx=1) from 111/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR2_F1 : Assigning value 0x00 (idx=1) from 116/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR_F1 : Assigning value 0x20 (idx=1) from 123/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKCKEL_F1 : Assigning value 0x06 (idx=1) from 130/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCMD_F1 : Assigning value 0x09 (idx=1) from 135/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCS_F1 : Assigning value 0x09 (idx=1) from 140/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCMD_F1 : Assigning value 0x06 (idx=1) from 145/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCS_F1 : Assigning value 0x06 (idx=1) from 150/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELPD_F1 : Assigning value 0x09 (idx=1) from 155/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKESR_F1 : Assigning value 0x09 (idx=1) from 163/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKE_F1 : Assigning value 0x09 (idx=1) from 171/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKSTAB_F1 : Assigning value 0x0000 (idx=1) from 179/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCMDCKE_F1 : Assigning value 0x03 (idx=1) from 195/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCPDED_F1 : Assigning value 0x00 (idx=1) from 203/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKEH_F1 : Assigning value 0x02 (idx=1) from 211/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKE_F1 : Assigning value 0x02 (idx=1) from 216/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSH_F1 : Assigning value 0x03 (idx=1) from 221/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSSR_F1 : Assigning value 0x1e (idx=1) from 229/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDAL_F1 : Assigning value 0x29 (idx=1) from 237/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TESCKE_F1 : Assigning value 0x03 (idx=1) from 245/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_DLR_F1 : Assigning value 0x0000 (idx=1) from 253/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_F1 : Assigning value 0x002b (idx=1) from 262/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_F1 : Assigning value 0x0f (idx=1) from 271/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_PAR_F1 : Assigning value 0x00 (idx=1) from 279/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_DELAY_F1 : Assigning value 0x0b (idx=1) from 291/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_F1 : Assigning value 0x000b (idx=1) from 303/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_PAR_F1 : Assigning value 0x0000 (idx=1) from 319/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRRI_F1 : Assigning value 0x17 (idx=1) from 343/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRWCKEL_F1 : Assigning value 0x0f (idx=1) from 363/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSCO_F1 : Assigning value 0x00 (idx=1) from 371/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSC_TRK_CALC_F1 : Assigning value 0x0000 (idx=1) from 379/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPDEX_F1 : Assigning value 0x0009 (idx=1) from 467/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPPD_F1 : Assigning value 0x04 (idx=1) from 483/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MAX_F1 : Assigning value 0x00d903 (idx=1) from 486/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MIN_F1 : Assigning value 0x002d (idx=1) from 506/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRCD_F1 : Assigning value 0x14 (idx=1) from 515/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRC_F1 : Assigning value 0x0041 (idx=1) from 523/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_F1 : Assigning value 0x001042 (idx=1) from 532/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_DLR_F1 : Assigning value 0x0060 (idx=1) from 572/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_F1 : Assigning value 0x00c1 (idx=1) from 582/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_DLR_F1 : Assigning value 0x0000 (idx=1) from 667/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_F1 : Assigning value 0x0000 (idx=1) from 677/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_F1 : Assigning value 0x14 (idx=1) from 743/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_DLR_F1 : Assigning value 0x00 (idx=1) from 751/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_F1 : Assigning value 0x0b (idx=1) from 759/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_L_F1 : Assigning value 0x00 (idx=1) from 767/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_AP_F1 : Assigning value 0x00 (idx=1) from 775/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_F1 : Assigning value 0x09 (idx=1) from 783/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TSR_F1 : Assigning value 0x11 (idx=1) from 791/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWR_F1 : Assigning value 0x15 (idx=1) from 799/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_AP_F1 : Assigning value 0x000c (idx=1) from 807/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_F1 : Assigning value 0x0c (idx=1) from 816/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_AP_F1 : Assigning value 0x0000 (idx=1) from 823/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_F1 : Assigning value 0x00 (idx=1) from 832/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSNR_F1 : Assigning value 0x00c9 (idx=1) from 839/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSR_F1 : Assigning value 0x00c9 (idx=1) from 855/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCAL_F1 : Assigning value 0x042c (idx=1) from 871/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCKE_F1 : Assigning value 0x03 (idx=1) from 883/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQLAT_F1 : Assigning value 0x21 (idx=1) from 891/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRLAT_F1 : Assigning value 0x12 (idx=1) from 898/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_PREAMBLE_LEN_F1 : Assigning value 0x01 (idx=1) from 905/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F1_0 : Assigning value 0x10 (idx=1) from 395/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F1_0 : Assigning value 0x0b (idx=1) from 411/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F1_0 : Assigning value 0x0000 (idx=1) from 427/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F1_0 : Assigning value 0x0061 (idx=1) from 447/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F1_0 : Assigning value 0x0000 (idx=1) from 595/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F1_0 : Assigning value 0x0061 (idx=1) from 615/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F1_0 : Assigning value 0x00 (idx=1) from 635/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F1_0 : Assigning value 0x00 (idx=1) from 651/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F1_0 : Assigning value 0x0000 (idx=1) from 687/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F1_0 : Assigning value 0x0000 (idx=1) from 707/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F1_0 : Assigning value 0x17 (idx=1) from 727/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F1_1 : Assigning value 0x10 (idx=1) from 403/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F1_1 : Assigning value 0x0b (idx=1) from 419/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F1_1 : Assigning value 0x0000 (idx=1) from 437/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F1_1 : Assigning value 0x0061 (idx=1) from 457/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F1_1 : Assigning value 0x0000 (idx=1) from 605/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F1_1 : Assigning value 0x0061 (idx=1) from 625/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F1_1 : Assigning value 0x00 (idx=1) from 643/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F1_1 : Assigning value 0x00 (idx=1) from 659/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F1_1 : Assigning value 0x0000 (idx=1) from 697/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F1_1 : Assigning value 0x0000 (idx=1) from 717/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F1_1 : Assigning value 0x17 (idx=1) from 735/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110000000100100100100001000000110100001011000000000011001001000000001100100100000000000000000001100000001100000101010001000100001001000000000000000000001011000000000001010000010111000101110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000010001100001000000000000000000000110011000001000110000000000000000000000101000000010000010000100010000010001010000010110100001101100100000011100000000000000100100011000010001100001000000000000000000000000101100001011000100000001000000000000000000000000000000001111000000000000000101110000100000000000000000000000000000001011001100001011010000000000000011110001010110000000000000001100101001000111100000001100010000100000000000000011000000000000000000001001000010010000100100110001100100101001001100100000000000000000000001000000100000000010000010000101000000010000100000000000000100000001010000000011000001100000001011000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000060249081a160064806480000c060a8884800005800a0b8b800000000000000000000000c230800003304600000501042208a0b43640e00048c2308000005858808000000078000b8400000005985a00078ac0006523c06210001800004848498c94990000020401042808400080a018301600</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OSC_VARIANCE_LIMIT = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRECHARGE_DLR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SRX_NOP_CMDS = 0x05</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TAAD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_DLR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_CS_LOW = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_HOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_SETUP = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPRR = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRR = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRROD2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_INTERVAL = 0x000005</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDITIVE_LAT_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CASLAT_LIN_F2 = 0x2c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_PARITY_LAT_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRE_F2 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CKSRX_F2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NWR_F2 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_PREAMBLE_LEN_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCACSH_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCDMW_F2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR2_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCCD_L_WR_F2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKCKEL_F2 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCMD_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKEHCS_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCMD_F2 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELCS_F2 = 0x06</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKELPD_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKESR_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKE_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCKSTAB_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCMDCKE_F2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCPDED_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKEH_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSCKE_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSH_F2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TCSSR_F2 = 0x1e</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDAL_F2 = 0x29</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TESCKE_F2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_DLR_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TFAW_F2 = 0x002b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_F2 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMOD_PAR_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMPC_DELAY_F2 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_F2 = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRD_PAR_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRRI_F2 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TMRWCKEL_F2 = 0x0f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSCO_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TOSC_TRK_CALC_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPDEX_F2 = 0x0009</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPPD_F2 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MAX_F2 = 0x00d903</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_MIN_F2 = 0x002d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRCD_F2 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRC_F2 = 0x0041</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_F2 = 0x001042</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_DLR_F2 = 0x0060</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_F2 = 0x00c1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_DLR_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_F2 = 0x14</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_DLR_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_F2 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRRD_L_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_AP_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRTP_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TSR_F2 = 0x11</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWR_F2 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_AP_F2 = 0x000c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_F2 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_AP_F2 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TWTR_L_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSNR_F2 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TXSR_F2 = 0x00c9</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCAL_F2 = 0x042c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQCKE_F2 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TZQLAT_F2 = 0x21</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRLAT_F2 = 0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_PREAMBLE_LEN_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F2_0 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F2_0 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F2_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F2_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F2_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F2_0 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F2_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F2_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F2_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F2_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F2_0 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_DLR_F2_1 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2ACT_F2_1 = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_DLR_F2_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TPBR2PBR_F2_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_DLR_F2_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFC_PB_F2_1 = 0x0061</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_DLR_F2_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM2ACT_F2_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_DLR_F2_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRFM_SB_F2_1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRP_AB_F2_1 = 0x17</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OSC_VARIANCE_LIMIT : Assigning value 0x0010 (idx=1) from 43/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRECHARGE_DLR : Assigning value 0x08 (idx=1) from 59/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SRX_NOP_CMDS : Assigning value 0x05 (idx=1) from 75/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TAAD : Assigning value 0x08 (idx=1) from 79/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD : Assigning value 0x08 (idx=1) from 95/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_DLR : Assigning value 0x00 (idx=1) from 106/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_CS_LOW : Assigning value 0x04 (idx=1) from 287/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_HOLD : Assigning value 0x03 (idx=1) from 299/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_SETUP : Assigning value 0x03 (idx=1) from 913/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPRR : Assigning value 0x00 (idx=1) from 917/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRR : Assigning value 0x08 (idx=1) from 335/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD1 : Assigning value 0x00 (idx=1) from 351/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRROD2 : Assigning value 0x00 (idx=1) from 357/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_INTERVAL : Assigning value 0x000005 (idx=1) from 552/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 592/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDITIVE_LAT_F2 : Assigning value 0x00 (idx=1) from 0/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CASLAT_LIN_F2 : Assigning value 0x2c (idx=1) from 7/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_PARITY_LAT_F2 : Assigning value 0x00 (idx=1) from 15/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRE_F2 : Assigning value 0x06 (idx=1) from 19/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CKSRX_F2 : Assigning value 0x03 (idx=1) from 27/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NWR_F2 : Assigning value 0x14 (idx=1) from 35/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_PREAMBLE_LEN_F2 : Assigning value 0x01 (idx=1) from 67/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCACSH_F2 : Assigning value 0x02 (idx=1) from 87/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCDMW_F2 : Assigning value 0x20 (idx=1) from 100/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_F2 : Assigning value 0x00 (idx=1) from 111/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR2_F2 : Assigning value 0x00 (idx=1) from 116/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCCD_L_WR_F2 : Assigning value 0x20 (idx=1) from 123/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKCKEL_F2 : Assigning value 0x06 (idx=1) from 130/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCMD_F2 : Assigning value 0x09 (idx=1) from 135/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKEHCS_F2 : Assigning value 0x09 (idx=1) from 140/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCMD_F2 : Assigning value 0x06 (idx=1) from 145/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELCS_F2 : Assigning value 0x06 (idx=1) from 150/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKELPD_F2 : Assigning value 0x09 (idx=1) from 155/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKESR_F2 : Assigning value 0x09 (idx=1) from 163/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKE_F2 : Assigning value 0x09 (idx=1) from 171/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCKSTAB_F2 : Assigning value 0x0000 (idx=1) from 179/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCMDCKE_F2 : Assigning value 0x03 (idx=1) from 195/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCPDED_F2 : Assigning value 0x00 (idx=1) from 203/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKEH_F2 : Assigning value 0x02 (idx=1) from 211/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSCKE_F2 : Assigning value 0x02 (idx=1) from 216/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSH_F2 : Assigning value 0x03 (idx=1) from 221/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TCSSR_F2 : Assigning value 0x1e (idx=1) from 229/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDAL_F2 : Assigning value 0x29 (idx=1) from 237/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TESCKE_F2 : Assigning value 0x03 (idx=1) from 245/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_DLR_F2 : Assigning value 0x0000 (idx=1) from 253/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TFAW_F2 : Assigning value 0x002b (idx=1) from 262/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_F2 : Assigning value 0x0f (idx=1) from 271/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMOD_PAR_F2 : Assigning value 0x00 (idx=1) from 279/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMPC_DELAY_F2 : Assigning value 0x0b (idx=1) from 291/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_F2 : Assigning value 0x000b (idx=1) from 303/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRD_PAR_F2 : Assigning value 0x0000 (idx=1) from 319/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRRI_F2 : Assigning value 0x17 (idx=1) from 343/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TMRWCKEL_F2 : Assigning value 0x0f (idx=1) from 363/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSCO_F2 : Assigning value 0x00 (idx=1) from 371/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TOSC_TRK_CALC_F2 : Assigning value 0x0000 (idx=1) from 379/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPDEX_F2 : Assigning value 0x0009 (idx=1) from 467/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPPD_F2 : Assigning value 0x04 (idx=1) from 483/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MAX_F2 : Assigning value 0x00d903 (idx=1) from 486/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_MIN_F2 : Assigning value 0x002d (idx=1) from 506/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRCD_F2 : Assigning value 0x14 (idx=1) from 515/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRC_F2 : Assigning value 0x0041 (idx=1) from 523/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_F2 : Assigning value 0x001042 (idx=1) from 532/20/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_DLR_F2 : Assigning value 0x0060 (idx=1) from 572/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_F2 : Assigning value 0x00c1 (idx=1) from 582/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_DLR_F2 : Assigning value 0x0000 (idx=1) from 667/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_F2 : Assigning value 0x0000 (idx=1) from 677/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_F2 : Assigning value 0x14 (idx=1) from 743/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_DLR_F2 : Assigning value 0x00 (idx=1) from 751/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_F2 : Assigning value 0x0b (idx=1) from 759/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRRD_L_F2 : Assigning value 0x00 (idx=1) from 767/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_AP_F2 : Assigning value 0x00 (idx=1) from 775/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRTP_F2 : Assigning value 0x09 (idx=1) from 783/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TSR_F2 : Assigning value 0x11 (idx=1) from 791/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWR_F2 : Assigning value 0x15 (idx=1) from 799/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_AP_F2 : Assigning value 0x000c (idx=1) from 807/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_F2 : Assigning value 0x0c (idx=1) from 816/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_AP_F2 : Assigning value 0x0000 (idx=1) from 823/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TWTR_L_F2 : Assigning value 0x00 (idx=1) from 832/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSNR_F2 : Assigning value 0x00c9 (idx=1) from 839/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TXSR_F2 : Assigning value 0x00c9 (idx=1) from 855/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCAL_F2 : Assigning value 0x042c (idx=1) from 871/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQCKE_F2 : Assigning value 0x03 (idx=1) from 883/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TZQLAT_F2 : Assigning value 0x21 (idx=1) from 891/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRLAT_F2 : Assigning value 0x12 (idx=1) from 898/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_PREAMBLE_LEN_F2 : Assigning value 0x01 (idx=1) from 905/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F2_0 : Assigning value 0x10 (idx=1) from 395/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F2_0 : Assigning value 0x0b (idx=1) from 411/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F2_0 : Assigning value 0x0000 (idx=1) from 427/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F2_0 : Assigning value 0x0061 (idx=1) from 447/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F2_0 : Assigning value 0x0000 (idx=1) from 595/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F2_0 : Assigning value 0x0061 (idx=1) from 615/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F2_0 : Assigning value 0x00 (idx=1) from 635/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F2_0 : Assigning value 0x00 (idx=1) from 651/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F2_0 : Assigning value 0x0000 (idx=1) from 687/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F2_0 : Assigning value 0x0000 (idx=1) from 707/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F2_0 : Assigning value 0x17 (idx=1) from 727/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_DLR_F2_1 : Assigning value 0x10 (idx=1) from 403/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2ACT_F2_1 : Assigning value 0x0b (idx=1) from 419/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_DLR_F2_1 : Assigning value 0x0000 (idx=1) from 437/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TPBR2PBR_F2_1 : Assigning value 0x0061 (idx=1) from 457/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_DLR_F2_1 : Assigning value 0x0000 (idx=1) from 605/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFC_PB_F2_1 : Assigning value 0x0061 (idx=1) from 625/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_DLR_F2_1 : Assigning value 0x00 (idx=1) from 643/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM2ACT_F2_1 : Assigning value 0x00 (idx=1) from 659/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_DLR_F2_1 : Assigning value 0x0000 (idx=1) from 697/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRFM_SB_F2_1 : Assigning value 0x0000 (idx=1) from 717/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRP_AB_F2_1 : Assigning value 0x17 (idx=1) from 735/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110000000100100100100001000000110100001011000000000011001001000000001100100100000000000000000001100000001100000101010001000100001001000000000000000000001011000000000001010000010111000101110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000011000010001100001000000000000000000000110011000001000110000000000000000000000101000000010000010000100010000010001010000010110100001101100100000011100000000000000100100011000010001100001000000000000000000000000101100001011000100000001000000000000000000000000000000001111000000000000000101110000100000000000000000000000000000001011001100001011010000000000000011110001010110000000000000001100101001000111100000001100010000100000000000000011000000000000000000001001000010010000100100110001100100101001001100100000000000000000000001000000100000000010000010000101000000010000100000000000000100000001010000000011000001100000001011000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000060249081a160064806480000c060a8884800005800a0b8b800000000000000000000000c230800003304600000501042208a0b43640e00048c2308000005858808000000078000b8400000005985a00078ac0006523c06210001800004848498c94990000020401042808400080a018301600</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_INVERSION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_MIRRORING = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_3DS_PIN_MUXING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_CID0_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEM_DP_REDUCTION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_DBI_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCK_GROUP = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_DBI_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS0 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS0 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS0 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS1 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS1 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS1 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_DEFAULT_VAL_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_INVERSION : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_MIRRORING : Assigning value 0x00 (idx=1) from 16/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP : Assigning value 0x01 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_0 : Assigning value 0x03 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_3DS_PIN_MUXING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_CID0_MAP : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEM_DP_REDUCTION : Assigning value 0x00 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_0 : Assigning value 0x01 (idx=1) from 42/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 44/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_DBI_EN : Assigning value 0x01 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCK_GROUP : Assigning value 0x02 (idx=1) from 12/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_DBI_EN : Assigning value 0x00 (idx=1) from 11/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS0 : Assigning value 0x0001 (idx=1) from 46/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS0 : Assigning value 0x0004 (idx=1) from 64/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS0 : Assigning value 0x0010 (idx=1) from 82/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 100/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 118/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 136/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 154/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 172/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 190/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_0 : Assigning value 0x01 (idx=1) from 18/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS0 : Assigning value 0x00 (idx=1) from 24/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS0 : Assigning value 0x00 (idx=1) from 40/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS1 : Assigning value 0x0001 (idx=1) from 55/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS1 : Assigning value 0x0004 (idx=1) from 73/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS1 : Assigning value 0x0010 (idx=1) from 91/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 109/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 127/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 145/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 163/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 181/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 199/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_1 : Assigning value 0x01 (idx=1) from 21/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS1 : Assigning value 0x00 (idx=1) from 32/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS1 : Assigning value 0x00 (idx=1) from 41/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_DEFAULT_VAL_F0 : Assigning value 0x00 (idx=1) from 208/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000001000000001000000000010000000010001000000000000000000001001000010010000001101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080400804008044000024240d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_INVERSION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_MIRRORING = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_3DS_PIN_MUXING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_CID0_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEM_DP_REDUCTION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_DBI_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCK_GROUP = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_DBI_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS0 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS0 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS0 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS1 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS1 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS1 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_DEFAULT_VAL_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_INVERSION : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_MIRRORING : Assigning value 0x00 (idx=1) from 16/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP : Assigning value 0x01 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_0 : Assigning value 0x03 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_3DS_PIN_MUXING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_CID0_MAP : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEM_DP_REDUCTION : Assigning value 0x00 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_0 : Assigning value 0x01 (idx=1) from 42/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 44/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_DBI_EN : Assigning value 0x01 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCK_GROUP : Assigning value 0x02 (idx=1) from 12/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_DBI_EN : Assigning value 0x00 (idx=1) from 11/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS0 : Assigning value 0x0001 (idx=1) from 46/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS0 : Assigning value 0x0004 (idx=1) from 64/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS0 : Assigning value 0x0010 (idx=1) from 82/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 100/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 118/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 136/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 154/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 172/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 190/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_0 : Assigning value 0x01 (idx=1) from 18/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS0 : Assigning value 0x00 (idx=1) from 24/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS0 : Assigning value 0x00 (idx=1) from 40/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS1 : Assigning value 0x0001 (idx=1) from 55/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS1 : Assigning value 0x0004 (idx=1) from 73/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS1 : Assigning value 0x0010 (idx=1) from 91/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 109/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 127/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 145/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 163/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 181/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 199/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_1 : Assigning value 0x01 (idx=1) from 21/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS1 : Assigning value 0x00 (idx=1) from 32/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS1 : Assigning value 0x00 (idx=1) from 41/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_DEFAULT_VAL_F1 : Assigning value 0x00 (idx=1) from 208/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000001000000001000000000010000000010001000000000000000000001001000010010000001101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080400804008044000024240d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_INVERSION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDRESS_MIRRORING = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_3DS_PIN_MUXING_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DDR4_DIMM_CID0_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEM_DP_REDUCTION = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RANK0_MAP_DIMM_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_DBI_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCK_GROUP = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_DBI_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS0 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS0 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS0 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE0_BYTE0_CS1 = 0x0001</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE1_BYTE0_CS1 = 0x0004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE2_BYTE0_CS1 = 0x0010</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE3_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE4_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE5_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE6_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE7_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DEVICE8_BYTE0_CS1 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEMDATA_RATIO_1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PDA_INVERT_ECC_DEV_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CA_DEFAULT_VAL_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_INVERSION : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDRESS_MIRRORING : Assigning value 0x00 (idx=1) from 16/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP : Assigning value 0x01 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_0 : Assigning value 0x03 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_3DS_PIN_MUXING_EN : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DDR4_DIMM_CID0_MAP : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEM_DP_REDUCTION : Assigning value 0x00 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_0 : Assigning value 0x01 (idx=1) from 42/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RANK0_MAP_DIMM_1 : Assigning value 0x00 (idx=1) from 44/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_DBI_EN : Assigning value 0x01 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCK_GROUP : Assigning value 0x02 (idx=1) from 12/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_DBI_EN : Assigning value 0x00 (idx=1) from 11/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS0 : Assigning value 0x0001 (idx=1) from 46/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS0 : Assigning value 0x0004 (idx=1) from 64/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS0 : Assigning value 0x0010 (idx=1) from 82/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 100/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 118/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 136/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 154/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 172/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS0 : Assigning value 0x0000 (idx=1) from 190/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_0 : Assigning value 0x01 (idx=1) from 18/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS0 : Assigning value 0x00 (idx=1) from 24/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS0 : Assigning value 0x00 (idx=1) from 40/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE0_BYTE0_CS1 : Assigning value 0x0001 (idx=1) from 55/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE1_BYTE0_CS1 : Assigning value 0x0004 (idx=1) from 73/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE2_BYTE0_CS1 : Assigning value 0x0010 (idx=1) from 91/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE3_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 109/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE4_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 127/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE5_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 145/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE6_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 163/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE7_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 181/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DEVICE8_BYTE0_CS1 : Assigning value 0x0000 (idx=1) from 199/9/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEMDATA_RATIO_1 : Assigning value 0x01 (idx=1) from 21/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_DEV_CS1 : Assigning value 0x00 (idx=1) from 32/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PDA_INVERT_ECC_DEV_CS1 : Assigning value 0x00 (idx=1) from 41/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CA_DEFAULT_VAL_F2 : Assigning value 0x00 (idx=1) from 208/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000100000000100000000001000000001000000000010000000010001000000000000000000001001000010010000001101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080400804008044000024240d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DLL_RST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR23_DATA = 0x000020</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR37_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKI_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F0_0 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F0_0 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F0_0 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F0_0 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F0_0 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F0_0 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F0_0 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F0_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F0_1 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F0_1 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F0_1 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F0_1 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F0_1 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F0_1 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F0_1 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F0_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DLL_RST : Assigning value 0x00 (idx=1) from 180/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR23_DATA : Assigning value 0x000020 (idx=1) from 649/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR37_DATA : Assigning value 0x000000 (idx=1) from 775/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKI_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 793/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 811/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 826/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 0/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F0_0 : Assigning value 0x0000b4 (idx=1) from 36/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F0_0 : Assigning value 0x00005b (idx=1) from 72/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F0_0 : Assigning value 0x000073 (idx=1) from 108/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 144/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 181/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 217/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 253/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F0_0 : Assigning value 0x000035 (idx=1) from 289/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F0_0 : Assigning value 0x00004d (idx=1) from 325/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_0 : Assigning value 0x000000 (idx=1) from 361/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F0_0 : Assigning value 0x000014 (idx=1) from 397/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_0 : Assigning value 0x000000 (idx=1) from 433/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 469/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 505/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 541/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 577/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F0_0 : Assigning value 0x000018 (idx=1) from 613/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 667/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 703/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F0_0 : Assigning value 0x000000 (idx=1) from 739/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 18/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F0_1 : Assigning value 0x0000b4 (idx=1) from 54/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F0_1 : Assigning value 0x00005b (idx=1) from 90/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F0_1 : Assigning value 0x000073 (idx=1) from 126/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 162/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 199/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 235/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 271/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F0_1 : Assigning value 0x000035 (idx=1) from 307/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F0_1 : Assigning value 0x00004d (idx=1) from 343/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_1 : Assigning value 0x000000 (idx=1) from 379/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F0_1 : Assigning value 0x000014 (idx=1) from 415/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_1 : Assigning value 0x000000 (idx=1) from 451/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 487/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 523/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 559/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 595/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F0_1 : Assigning value 0x000018 (idx=1) from 631/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 685/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 721/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F0_1 : Assigning value 0x000000 (idx=1) from 757/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000110000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000000101000000000000000000000000000000000000000000000000010011010000000000010011010000000000001101010000000000001101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110011000000000001110011000000000001011011000000000001011011000000000010110100000000000010110100000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000040000c00030000000000000000000000000000000000000000000000000a0002800000000000268009a001a8006a000000000000000000000000000000000000001cc00730016c005b002d000b4000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DLL_RST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR23_DATA = 0x000020</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR37_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKI_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F1_0 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F1_0 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F1_0 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F1_0 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F1_0 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F1_0 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F1_0 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F1_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F1_1 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F1_1 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F1_1 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F1_1 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F1_1 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F1_1 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F1_1 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F1_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DLL_RST : Assigning value 0x00 (idx=1) from 180/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR23_DATA : Assigning value 0x000020 (idx=1) from 649/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR37_DATA : Assigning value 0x000000 (idx=1) from 775/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKI_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 793/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 811/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 826/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 0/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F1_0 : Assigning value 0x0000b4 (idx=1) from 36/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F1_0 : Assigning value 0x00005b (idx=1) from 72/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F1_0 : Assigning value 0x000073 (idx=1) from 108/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 144/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 181/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 217/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 253/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F1_0 : Assigning value 0x000035 (idx=1) from 289/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F1_0 : Assigning value 0x00004d (idx=1) from 325/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_0 : Assigning value 0x000000 (idx=1) from 361/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F1_0 : Assigning value 0x000014 (idx=1) from 397/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_0 : Assigning value 0x000000 (idx=1) from 433/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 469/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 505/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 541/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 577/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F1_0 : Assigning value 0x000018 (idx=1) from 613/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 667/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 703/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F1_0 : Assigning value 0x000000 (idx=1) from 739/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 18/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F1_1 : Assigning value 0x0000b4 (idx=1) from 54/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F1_1 : Assigning value 0x00005b (idx=1) from 90/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F1_1 : Assigning value 0x000073 (idx=1) from 126/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 162/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 199/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 235/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 271/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F1_1 : Assigning value 0x000035 (idx=1) from 307/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F1_1 : Assigning value 0x00004d (idx=1) from 343/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_1 : Assigning value 0x000000 (idx=1) from 379/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F1_1 : Assigning value 0x000014 (idx=1) from 415/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_1 : Assigning value 0x000000 (idx=1) from 451/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 487/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 523/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 559/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 595/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F1_1 : Assigning value 0x000018 (idx=1) from 631/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 685/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 721/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F1_1 : Assigning value 0x000000 (idx=1) from 757/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000110000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000000101000000000000000000000000000000000000000000000000010011010000000000010011010000000000001101010000000000001101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110011000000000001110011000000000001011011000000000001011011000000000010110100000000000010110100000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000040000c00030000000000000000000000000000000000000000000000000a0002800000000000268009a001a8006a000000000000000000000000000000000000001cc00730016c005b002d000b4000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DLL_RST = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR23_DATA = 0x000020</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR37_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKI_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_PERIOD = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WCKO_OSC_TIMER_DATA = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F2_0 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F2_0 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F2_0 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F2_0 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F2_0 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F2_0 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F2_0 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F2_0 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR0_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR1_DATA_F2_1 = 0x0000b4</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR2_DATA_F2_1 = 0x00005b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR3_DATA_F2_1 = 0x000073</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR4_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR5_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR6_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR10_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR11_DATA_F2_1 = 0x000035</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR12_DATA_F2_1 = 0x00004d</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR13_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR14_DATA_F2_1 = 0x000014</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR16_DATA_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR17_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR18_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR19_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR20_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR22_DATA_F2_1 = 0x000018</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR33_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR34_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MR35_DATA_F2_1 = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DLL_RST : Assigning value 0x00 (idx=1) from 180/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR23_DATA : Assigning value 0x000020 (idx=1) from 649/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR37_DATA : Assigning value 0x000000 (idx=1) from 775/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKI_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 793/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_PERIOD : Assigning value 0x0200 (idx=1) from 811/15/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WCKO_OSC_TIMER_DATA : Assigning value 0x000000 (idx=1) from 826/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 0/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F2_0 : Assigning value 0x0000b4 (idx=1) from 36/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F2_0 : Assigning value 0x00005b (idx=1) from 72/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F2_0 : Assigning value 0x000073 (idx=1) from 108/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 144/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 181/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 217/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 253/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F2_0 : Assigning value 0x000035 (idx=1) from 289/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F2_0 : Assigning value 0x00004d (idx=1) from 325/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_0 : Assigning value 0x000000 (idx=1) from 361/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F2_0 : Assigning value 0x000014 (idx=1) from 397/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_0 : Assigning value 0x000000 (idx=1) from 433/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 469/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 505/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 541/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 577/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F2_0 : Assigning value 0x000018 (idx=1) from 613/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 667/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 703/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F2_0 : Assigning value 0x000000 (idx=1) from 739/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR0_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 18/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR1_DATA_F2_1 : Assigning value 0x0000b4 (idx=1) from 54/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR2_DATA_F2_1 : Assigning value 0x00005b (idx=1) from 90/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR3_DATA_F2_1 : Assigning value 0x000073 (idx=1) from 126/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR4_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 162/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR5_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 199/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR6_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 235/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR10_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 271/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR11_DATA_F2_1 : Assigning value 0x000035 (idx=1) from 307/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR12_DATA_F2_1 : Assigning value 0x00004d (idx=1) from 343/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR13_DATA_1 : Assigning value 0x000000 (idx=1) from 379/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR14_DATA_F2_1 : Assigning value 0x000014 (idx=1) from 415/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR16_DATA_1 : Assigning value 0x000000 (idx=1) from 451/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR17_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 487/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR18_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 523/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR19_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 559/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR20_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 595/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR22_DATA_F2_1 : Assigning value 0x000018 (idx=1) from 631/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR33_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 685/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR34_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 721/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MR35_DATA_F2_1 : Assigning value 0x000000 (idx=1) from 757/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000000000000000000110000000000000000110000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000101000000000000000101000000000000000000000000000000000000000000000000010011010000000000010011010000000000001101010000000000001101010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001110011000000000001110011000000000001011011000000000001011011000000000010110100000000000010110100000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000010000000000000000000000000000000000000000040000c00030000000000000000000000000000000000000000000000000a0002800000000000268009a001a8006a000000000000000000000000000000000000001cc00730016c005b002d000b4000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key APREBIT = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BURST_ON_FLY_BIT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DRAM_CLASS = 0x0b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LOGICAL_CS_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key LRDIMM_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MDQS_MULT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key MEM_3DS_SUPPORT_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NO_MEMORY_DM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key REG_DIMM_ENABLE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_DIFF_0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BG_DIFF_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CID_DIFF_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key COL_DIFF_0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ROW_DIFF_0 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_DIFF_1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BG_DIFF_1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CID_DIFF_1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key COL_DIFF_1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ROW_DIFF_1 = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.APREBIT : Assigning value 0x0b (idx=1) from 10/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BURST_ON_FLY_BIT : Assigning value 0x00 (idx=1) from 15/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.DRAM_CLASS is {} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LOGICAL_CS_MAP : Assigning value 0x00 (idx=1) from 0/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.LRDIMM_ENABLE : Assigning value 0x00 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MDQS_MULT : Assigning value 0x01 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.MEM_3DS_SUPPORT_EN : Assigning value 0x00 (idx=1) from 6/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NO_MEMORY_DM : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.REG_DIMM_ENABLE : Assigning value 0x00 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_DIFF_0 : Assigning value 0x02 (idx=1) from 25/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BG_DIFF_0 : Assigning value 0x03 (idx=1) from 29/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CID_DIFF_0 : Assigning value 0x01 (idx=1) from 41/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.COL_DIFF_0 : Assigning value 0x01 (idx=1) from 33/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ROW_DIFF_0 : Assigning value 0x03 (idx=1) from 19/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_DIFF_1 : Assigning value 0x02 (idx=1) from 27/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BG_DIFF_1 : Assigning value 0x03 (idx=1) from 31/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CID_DIFF_1 : Assigning value 0x01 (idx=1) from 42/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.COL_DIFF_1 : Assigning value 0x01 (idx=1) from 37/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ROW_DIFF_1 : Assigning value 0x03 (idx=1) from 22/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx1100010001111110100110110000010110000010000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000623f4d82c10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CA_PARITY_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_HOLD_CKE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_MAP = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRC = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_DFS_CW_MAP_F0 = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TSTAB_F0 = 0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F0_0 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F0_1 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CA_PARITY_EN : Assigning value 0x00 (idx=1) from 28/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_HOLD_CKE_EN : Assigning value 0x00 (idx=1) from 27/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_MAP : Assigning value 0x00000000 (idx=1) from 0/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRC : Assigning value 0x10 (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD : Assigning value 0x000b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L : Assigning value 0x10 (idx=1) from 50/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L2 : Assigning value 0x20 (idx=1) from 55/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_DFS_CW_MAP_F0 : Assigning value 0x00000000 (idx=1) from 389/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TSTAB_F0 : Assigning value 0x001904 (idx=1) from 365/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F0_0 is {RDIMM_CTL_F0_0_0 RDIMM_CTL_F0_0_1 RDIMM_CTL_F0_0_2 RDIMM_CTL_F0_0_3 RDIMM_CTL_F0_0_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 61/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 93/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 125/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 157/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 189/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F0_1 is {RDIMM_CTL_F0_1_0 RDIMM_CTL_F0_1_1 RDIMM_CTL_F0_1_2 RDIMM_CTL_F0_1_3 RDIMM_CTL_F0_1_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 213/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 245/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 277/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 309/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F0_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 341/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000110010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001000000000000000010111000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000032080000000000000000000000000000000000000000000000000000000000000000000000000001040002e00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CA_PARITY_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_HOLD_CKE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_MAP = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRC = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_DFS_CW_MAP_F1 = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TSTAB_F1 = 0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F1_0 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F1_1 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CA_PARITY_EN : Assigning value 0x00 (idx=1) from 28/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_HOLD_CKE_EN : Assigning value 0x00 (idx=1) from 27/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_MAP : Assigning value 0x00000000 (idx=1) from 0/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRC : Assigning value 0x10 (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD : Assigning value 0x000b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L : Assigning value 0x10 (idx=1) from 50/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L2 : Assigning value 0x20 (idx=1) from 55/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_DFS_CW_MAP_F1 : Assigning value 0x00000000 (idx=1) from 389/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TSTAB_F1 : Assigning value 0x001904 (idx=1) from 365/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F1_0 is {RDIMM_CTL_F1_0_0 RDIMM_CTL_F1_0_1 RDIMM_CTL_F1_0_2 RDIMM_CTL_F1_0_3 RDIMM_CTL_F1_0_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 61/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 93/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 125/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 157/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 189/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F1_1 is {RDIMM_CTL_F1_1_0 RDIMM_CTL_F1_1_1 RDIMM_CTL_F1_1_2 RDIMM_CTL_F1_1_3 RDIMM_CTL_F1_1_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 213/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 245/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 277/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 309/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F1_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 341/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000110010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001000000000000000010111000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000032080000000000000000000000000000000000000000000000000000000000000000000000000001040002e00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CA_PARITY_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_HOLD_CKE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CW_MAP = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRC = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD = 0x000b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TMRD_L2 = 0x20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_DFS_CW_MAP_F2 = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_TSTAB_F2 = 0x001904</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F2_0 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RDIMM_CTL_F2_1 = 0x00000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CA_PARITY_EN : Assigning value 0x00 (idx=1) from 28/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_HOLD_CKE_EN : Assigning value 0x00 (idx=1) from 27/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CW_MAP : Assigning value 0x00000000 (idx=1) from 0/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRC : Assigning value 0x10 (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD : Assigning value 0x000b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L : Assigning value 0x10 (idx=1) from 50/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TMRD_L2 : Assigning value 0x20 (idx=1) from 55/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_DFS_CW_MAP_F2 : Assigning value 0x00000000 (idx=1) from 389/27/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_TSTAB_F2 : Assigning value 0x001904 (idx=1) from 365/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F2_0 is {RDIMM_CTL_F2_0_0 RDIMM_CTL_F2_0_1 RDIMM_CTL_F2_0_2 RDIMM_CTL_F2_0_3 RDIMM_CTL_F2_0_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 61/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 93/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 125/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 157/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_0 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 189/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.RDIMM_CTL_F2_1 is {RDIMM_CTL_F2_1_0 RDIMM_CTL_F2_1_1 RDIMM_CTL_F2_1_2 RDIMM_CTL_F2_1_3 RDIMM_CTL_F2_1_4} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=1) from 213/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=4294967296) from 245/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=18446744073709551616) from 277/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 309/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RDIMM_CTL_F2_1 : Assigning value 0x00000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 341/24/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000000000000110010000010000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001000001000000000000000010111000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000032080000000000000000000000000000000000000000000000000000000000000000000000000001040002e00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Miscellaneous Parameter Configuration = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx10;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Miscellaneous Parameter Configuration = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000002</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_CMP_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_COLLISION_MPM_DIS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BG_ROTATE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BSTLEN = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CMD_BLK_SPLIT_SIZE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key COMMAND_AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CONCURRENTAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_MEMORY_MASKED_WRITE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RD_INTERLEAVE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RW_GROUP_W_BNK_CONFLICT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INHIBIT_DRAM_CMD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key IN_ORDER_ACCEPT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NUM_Q_ENTRIES_ACT_DISABLE = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OPTIMAL_RMODW_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PLACEMENT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRIORITY_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key Q_FULLNESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_PAGE_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SWAP_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_LOCKOUT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITEINTERP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_ORDER_REQ = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_ARCH_MODE_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_CMP_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_COLLISION_MPM_DIS : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AGE_COUNT : Assigning value 0xff (idx=1) from 2/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AP : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_SPLIT_EN : Assigning value 0x01 (idx=1) from 13/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BG_ROTATE_EN : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BSTLEN : Assigning value 0x04 (idx=1) from 16/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CMD_BLK_SPLIT_SIZE : Assigning value 0x00 (idx=1) from 22/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.COMMAND_AGE_COUNT : Assigning value 0xff (idx=1) from 23/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CONCURRENTAP : Assigning value 0x01 (idx=1) from 31/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_SAME_EN : Assigning value 0x01 (idx=1) from 32/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_MEMORY_MASKED_WRITE : Assigning value 0x00 (idx=1) from 33/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RD_INTERLEAVE : Assigning value 0x01 (idx=1) from 34/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RW_GROUP_W_BNK_CONFLICT : Assigning value 0x01 (idx=1) from 35/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INHIBIT_DRAM_CMD : Assigning value 0x00 (idx=1) from 37/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.IN_ORDER_ACCEPT : Assigning value 0x00 (idx=1) from 39/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NUM_Q_ENTRIES_ACT_DISABLE : Assigning value 0x10 (idx=1) from 40/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OPTIMAL_RMODW_EN : Assigning value 0x01 (idx=1) from 45/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PLACEMENT_EN : Assigning value 0x01 (idx=1) from 46/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRIORITY_EN : Assigning value 0x01 (idx=1) from 47/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.Q_FULLNESS : Assigning value 0x00 (idx=1) from 48/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_EN : Assigning value 0x01 (idx=1) from 53/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_PAGE_EN : Assigning value 0x01 (idx=1) from 54/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SWAP_EN : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_LOCKOUT : Assigning value 0x01 (idx=1) from 56/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SPLIT_EN : Assigning value 0x01 (idx=1) from 57/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITEINTERP : Assigning value 0x00 (idx=1) from 58/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_ORDER_REQ : Assigning value 0x00 (idx=1) from 59/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_ARCH_MODE_F0 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0001101100000111100000000110111111111100001000010001111111101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360f00dff8423fd</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_CMP_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_COLLISION_MPM_DIS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BG_ROTATE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BSTLEN = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CMD_BLK_SPLIT_SIZE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key COMMAND_AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CONCURRENTAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_MEMORY_MASKED_WRITE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RD_INTERLEAVE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RW_GROUP_W_BNK_CONFLICT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INHIBIT_DRAM_CMD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key IN_ORDER_ACCEPT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NUM_Q_ENTRIES_ACT_DISABLE = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OPTIMAL_RMODW_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PLACEMENT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRIORITY_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key Q_FULLNESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_PAGE_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SWAP_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_LOCKOUT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITEINTERP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_ORDER_REQ = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_ARCH_MODE_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_CMP_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_COLLISION_MPM_DIS : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AGE_COUNT : Assigning value 0xff (idx=1) from 2/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AP : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_SPLIT_EN : Assigning value 0x01 (idx=1) from 13/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BG_ROTATE_EN : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BSTLEN : Assigning value 0x04 (idx=1) from 16/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CMD_BLK_SPLIT_SIZE : Assigning value 0x00 (idx=1) from 22/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.COMMAND_AGE_COUNT : Assigning value 0xff (idx=1) from 23/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CONCURRENTAP : Assigning value 0x01 (idx=1) from 31/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_SAME_EN : Assigning value 0x01 (idx=1) from 32/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_MEMORY_MASKED_WRITE : Assigning value 0x00 (idx=1) from 33/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RD_INTERLEAVE : Assigning value 0x01 (idx=1) from 34/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RW_GROUP_W_BNK_CONFLICT : Assigning value 0x01 (idx=1) from 35/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INHIBIT_DRAM_CMD : Assigning value 0x00 (idx=1) from 37/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.IN_ORDER_ACCEPT : Assigning value 0x00 (idx=1) from 39/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NUM_Q_ENTRIES_ACT_DISABLE : Assigning value 0x10 (idx=1) from 40/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OPTIMAL_RMODW_EN : Assigning value 0x01 (idx=1) from 45/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PLACEMENT_EN : Assigning value 0x01 (idx=1) from 46/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRIORITY_EN : Assigning value 0x01 (idx=1) from 47/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.Q_FULLNESS : Assigning value 0x00 (idx=1) from 48/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_EN : Assigning value 0x01 (idx=1) from 53/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_PAGE_EN : Assigning value 0x01 (idx=1) from 54/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SWAP_EN : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_LOCKOUT : Assigning value 0x01 (idx=1) from 56/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SPLIT_EN : Assigning value 0x01 (idx=1) from 57/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITEINTERP : Assigning value 0x00 (idx=1) from 58/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_ORDER_REQ : Assigning value 0x00 (idx=1) from 59/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_ARCH_MODE_F1 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0001101100000111100000000110111111111100001000010001111111101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360f00dff8423fd</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_CMP_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ADDR_COLLISION_MPM_DIS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BG_ROTATE_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BSTLEN = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CMD_BLK_SPLIT_SIZE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key COMMAND_AGE_COUNT = 0xff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CONCURRENTAP = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_MEMORY_MASKED_WRITE = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RD_INTERLEAVE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DISABLE_RW_GROUP_W_BNK_CONFLICT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key INHIBIT_DRAM_CMD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key IN_ORDER_ACCEPT = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key NUM_Q_ENTRIES_ACT_DISABLE = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key OPTIMAL_RMODW_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PLACEMENT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PRIORITY_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key Q_FULLNESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW_SAME_PAGE_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SWAP_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TRAS_LOCKOUT = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SPLIT_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WRITEINTERP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_ORDER_REQ = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key BANK_ARCH_MODE_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_CMP_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ADDR_COLLISION_MPM_DIS : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AGE_COUNT : Assigning value 0xff (idx=1) from 2/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AP : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_SPLIT_EN : Assigning value 0x01 (idx=1) from 13/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BG_ROTATE_EN : Assigning value 0x00 (idx=1) from 14/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BSTLEN : Assigning value 0x04 (idx=1) from 16/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CMD_BLK_SPLIT_SIZE : Assigning value 0x00 (idx=1) from 22/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.COMMAND_AGE_COUNT : Assigning value 0xff (idx=1) from 23/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CONCURRENTAP : Assigning value 0x01 (idx=1) from 31/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_SAME_EN : Assigning value 0x01 (idx=1) from 32/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_MEMORY_MASKED_WRITE : Assigning value 0x00 (idx=1) from 33/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RD_INTERLEAVE : Assigning value 0x01 (idx=1) from 34/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DISABLE_RW_GROUP_W_BNK_CONFLICT : Assigning value 0x01 (idx=1) from 35/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.INHIBIT_DRAM_CMD : Assigning value 0x00 (idx=1) from 37/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.IN_ORDER_ACCEPT : Assigning value 0x00 (idx=1) from 39/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.NUM_Q_ENTRIES_ACT_DISABLE : Assigning value 0x10 (idx=1) from 40/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.OPTIMAL_RMODW_EN : Assigning value 0x01 (idx=1) from 45/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PLACEMENT_EN : Assigning value 0x01 (idx=1) from 46/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PRIORITY_EN : Assigning value 0x01 (idx=1) from 47/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.Q_FULLNESS : Assigning value 0x00 (idx=1) from 48/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_EN : Assigning value 0x01 (idx=1) from 53/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW_SAME_PAGE_EN : Assigning value 0x01 (idx=1) from 54/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SWAP_EN : Assigning value 0x00 (idx=1) from 55/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TRAS_LOCKOUT : Assigning value 0x01 (idx=1) from 56/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SPLIT_EN : Assigning value 0x01 (idx=1) from 57/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WRITEINTERP : Assigning value 0x00 (idx=1) from 58/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_ORDER_REQ : Assigning value 0x00 (idx=1) from 59/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.BANK_ARCH_MODE_F2 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0001101100000111100000000110111111111100001000010001111111101;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000360f00dff8423fd</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DLL_RST_ADJ_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DLL_RST_DELAY = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DLL_RST_ADJ_DLY : Assigning value 0x00 (idx=1) from 16/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DLL_RST_DELAY : Assigning value 0x0000 (idx=1) from 0/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_BANK_ADDRESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_CID_ADDRESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_COMMAND_MRR_REGNUM = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_CONTROL = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_CS_ADDRESS = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_DATA = 0x0000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_ECC = 0x00000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PPR_ROW_ADDRESS = 0x000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_BANK_ADDRESS : Assigning value 0x00 (idx=1) from 10/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_CID_ADDRESS : Assigning value 0x00 (idx=1) from 15/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_COMMAND_MRR_REGNUM : Assigning value 0x00 (idx=1) from 2/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_CONTROL : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_CS_ADDRESS : Assigning value 0x00 (idx=1) from 1/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Aggregate list for base register HMC_REG.PPR_DATA is {PPR_DATA_0 PPR_DATA_1 PPR_DATA_2 PPR_DATA_3 PPR_DATA_4 PPR_DATA_5 PPR_DATA_6 PPR_DATA_7} - next_base=UNDEFINED</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=1) from 34/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=4294967296) from 66/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=18446744073709551616) from 98/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=79228162514264337593543950336) from 130/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=340282366920938463463374607431768211456) from 162/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=1461501637330902918203684832716283019655932542976) from 194/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=6277101735386680763835789423207666416102355444464034512896) from 226/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_DATA : Assigning value 0x0000000000000000000000000000000000000000000000000000000000000000 (idx=26959946667150639794667015087019630673637144422540572481103610249216) from 258/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_ECC : Assigning value 0x00000000 (idx=1) from 290/32/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PPR_ROW_ADDRESS : Assigning value 0x000000 (idx=1) from 16/18/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_CMD_MAX_PER_TREFI = 0x08</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_MAX_CREDIT = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_MAX_DEFICIT = 0x18</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key AREF_PBR_CONT_EN_THRESHOLD = 0x12</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_COMPARISON_FOR_REFRESH_DEPTH = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ENABLE_QUICK_SREFRESH = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PBR_CONT_REQ_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PBR_MODE_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PBR_NUMERIC_ORDER = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PHYMSTR_NO_AREF = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RAAIMT = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RAAMMT = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RAA_CNT_DECR_PER_REF = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key REF_RFM_PRIO = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RFM_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RFM_HIGH_THRESHOLD = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RFM_NORM_THRESHOLD = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RFM_SB_CONT_EN_THRESHOLD = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SELECT_BANK_IN_Q = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key SREFRESH_EXIT_NO_REFRESH = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TREF_ENABLE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_CMD_MAX_PER_TREFI : Assigning value 0x08 (idx=1) from 10/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_MAX_CREDIT : Assigning value 0x0c (idx=1) from 14/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_MAX_DEFICIT : Assigning value 0x18 (idx=1) from 19/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.AREF_PBR_CONT_EN_THRESHOLD : Assigning value 0x12 (idx=1) from 24/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_COMPARISON_FOR_REFRESH_DEPTH : Assigning value 0x10 (idx=1) from 1/6/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ENABLE_QUICK_SREFRESH : Assigning value 0x01 (idx=1) from 7/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PBR_CONT_REQ_EN : Assigning value 0x01 (idx=1) from 29/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PBR_MODE_EN : Assigning value 0x01 (idx=1) from 30/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PBR_NUMERIC_ORDER : Assigning value 0x00 (idx=1) from 34/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PHYMSTR_NO_AREF : Assigning value 0x00 (idx=1) from 35/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RAAIMT : Assigning value 0x0000 (idx=1) from 36/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RAAMMT : Assigning value 0x0000 (idx=1) from 46/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RAA_CNT_DECR_PER_REF : Assigning value 0x0000 (idx=1) from 56/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.REF_RFM_PRIO : Assigning value 0x01 (idx=1) from 67/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RFM_EN : Assigning value 0x00 (idx=1) from 66/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RFM_HIGH_THRESHOLD : Assigning value 0x0000 (idx=1) from 78/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RFM_NORM_THRESHOLD : Assigning value 0x0000 (idx=1) from 68/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RFM_SB_CONT_EN_THRESHOLD : Assigning value 0x0000 (idx=1) from 88/10/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SELECT_BANK_IN_Q : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.SREFRESH_EXIT_NO_REFRESH : Assigning value 0x00 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TREF_ENABLE : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000000000000000000000010000000000000000000000000000000000001110010110000110010000010100001;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000080000000072c320a1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_PHASE_2N = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POSTAMBLE_SUPPORT = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_1T_TIMING_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_DIFFCS_DLY_F0 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_DIFFCS_DLY_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_SAMECS_DLY_F0 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW2MRW_DLY_F0 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MAX_F0 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MIN_F0 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_DIFFCS_DLY_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_DIFFCS_DLY_F0 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_PHASE_2N : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POSTAMBLE_SUPPORT : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 3/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 8/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_SAMECS_DLY : Assigning value 0x00 (idx=1) from 13/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_1T_TIMING_F0 : Assigning value 0x00 (idx=1) from 18/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_DIFFCS_DLY_F0 : Assigning value 0x0c (idx=1) from 19/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_DIFFCS_DLY_F0 : Assigning value 0x0a (idx=1) from 24/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_SAMECS_DLY_F0 : Assigning value 0x0a (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW2MRW_DLY_F0 : Assigning value 0x09 (idx=1) from 34/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MAX_F0 : Assigning value 0x04 (idx=1) from 39/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MIN_F0 : Assigning value 0x02 (idx=1) from 43/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_DIFFCS_DLY_F0 : Assigning value 0x01 (idx=1) from 46/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_DIFFCS_DLY_F0 : Assigning value 0x0c (idx=1) from 51/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01100000010100100010010101001010011000000000000000000100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006052254a600004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_PHASE_2N = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POSTAMBLE_SUPPORT = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_1T_TIMING_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_DIFFCS_DLY_F1 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_DIFFCS_DLY_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_SAMECS_DLY_F1 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW2MRW_DLY_F1 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MAX_F1 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MIN_F1 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_DIFFCS_DLY_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_DIFFCS_DLY_F1 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_PHASE_2N : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POSTAMBLE_SUPPORT : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 3/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 8/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_SAMECS_DLY : Assigning value 0x00 (idx=1) from 13/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_1T_TIMING_F1 : Assigning value 0x00 (idx=1) from 18/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_DIFFCS_DLY_F1 : Assigning value 0x0c (idx=1) from 19/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_DIFFCS_DLY_F1 : Assigning value 0x0a (idx=1) from 24/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_SAMECS_DLY_F1 : Assigning value 0x0a (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW2MRW_DLY_F1 : Assigning value 0x09 (idx=1) from 34/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MAX_F1 : Assigning value 0x04 (idx=1) from 39/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MIN_F1 : Assigning value 0x02 (idx=1) from 43/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_DIFFCS_DLY_F1 : Assigning value 0x01 (idx=1) from 46/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_DIFFCS_DLY_F1 : Assigning value 0x0c (idx=1) from 51/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01100000010100100010010101001010011000000000000000000100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006052254a600004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_PHASE_2N = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key POSTAMBLE_SUPPORT = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_SAMECS_DLY = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_1T_TIMING_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2R_DIFFCS_DLY_F2 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_DIFFCS_DLY_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key R2W_SAMECS_DLY_F2 = 0x0a</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RW2MRW_DLY_F2 = 0x09</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MAX_F2 = 0x04</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TDQSCK_MIN_F2 = 0x02</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2R_DIFFCS_DLY_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key W2W_DIFFCS_DLY_F2 = 0x0c</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_PHASE_2N : Assigning value 0x00 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.POSTAMBLE_SUPPORT : Assigning value 0x02 (idx=1) from 1/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 3/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_SAMECS_DLY : Assigning value 0x00 (idx=1) from 8/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_SAMECS_DLY : Assigning value 0x00 (idx=1) from 13/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_1T_TIMING_F2 : Assigning value 0x00 (idx=1) from 18/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2R_DIFFCS_DLY_F2 : Assigning value 0x0c (idx=1) from 19/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_DIFFCS_DLY_F2 : Assigning value 0x0a (idx=1) from 24/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.R2W_SAMECS_DLY_F2 : Assigning value 0x0a (idx=1) from 29/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RW2MRW_DLY_F2 : Assigning value 0x09 (idx=1) from 34/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MAX_F2 : Assigning value 0x04 (idx=1) from 39/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TDQSCK_MIN_F2 : Assigning value 0x02 (idx=1) from 43/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2R_DIFFCS_DLY_F2 : Assigning value 0x01 (idx=1) from 46/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.W2W_DIFFCS_DLY_F2 : Assigning value 0x0c (idx=1) from 51/5/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01100000010100100010010101001010011000000000000000000100;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000006052254a600004</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_ODT_ASSERT_EXCEPT_RD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_VALUE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_EN_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PD_NT_ODT_EN_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_TO_ODTH_F0 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_RD_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_WR_F0 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTL_2CMD_F0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTUP_F0 = 0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_TO_ODTH_F0 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_ODT_ASSERT_EXCEPT_RD : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_VALUE : Assigning value 0x01 (idx=1) from 57/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS0 : Assigning value 0x00 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS0 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS1 : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS1 : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_EN_F0 : Assigning value 0x01 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PD_NT_ODT_EN_F0 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_TO_ODTH_F0 : Assigning value 0x15 (idx=1) from 11/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_RD_F0 : Assigning value 0x01 (idx=1) from 18/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_WR_F0 : Assigning value 0x01 (idx=1) from 22/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTL_2CMD_F0 : Assigning value 0x00 (idx=1) from 26/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTUP_F0 : Assigning value 0x010b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_TO_ODTH_F0 : Assigning value 0x10 (idx=1) from 50/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01001000000000001000010110000000000010001001010101000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000240042c0044aa00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_ODT_ASSERT_EXCEPT_RD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_VALUE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_EN_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PD_NT_ODT_EN_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_TO_ODTH_F1 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_RD_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_WR_F1 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTL_2CMD_F1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTUP_F1 = 0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_TO_ODTH_F1 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_ODT_ASSERT_EXCEPT_RD : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_VALUE : Assigning value 0x01 (idx=1) from 57/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS0 : Assigning value 0x00 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS0 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS1 : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS1 : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_EN_F1 : Assigning value 0x01 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PD_NT_ODT_EN_F1 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_TO_ODTH_F1 : Assigning value 0x15 (idx=1) from 11/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_RD_F1 : Assigning value 0x01 (idx=1) from 18/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_WR_F1 : Assigning value 0x01 (idx=1) from 22/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTL_2CMD_F1 : Assigning value 0x00 (idx=1) from 26/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTUP_F1 : Assigning value 0x010b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_TO_ODTH_F1 : Assigning value 0x10 (idx=1) from 50/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01001000000000001000010110000000000010001001010101000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000240042c0044aa00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key EN_ODT_ASSERT_EXCEPT_RD = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_VALUE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_RD_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_WR_MAP_CS1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ODT_EN_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PD_NT_ODT_EN_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key RD_TO_ODTH_F2 = 0x15</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_RD_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTH_WR_F2 = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTL_2CMD_F2 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key TODTUP_F2 = 0x010b</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key WR_TO_ODTH_F2 = 0x10</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.EN_ODT_ASSERT_EXCEPT_RD : Assigning value 0x00 (idx=1) from 8/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_VALUE : Assigning value 0x01 (idx=1) from 57/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS0 : Assigning value 0x00 (idx=1) from 0/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS0 : Assigning value 0x00 (idx=1) from 4/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_RD_MAP_CS1 : Assigning value 0x00 (idx=1) from 2/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_WR_MAP_CS1 : Assigning value 0x00 (idx=1) from 6/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ODT_EN_F2 : Assigning value 0x01 (idx=1) from 9/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PD_NT_ODT_EN_F2 : Assigning value 0x00 (idx=1) from 10/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.RD_TO_ODTH_F2 : Assigning value 0x15 (idx=1) from 11/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_RD_F2 : Assigning value 0x01 (idx=1) from 18/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTH_WR_F2 : Assigning value 0x01 (idx=1) from 22/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTL_2CMD_F2 : Assigning value 0x00 (idx=1) from 26/8/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.TODTUP_F2 : Assigning value 0x010b (idx=1) from 34/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.WR_TO_ODTH_F2 : Assigning value 0x10 (idx=1) from 50/7/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx01001000000000001000010110000000000010001001010101000000000;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000240042c0044aa00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PORT_ADDR_PROTECTION_EN = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key PROGRAMMABLE_ADDRESS_ORDER = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MSK_0 = 0x001f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_VAL_LOWER_0 = 0x0000</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_VAL_UPPER_0 = 0x00ff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ROW_START_VAL_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_MSK_1 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_VAL_LOWER_1 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key CS_VAL_UPPER_1 = 0xffff</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ROW_START_VAL_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PORT_ADDR_PROTECTION_EN : Assigning value 0x00 (idx=1) from 106/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.PROGRAMMABLE_ADDRESS_ORDER : Assigning value 0x00 (idx=1) from 96/4/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MSK_0 : Assigning value 0x001f (idx=1) from 0/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_VAL_LOWER_0 : Assigning value 0x0000 (idx=1) from 32/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_VAL_UPPER_0 : Assigning value 0x00ff (idx=1) from 64/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ROW_START_VAL_0 : Assigning value 0x00 (idx=1) from 100/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_MSK_1 : Assigning value 0xffff (idx=1) from 16/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_VAL_LOWER_1 : Assigning value 0xffff (idx=1) from 48/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.CS_VAL_UPPER_1 : Assigning value 0xffff (idx=1) from 80/16/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ROW_START_VAL_1 : Assigning value 0x00 (idx=1) from 103/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx00000000000111111111111111100000000111111111111111111111111000000000000000011111111111111110000000000011111;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000ffff00ffffff0000ffff001f</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ZQ_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_ROTATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_SW_REQ_START_LATCH_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCL_F0 = 0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_F0 = 0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQINIT_F0 = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQRESET_F0 = 0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ZQ_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 1/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_ROTATE : Assigning value 0x01 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_SW_REQ_START_LATCH_MAP : Assigning value 0x00 (idx=1) from 13/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_0 : Assigning value 0x00 (idx=1) from 9/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_0 : Assigning value 0x00 (idx=1) from 5/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_1 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_1 : Assigning value 0x00 (idx=1) from 7/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCL_F0 : Assigning value 0x0100 (idx=1) from 15/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_F0 : Assigning value 0x0040 (idx=1) from 27/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQINIT_F0 : Assigning value 0x0200 (idx=1) from 39/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQRESET_F0 : Assigning value 0x0036 (idx=1) from 51/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110110001000000000000001000000000100000000000000000010111;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b1000200800017</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ZQ_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_ROTATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_SW_REQ_START_LATCH_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCL_F1 = 0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_F1 = 0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQINIT_F1 = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQRESET_F1 = 0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ZQ_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 1/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_ROTATE : Assigning value 0x01 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_SW_REQ_START_LATCH_MAP : Assigning value 0x00 (idx=1) from 13/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_0 : Assigning value 0x00 (idx=1) from 9/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_0 : Assigning value 0x00 (idx=1) from 5/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_1 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_1 : Assigning value 0x00 (idx=1) from 7/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCL_F1 : Assigning value 0x0100 (idx=1) from 15/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_F1 : Assigning value 0x0040 (idx=1) from 27/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQINIT_F1 : Assigning value 0x0200 (idx=1) from 39/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQRESET_F1 : Assigning value 0x0036 (idx=1) from 51/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110110001000000000000001000000000100000000000000000010111;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b1000200800017</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key DFS_ZQ_EN = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_OPT_THRESHOLD = 0x03</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_ROTATE = 0x01</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_SW_REQ_START_LATCH_MAP = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_0 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_LATCH_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQ_CAL_START_MAP_1 = 0x00</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCL_F2 = 0x0100</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQCS_F2 = 0x0040</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQINIT_F2 = 0x0200</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_REG _safe_dict_get: Key ZQRESET_F2 = 0x0036</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.DFS_ZQ_EN : Assigning value 0x01 (idx=1) from 0/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_OPT_THRESHOLD : Assigning value 0x03 (idx=1) from 1/3/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_ROTATE : Assigning value 0x01 (idx=1) from 4/1/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_SW_REQ_START_LATCH_MAP : Assigning value 0x00 (idx=1) from 13/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_0 : Assigning value 0x00 (idx=1) from 9/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_0 : Assigning value 0x00 (idx=1) from 5/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_LATCH_MAP_1 : Assigning value 0x00 (idx=1) from 11/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQ_CAL_START_MAP_1 : Assigning value 0x00 (idx=1) from 7/2/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCL_F2 : Assigning value 0x0100 (idx=1) from 15/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQCS_F2 : Assigning value 0x0040 (idx=1) from 27/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQINIT_F2 : Assigning value 0x0200 (idx=1) from 39/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL: HMC_REG.ZQRESET_F2 : Assigning value 0x0036 (idx=1) from 51/12/1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'bxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx000000110110001000000000000001000000000100000000000000000010111;</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: NOVAL = 1024'h00000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000001b1000200800017</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of BOF_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of Burst_Length: Parameter value 16</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling get_max_timing with {twr}, 0 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of twr: Parameter value {18.0 ns}</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {18.0 ns}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of temperatureReg: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of twr: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: Calling value_of_time with {1 simclk}, 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">inter_twr = 18.0 / 0.937 = 19.2102454642476</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tWR_135V: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of VDD_RANGE: yes</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of VDD_RANGE: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPREAMBLE_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: ERROR: Global Parameter part_class does not exist!</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of validCWL: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of cwlSpBin: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of tckCL_CWL_min: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of CasLatencyList: Parameter value 22</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of csMemParms: Array name csMemParms</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WLS_EN: Parameter value 1.0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: INFO_GLOBALS: Checking for existence of Framework_Management_Version_1: no</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of SimMhzList: Parameter value 1066.667 1066.667</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRPSTMBLE_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_drive_strength: Parameter value 6</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of RDDBI_EN: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of WRDBI_EN: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rtt_dq: Parameter value 5</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_comm_odt: Parameter value 3</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_value: Parameter value 13</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_vref_range: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of data_mask_en: Parameter value true</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq: Parameter value 20</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_rx_vref_dq_range: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ck_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_cs_odt_en: Parameter value 1</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: GET_GLOBAL: Retrieving value of lpddr4_ca_odt_dis: Parameter value 0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">HMC_DEBUG: HMC=1 (0: Wide/1: Slim) is_used=0</message>
   <message level="Debug" culprit="emif_io96b_lpddr4_0">quartus_synth fileset time: 717.63 ms</message>
   <message level="Info" culprit="cal_0">"Generating: cal_0"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_emif_io96b_cal_411_tsrqcha"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i"</message>
   <message level="Debug" culprit="cal_0">quartus_synth fileset time: 278.39 ms</message>
   <message level="Info" culprit="jamb">"Generating: jamb"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_jtag_interface"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_timing_adapter_1950_bbjt6kq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_altera_avalon_sc_fifo_1932_onpcouq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_bytes_to_packets"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_packets_to_bytes"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_packets_to_master"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_rd56ufy"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_5vp3d5a"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_reset_controller"</message>
  </messages>
 </entity>
 <entity
   kind="emif_io96b_lpddr4_emif_io96b_cal"
   version="4.1.1"
   name="EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_emif_io96b_cal_411_tsrqcha">
  <parameter name="SYSINFO_DEVICE_SPEEDGRADE" value="4" />
  <parameter name="INSTANCE_NAME" value="cal_0" />
  <parameter name="SYSINFO_DEVICE_DIE_REVISIONS" value="MAIN_SM4_REVB" />
  <parameter name="SYSINFO_DEVICE_GROUP" value="B" />
  <parameter name="ALL_INTFS" value="true" />
  <parameter name="SYSINFO_DEVICE_IOBANK_REVISION" value="IO96B_REVB1" />
  <parameter name="SYSINFO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="INSTANCE_ID" value="0" />
  <parameter name="NUM_CALBUS_PLLS" value="0" />
  <parameter name="SYSINFO_BOARD" value="default" />
  <parameter name="IS_PART_OF_BANK_ADJACENT_PAIR" value="false" />
  <parameter name="SYSINFO_DEVICE_POWER_MODEL" value="STANDARD_POWER_FIXED" />
  <parameter name="DEBUG_TOOLS_EN" value="true" />
  <parameter name="SYSINFO_BOARD_TRAIT" value="" />
  <parameter name="SYSINFO_DEVICE_BASE_DIE" value="SM4REVB" />
  <parameter name="NUM_CALBUS_PERIPHS" value="1" />
  <parameter name="LOCKSTEP_ENABLE" value="false" />
  <parameter name="IS_HPS" value="false" />
  <parameter name="PORT_S_AXIL_MODE" value="FABRIC" />
  <parameter name="PORT_M_AXIL_ENABLE" value="false" />
  <parameter name="SYSINFO_SUPPORTS_VID" value="0" />
  <parameter name="SYSINFO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="SYSINFO_DEVICE_TEMPERATURE_GRADE" value="EXTENDED" />
  <parameter name="BANK_ADJACENT_PAIR_ID" value="0" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_emif_io96b_cal_411_tsrqcha.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_lpddr4_411/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_emif_io96b_cal_411_tsrqcha.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles/>
  <childSourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/emif_io96b/ip_cal/ip/emif_io96b_cal_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/alt_mem_if/alt_mem_if_jtag_master/alt_mem_if_jtag_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_avalon_st_jtag_interface_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_bytes_to_packets/altera_avalon_st_bytes_to_packets_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_packets_to_master/altera_avalon_packets_to_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </childSourceFiles>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_411_nzsevry"
     as="cal_0" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_emif_io96b_cal_411_tsrqcha"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i"</message>
   <message level="Debug" culprit="cal_0">quartus_synth fileset time: 278.39 ms</message>
   <message level="Info" culprit="jamb">"Generating: jamb"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_jtag_interface"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_timing_adapter_1950_bbjt6kq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_altera_avalon_sc_fifo_1932_onpcouq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_bytes_to_packets"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_packets_to_bytes"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_packets_to_master"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_rd56ufy"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_5vp3d5a"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_reset_controller"</message>
  </messages>
 </entity>
 <entity
   kind="emif_io96b_cal"
   version="2.3.1"
   name="EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i">
  <parameter name="SYSINFO_DEVICE_SPEEDGRADE" value="4" />
  <parameter name="INSTANCE_NAME" value="cal_0" />
  <parameter name="SYSINFO_DEVICE_DIE_REVISIONS" value="MAIN_SM4_REVB" />
  <parameter name="SYSINFO_DEVICE_GROUP" value="B" />
  <parameter name="ALL_INTFS" value="true" />
  <parameter name="SYSINFO_DEVICE_IOBANK_REVISION" value="IO96B_REVB1" />
  <parameter name="SYSINFO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="INSTANCE_ID" value="0" />
  <parameter name="NUM_CALBUS_PLLS" value="0" />
  <parameter name="SYSINFO_BOARD" value="default" />
  <parameter name="IS_PART_OF_BANK_ADJACENT_PAIR" value="false" />
  <parameter name="SYSINFO_DEVICE_POWER_MODEL" value="STANDARD_POWER_FIXED" />
  <parameter name="DEBUG_TOOLS_EN" value="true" />
  <parameter name="SYSINFO_BOARD_TRAIT" value="" />
  <parameter name="SYSINFO_DEVICE_BASE_DIE" value="SM4REVB" />
  <parameter name="NUM_CALBUS_PERIPHS" value="1" />
  <parameter name="LOCKSTEP_ENABLE" value="false" />
  <parameter name="IS_HPS" value="false" />
  <parameter name="PORT_S_AXIL_MODE" value="FABRIC" />
  <parameter name="PORT_M_AXIL_ENABLE" value="false" />
  <parameter name="SYSINFO_SUPPORTS_VID" value="0" />
  <parameter name="SYSINFO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="SYSINFO_DEVICE_TEMPERATURE_GRADE" value="EXTENDED" />
  <parameter name="BANK_ADJACENT_PAIR_ID" value="0" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_atom_attr_fa_c2p_ssm.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_atom_attr_fa_p2c_ssm.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_atom_attr_iossm.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_atom_attr_seq.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/iossm_cal_boot.hex"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/iossm_cal.hex"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_arbitrator.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_cal_arch_fp_top.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_cal_arch_fp_atom_inst_iossm.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_cal_arch_fp_atom_inst_seq.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_cal_arch_fp_atom_inst_fa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_cal_arch_fp_atom_inst_comp.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/cal_io96b_interface.svh"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/altera_emif_cal_gearbox.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/altera_emif_cal_gearbox_bidir.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_translator_1931_d46vvwa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_reset_controller.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_avalon_st_bytes_to_packets.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_avalon_packets_to_master.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_master_ni_1962_2kryw2a.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_merlin_reorder_memory.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_7ekoqry.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_1921_bk6lvda.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_channel_adapter_1921_fkajlia.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_jy53pgi.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_ctb2miq.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_7b7u3ni.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_252f2xa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_merlin_arbitrator.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/rd_pri_mux_cwyib4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/rd_comp_sel_kt2puei.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_channel_adapter_1921_5wnzrci.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_avalon_st_pipeline_stage_1930_bv2ucky.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_avalon_st_packets_to_bytes.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/wr_sipo_plus_kt2puei.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/wr_response_mem_kt2puei.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/wr_comp_sel_kt2puei.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/rd_response_mem_kt2puei.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/wr_sipo_plus_cwyib4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/wr_comp_sel_cwyib4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/rd_sipo_plus_kt2puei.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/rd_sipo_plus_cwyib4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_vnonqiy.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_alj3kza.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_ysgnmwa.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/compare_eq.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/wr_response_mem_cwyib4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/rd_response_mem_cwyib4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/rd_pri_mux_kt2puei.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/rd_comp_sel_cwyib4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_sc_fifo_1971_o34766q.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_1971_kt2puei.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_1971_cwyib4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/wr_pri_mux_kt2puei.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/wr_pri_mux_cwyib4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_h6wexfa.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_slave_ni_altera_avalon_st_pipeline_stage_1971_cgpn6xq.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_avalon_sc_fifo_1931_fzgstwy.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_merlin_burst_uncompressor.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_width_adapter_1933_2qdsena.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_master_agent_1921_2inlndi.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_rcor4va.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_ekcygpi.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_demultiplexer_1921_c2mlp5i.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_merlin_address_alignment.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_width_adapter_1933_sqfzewq.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1931_glj62si.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_merlin_burst_adapter_uncmpr.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_merlin_burst_adapter_new.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_burst_adapter_1931_hbsisni.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_wrap_burst_converter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_merlin_burst_adapter_13_1.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_incr_burst_converter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_default_burst_converter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_timing_adapter_1940_5ju4ddy.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/intel_axi4lite_injector_dcfifo_s.sv"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/intel_axi4lite_injector_util.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/intel_axi4lite_injector_ph2.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_intel_axi4lite_injector_100_2yowc3a.sv"
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_hs_clk_xer_1940_hvja46q.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_hs_clk_xer_1940_4s7hdhy.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_mm_interconnect_1920_jmzr6ly.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_mm_interconnect_1920_5sovoyi.v"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_master_translator_192_lykd4la.sv"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_std_synchronizer_nocut.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_reset_synchronizer.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_avalon_st_pipeline_base.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_avalon_st_clock_crosser.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_vbaxzva.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_nxsnrbi.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_irryw4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_wqohhgi.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_4ytgf2y.sv"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_2jqun3q.sv"
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  </generatedFiles>
  <childGeneratedFiles>
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_atom_attr_fa_c2p_ssm.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_atom_attr_fa_p2c_ssm.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_atom_attr_iossm.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/io0_EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_atom_attr_seq.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/iossm_cal_boot.hex"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/iossm_cal.hex"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_arbitrator.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_cal_arch_fp_top.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_cal_arch_fp_atom_inst_iossm.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_cal_arch_fp_atom_inst_seq.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_cal_arch_fp_atom_inst_fa.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i_cal_arch_fp_atom_inst_comp.sv"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/cal_io96b_interface.svh"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/altera_emif_cal_gearbox.sv"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/altera_emif_cal_gearbox_bidir.sv"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_translator_1931_d46vvwa.sv"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_reset_controller.v"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_avalon_st_bytes_to_packets.v"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_avalon_packets_to_master.v"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_axi_master_ni_1962_2kryw2a.sv"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_merlin_reorder_memory.sv"
       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_altera_avalon_sc_fifo_1921_7ekoqry.v"
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_traffic_limiter_1921_bk6lvda.sv"
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_channel_adapter_1921_fkajlia.sv"
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_jy53pgi.sv"
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_ctb2miq.sv"
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_multiplexer_1922_7b7u3ni.sv"
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       attributes="" />
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_avalon_st_pipeline_stage_1930_bv2ucky.sv"
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       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_avalon_st_packets_to_bytes.v"
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       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/altera_avalon_st_clock_crosser.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_vbaxzva.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_nxsnrbi.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_irryw4q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_wqohhgi.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_4ytgf2y.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/interconnect/ed_synth_dut_altera_merlin_router_1921_2jqun3q.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/emif_io96b/ip_cal/ip/emif_io96b_cal_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/alt_mem_if/alt_mem_if_jtag_master/alt_mem_if_jtag_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_avalon_st_jtag_interface_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_bytes_to_packets/altera_avalon_st_bytes_to_packets_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_packets_to_master/altera_avalon_packets_to_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </childSourceFiles>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_lpddr4_emif_io96b_cal_411_tsrqcha"
     as="cal_0" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i"</message>
   <message level="Debug" culprit="cal_0">quartus_synth fileset time: 278.39 ms</message>
   <message level="Info" culprit="jamb">"Generating: jamb"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_jtag_interface"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_timing_adapter_1950_bbjt6kq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_altera_avalon_sc_fifo_1932_onpcouq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_bytes_to_packets"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_packets_to_bytes"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_packets_to_master"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_rd56ufy"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_5vp3d5a"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_reset_controller"</message>
  </messages>
 </entity>
 <entity
   kind="emif_io96b_cal_alt_mem_if_jtag_master"
   version="2.3.1"
   name="EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq">
  <parameter name="FAST_VER" value="0" />
  <parameter name="AUTO_DEVICE" value="" />
  <parameter name="AUTO_DEVICE_FAMILY" value="" />
  <parameter name="AUTO_BOARD" value="" />
  <parameter name="USE_PLI" value="0" />
  <parameter name="PLI_PORT" value="50000" />
  <parameter name="COMPONENT_CLOCK" value="0" />
  <parameter name="FIFO_DEPTHS" value="2" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/emif_io96b_cal_231/synth/EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles/>
  <childSourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/alt_mem_if/alt_mem_if_jtag_master/alt_mem_if_jtag_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_avalon_st_jtag_interface_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_bytes_to_packets/altera_avalon_st_bytes_to_packets_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_packets_to_master/altera_avalon_packets_to_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </childSourceFiles>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_231_kbj563i"
     as="jamb" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_jtag_interface"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_timing_adapter_1950_bbjt6kq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_altera_avalon_sc_fifo_1932_onpcouq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_bytes_to_packets"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_packets_to_bytes"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_packets_to_master"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_rd56ufy"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_5vp3d5a"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_reset_controller"</message>
  </messages>
 </entity>
 <entity
   kind="alt_mem_if_jtag_master"
   version="19.1"
   name="EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi">
  <parameter name="FAST_VER" value="0" />
  <parameter name="AUTO_DEVICE" value="" />
  <parameter name="AUTO_DEVICE_FAMILY" value="" />
  <parameter name="AUTO_BOARD" value="" />
  <parameter name="USE_PLI" value="0" />
  <parameter name="PLI_PORT" value="50000" />
  <parameter name="COMPONENT_CLOCK" value="0" />
  <parameter name="FIFO_DEPTHS" value="2" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/alt_mem_if_jtag_master_191/synth/EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/alt_mem_if_jtag_master_191/synth/EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/alt_mem_if/alt_mem_if_jtag_master/alt_mem_if_jtag_master_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_avalon_st_jtag_interface_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_bytes_to_packets/altera_avalon_st_bytes_to_packets_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_packets_to_master/altera_avalon_packets_to_master_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </childSourceFiles>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_emif_io96b_cal_alt_mem_if_jtag_master_231_7ir2qwq"
     as="jamb" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_jtag_interface"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_timing_adapter_1950_bbjt6kq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_altera_avalon_sc_fifo_1932_onpcouq"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_bytes_to_packets"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_packets_to_bytes"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_packets_to_master"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_rd56ufy"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_5vp3d5a"</message>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_reset_controller"</message>
  </messages>
 </entity>
 <entity
   kind="altera_jtag_dc_streaming"
   version="19.1"
   name="altera_avalon_st_jtag_interface">
  <parameter name="UPSTREAM_FIFO_SIZE" value="0" />
  <parameter name="USE_DOWNSTREAM_READY" value="0" />
  <parameter name="FABRIC" value="2.0" />
  <parameter name="DOWNSTREAM_FIFO_SIZE" value="64" />
  <parameter name="MGMT_CHANNEL_WIDTH" value="-1" />
  <parameter name="PURPOSE" value="1" />
  <parameter name="USE_PLI" value="0" />
  <parameter name="PLI_PORT" value="50000" />
  <parameter name="COMPONENT_CLOCK" value="0" />
  <parameter name="EXPORT_JTAG" value="0" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.sdc"
       attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_jtag_dc_streaming.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_jtag_sld_node.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_jtag_streaming.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_clock_crosser.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_reset_synchronizer.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_std_synchronizer_nocut.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_base.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_remover.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_idle_inserter.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_pipeline_stage.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_jtag_dc_streaming_191/synth/altera_avalon_st_jtag_interface.sdc"
       attributes="NO_AUTO_INSTANCE_DISCOVERY NO_SDC_PROMOTION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_jtag_phy/altera_avalon_st_jtag_interface_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"
     as="jtag_phy_embedded_in_jtag_master" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_jtag_interface"</message>
  </messages>
 </entity>
 <entity
   kind="timing_adapter"
   version="19.5.0"
   name="EMIF_Qsys_emif_io96b_lpddr4_0_timing_adapter_1950_bbjt6kq">
  <parameter name="inErrorWidth" value="0" />
  <parameter name="inUseValid" value="true" />
  <parameter name="inUseReady" value="false" />
  <parameter name="inBitsPerSymbol" value="8" />
  <parameter name="outReadyLatency" value="0" />
  <parameter name="inChannelWidth" value="0" />
  <parameter name="inSymbolsPerBeat" value="1" />
  <parameter name="inUseEmptyPort" value="NO" />
  <parameter name="FAMILY" value="Unknown" />
  <parameter name="outUseReady" value="true" />
  <parameter name="outUseValid" value="true" />
  <parameter name="FIFO_MEM_TYPE" value="0" />
  <parameter name="inReadyLatency" value="0" />
  <parameter name="inUseEmpty" value="false" />
  <parameter name="SYNC_RESET" value="0" />
  <parameter name="inUsePackets" value="false" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/timing_adapter_1950/synth/EMIF_Qsys_emif_io96b_lpddr4_0_timing_adapter_1950_bbjt6kq.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/timing_adapter_1950/synth/EMIF_Qsys_emif_io96b_lpddr4_0_timing_adapter_1950_bbjt6kq.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_timing_adapter/avalon-st_timing_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"
     as="timing_adt" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_timing_adapter_1950_bbjt6kq"</message>
  </messages>
 </entity>
 <entity
   kind="altera_avalon_sc_fifo"
   version="19.3.2"
   name="EMIF_Qsys_emif_io96b_lpddr4_0_altera_avalon_sc_fifo_1932_onpcouq">
  <parameter name="EXPLICIT_MAXCHANNEL" value="0" />
  <parameter name="EMPTY_WIDTH" value="1" />
  <parameter name="SYNC_RESET" value="0" />
  <parameter name="ENABLE_EXPLICIT_MAXCHANNEL" value="false" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_avalon_sc_fifo_1932/synth/EMIF_Qsys_emif_io96b_lpddr4_0_altera_avalon_sc_fifo_1932_onpcouq.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_avalon_sc_fifo_1932/synth/EMIF_Qsys_emif_io96b_lpddr4_0_altera_avalon_sc_fifo_1932_onpcouq.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"
     as="fifo" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_altera_avalon_sc_fifo_1932_onpcouq"</message>
  </messages>
 </entity>
 <entity
   kind="altera_avalon_st_bytes_to_packets"
   version="19.2.2"
   name="altera_avalon_st_bytes_to_packets">
  <parameter name="CHANNEL_WIDTH_DERIVED" value="8" />
  <parameter name="ENCODING" value="0" />
  <parameter name="CHANNEL_WIDTH" value="8" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_avalon_st_bytes_to_packets_1922/synth/altera_avalon_st_bytes_to_packets.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_bytes_to_packets/altera_avalon_st_bytes_to_packets_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"
     as="b2p" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_bytes_to_packets"</message>
  </messages>
 </entity>
 <entity
   kind="altera_avalon_st_packets_to_bytes"
   version="19.2.2"
   name="altera_avalon_st_packets_to_bytes">
  <parameter name="CHANNEL_WIDTH_DERIVED" value="8" />
  <parameter name="ENCODING" value="0" />
  <parameter name="CHANNEL_WIDTH" value="8" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_avalon_st_packets_to_bytes_1922/synth/altera_avalon_st_packets_to_bytes.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_st_packets_to_bytes/altera_avalon_st_packets_to_bytes_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"
     as="p2b" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_st_packets_to_bytes"</message>
  </messages>
 </entity>
 <entity
   kind="altera_avalon_packets_to_master"
   version="19.2.2"
   name="altera_avalon_packets_to_master">
  <parameter name="EXPORT_MASTER_SIGNALS" value="0" />
  <parameter name="FAST_VER" value="0" />
  <parameter name="FIFO_WIDTHU" value="1" />
  <parameter name="FIFO_DEPTHS" value="2" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_avalon_packets_to_master_1922/synth/altera_avalon_packets_to_master.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/platform_designer_ip/altera_avalon_packets_to_master/altera_avalon_packets_to_master_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"
     as="transacto" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_avalon_packets_to_master"</message>
  </messages>
 </entity>
 <entity
   kind="channel_adapter"
   version="19.2.2"
   name="EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_rd56ufy">
  <parameter name="inErrorWidth" value="0" />
  <parameter name="inUseReady" value="true" />
  <parameter name="inMaxChannel" value="255" />
  <parameter name="inBitsPerSymbol" value="8" />
  <parameter name="outMaxChannel" value="0" />
  <parameter name="inUseEmpty" value="false" />
  <parameter name="inChannelWidth" value="8" />
  <parameter name="inSymbolsPerBeat" value="1" />
  <parameter name="suppressHigherChannels" value="true" />
  <parameter name="outChannelWidth" value="0" />
  <parameter name="inUsePackets" value="true" />
  <parameter name="inUseEmptyPort" value="AUTO" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/channel_adapter_1922/synth/EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_rd56ufy.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/channel_adapter_1922/synth/EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_rd56ufy.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"
     as="b2p_adapter" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_rd56ufy"</message>
  </messages>
 </entity>
 <entity
   kind="channel_adapter"
   version="19.2.2"
   name="EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_5vp3d5a">
  <parameter name="inErrorWidth" value="0" />
  <parameter name="inUseReady" value="true" />
  <parameter name="inMaxChannel" value="0" />
  <parameter name="inBitsPerSymbol" value="8" />
  <parameter name="outMaxChannel" value="255" />
  <parameter name="inUseEmpty" value="false" />
  <parameter name="inChannelWidth" value="0" />
  <parameter name="inSymbolsPerBeat" value="1" />
  <parameter name="suppressHigherChannels" value="true" />
  <parameter name="outChannelWidth" value="8" />
  <parameter name="inUsePackets" value="true" />
  <parameter name="inUseEmptyPort" value="AUTO" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/channel_adapter_1922/synth/EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_5vp3d5a.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/channel_adapter_1922/synth/EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_5vp3d5a.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/avalon_st/altera_avalon_st_channel_adapter/avalon-st_channel_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"
     as="p2b_adapter" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: EMIF_Qsys_emif_io96b_lpddr4_0_channel_adapter_1922_5vp3d5a"</message>
  </messages>
 </entity>
 <entity
   kind="altera_reset_controller"
   version="19.2.4"
   name="altera_reset_controller">
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_reset_controller_1924/synth/altera_reset_controller.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_reset_controller_1924/synth/altera_reset_synchronizer.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_reset_controller_1924/synth/altera_reset_controller.sdc"
       attributes="NO_SDC_PROMOTION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_reset_controller_1924/synth/altera_reset_controller.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_reset_controller_1924/synth/altera_reset_synchronizer.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/RTL_LPDDR4_AXI4_Test/ip/EMIF_Qsys/EMIF_Qsys_emif_io96b_lpddr4_0/altera_reset_controller_1924/synth/altera_reset_controller.sdc"
       attributes="NO_SDC_PROMOTION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/altera_pro/25.3.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="EMIF_Qsys_emif_io96b_lpddr4_0_alt_mem_if_jtag_master_191_2xbfrbi"
     as="rst_controller" />
  <messages>
   <message level="Info" culprit="EMIF_Qsys_emif_io96b_lpddr4_0">"Generating: altera_reset_controller"</message>
  </messages>
 </entity>
</deploy>
