// retroDE_ps2 — tb_ee_core_pcpyld
//
// Ch278 — Focused TB for R5900 EE MMI2/PCPYLD (Parallel Copy
// Lower Doubleword). Primary opcode 0x1C, funct 0x09 (MMI2), sa
// 0x0E (PCPYLD). qbert.elf hits `pcpyld $t2, $t1, $t1` (instr
// 0x71295389) at PC 0x00112C84 — note rs=rt=$t1 in the actual
// qbert encoding (my initial decode read it as rs=$a1, which was
// wrong; the bits[25:21] = 01001 = 9 = $t1).
//
// Architectural semantics (128-bit):
//   rd[127:64] = rs[63:0]    (upper 64 of rd = lower 64 of rs)
//   rd[63:0]   = rt[63:0]    (lower 64 of rd = lower 64 of rt)
//
// In our 32-bit GPR model the observable result collapses to
// rd_low32 = rt_low32. rs has no observable effect (its
// contribution would be the unrepresentable rd[127:64] half).
//
// Cases:
//   1. Exact qbert encoding: pcpyld $t2, $t1, $t1 (rd=10, rs=9,
//      rt=9, sa=0x0E, funct=0x09). enc_rtype() built result
//      asserted == 0x71295389. With $t1=0xBBBBBBBB, $t2 must
//      become 0xBBBBBBBB.
//   2. Different rs/rt sentinels prove rd <- rt, NOT rs:
//      pcpyld $t3, $a0, $a1 with $a0=0xDEADBEEF, $a1=0xCAFEF00D →
//      $t3 = 0xCAFEF00D (rt), not 0xDEADBEEF (rs).
//
// Strict mode ON.

`timescale 1ns/1ps

module tb_ee_core_pcpyld;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 4 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR   = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA   = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    // Case 1: exact qbert encoding
    localparam int B_LUI_A1_H    = BOOTSTRAP_SLOT + 0;   // lui $a1,0xAAAA
    localparam int B_ORI_A1_L    = BOOTSTRAP_SLOT + 1;   // ori $a1,$a1,0xAAAA
    localparam int B_LUI_T1_H    = BOOTSTRAP_SLOT + 2;   // lui $t1,0xBBBB
    localparam int B_ORI_T1_L    = BOOTSTRAP_SLOT + 3;   // ori $t1,$t1,0xBBBB
    localparam int B_PCPYLD_T2   = BOOTSTRAP_SLOT + 4;   // pcpyld $t2,$a1,$t1 (qbert exact)
    localparam int B_LUI_TMP_B   = BOOTSTRAP_SLOT + 5;   // lui $tmp,0xBBBB (expected)
    localparam int B_ORI_TMP_B   = BOOTSTRAP_SLOT + 6;   // ori $tmp,$tmp,0xBBBB
    localparam int B_BNE_QB      = BOOTSTRAP_SLOT + 7;   // bne $t2,$tmp,FAIL
    localparam int B_DS_QB       = BOOTSTRAP_SLOT + 8;

    // Case 2: distinct rs/rt sentinels (rd<-rt, not rs)
    localparam int B_LUI_A0_H    = BOOTSTRAP_SLOT + 9;   // lui $a0,0xDEAD
    localparam int B_ORI_A0_L    = BOOTSTRAP_SLOT + 10;  // ori $a0,$a0,0xBEEF
    localparam int B_LUI_A1B_H   = BOOTSTRAP_SLOT + 11;  // lui $a1,0xCAFE
    localparam int B_ORI_A1B_L   = BOOTSTRAP_SLOT + 12;  // ori $a1,$a1,0xF00D
    localparam int B_PCPYLD_T3   = BOOTSTRAP_SLOT + 13;  // pcpyld $t3,$a0,$a1
    localparam int B_LUI_TMP_C   = BOOTSTRAP_SLOT + 14;  // lui $tmp,0xCAFE
    localparam int B_ORI_TMP_C   = BOOTSTRAP_SLOT + 15;  // ori $tmp,$tmp,0xF00D
    localparam int B_BNE_DSTR    = BOOTSTRAP_SLOT + 16;  // bne $t3,$tmp,FAIL
    localparam int B_DS_DSTR     = BOOTSTRAP_SLOT + 17;

    localparam int B_PASS        = BOOTSTRAP_SLOT + 18;  // syscall PASS

    // Negative slot (used only by tb #2 below — see "unknown_mmi"
    // case separately invoked).
    localparam int B_FAIL        = BOOTSTRAP_SLOT + 19;

    localparam logic [5:0] OP_J     = 6'h02;
    localparam logic [5:0] OP_BNE   = 6'h05;
    localparam logic [5:0] OP_ORI   = 6'h0D;
    localparam logic [5:0] OP_LUI   = 6'h0F;
    localparam logic [5:0] OP_MMI   = 6'h1C;
    localparam logic [5:0] FUNC_MMI2 = 6'h09;
    localparam logic [4:0] SA_PCPYLD = 5'h0E;

    // GPRs
    localparam int RA0 = 4;
    localparam int RA1 = 5;
    localparam int RT1 = 9;
    localparam int RT2 = 10;
    localparam int RT3 = 11;
    localparam int RTMP = 24;

    logic clk, rst_n;
    initial clk = 1'b0;
    always #5 clk = ~clk;

    // ----- EE core -----
    logic        core_go, core_halt, core_trap;
    logic [31:0] core_pc, core_trap_pc, core_trap_instr;
    logic        ee_rd_en, ee_rd_valid, ee_wr_en;
    logic [31:0] ee_rd_addr, ee_rd_data, ee_wr_addr, ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(.STRICT_UNSUPPORTED(1'b1)) u_core (
        .clk(clk), .rst_n(rst_n), .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(1'b0),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    // ----- Map + RAM + BIOS -----
    logic         bios_rd_en, bios_rd_valid;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         ee_ram_rd_en, ee_ram_rd_valid, ee_ram_wr_en;
    logic [24:0]  ee_ram_rd_addr, ee_ram_wr_addr;
    logic [127:0] ee_ram_rd_data, ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_pcpyld_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events, core_halt_events, core_trap_events, errors;
    initial begin
        core_retired_events = 0; core_halt_events = 0;
        core_trap_events = 0; errors = 0;
    end
    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0) core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0) core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask
    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction
    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction
    function automatic logic [31:0] enc_rtype(input logic [5:0] op,
                                              input int rs, input int rt,
                                              input int rd, input int sa,
                                              input logic [5:0] funct);
        return {op, rs[4:0], rt[4:0], rd[4:0], sa[4:0], funct};
    endfunction
    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    initial begin
        logic [31:0] qbert_pcpyld_raw;

        rst_n = 1'b0; core_go = 1'b0;
        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_word(RESET_SLOT,     enc_j(BOOTSTRAP_VA));
        bios_word(RESET_SLOT + 1, 32'd0);

        // ===== Case 1: exact qbert encoding =====
        // $t1 = 0xBBBBBBBB (the only source needed — rs=rt=$t1 in
        // qbert's actual encoding 0x71295389).
        bios_word(B_LUI_A1_H, enc_i(OP_LUI, 0, RT1, 16'hBBBB));  // recycled slot
        bios_word(B_ORI_A1_L, enc_i(OP_ORI, RT1, RT1, 16'hBBBB));
        bios_word(B_LUI_T1_H, 32'd0);  // unused (clean nop)
        bios_word(B_ORI_T1_L, 32'd0);  // unused (clean nop)
        // pcpyld $t2, $t1, $t1  (rd=10, rs=9, rt=9, sa=0x0E, funct=0x09)
        qbert_pcpyld_raw = enc_rtype(OP_MMI, RT1, RT1, RT2, SA_PCPYLD, FUNC_MMI2);
        if (qbert_pcpyld_raw !== 32'h7129_5389) begin
            $error("[tb_ee_core_pcpyld] enc_rtype mismatch: produced 0x%08h, expected 0x71295389",
                   qbert_pcpyld_raw);
            errors = errors + 1;
        end
        bios_word(B_PCPYLD_T2, qbert_pcpyld_raw);
        // Verify $t2 == 0xBBBBBBBB (rt = $t1, NOT rs = $a1).
        bios_word(B_LUI_TMP_B, enc_i(OP_LUI, 0, RTMP, 16'hBBBB));
        bios_word(B_ORI_TMP_B, enc_i(OP_ORI, RTMP, RTMP, 16'hBBBB));
        bios_word(B_BNE_QB,    enc_i(OP_BNE, RT2, RTMP, branch_imm(B_BNE_QB, B_FAIL)));
        bios_word(B_DS_QB,     32'd0);

        // ===== Case 2: distinct sentinels prove rd<-rt =====
        // $a0 = 0xDEADBEEF, $a1 = 0xCAFEF00D
        bios_word(B_LUI_A0_H,  enc_i(OP_LUI, 0, RA0, 16'hDEAD));
        bios_word(B_ORI_A0_L,  enc_i(OP_ORI, RA0, RA0, 16'hBEEF));
        bios_word(B_LUI_A1B_H, enc_i(OP_LUI, 0, RA1, 16'hCAFE));
        bios_word(B_ORI_A1B_L, enc_i(OP_ORI, RA1, RA1, 16'hF00D));
        // pcpyld $t3, $a0, $a1
        bios_word(B_PCPYLD_T3, enc_rtype(OP_MMI, RA0, RA1, RT3, SA_PCPYLD, FUNC_MMI2));
        // Verify $t3 == 0xCAFEF00D (rt, NOT rs=0xDEADBEEF).
        bios_word(B_LUI_TMP_C, enc_i(OP_LUI, 0, RTMP, 16'hCAFE));
        bios_word(B_ORI_TMP_C, enc_i(OP_ORI, RTMP, RTMP, 16'hF00D));
        bios_word(B_BNE_DSTR,  enc_i(OP_BNE, RT3, RTMP, branch_imm(B_BNE_DSTR, B_FAIL)));
        bios_word(B_DS_DSTR,   32'd0);

        bios_word(B_PASS, 32'h0000_000C);
        bios_word(B_FAIL, 32'h0000_000C);

        @(negedge clk); core_go = 1'b1;
        @(negedge clk); core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        if (core_trap_events != 0) begin
            $error("[tb_ee_core_pcpyld] unexpected trap: %0d pc=0x%08h instr=0x%08h",
                   core_trap_events, core_trap_pc, core_trap_instr);
            errors = errors + 1;
        end
        if (core_halt_events != 1) begin
            $error("[tb_ee_core_pcpyld] expected 1 halt, got %0d", core_halt_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_pcpyld] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc, BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        // Register peek checks (sim-only).
        if (u_core.regfile[RT2] !== 32'hBBBB_BBBB) begin
            $error("[tb_ee_core_pcpyld] CASE 1: $t2 = 0x%08h (expected 0xBBBBBBBB, the rt value)",
                   u_core.regfile[RT2]);
            errors = errors + 1;
        end
        if (u_core.regfile[RT3] !== 32'hCAFE_F00D) begin
            $error("[tb_ee_core_pcpyld] CASE 2: $t3 = 0x%08h (expected 0xCAFEF00D, the rt value — NOT rs=0xDEADBEEF)",
                   u_core.regfile[RT3]);
            errors = errors + 1;
        end

        $display("[tb_ee_core_pcpyld] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);
        $display("[tb_ee_core_pcpyld]   $t2=0x%08h $t3=0x%08h",
                 u_core.regfile[RT2], u_core.regfile[RT3]);

        if (errors == 0)
            $display("[tb_ee_core_pcpyld] PASS");
        else
            $display("[tb_ee_core_pcpyld] FAIL");
        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_pcpyld] timeout");
        $finish;
    end

endmodule : tb_ee_core_pcpyld
