// retroDE_ps2 — tb_ee_core_bnel
//
// Ch277 — Focused TB for MIPS-II BNEL (Branch on Not Equal Likely),
// opcode 0x15. Mirror of tb_ee_core_beql with the inverted condition.
// qbert.elf hits this at PC 0x00112C7C inside a stdlib-style function
// body (instr 0x54400019 = `bnel $v0, $0, +25*4`).
//
// Cases:
//   1. BNEL TAKEN ($t0 != $t1): branch reaches target; delay slot
//      executes (writes sentinel into $t5). $t6 = 0xCAFE at target.
//   2. BNEL NOT-TAKEN ($t2 == $t3): delay slot SQUASHED. Inline BNE
//      check verifies $t5 stayed at 0xBEEF0000 (delay did NOT fire).
//   3. BNE NOT-TAKEN cross-check (same operands, plain BNE): BNE
//      delay slot DOES execute; $t5 = 0xBABE0CAB. Proves BNEL
//      differs.
//
// Strict mode ON. Final PC = PASS slot.

`timescale 1ns/1ps

module tb_ee_core_bnel;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 4 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR   = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA   = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    // Slot layout — mirror of tb_ee_core_beql.
    // Case 1: BNEL taken. $t0=5, $t1=7 (differ) → taken.
    localparam int B_ORI_T0_5      = BOOTSTRAP_SLOT + 0;
    localparam int B_ORI_T1_7      = BOOTSTRAP_SLOT + 1;
    localparam int B_LUI_T5_DEAD   = BOOTSTRAP_SLOT + 2;
    localparam int B_BNEL_TAKEN    = BOOTSTRAP_SLOT + 3;
    localparam int B_DS_TAKEN      = BOOTSTRAP_SLOT + 4;
    localparam int B_FALL_TAKEN_A  = BOOTSTRAP_SLOT + 5;
    localparam int B_FALL_TAKEN_B  = BOOTSTRAP_SLOT + 6;
    localparam int B_FALL_TAKEN_C  = BOOTSTRAP_SLOT + 7;
    localparam int B_CASE1_LAND    = BOOTSTRAP_SLOT + 8;

    // Case 2: BNEL NOT-TAKEN ($t2 == $t3) → squash.
    localparam int B_LUI_T5_BEEF   = BOOTSTRAP_SLOT + 9;
    localparam int B_ORI_T2_3      = BOOTSTRAP_SLOT + 10;
    localparam int B_ORI_T3_3      = BOOTSTRAP_SLOT + 11;  // $t3 = 3 (equal to $t2)
    localparam int B_BNEL_NOTAKEN  = BOOTSTRAP_SLOT + 12;
    localparam int B_DS_NOTAKEN    = BOOTSTRAP_SLOT + 13;
    localparam int B_ORI_T7_CASE2  = BOOTSTRAP_SLOT + 14;
    localparam int B_LUI_T4_BEEF   = BOOTSTRAP_SLOT + 15;
    localparam int B_BNE_T5_CHECK  = BOOTSTRAP_SLOT + 16;
    localparam int B_DS_T5_CHECK   = BOOTSTRAP_SLOT + 17;

    // Case 3: BNE not-taken cross-check.
    localparam int B_LUI_T5_BABE   = BOOTSTRAP_SLOT + 18;
    localparam int B_BNE_NOTAKEN   = BOOTSTRAP_SLOT + 19;
    localparam int B_DS_BNE_NOTK   = BOOTSTRAP_SLOT + 20;
    localparam int B_ORI_T8_CASE3  = BOOTSTRAP_SLOT + 21;

    localparam int B_PASS          = BOOTSTRAP_SLOT + 22;
    localparam int B_FAIL          = BOOTSTRAP_SLOT + 23;

    localparam logic [5:0] OP_J     = 6'h02;
    localparam logic [5:0] OP_BEQ   = 6'h04;
    localparam logic [5:0] OP_BNE   = 6'h05;
    localparam logic [5:0] OP_ORI   = 6'h0D;
    localparam logic [5:0] OP_LUI   = 6'h0F;
    localparam logic [5:0] OP_BNEL  = 6'h15;

    localparam int RT0 = 8;
    localparam int RT1 = 9;
    localparam int RT2 = 10;
    localparam int RT3 = 11;
    localparam int RT4 = 12;
    localparam int RT5 = 13;
    localparam int RT6 = 14;
    localparam int RT7 = 15;
    localparam int RT8 = 24;

    logic clk, rst_n;
    initial clk = 1'b0;
    always #5 clk = ~clk;

    logic        core_go, core_halt, core_trap;
    logic [31:0] core_pc, core_trap_pc, core_trap_instr;
    logic        ee_rd_en, ee_rd_valid, ee_wr_en;
    logic [31:0] ee_rd_addr, ee_rd_data, ee_wr_addr, ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(.STRICT_UNSUPPORTED(1'b1)) u_core (
        .clk(clk), .rst_n(rst_n), .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(1'b0),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    logic         bios_rd_en, bios_rd_valid;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         ee_ram_rd_en, ee_ram_rd_valid, ee_ram_wr_en;
    logic [24:0]  ee_ram_rd_addr, ee_ram_wr_addr;
    logic [127:0] ee_ram_rd_data, ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_bnel_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events, core_halt_events, core_trap_events, errors;
    initial begin
        core_retired_events = 0; core_halt_events = 0;
        core_trap_events = 0; errors = 0;
    end
    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0) core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0) core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask
    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction
    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction
    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    initial begin
        rst_n = 1'b0; core_go = 1'b0;
        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_word(RESET_SLOT,     enc_j(BOOTSTRAP_VA));
        bios_word(RESET_SLOT + 1, 32'd0);

        // ===== Case 1: BNEL TAKEN. $t0=5, $t1=7 (differ) =====
        bios_word(B_ORI_T0_5,    enc_i(OP_ORI, 0, RT0, 16'h0005));
        bios_word(B_ORI_T1_7,    enc_i(OP_ORI, 0, RT1, 16'h0007));
        bios_word(B_LUI_T5_DEAD, enc_i(OP_LUI, 0, RT5, 16'hDEAD));
        bios_word(B_BNEL_TAKEN,  enc_i(OP_BNEL, RT0, RT1,
                                       branch_imm(B_BNEL_TAKEN, B_CASE1_LAND)));
        bios_word(B_DS_TAKEN,    enc_i(OP_ORI, RT5, RT5, 16'h0011));   // delay fires
        bios_word(B_FALL_TAKEN_A, enc_i(OP_ORI, RT5, RT5, 16'h2200));  // skipped
        bios_word(B_FALL_TAKEN_B, enc_i(OP_ORI, RT5, RT5, 16'h4400));
        bios_word(B_FALL_TAKEN_C, enc_i(OP_ORI, RT5, RT5, 16'h8800));
        bios_word(B_CASE1_LAND,   enc_i(OP_ORI, 0, RT6, 16'hCAFE));

        // ===== Case 2: BNEL NOT-TAKEN. $t2=$t3=3 (equal) → squash =====
        bios_word(B_LUI_T5_BEEF, enc_i(OP_LUI, 0, RT5, 16'hBEEF));   // $t5 = 0xBEEF0000
        bios_word(B_ORI_T2_3,    enc_i(OP_ORI, 0, RT2, 16'h0003));
        bios_word(B_ORI_T3_3,    enc_i(OP_ORI, 0, RT3, 16'h0003));   // equal → BNEL not taken
        bios_word(B_BNEL_NOTAKEN, enc_i(OP_BNEL, RT2, RT3,
                                        branch_imm(B_BNEL_NOTAKEN, B_FAIL)));
        // OR-INTO so delay-fired (bug) makes $t5 = 0xBEEF0BAD;
        // delay-squashed (correct) leaves $t5 = 0xBEEF0000.
        bios_word(B_DS_NOTAKEN,  enc_i(OP_ORI, RT5, RT5, 16'h0BAD));
        bios_word(B_ORI_T7_CASE2, enc_i(OP_ORI, 0, RT7, 16'h2222));
        // Verify $t5 == 0xBEEF0000 (delay was squashed).
        bios_word(B_LUI_T4_BEEF,  enc_i(OP_LUI, 0, RT4, 16'hBEEF));
        bios_word(B_BNE_T5_CHECK, enc_i(OP_BNE, RT5, RT4,
                                        branch_imm(B_BNE_T5_CHECK, B_FAIL)));
        bios_word(B_DS_T5_CHECK,  32'd0);

        // ===== Case 3: BNE NOT-TAKEN cross-check. $t2=$t3 →  BNE not-taken
        // (same operands). BNE's delay slot DOES execute, so $t5 gets
        // 0x0CAB ORed into the low half.
        bios_word(B_LUI_T5_BABE, enc_i(OP_LUI, 0, RT5, 16'hBABE));   // $t5 = 0xBABE0000
        bios_word(B_BNE_NOTAKEN, enc_i(OP_BNE, RT2, RT3,
                                       branch_imm(B_BNE_NOTAKEN, B_FAIL)));
        bios_word(B_DS_BNE_NOTK, enc_i(OP_ORI, RT5, RT5, 16'h0CAB));
        bios_word(B_ORI_T8_CASE3, enc_i(OP_ORI, 0, RT8, 16'h3333));

        bios_word(B_PASS, 32'h0000_000C);
        bios_word(B_FAIL, 32'h0000_000C);

        @(negedge clk); core_go = 1'b1;
        @(negedge clk); core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        if (core_trap_events != 0) begin
            $error("[tb_ee_core_bnel] unexpected trap: %0d trap_pc=0x%08h instr=0x%08h",
                   core_trap_events, core_trap_pc, core_trap_instr);
            errors = errors + 1;
        end
        if (core_halt_events != 1) begin
            $error("[tb_ee_core_bnel] expected 1 halt, got %0d", core_halt_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_bnel] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc, BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        // Case 1 (BNEL taken): we reached the target → $t6=0xCAFE.
        if (u_core.regfile[RT6] !== 32'h0000_CAFE) begin
            $error("[tb_ee_core_bnel] CASE 1 (BNEL taken): $t6 = 0x%08h (expected 0xCAFE)",
                   u_core.regfile[RT6]);
            errors = errors + 1;
        end

        // Case 2 (BNEL not-taken): $t7=0x2222 proves PC+8 landing.
        // The inline BNE check above proved $t5 was preserved.
        if (u_core.regfile[RT7] !== 32'h0000_2222) begin
            $error("[tb_ee_core_bnel] CASE 2 (BNEL not-taken): $t7 = 0x%08h (expected 0x2222)",
                   u_core.regfile[RT7]);
            errors = errors + 1;
        end

        // Case 3 (BNE not-taken cross-check): BNE delay fired so
        // $t5 = 0xBABE0CAB; $t8 = 0x3333.
        if (u_core.regfile[RT5] !== 32'hBABE_0CAB) begin
            $error("[tb_ee_core_bnel] CASE 3 (BNE not-taken): $t5 = 0x%08h (expected 0xBABE0CAB)",
                   u_core.regfile[RT5]);
            errors = errors + 1;
        end
        if (u_core.regfile[RT8] !== 32'h0000_3333) begin
            $error("[tb_ee_core_bnel] CASE 3 (BNE not-taken): $t8 = 0x%08h (expected 0x3333)",
                   u_core.regfile[RT8]);
            errors = errors + 1;
        end

        $display("[tb_ee_core_bnel] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);
        $display("[tb_ee_core_bnel]   $t5=0x%08h $t6=0x%08h $t7=0x%08h $t8=0x%08h",
                 u_core.regfile[RT5], u_core.regfile[RT6],
                 u_core.regfile[RT7], u_core.regfile[RT8]);

        if (errors == 0)
            $display("[tb_ee_core_bnel] PASS");
        else
            $display("[tb_ee_core_bnel] FAIL");
        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_bnel] timeout");
        $finish;
    end

endmodule : tb_ee_core_bnel
