// retroDE_ps2 — tb_ee_core_rtype_logic
//
// Fourth evidence-driven opcode growth. Real-BIOS trapped on OR
// (SPECIAL func 0x25) at 0xBFC0_2074 right after ANDI landed. Rather
// than land just OR and iterate four separate chapters (AND/OR/XOR/NOR
// will all hit within a handful of BIOS instructions of each other),
// this TB covers the whole R-type logic family in one pass — they
// share the exact same R-type ALU plumbing and Codex's no-regret
// pre-batch review explicitly grouped them.
//
// R-type has a different destination-register slot than the I-type
// ALU ops covered so far: rd (bits [15:11]), not rt. This TB exists
// specifically to catch the "wrote to rt instead of rd" class of
// bugs alongside the functional op checks.
//
// Probes (all with $2 = 0xCAFE_F00D, $3 = 0x1234_5678):
//   and $4, $2, $3   → 0x0234_5008
//   or  $5, $2, $3   → 0xDAFE_F67D
//   xor $6, $2, $3   → 0xD8CA_A675
//   nor $7, $2, $3   → 0x2501_0982
//
// Same FAIL/PASS SYSCALL shape. STRICT_UNSUPPORTED=1 — if any op's
// decode path is wrong, the trap surfaces it.

`timescale 1ns/1ps

module tb_ee_core_rtype_logic;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 4 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR  = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA  = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    // Expected results from $2=0xCAFE_F00D, $3=0x1234_5678
    localparam logic [31:0] EXPECT_AND = 32'h0234_5008;
    localparam logic [31:0] EXPECT_OR  = 32'hDAFE_F67D;
    localparam logic [31:0] EXPECT_XOR = 32'hD8CA_A675;
    localparam logic [31:0] EXPECT_NOR = 32'h2501_0982;

    // Bootstrap slot layout
    localparam int B_LUI_2    = BOOTSTRAP_SLOT + 0;
    localparam int B_ORI_2    = BOOTSTRAP_SLOT + 1;
    localparam int B_LUI_3    = BOOTSTRAP_SLOT + 2;
    localparam int B_ORI_3    = BOOTSTRAP_SLOT + 3;
    localparam int B_AND      = BOOTSTRAP_SLOT + 4;    // $4 = $2 & $3
    localparam int B_OR       = BOOTSTRAP_SLOT + 5;    // $5 = $2 | $3
    localparam int B_XOR      = BOOTSTRAP_SLOT + 6;    // $6 = $2 ^ $3
    localparam int B_NOR      = BOOTSTRAP_SLOT + 7;    // $7 = ~($2 | $3)
    // Expected-value regs
    localparam int B_LUI_E1   = BOOTSTRAP_SLOT + 8;
    localparam int B_ORI_E1   = BOOTSTRAP_SLOT + 9;    // $10 = EXPECT_AND
    localparam int B_BNE_AND  = BOOTSTRAP_SLOT + 10;
    localparam int B_DS_AND   = BOOTSTRAP_SLOT + 11;
    localparam int B_LUI_E2   = BOOTSTRAP_SLOT + 12;
    localparam int B_ORI_E2   = BOOTSTRAP_SLOT + 13;   // $11 = EXPECT_OR
    localparam int B_BNE_OR   = BOOTSTRAP_SLOT + 14;
    localparam int B_DS_OR    = BOOTSTRAP_SLOT + 15;
    localparam int B_LUI_E3   = BOOTSTRAP_SLOT + 16;
    localparam int B_ORI_E3   = BOOTSTRAP_SLOT + 17;   // $12 = EXPECT_XOR
    localparam int B_BNE_XOR  = BOOTSTRAP_SLOT + 18;
    localparam int B_DS_XOR   = BOOTSTRAP_SLOT + 19;
    localparam int B_LUI_E4   = BOOTSTRAP_SLOT + 20;
    localparam int B_ORI_E4   = BOOTSTRAP_SLOT + 21;   // $13 = EXPECT_NOR
    localparam int B_BNE_NOR  = BOOTSTRAP_SLOT + 22;
    localparam int B_DS_NOR   = BOOTSTRAP_SLOT + 23;
    localparam int B_PASS     = BOOTSTRAP_SLOT + 24;
    localparam int B_FAIL     = BOOTSTRAP_SLOT + 25;

    localparam logic [5:0] OP_SPECIAL = 6'h00;
    localparam logic [5:0] OP_J       = 6'h02;
    localparam logic [5:0] OP_BNE     = 6'h05;
    localparam logic [5:0] OP_ORI     = 6'h0D;
    localparam logic [5:0] OP_LUI     = 6'h0F;
    localparam logic [5:0] FUNC_AND   = 6'h24;
    localparam logic [5:0] FUNC_OR    = 6'h25;
    localparam logic [5:0] FUNC_XOR   = 6'h26;
    localparam logic [5:0] FUNC_NOR   = 6'h27;

    logic clk;
    logic rst_n;

    initial clk = 1'b0;
    always #5 clk = ~clk;

    // ------------------------------------------------------------------
    // EE core — strict mode ON
    // ------------------------------------------------------------------

    logic        core_go;
    logic        core_halt;
    logic [31:0] core_pc;
    logic        core_trap;
    logic [31:0] core_trap_pc;
    logic [31:0] core_trap_instr;

    logic        ee_rd_en;
    logic [31:0] ee_rd_addr;
    logic [31:0] ee_rd_data;
    logic        ee_rd_valid;

    logic        ee_wr_en;
    logic [31:0] ee_wr_addr;
    logic [31:0] ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic        ee_cpu_irq;
    assign ee_cpu_irq = 1'b0;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(
        .STRICT_UNSUPPORTED(1'b1)
    ) u_core (
        .clk(clk), .rst_n(rst_n),
        .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(ee_cpu_irq),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    // ------------------------------------------------------------------
    // Map + RAM + BIOS
    // ------------------------------------------------------------------

    logic         bios_rd_en;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         bios_rd_valid;

    logic         ee_ram_rd_en;
    logic [24:0]  ee_ram_rd_addr;
    logic [127:0] ee_ram_rd_data;
    logic         ee_ram_rd_valid;
    logic         ee_ram_wr_en;
    logic [24:0]  ee_ram_wr_addr;
    logic [127:0] ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_rtype_logic_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    // ------------------------------------------------------------------
    // Observers
    // ------------------------------------------------------------------

    int core_retired_events;
    int core_halt_events;
    int core_trap_events;
    int errors;

    initial begin
        core_retired_events = 0;
        core_halt_events    = 0;
        core_trap_events    = 0;
        errors              = 0;
    end

    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0)
                core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0)
                core_trap_events <= core_trap_events + 1;
        end
    end

    // ------------------------------------------------------------------
    // BIOS preload helpers
    // ------------------------------------------------------------------

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask

    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction

    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction

    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    // R-type SPECIAL encoding: opcode(6)=0 | rs(5) | rt(5) | rd(5) |
    // sa(5)=0 | func(6)
    function automatic logic [31:0] enc_rtype(input logic [5:0] fn,
                                              input int rd, input int rs,
                                              input int rt);
        return {OP_SPECIAL, rs[4:0], rt[4:0], rd[4:0], 5'd0, fn};
    endfunction

    task automatic bios_j(input int slot, input logic [31:0] tgt);
        bios_word(slot, enc_j(tgt));
    endtask
    task automatic bios_nop(input int slot);
        bios_word(slot, 32'd0);
    endtask
    task automatic bios_lui(input int slot, input int rt,
                            input logic [15:0] imm);
        bios_word(slot, enc_i(OP_LUI, 0, rt, imm));
    endtask
    task automatic bios_ori(input int slot, input int rt, input int rs,
                            input logic [15:0] imm);
        bios_word(slot, enc_i(OP_ORI, rs, rt, imm));
    endtask
    task automatic bios_bne(input int slot, input int rs, input int rt,
                            input int target_slot);
        bios_word(slot, enc_i(OP_BNE, rs, rt,
                              branch_imm(slot, target_slot)));
    endtask
    task automatic bios_and(input int slot, input int rd, input int rs, input int rt);
        bios_word(slot, enc_rtype(FUNC_AND, rd, rs, rt));
    endtask
    task automatic bios_or (input int slot, input int rd, input int rs, input int rt);
        bios_word(slot, enc_rtype(FUNC_OR,  rd, rs, rt));
    endtask
    task automatic bios_xor(input int slot, input int rd, input int rs, input int rt);
        bios_word(slot, enc_rtype(FUNC_XOR, rd, rs, rt));
    endtask
    task automatic bios_nor(input int slot, input int rd, input int rs, input int rt);
        bios_word(slot, enc_rtype(FUNC_NOR, rd, rs, rt));
    endtask
    task automatic bios_syscall(input int slot);
        bios_word(slot, 32'h0000_000C);
    endtask

    // ------------------------------------------------------------------
    // Stimulus
    // ------------------------------------------------------------------

    initial begin
        rst_n   = 1'b0;
        core_go = 1'b0;

        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_j  (RESET_SLOT,     BOOTSTRAP_VA);
        bios_nop(RESET_SLOT + 1);

        // Operands
        bios_lui(B_LUI_2, 2, 16'hCAFE);
        bios_ori(B_ORI_2, 2, 2, 16'hF00D);             // $2 = 0xCAFE_F00D
        bios_lui(B_LUI_3, 3, 16'h1234);
        bios_ori(B_ORI_3, 3, 3, 16'h5678);             // $3 = 0x1234_5678

        // R-type logic probes
        bios_and(B_AND, 4, 2, 3);                      // $4 = $2 & $3
        bios_or (B_OR,  5, 2, 3);                      // $5 = $2 | $3
        bios_xor(B_XOR, 6, 2, 3);                      // $6 = $2 ^ $3
        bios_nor(B_NOR, 7, 2, 3);                      // $7 = ~($2 | $3)

        // Check AND
        bios_lui(B_LUI_E1, 10, EXPECT_AND[31:16]);
        bios_ori(B_ORI_E1, 10, 10, EXPECT_AND[15:0]);  // $10 = EXPECT_AND
        bios_bne(B_BNE_AND, 4, 10, B_FAIL);
        bios_nop(B_DS_AND);

        // Check OR
        bios_lui(B_LUI_E2, 11, EXPECT_OR[31:16]);
        bios_ori(B_ORI_E2, 11, 11, EXPECT_OR[15:0]);   // $11 = EXPECT_OR
        bios_bne(B_BNE_OR, 5, 11, B_FAIL);
        bios_nop(B_DS_OR);

        // Check XOR
        bios_lui(B_LUI_E3, 12, EXPECT_XOR[31:16]);
        bios_ori(B_ORI_E3, 12, 12, EXPECT_XOR[15:0]);  // $12 = EXPECT_XOR
        bios_bne(B_BNE_XOR, 6, 12, B_FAIL);
        bios_nop(B_DS_XOR);

        // Check NOR
        bios_lui(B_LUI_E4, 13, EXPECT_NOR[31:16]);
        bios_ori(B_ORI_E4, 13, 13, EXPECT_NOR[15:0]);  // $13 = EXPECT_NOR
        bios_bne(B_BNE_NOR, 7, 13, B_FAIL);
        bios_nop(B_DS_NOR);

        bios_syscall(B_PASS);
        bios_syscall(B_FAIL);

        @(negedge clk);
        core_go = 1'b1;
        @(negedge clk);
        core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        // --------------------------------------------------------------
        // Checks
        // --------------------------------------------------------------
        if (core_halt_events != 1) begin
            $error("[tb_ee_core_rtype_logic] expected 1 halt, got %0d",
                   core_halt_events);
            errors = errors + 1;
        end
        if (core_trap_events != 0) begin
            $error("[tb_ee_core_rtype_logic] unexpected strict trap: %0d",
                   core_trap_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_rtype_logic] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc,
                   BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        $display("[tb_ee_core_rtype_logic] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);

        if (errors == 0 &&
            core_halt_events == 1 &&
            core_trap_events == 0 &&
            core_pc == BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2))
            $display("[tb_ee_core_rtype_logic] PASS");
        else
            $display("[tb_ee_core_rtype_logic] FAIL");

        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_rtype_logic] timeout");
        $finish;
    end

endmodule : tb_ee_core_rtype_logic
