<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2026.05.11.21:04:30"
 outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Agilex 5"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="A5EB013BB23BE4SCS"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="4"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_BOARD"
     type="String"
     defaultValue="default"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_REF_CLK_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_REF_CLK_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_REF_CLK_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <interface name="io96b0_to_hps" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="s0_noc_axi4lite_clock"
       direction="output"
       role="ch0_axil_clk"
       width="1" />
   <port
       name="s0_noc_axi4lite_reset_n"
       direction="output"
       role="ch0_axil_reset_n"
       width="1" />
   <port
       name="s0_noc_axi4lite_awaddr"
       direction="input"
       role="ch0_axil_awaddr"
       width="27" />
   <port
       name="s0_noc_axi4lite_awvalid"
       direction="input"
       role="ch0_axil_awvalid"
       width="1" />
   <port
       name="s0_noc_axi4lite_awready"
       direction="output"
       role="ch0_axil_awready"
       width="1" />
   <port
       name="s0_noc_axi4lite_araddr"
       direction="input"
       role="ch0_axil_araddr"
       width="27" />
   <port
       name="s0_noc_axi4lite_arvalid"
       direction="input"
       role="ch0_axil_arvalid"
       width="1" />
   <port
       name="s0_noc_axi4lite_arready"
       direction="output"
       role="ch0_axil_arready"
       width="1" />
   <port
       name="s0_noc_axi4lite_wdata"
       direction="input"
       role="ch0_axil_wdata"
       width="32" />
   <port
       name="s0_noc_axi4lite_wvalid"
       direction="input"
       role="ch0_axil_wvalid"
       width="1" />
   <port
       name="s0_noc_axi4lite_wready"
       direction="output"
       role="ch0_axil_wready"
       width="1" />
   <port
       name="s0_noc_axi4lite_rresp"
       direction="output"
       role="ch0_axil_rresp"
       width="2" />
   <port
       name="s0_noc_axi4lite_rdata"
       direction="output"
       role="ch0_axil_rdata"
       width="32" />
   <port
       name="s0_noc_axi4lite_rvalid"
       direction="output"
       role="ch0_axil_rvalid"
       width="1" />
   <port
       name="s0_noc_axi4lite_rready"
       direction="input"
       role="ch0_axil_rready"
       width="1" />
   <port
       name="s0_noc_axi4lite_bresp"
       direction="output"
       role="ch0_axil_bresp"
       width="2" />
   <port
       name="s0_noc_axi4lite_bvalid"
       direction="output"
       role="ch0_axil_bvalid"
       width="1" />
   <port
       name="s0_noc_axi4lite_bready"
       direction="input"
       role="ch0_axil_bready"
       width="1" />
   <port
       name="s0_noc_axi4lite_awprot"
       direction="input"
       role="ch0_axil_awprot"
       width="3" />
   <port
       name="s0_noc_axi4lite_arprot"
       direction="input"
       role="ch0_axil_arprot"
       width="3" />
   <port
       name="s0_noc_axi4lite_wstrb"
       direction="input"
       role="ch0_axil_wstrb"
       width="4" />
   <port
       name="s0_axi4_awaddr"
       direction="input"
       role="axi4_ch0_awaddr"
       width="40" />
   <port
       name="s0_axi4_awburst"
       direction="input"
       role="axi4_ch0_awburst"
       width="2" />
   <port name="s0_axi4_awid" direction="input" role="axi4_ch0_awid" width="7" />
   <port
       name="s0_axi4_awlen"
       direction="input"
       role="axi4_ch0_awlen"
       width="8" />
   <port
       name="s0_axi4_awlock"
       direction="input"
       role="axi4_ch0_awlock"
       width="1" />
   <port
       name="s0_axi4_awqos"
       direction="input"
       role="axi4_ch0_awqos"
       width="4" />
   <port
       name="s0_axi4_awsize"
       direction="input"
       role="axi4_ch0_awsize"
       width="3" />
   <port
       name="s0_axi4_awvalid"
       direction="input"
       role="axi4_ch0_awvalid"
       width="1" />
   <port
       name="s0_axi4_awuser"
       direction="input"
       role="axi4_ch0_awuser"
       width="14" />
   <port
       name="s0_axi4_awprot"
       direction="input"
       role="axi4_ch0_awprot"
       width="3" />
   <port
       name="s0_axi4_awready"
       direction="output"
       role="axi4_ch0_awready"
       width="1" />
   <port
       name="s0_axi4_araddr"
       direction="input"
       role="axi4_ch0_araddr"
       width="40" />
   <port
       name="s0_axi4_arburst"
       direction="input"
       role="axi4_ch0_arburst"
       width="2" />
   <port name="s0_axi4_arid" direction="input" role="axi4_ch0_arid" width="7" />
   <port
       name="s0_axi4_arlen"
       direction="input"
       role="axi4_ch0_arlen"
       width="8" />
   <port
       name="s0_axi4_arlock"
       direction="input"
       role="axi4_ch0_arlock"
       width="1" />
   <port
       name="s0_axi4_arqos"
       direction="input"
       role="axi4_ch0_arqos"
       width="4" />
   <port
       name="s0_axi4_arsize"
       direction="input"
       role="axi4_ch0_arsize"
       width="3" />
   <port
       name="s0_axi4_arvalid"
       direction="input"
       role="axi4_ch0_arvalid"
       width="1" />
   <port
       name="s0_axi4_aruser"
       direction="input"
       role="axi4_ch0_aruser"
       width="14" />
   <port
       name="s0_axi4_arprot"
       direction="input"
       role="axi4_ch0_arprot"
       width="3" />
   <port
       name="s0_axi4_arready"
       direction="output"
       role="axi4_ch0_arready"
       width="1" />
   <port
       name="s0_axi4_wdata"
       direction="input"
       role="axi4_ch0_wdata"
       width="256" />
   <port
       name="s0_axi4_wstrb"
       direction="input"
       role="axi4_ch0_wstrb"
       width="32" />
   <port
       name="s0_axi4_wlast"
       direction="input"
       role="axi4_ch0_wlast"
       width="1" />
   <port
       name="s0_axi4_wvalid"
       direction="input"
       role="axi4_ch0_wvalid"
       width="1" />
   <port
       name="s0_axi4_wready"
       direction="output"
       role="axi4_ch0_wready"
       width="1" />
   <port
       name="s0_axi4_bready"
       direction="input"
       role="axi4_ch0_bready"
       width="1" />
   <port name="s0_axi4_bid" direction="output" role="axi4_ch0_bid" width="7" />
   <port
       name="s0_axi4_bresp"
       direction="output"
       role="axi4_ch0_bresp"
       width="2" />
   <port
       name="s0_axi4_bvalid"
       direction="output"
       role="axi4_ch0_bvalid"
       width="1" />
   <port
       name="s0_axi4_rready"
       direction="input"
       role="axi4_ch0_rready"
       width="1" />
   <port
       name="s0_axi4_rdata"
       direction="output"
       role="axi4_ch0_rdata"
       width="256" />
   <port name="s0_axi4_rid" direction="output" role="axi4_ch0_rid" width="7" />
   <port
       name="s0_axi4_rlast"
       direction="output"
       role="axi4_ch0_rlast"
       width="1" />
   <port
       name="s0_axi4_rresp"
       direction="output"
       role="axi4_ch0_rresp"
       width="2" />
   <port
       name="s0_axi4_rvalid"
       direction="output"
       role="axi4_ch0_rvalid"
       width="1" />
   <port name="noc_aclk_0" direction="output" role="axi4_ch0_clk" width="1" />
   <port
       name="noc_rst_n_0"
       direction="output"
       role="axi4_ch0_reset_n"
       width="1" />
   <port
       name="s0_axi4_wuser"
       direction="input"
       role="axi4_ch0_wuser"
       width="32" />
   <port
       name="s0_axi4_ruser"
       direction="output"
       role="axi4_ch0_ruser"
       width="32" />
  </interface>
  <interface name="mem_0" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="mem_0_cs" direction="output" role="mem_cs" width="1" />
   <port name="mem_0_ca" direction="output" role="mem_ca" width="6" />
   <port name="mem_0_cke" direction="output" role="mem_cke" width="1" />
   <port name="mem_0_dq" direction="bidir" role="mem_dq" width="32" />
   <port name="mem_0_dqs_t" direction="bidir" role="mem_dqs_t" width="4" />
   <port name="mem_0_dqs_c" direction="bidir" role="mem_dqs_c" width="4" />
   <port name="mem_0_dmi" direction="bidir" role="mem_dmi" width="4" />
  </interface>
  <interface name="mem_ck_0" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="mem_0_ck_t" direction="output" role="mem_ck_t" width="1" />
   <port name="mem_0_ck_c" direction="output" role="mem_ck_c" width="1" />
  </interface>
  <interface name="mem_reset_n" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="mem_0_reset_n" direction="output" role="mem_reset_n" width="1" />
  </interface>
  <interface name="oct_0" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port name="oct_rzqin_0" direction="input" role="oct_rzqin" width="1" />
  </interface>
  <interface name="ref_clk" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="ref_clk" direction="input" role="clk" width="1" />
  </interface>
 </perimeter>
 <entity kind="emif_io96b_hps" version="1.0" name="emif_io96b_hps">
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="AUTO_BOARD" value="default" />
  <parameter name="AUTO_REF_CLK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_REF_CLK_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_REF_CLK_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/synth/emif_io96b_hps.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/synth/emif_io96b_hps.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps.ip" />
  </sourceFiles>
  <childSourceFiles/>
  <messages>
   <message level="Info" culprit="emif_io96b_hps">"Generating: emif_io96b_hps"</message>
   <message level="Info" culprit="emif_io96b_hps">"Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"</message>
   <message level="Debug" culprit="emif_io96b_hps">validation time: 1.08 ms</message>
   <message level="Debug">set_validation_property AUTOMATIC_VALIDATION false</message>
   <message level="Debug">set_project_property DEVICE_FAMILY Agilex 5</message>
   <message level="Debug">The device and speed grade is changed to the defaults of the device family, Agilex 5.</message>
   <message level="Debug">set_project_property DEVICE A5EB013BB23BE4SCS</message>
   <message level="Debug">remove_dangling_connections </message>
   <message level="Debug">get_connections </message>
   <message level="Debug">remove_connections </message>
   <message level="Debug">get_interfaces </message>
   <message level="Debug">remove_interfaces </message>
   <message level="Debug">get_instances </message>
   <message level="Debug">set_instance_property emif_0_ddr4comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_ddr5comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_ddr5dimm ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr5 ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr4comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr5comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr5dimm ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_lpddr4 ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_lpddr5 ENABLED false</message>
   <message level="Debug">set_instance_property refclk_bridge ENABLED false</message>
   <message level="Debug">set_instance_property refclk_gpio ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED true</message>
   <message level="Debug">load_component emif_0_lpddr4</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">get_component_parameter_values PHY_MAINBAND_ACCESS_MODE INSTANCE_ID PHY_TERM_X_REFCLK_IO_STD_TYPE PHY_TERM_X_R_T_REFCLK_INPUT_OHM MEM_CHANNEL_CAPACITY_GBITS</message>
   <message level="Debug">set_component_parameter_values MEM_CHANNEL_DATA_DQ_WIDTH 32</message>
   <message level="Debug">set_component_parameter_value PHY_AC_PLACEMENT BOT</message>
   <message level="Debug">set_component_parameter_value MEM_NUM_CHANNELS 1</message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED true</message>
   <message level="Debug">load_component emif_0_lpddr4</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">get_component_parameters </message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_MARGIN</message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_REQ</message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_WEQ</message>
   <message level="Debug">get_component_parameter_value ANALOG_PARAM_DERIVATION_PARAM_NAME</message>
   <message level="Debug">get_component_parameter_value AXI4_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value CTRL_ALL_STRB_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_AUTO_PRECHARGE_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_DM_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_ECC_AUTOCORRECT_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_ECC_INLINE_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_PRIORITY_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_R_PRIORITY</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_W_PRIORITY</message>
   <message level="Debug">get_component_parameter_value CTRL_PERFORMANCE_PROFILE</message>
   <message level="Debug">get_component_parameter_value CTRL_PLACEMENT_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_RD_DBI_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_SCRAMBLER_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_WR_DBI_EN</message>
   <message level="Debug">get_component_parameter_value DEBUG_PRINT_LEVEL</message>
   <message level="Debug">get_component_parameter_value DEBUG_TOOLS_EN</message>
   <message level="Debug">get_component_parameter_value DIAG_EXTRA_PARAMETERS</message>
   <message level="Debug">get_component_parameter_value DIAG_FORCE_SLIM_EN</message>
   <message level="Debug">get_component_parameter_value DIAG_HMC_ADDR_SWAP_EN</message>
   <message level="Debug">get_component_parameter_value EMIF_INST_NAME</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_CDC</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_SIM</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_SYNTH</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_HDL_FORMAT</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH0_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH1_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH2_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH3_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_INTERNAL_JAMB_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_CSR_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_PROGRAM</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_WIDE_IF</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value INSTANCE_ID</message>
   <message level="Debug">get_component_parameter_value IS_HPS</message>
   <message level="Debug">get_component_parameter_value JEDEC_OVERRIDE_TABLE_PARAM_NAME</message>
   <message level="Debug">get_component_parameter_value MEM_BANK_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CA_VREF</message>
   <message level="Debug">get_component_parameter_value MEM_CA_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_ADDR_NUM_BITS</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_CAPACITY_GBITS</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_CS_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_DATA_DQ_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CKE_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CK_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CL_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_COL_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CS_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CWL_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_DIE_DENSITY_GBITS</message>
   <message level="Debug">get_component_parameter_value MEM_DQ_PER_DQS</message>
   <message level="Debug">get_component_parameter_value MEM_DQ_VREF</message>
   <message level="Debug">get_component_parameter_value MEM_MINNUMREFSREQ</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_CHANNELS</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_CHANNELS_PER_IO96</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_IO96</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CA_COMM</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CA_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CK_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CS_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_IDLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_RON</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_TGT_WR</message>
   <message level="Debug">get_component_parameter_value MEM_OPERATING_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value MEM_OPERATING_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value MEM_PER_BANK_REF_EN</message>
   <message level="Debug">get_component_parameter_value MEM_RD_POSTAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_RD_PREAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_ROW_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_TCCD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKCKEH_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKCKEL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKEHCMD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKELCK_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKELCMD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCMDCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCSCKEH_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCSCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TDQSCK_MAX_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TDQSCK_MIN_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TECH_IS_X</message>
   <message level="Debug">get_component_parameter_value MEM_TESCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TFAW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRWCKEL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TPPD_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_TRAS_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRCD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRC_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TREFI_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TREFW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRFCAB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRFCPB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRPAB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRPPB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRRD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRTP_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TSR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TWR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TWTR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TXP_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TXSR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQCAL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQLAT_NS</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_CA_X_CA_RANGE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_CA_X_CA_VALUE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_DQ_X_RANGE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_DQ_X_VALUE</message>
   <message level="Debug">get_component_parameter_value MEM_WLS</message>
   <message level="Debug">get_component_parameter_value MEM_WR_POSTAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value NUM_IO96_IN_CHIP</message>
   <message level="Debug">get_component_parameter_value PHY_AC_PLACEMENT</message>
   <message level="Debug">get_component_parameter_value PHY_AC_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_CK_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_CS_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_DQ_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_MAINBAND_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_ADVANCED_SELECT_EN</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_SIDEBAND_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_SWIZZLE_MAP</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_AC_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_AC_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CK_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CK_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CS_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CS_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQS_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_VREF</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_GPIO_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_REFCLK_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_AC_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_CK_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_CS_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_DQ_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_DQ_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_GPIO_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_REFCLK_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PLACEMENT_SCHEMES</message>
   <message level="Debug">get_component_parameter_value S0_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S1_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S2_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S3_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value SYSINFO_BOARD</message>
   <message level="Debug">get_component_parameter_value SYSINFO_BOARD_TRAIT</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_BASE_DIE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_DIE_REVISIONS</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_FAMILY</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_GROUP</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_IOBANK_REVISION</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_POWER_MODEL</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_SPEEDGRADE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_TEMPERATURE_GRADE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_SUPPORTS_VID</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2R_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2R_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2W_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2W_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2R_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2R_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2W_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2W_SAMECS_CYC</message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property refclk_bridge ENABLED true</message>
   <message level="Debug">load_component refclk_bridge</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">set_component_parameter_values INTERFACES {refclk_in        clock    sink} {refclk_out       clock    source} {refclk_in_gpio   conduit  end} {refclk_out_gpio  conduit  start} PORTS {refclk_in        refclk_in         clk      input    1} {refclk_out       refclk_out        clk      output   1} {refclk_in_gpio   refclk_in_gpio    export   output   1} {refclk_out_gpio  refclk_out_gpio   export   input    1} CONNECTIONS {refclk_in        refclk_in_gpio} {refclk_out_gpio  refclk_out} CUSTOM_ELABORATION_COMMANDS </message>
   <message level="Debug">get_component_parameters </message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property refclk_gpio ENABLED true</message>
   <message level="Debug">sync_sysinfo_parameters refclk_gpio</message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_gpio</strong>]]></message>
   <message level="Debug">add_connection refclk_gpio.dout refclk_bridge.refclk_out_gpio</message>
   <message level="Debug">add_connection refclk_bridge.refclk_in_gpio refclk_gpio.pad_in</message>
   <message level="Debug">add_connection refclk_bridge.refclk_out emif_0_lpddr4.ref_clk</message>
   <message level="Debug">get_connections </message>
   <message level="Debug">get_interfaces </message>
   <message level="Debug">get_wirelevel_expressions </message>
   <message level="Debug">get_instances </message>
   <message level="Debug">get_instance_property emif_0_ddr4comp ENABLED</message>
   <message level="Debug">get_instance_property emif_0_ddr5comp ENABLED</message>
   <message level="Debug">get_instance_property emif_0_ddr5dimm ENABLED</message>
   <message level="Debug">get_instance_property emif_0_lpddr4 ENABLED</message>
   <message level="Debug">get_instance_interfaces emif_0_lpddr4</message>
   <message level="Debug">get_instance_property emif_0_lpddr5 ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr4comp ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr5comp ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr5dimm ENABLED</message>
   <message level="Debug">get_instance_property emif_1_lpddr4 ENABLED</message>
   <message level="Debug">get_instance_property emif_1_lpddr5 ENABLED</message>
   <message level="Debug">get_instance_property refclk_bridge ENABLED</message>
   <message level="Debug">get_instance_interfaces refclk_bridge</message>
   <message level="Debug">get_instance_property refclk_gpio ENABLED</message>
   <message level="Debug">get_instance_interfaces refclk_gpio</message>
   <message level="Debug">add_interface io96b0_to_hps  </message>
   <message level="Debug">set_interface_property io96b0_to_hps EXPORT_OF emif_0_lpddr4.io96b0_to_hps</message>
   <message level="Debug">get_interface_ports io96b0_to_hps</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 io96b0_to_hps</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_clock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_reset_n ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awaddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_araddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wstrb ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awaddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awburst ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awlen ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awlock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awqos ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awsize ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awuser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_araddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arburst ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arlen ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arlock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arqos ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arsize ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_aruser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wstrb ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wlast ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rlast ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps noc_aclk_0 ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps noc_rst_n_0 ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wuser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_ruser ROLE</message>
   <message level="Debug">set_interface_ports_property io96b0_to_hps NAME io96b0_to_hps_ch0_axil_clk s0_noc_axi4lite_clock io96b0_to_hps_ch0_axil_reset_n s0_noc_axi4lite_reset_n io96b0_to_hps_ch0_axil_awaddr s0_noc_axi4lite_awaddr io96b0_to_hps_ch0_axil_awvalid s0_noc_axi4lite_awvalid io96b0_to_hps_ch0_axil_awready s0_noc_axi4lite_awready io96b0_to_hps_ch0_axil_araddr s0_noc_axi4lite_araddr io96b0_to_hps_ch0_axil_arvalid s0_noc_axi4lite_arvalid io96b0_to_hps_ch0_axil_arready s0_noc_axi4lite_arready io96b0_to_hps_ch0_axil_wdata s0_noc_axi4lite_wdata io96b0_to_hps_ch0_axil_wvalid s0_noc_axi4lite_wvalid io96b0_to_hps_ch0_axil_wready s0_noc_axi4lite_wready io96b0_to_hps_ch0_axil_rresp s0_noc_axi4lite_rresp io96b0_to_hps_ch0_axil_rdata s0_noc_axi4lite_rdata io96b0_to_hps_ch0_axil_rvalid s0_noc_axi4lite_rvalid io96b0_to_hps_ch0_axil_rready s0_noc_axi4lite_rready io96b0_to_hps_ch0_axil_bresp s0_noc_axi4lite_bresp io96b0_to_hps_ch0_axil_bvalid s0_noc_axi4lite_bvalid io96b0_to_hps_ch0_axil_bready s0_noc_axi4lite_bready io96b0_to_hps_ch0_axil_awprot s0_noc_axi4lite_awprot io96b0_to_hps_ch0_axil_arprot s0_noc_axi4lite_arprot io96b0_to_hps_ch0_axil_wstrb s0_noc_axi4lite_wstrb io96b0_to_hps_axi4_ch0_awaddr s0_axi4_awaddr io96b0_to_hps_axi4_ch0_awburst s0_axi4_awburst io96b0_to_hps_axi4_ch0_awid s0_axi4_awid io96b0_to_hps_axi4_ch0_awlen s0_axi4_awlen io96b0_to_hps_axi4_ch0_awlock s0_axi4_awlock io96b0_to_hps_axi4_ch0_awqos s0_axi4_awqos io96b0_to_hps_axi4_ch0_awsize s0_axi4_awsize io96b0_to_hps_axi4_ch0_awvalid s0_axi4_awvalid io96b0_to_hps_axi4_ch0_awuser s0_axi4_awuser io96b0_to_hps_axi4_ch0_awprot s0_axi4_awprot io96b0_to_hps_axi4_ch0_awready s0_axi4_awready io96b0_to_hps_axi4_ch0_araddr s0_axi4_araddr io96b0_to_hps_axi4_ch0_arburst s0_axi4_arburst io96b0_to_hps_axi4_ch0_arid s0_axi4_arid io96b0_to_hps_axi4_ch0_arlen s0_axi4_arlen io96b0_to_hps_axi4_ch0_arlock s0_axi4_arlock io96b0_to_hps_axi4_ch0_arqos s0_axi4_arqos io96b0_to_hps_axi4_ch0_arsize s0_axi4_arsize io96b0_to_hps_axi4_ch0_arvalid s0_axi4_arvalid io96b0_to_hps_axi4_ch0_aruser s0_axi4_aruser io96b0_to_hps_axi4_ch0_arprot s0_axi4_arprot io96b0_to_hps_axi4_ch0_arready s0_axi4_arready io96b0_to_hps_axi4_ch0_wdata s0_axi4_wdata io96b0_to_hps_axi4_ch0_wstrb s0_axi4_wstrb io96b0_to_hps_axi4_ch0_wlast s0_axi4_wlast io96b0_to_hps_axi4_ch0_wvalid s0_axi4_wvalid io96b0_to_hps_axi4_ch0_wready s0_axi4_wready io96b0_to_hps_axi4_ch0_bready s0_axi4_bready io96b0_to_hps_axi4_ch0_bid s0_axi4_bid io96b0_to_hps_axi4_ch0_bresp s0_axi4_bresp io96b0_to_hps_axi4_ch0_bvalid s0_axi4_bvalid io96b0_to_hps_axi4_ch0_rready s0_axi4_rready io96b0_to_hps_axi4_ch0_rdata s0_axi4_rdata io96b0_to_hps_axi4_ch0_rid s0_axi4_rid io96b0_to_hps_axi4_ch0_rlast s0_axi4_rlast io96b0_to_hps_axi4_ch0_rresp s0_axi4_rresp io96b0_to_hps_axi4_ch0_rvalid s0_axi4_rvalid io96b0_to_hps_axi4_ch0_clk noc_aclk_0 io96b0_to_hps_axi4_ch0_reset_n noc_rst_n_0 io96b0_to_hps_axi4_ch0_wuser s0_axi4_wuser io96b0_to_hps_axi4_ch0_ruser s0_axi4_ruser</message>
   <message level="Debug">add_interface mem_0  </message>
   <message level="Debug">set_interface_property mem_0 EXPORT_OF emif_0_lpddr4.mem_0</message>
   <message level="Debug">get_interface_ports mem_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_cs ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_ca ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_cke ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dq ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dqs_t ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dqs_c ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dmi ROLE</message>
   <message level="Debug">set_interface_ports_property mem_0 NAME mem_0_mem_cs mem_0_cs mem_0_mem_ca mem_0_ca mem_0_mem_cke mem_0_cke mem_0_mem_dq mem_0_dq mem_0_mem_dqs_t mem_0_dqs_t mem_0_mem_dqs_c mem_0_dqs_c mem_0_mem_dmi mem_0_dmi</message>
   <message level="Debug">add_interface mem_ck_0  </message>
   <message level="Debug">set_interface_property mem_ck_0 EXPORT_OF emif_0_lpddr4.mem_ck_0</message>
   <message level="Debug">get_interface_ports mem_ck_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_ck_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_ck_0 mem_0_ck_t ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_ck_0 mem_0_ck_c ROLE</message>
   <message level="Debug">set_interface_ports_property mem_ck_0 NAME mem_ck_0_mem_ck_t mem_0_ck_t mem_ck_0_mem_ck_c mem_0_ck_c</message>
   <message level="Debug">add_interface mem_reset_n  </message>
   <message level="Debug">set_interface_property mem_reset_n EXPORT_OF emif_0_lpddr4.mem_reset_n</message>
   <message level="Debug">get_interface_ports mem_reset_n</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_reset_n</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_reset_n mem_0_reset_n ROLE</message>
   <message level="Debug">set_interface_ports_property mem_reset_n NAME mem_reset_n_mem_reset_n mem_0_reset_n</message>
   <message level="Debug">add_interface oct_0  </message>
   <message level="Debug">set_interface_property oct_0 EXPORT_OF emif_0_lpddr4.oct_0</message>
   <message level="Debug">get_interface_ports oct_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 oct_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 oct_0 oct_rzqin_0 ROLE</message>
   <message level="Debug">set_interface_ports_property oct_0 NAME oct_0_oct_rzqin oct_rzqin_0</message>
   <message level="Debug">add_interface ref_clk  </message>
   <message level="Debug">set_interface_property ref_clk EXPORT_OF refclk_bridge.refclk_in</message>
   <message level="Debug">get_interface_ports ref_clk</message>
   <message level="Debug">get_instance_interface_ports refclk_bridge refclk_in</message>
   <message level="Debug">get_instance_interface_port_property refclk_bridge refclk_in refclk_in ROLE</message>
   <message level="Debug">set_interface_ports_property ref_clk NAME ref_clk_clk ref_clk</message>
   <message level="Debug">sync_sysinfo_parameters </message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>emif_0_lpddr4</strong>]]></message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_bridge</strong>]]></message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_gpio</strong>]]></message>
   <message level="Debug">validate_system </message>
   <message level="Debug">save_system </message>
   <message level="Debug">All modules have been converted to Generic Components.</message>
   <message level="Debug">send_message Debug RESULT:messages {} | cmds {{set_instance_package_parameter_property emif_0_lpddr4 PHY_AC_PLACEMENT DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 MEM_NUM_CHANNELS DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 PHY_MAINBAND_ACCESS_MODE DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 PHY_MAINBAND_ACCESS_MODE DISABLED false} {set_instance_package_parameter_property refclk_bridge CONNECTIONS DISABLED true} {set_instance_package_parameter_property refclk_bridge CUSTOM_ELABORATION_COMMANDS DISABLED true} {set_instance_package_parameter_property refclk_bridge INTERFACES DISABLED true} {set_instance_package_parameter_property refclk_bridge PORTS DISABLED true}} | PHY_TERM_X_R_T_REFCLK_INPUT_OHM RT_DIFF MEM_CHANNEL_CAPACITY_GBITS 16.0 PHY_TERM_X_REFCLK_IO_STD_TYPE TRUE_DIFF</message>
   <message level="Debug" culprit="emif_io96b_hps">elaboration time: 2.63 s</message>
   <message level="Debug">load_component emif_0_lpddr4</message>
   <message level="Debug">set_component_parameter_value PHY_CS_TX_EQUALIZATION OFF</message>
   <message level="Debug">set_component_parameter_value MEM_DIE_DENSITY_GBITS 4</message>
   <message level="Debug">set_component_parameter_value MEM_MINNUMREFSREQ 8192.0</message>
   <message level="Debug">set_component_parameter_value MEM_TREFI_NS 3904.0</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_R2W_SAMECS_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_CHANNEL_CS_WIDTH 1</message>
   <message level="Debug">set_component_parameter_value CTRL_FIXED_W_PRIORITY 0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_S_CK_OUTPUT_OHM SERIES_40_OHM_CAL</message>
   <message level="Debug">set_component_parameter_value INSTANCE_ID 0</message>
   <message level="Debug">set_component_parameter_value MEM_TCKEHCMD_NS 7.5</message>
   <message level="Debug">set_component_parameter_value MEM_TRPPB_NS 18.0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_S_DQ_OUTPUT_OHM SERIES_40_OHM_CAL</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_DQ_VREF 17.5</message>
   <message level="Debug">set_component_parameter_value MEM_TRCD_NS 18.0</message>
   <message level="Debug">set_component_parameter_value EX_DESIGN_TG_WIDE_IF false</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_DQ_X_IDLE off</message>
   <message level="Debug">set_component_parameter_value MEM_TRC_NS 63.0</message>
   <message level="Debug">set_component_parameter_value MEM_OPERATING_FREQ_MHZ 1333.333</message>
   <message level="Debug">set_component_parameter_value CTRL_FIXED_R_PRIORITY 0</message>
   <message level="Debug">set_component_parameter_value PHY_AC_PLACEMENT BOT</message>
   <message level="Debug">set_component_parameter_value CTRL_FIXED_PRIORITY_EN false</message>
   <message level="Debug">set_component_parameter_value CTRL_AUTO_PRECHARGE_EN false</message>
   <message level="Debug">set_component_parameter_value PHY_REFCLK_FREQ_MHZ_AUTOSET_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_DQ_VREF 45</message>
   <message level="Debug">set_component_parameter_value MEM_TCMDCKE_NS 2.25</message>
   <message level="Debug">set_component_parameter_value EX_DESIGN_PMON_CH2_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_NUM_CHANNELS 1</message>
   <message level="Debug">set_component_parameter_value MEM_TXSR_NS 187.5</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_W2W_SAMECS_CYC 0</message>
   <message level="Debug">set_component_parameter_value EX_DESIGN_PMON_INTERNAL_JAMB_EN true</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_GPIO_IO_STD_TYPE LVCMOS</message>
   <message level="Debug">set_component_parameter_value MEM_TRAS_NS 42.0</message>
   <message level="Debug">set_component_parameter_value ADV_CAL_ENABLE_REQ false</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_CK_SLEW_RATE FASTEST</message>
   <message level="Debug">set_component_parameter_value ADV_CAL_ENABLE_MARGIN false</message>
   <message level="Debug">set_component_parameter_value MEM_PER_BANK_REF_EN 1</message>
   <message level="Debug">set_component_parameter_value MEM_CWL_CYC 22</message>
   <message level="Debug">set_component_parameter_value JEDEC_OVERRIDE_TABLE_PARAM_NAME MEM_TCCD_NS</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_CS_SLEW_RATE FASTEST</message>
   <message level="Debug">set_component_parameter_value MEM_RD_PREAMBLE_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_TRFCAB_NS 180.0</message>
   <message level="Debug">set_component_parameter_value MEM_TSR_NS 15.0</message>
   <message level="Debug">set_component_parameter_value CTRL_WR_DBI_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_TPPD_CYC 4.0</message>
   <message level="Debug">set_component_parameter_value MEM_CA_VREF 33</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_DQS_IO_STD_TYPE DF_LVSTL</message>
   <message level="Debug">set_component_parameter_value PHY_CK_TX_EQUALIZATION OFF</message>
   <message level="Debug">set_component_parameter_value MEM_TWR_NS 18.0</message>
   <message level="Debug">set_component_parameter_value MEM_TESCKE_NS 2.25</message>
   <message level="Debug">set_component_parameter_value MEM_TXP_NS 7.5</message>
   <message level="Debug">set_component_parameter_value CTRL_DM_EN true</message>
   <message level="Debug">set_component_parameter_value ANALOG_PARAM_DERIVATION_PARAM_NAME MEM_VREF_DQ_X_VALUE MEM_VREF_CA_X_CA_VALUE MEM_VREF_CA_X_CA_RANGE</message>
   <message level="Debug">set_component_parameter_value CTRL_SCRAMBLER_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_TECH_IS_X false</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_CA_X_CA_ENABLE true</message>
   <message level="Debug">set_component_parameter_value MEM_TDQSCK_MAX_NS 3.5</message>
   <message level="Debug">set_component_parameter_value MEM_TWTR_NS 10.0</message>
   <message level="Debug">set_component_parameter_value DIAG_HMC_ADDR_SWAP_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_TRRD_NS 10.0</message>
   <message level="Debug">set_component_parameter_value MEM_TCSCKEH_NS 1.75</message>
   <message level="Debug">set_component_parameter_value MEM_TCKCKEH_NS 2.25</message>
   <message level="Debug">set_component_parameter_value MEM_VREF_CA_X_CA_RANGE 1</message>
   <message level="Debug">set_component_parameter_value MEM_VREF_CA_X_CA_VALUE 23.2</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_W2W_DIFFCS_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_TCKELCMD_NS 5.0</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_CA_X_CA_COMM 3</message>
   <message level="Debug">set_component_parameter_value MEM_TMRR_NS 6.0</message>
   <message level="Debug">set_component_parameter_value PHY_AC_TX_EQUALIZATION OFF</message>
   <message level="Debug">set_component_parameter_value CTRL_ECC_INLINE_EN false</message>
   <message level="Debug">set_component_parameter_value EX_DESIGN_PMON_CH1_EN false</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_AC_SLEW_RATE FASTEST</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_S_AC_OUTPUT_OHM SERIES_40_OHM_CAL</message>
   <message level="Debug">set_component_parameter_value MEM_TCKELCK_NS 5.0</message>
   <message level="Debug">set_component_parameter_value CTRL_PLACEMENT_EN true</message>
   <message level="Debug">set_component_parameter_value MEM_TCCD_NS 8.0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_DQ_SLEW_RATE FASTEST</message>
   <message level="Debug">set_component_parameter_value DIAG_FORCE_SLIM_EN false</message>
   <message level="Debug">set_component_parameter_value CTRL_ALL_STRB_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_TDQSCK_MIN_NS 1.5</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_W2R_SAMECS_CYC 0</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_R2R_DIFFCS_CYC 0</message>
   <message level="Debug">set_component_parameter_value PHY_REFCLK_ADVANCED_SELECT_EN true</message>
   <message level="Debug">set_component_parameter_value CTRL_RD_DBI_EN true</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_R2R_SAMECS_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_VREF_DQ_X_VALUE 28.0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_S_CS_OUTPUT_OHM SERIES_40_OHM_CAL</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_AC_OUTPUT_IO_STD_TYPE LVSTL</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_DQ_X_RON 6</message>
   <message level="Debug">set_component_parameter_value MEM_VREF_DQ_X_RANGE 1</message>
   <message level="Debug">set_component_parameter_value ADV_CAL_ENABLE_WEQ false</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_T_DQ_INPUT_OHM RT_50_OHM_CAL</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_CA_X_CK_ENABLE true</message>
   <message level="Debug">set_component_parameter_value MEM_TMRD_NS 14.0</message>
   <message level="Debug">set_component_parameter_value MEM_TFAW_NS 40.0</message>
   <message level="Debug">set_component_parameter_value MEM_TZQCKE_NS 2.25</message>
   <message level="Debug">set_component_parameter_value MEM_TMRW_NS 10.0</message>
   <message level="Debug">set_component_parameter_value MEM_RD_POSTAMBLE_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_OPERATING_FREQ_MHZ_AUTOSET_EN true</message>
   <message level="Debug">set_component_parameter_value MEM_TCSCKE_NS 1.75</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_DQ_IO_STD_TYPE LVSTL</message>
   <message level="Debug">set_component_parameter_value MEM_TRTP_NS 7.5</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_W2R_DIFFCS_CYC 0</message>
   <message level="Debug">set_component_parameter_value CTRL_PERFORMANCE_PROFILE SEQ</message>
   <message level="Debug">set_component_parameter_value EX_DESIGN_PMON_CH3_EN false</message>
   <message level="Debug">set_component_parameter_value PHY_REFCLK_FREQ_MHZ 166.6666</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_DQ_X_TGT_WR 5</message>
   <message level="Debug">set_component_parameter_value MEM_CL_CYC 28</message>
   <message level="Debug">set_component_parameter_value MEM_TREFW_NS 3.2E7</message>
   <message level="Debug">set_component_parameter_value CTRL_ECC_AUTOCORRECT_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_WR_POSTAMBLE_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_TCKE_NS 7.5</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_CK_OUTPUT_IO_STD_TYPE DF_LVSTL</message>
   <message level="Debug">set_component_parameter_value PHY_DQ_TX_EQUALIZATION OFF</message>
   <message level="Debug">set_component_parameter_value MEM_TZQCAL_NS 1000.0</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_CA_X_CS_ENABLE true</message>
   <message level="Debug">set_component_parameter_value MEM_TMRWCKEL_NS 14.0</message>
   <message level="Debug">set_component_parameter_value MEM_WLS 1.0</message>
   <message level="Debug">set_component_parameter_value PHY_SWIZZLE_MAP PIN_SWIZZLE_CH0_DQS0=5 4 0 7 1 6 2 3;PIN_SWIZZLE_CH0_DQS1=15 8 14 9 12 13 11 10;PIN_SWIZZLE_CH0_DQS2=18 22 19 20 21 23 16 17;PIN_SWIZZLE_CH0_DQS3=27 29 28 26 24 25 31 30;</message>
   <message level="Debug">set_component_parameter_value MEM_TRFCPB_NS 90.0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_CS_OUTPUT_IO_STD_TYPE LVSTL</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_REFCLK_IO_STD_TYPE TRUE_DIFF</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_T_REFCLK_INPUT_OHM RT_DIFF</message>
   <message level="Debug">set_component_parameter_value MEM_TCKCKEL_NS 5.0</message>
   <message level="Debug">set_component_parameter_value IS_HPS true</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_R2W_DIFFCS_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_TRPAB_NS 21.0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_T_GPIO_INPUT_OHM RT_OFF</message>
   <message level="Debug">set_component_parameter_value MEM_TZQLAT_NS 30.0</message>
   <message level="Debug">save_component </message>
   <message level="Debug">load_component refclk_bridge</message>
   <message level="Debug">set_component_parameter_value INTERFACES {refclk_in        clock    sink} {refclk_out       clock    source} {refclk_in_gpio   conduit  end} {refclk_out_gpio  conduit  start}</message>
   <message level="Debug">set_component_parameter_value CONNECTIONS {refclk_in        refclk_in_gpio} {refclk_out_gpio  refclk_out}</message>
   <message level="Debug">set_component_parameter_value PORTS {refclk_in        refclk_in         clk      input    1} {refclk_out       refclk_out        clk      output   1} {refclk_in_gpio   refclk_in_gpio    export   output   1} {refclk_out_gpio  refclk_out_gpio   export   input    1}</message>
   <message level="Debug">save_component </message>
   <message level="Debug">save_system </message>
   <message level="Debug">All modules have been converted to Generic Components.</message>
   <message level="Debug">set_validation_property AUTOMATIC_VALIDATION false</message>
   <message level="Debug">set_project_property DEVICE_FAMILY Agilex 5</message>
   <message level="Debug">set_project_property DEVICE A5EB013BB23BE4SCS</message>
   <message level="Debug">remove_dangling_connections </message>
   <message level="Debug">get_connections </message>
   <message level="Debug">remove_connections refclk_bridge.refclk_in_gpio/refclk_gpio.pad_in refclk_bridge.refclk_out/emif_0_lpddr4.ref_clk refclk_gpio.dout/refclk_bridge.refclk_out_gpio</message>
   <message level="Debug">get_interfaces </message>
   <message level="Debug">remove_interfaces io96b0_to_hps mem_0 mem_ck_0 mem_reset_n oct_0 ref_clk</message>
   <message level="Debug">get_instances </message>
   <message level="Debug">set_instance_property emif_0_ddr4comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_ddr5comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_ddr5dimm ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr5 ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr4comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr5comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr5dimm ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_lpddr4 ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_lpddr5 ENABLED false</message>
   <message level="Debug">set_instance_property refclk_bridge ENABLED false</message>
   <message level="Debug">set_instance_property refclk_gpio ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED true</message>
   <message level="Debug">load_component emif_0_lpddr4</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">get_component_parameter_values PHY_MAINBAND_ACCESS_MODE INSTANCE_ID PHY_TERM_X_REFCLK_IO_STD_TYPE PHY_TERM_X_R_T_REFCLK_INPUT_OHM MEM_CHANNEL_CAPACITY_GBITS</message>
   <message level="Debug">set_component_parameter_values MEM_CHANNEL_DATA_DQ_WIDTH 32</message>
   <message level="Debug">set_component_parameter_value PHY_AC_PLACEMENT BOT</message>
   <message level="Debug">set_component_parameter_value MEM_NUM_CHANNELS 1</message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED true</message>
   <message level="Debug">load_component emif_0_lpddr4</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">get_component_parameters </message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_MARGIN</message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_REQ</message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_WEQ</message>
   <message level="Debug">get_component_parameter_value ANALOG_PARAM_DERIVATION_PARAM_NAME</message>
   <message level="Debug">get_component_parameter_value AXI4_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value CTRL_ALL_STRB_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_AUTO_PRECHARGE_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_DM_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_ECC_AUTOCORRECT_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_ECC_INLINE_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_PRIORITY_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_R_PRIORITY</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_W_PRIORITY</message>
   <message level="Debug">get_component_parameter_value CTRL_PERFORMANCE_PROFILE</message>
   <message level="Debug">get_component_parameter_value CTRL_PLACEMENT_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_RD_DBI_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_SCRAMBLER_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_WR_DBI_EN</message>
   <message level="Debug">get_component_parameter_value DEBUG_PRINT_LEVEL</message>
   <message level="Debug">get_component_parameter_value DEBUG_TOOLS_EN</message>
   <message level="Debug">get_component_parameter_value DIAG_EXTRA_PARAMETERS</message>
   <message level="Debug">get_component_parameter_value DIAG_FORCE_SLIM_EN</message>
   <message level="Debug">get_component_parameter_value DIAG_HMC_ADDR_SWAP_EN</message>
   <message level="Debug">get_component_parameter_value EMIF_INST_NAME</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_CDC</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_SIM</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_SYNTH</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_HDL_FORMAT</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH0_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH1_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH2_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH3_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_INTERNAL_JAMB_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_CSR_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_PROGRAM</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_WIDE_IF</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value INSTANCE_ID</message>
   <message level="Debug">get_component_parameter_value IS_HPS</message>
   <message level="Debug">get_component_parameter_value JEDEC_OVERRIDE_TABLE_PARAM_NAME</message>
   <message level="Debug">get_component_parameter_value MEM_BANK_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CA_VREF</message>
   <message level="Debug">get_component_parameter_value MEM_CA_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_ADDR_NUM_BITS</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_CAPACITY_GBITS</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_CS_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_DATA_DQ_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CKE_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CK_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CL_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_COL_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CS_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CWL_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_DIE_DENSITY_GBITS</message>
   <message level="Debug">get_component_parameter_value MEM_DQ_PER_DQS</message>
   <message level="Debug">get_component_parameter_value MEM_DQ_VREF</message>
   <message level="Debug">get_component_parameter_value MEM_MINNUMREFSREQ</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_CHANNELS</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_CHANNELS_PER_IO96</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_IO96</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CA_COMM</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CA_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CK_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CS_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_IDLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_RON</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_TGT_WR</message>
   <message level="Debug">get_component_parameter_value MEM_OPERATING_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value MEM_OPERATING_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value MEM_PER_BANK_REF_EN</message>
   <message level="Debug">get_component_parameter_value MEM_RD_POSTAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_RD_PREAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_ROW_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_TCCD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKCKEH_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKCKEL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKEHCMD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKELCK_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKELCMD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCMDCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCSCKEH_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCSCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TDQSCK_MAX_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TDQSCK_MIN_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TECH_IS_X</message>
   <message level="Debug">get_component_parameter_value MEM_TESCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TFAW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRWCKEL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TPPD_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_TRAS_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRCD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRC_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TREFI_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TREFW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRFCAB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRFCPB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRPAB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRPPB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRRD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRTP_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TSR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TWR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TWTR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TXP_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TXSR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQCAL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQLAT_NS</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_CA_X_CA_RANGE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_CA_X_CA_VALUE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_DQ_X_RANGE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_DQ_X_VALUE</message>
   <message level="Debug">get_component_parameter_value MEM_WLS</message>
   <message level="Debug">get_component_parameter_value MEM_WR_POSTAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value NUM_IO96_IN_CHIP</message>
   <message level="Debug">get_component_parameter_value PHY_AC_PLACEMENT</message>
   <message level="Debug">get_component_parameter_value PHY_AC_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_CK_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_CS_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_DQ_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_MAINBAND_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_ADVANCED_SELECT_EN</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_SIDEBAND_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_SWIZZLE_MAP</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_AC_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_AC_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CK_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CK_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CS_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CS_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQS_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_VREF</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_GPIO_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_REFCLK_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_AC_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_CK_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_CS_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_DQ_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_DQ_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_GPIO_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_REFCLK_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PLACEMENT_SCHEMES</message>
   <message level="Debug">get_component_parameter_value S0_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S1_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S2_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S3_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value SYSINFO_BOARD</message>
   <message level="Debug">get_component_parameter_value SYSINFO_BOARD_TRAIT</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_BASE_DIE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_DIE_REVISIONS</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_FAMILY</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_GROUP</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_IOBANK_REVISION</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_POWER_MODEL</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_SPEEDGRADE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_TEMPERATURE_GRADE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_SUPPORTS_VID</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2R_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2R_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2W_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2W_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2R_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2R_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2W_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2W_SAMECS_CYC</message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property refclk_bridge ENABLED true</message>
   <message level="Debug">load_component refclk_bridge</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">set_component_parameter_values INTERFACES {refclk_in        clock    sink} {refclk_out       clock    source} {refclk_in_gpio   conduit  end} {refclk_out_gpio  conduit  start} PORTS {refclk_in        refclk_in         clk      input    1} {refclk_out       refclk_out        clk      output   1} {refclk_in_gpio   refclk_in_gpio    export   output   1} {refclk_out_gpio  refclk_out_gpio   export   input    1} CONNECTIONS {refclk_in        refclk_in_gpio} {refclk_out_gpio  refclk_out} CUSTOM_ELABORATION_COMMANDS </message>
   <message level="Debug">get_component_parameters </message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property refclk_gpio ENABLED true</message>
   <message level="Debug">sync_sysinfo_parameters refclk_gpio</message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_gpio</strong>]]></message>
   <message level="Debug">add_connection refclk_gpio.dout refclk_bridge.refclk_out_gpio</message>
   <message level="Debug">add_connection refclk_bridge.refclk_in_gpio refclk_gpio.pad_in</message>
   <message level="Debug">add_connection refclk_bridge.refclk_out emif_0_lpddr4.ref_clk</message>
   <message level="Debug">get_connections </message>
   <message level="Debug">get_interfaces </message>
   <message level="Debug">get_wirelevel_expressions </message>
   <message level="Debug">get_instances </message>
   <message level="Debug">get_instance_property emif_0_ddr4comp ENABLED</message>
   <message level="Debug">get_instance_property emif_0_ddr5comp ENABLED</message>
   <message level="Debug">get_instance_property emif_0_ddr5dimm ENABLED</message>
   <message level="Debug">get_instance_property emif_0_lpddr4 ENABLED</message>
   <message level="Debug">get_instance_interfaces emif_0_lpddr4</message>
   <message level="Debug">get_instance_property emif_0_lpddr5 ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr4comp ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr5comp ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr5dimm ENABLED</message>
   <message level="Debug">get_instance_property emif_1_lpddr4 ENABLED</message>
   <message level="Debug">get_instance_property emif_1_lpddr5 ENABLED</message>
   <message level="Debug">get_instance_property refclk_bridge ENABLED</message>
   <message level="Debug">get_instance_interfaces refclk_bridge</message>
   <message level="Debug">get_instance_property refclk_gpio ENABLED</message>
   <message level="Debug">get_instance_interfaces refclk_gpio</message>
   <message level="Debug">add_interface io96b0_to_hps  </message>
   <message level="Debug">set_interface_property io96b0_to_hps EXPORT_OF emif_0_lpddr4.io96b0_to_hps</message>
   <message level="Debug">get_interface_ports io96b0_to_hps</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 io96b0_to_hps</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_clock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_reset_n ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awaddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_araddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wstrb ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awaddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awburst ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awlen ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awlock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awqos ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awsize ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awuser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_araddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arburst ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arlen ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arlock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arqos ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arsize ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_aruser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wstrb ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wlast ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rlast ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps noc_aclk_0 ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps noc_rst_n_0 ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wuser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_ruser ROLE</message>
   <message level="Debug">set_interface_ports_property io96b0_to_hps NAME io96b0_to_hps_ch0_axil_clk s0_noc_axi4lite_clock io96b0_to_hps_ch0_axil_reset_n s0_noc_axi4lite_reset_n io96b0_to_hps_ch0_axil_awaddr s0_noc_axi4lite_awaddr io96b0_to_hps_ch0_axil_awvalid s0_noc_axi4lite_awvalid io96b0_to_hps_ch0_axil_awready s0_noc_axi4lite_awready io96b0_to_hps_ch0_axil_araddr s0_noc_axi4lite_araddr io96b0_to_hps_ch0_axil_arvalid s0_noc_axi4lite_arvalid io96b0_to_hps_ch0_axil_arready s0_noc_axi4lite_arready io96b0_to_hps_ch0_axil_wdata s0_noc_axi4lite_wdata io96b0_to_hps_ch0_axil_wvalid s0_noc_axi4lite_wvalid io96b0_to_hps_ch0_axil_wready s0_noc_axi4lite_wready io96b0_to_hps_ch0_axil_rresp s0_noc_axi4lite_rresp io96b0_to_hps_ch0_axil_rdata s0_noc_axi4lite_rdata io96b0_to_hps_ch0_axil_rvalid s0_noc_axi4lite_rvalid io96b0_to_hps_ch0_axil_rready s0_noc_axi4lite_rready io96b0_to_hps_ch0_axil_bresp s0_noc_axi4lite_bresp io96b0_to_hps_ch0_axil_bvalid s0_noc_axi4lite_bvalid io96b0_to_hps_ch0_axil_bready s0_noc_axi4lite_bready io96b0_to_hps_ch0_axil_awprot s0_noc_axi4lite_awprot io96b0_to_hps_ch0_axil_arprot s0_noc_axi4lite_arprot io96b0_to_hps_ch0_axil_wstrb s0_noc_axi4lite_wstrb io96b0_to_hps_axi4_ch0_awaddr s0_axi4_awaddr io96b0_to_hps_axi4_ch0_awburst s0_axi4_awburst io96b0_to_hps_axi4_ch0_awid s0_axi4_awid io96b0_to_hps_axi4_ch0_awlen s0_axi4_awlen io96b0_to_hps_axi4_ch0_awlock s0_axi4_awlock io96b0_to_hps_axi4_ch0_awqos s0_axi4_awqos io96b0_to_hps_axi4_ch0_awsize s0_axi4_awsize io96b0_to_hps_axi4_ch0_awvalid s0_axi4_awvalid io96b0_to_hps_axi4_ch0_awuser s0_axi4_awuser io96b0_to_hps_axi4_ch0_awprot s0_axi4_awprot io96b0_to_hps_axi4_ch0_awready s0_axi4_awready io96b0_to_hps_axi4_ch0_araddr s0_axi4_araddr io96b0_to_hps_axi4_ch0_arburst s0_axi4_arburst io96b0_to_hps_axi4_ch0_arid s0_axi4_arid io96b0_to_hps_axi4_ch0_arlen s0_axi4_arlen io96b0_to_hps_axi4_ch0_arlock s0_axi4_arlock io96b0_to_hps_axi4_ch0_arqos s0_axi4_arqos io96b0_to_hps_axi4_ch0_arsize s0_axi4_arsize io96b0_to_hps_axi4_ch0_arvalid s0_axi4_arvalid io96b0_to_hps_axi4_ch0_aruser s0_axi4_aruser io96b0_to_hps_axi4_ch0_arprot s0_axi4_arprot io96b0_to_hps_axi4_ch0_arready s0_axi4_arready io96b0_to_hps_axi4_ch0_wdata s0_axi4_wdata io96b0_to_hps_axi4_ch0_wstrb s0_axi4_wstrb io96b0_to_hps_axi4_ch0_wlast s0_axi4_wlast io96b0_to_hps_axi4_ch0_wvalid s0_axi4_wvalid io96b0_to_hps_axi4_ch0_wready s0_axi4_wready io96b0_to_hps_axi4_ch0_bready s0_axi4_bready io96b0_to_hps_axi4_ch0_bid s0_axi4_bid io96b0_to_hps_axi4_ch0_bresp s0_axi4_bresp io96b0_to_hps_axi4_ch0_bvalid s0_axi4_bvalid io96b0_to_hps_axi4_ch0_rready s0_axi4_rready io96b0_to_hps_axi4_ch0_rdata s0_axi4_rdata io96b0_to_hps_axi4_ch0_rid s0_axi4_rid io96b0_to_hps_axi4_ch0_rlast s0_axi4_rlast io96b0_to_hps_axi4_ch0_rresp s0_axi4_rresp io96b0_to_hps_axi4_ch0_rvalid s0_axi4_rvalid io96b0_to_hps_axi4_ch0_clk noc_aclk_0 io96b0_to_hps_axi4_ch0_reset_n noc_rst_n_0 io96b0_to_hps_axi4_ch0_wuser s0_axi4_wuser io96b0_to_hps_axi4_ch0_ruser s0_axi4_ruser</message>
   <message level="Debug">add_interface mem_0  </message>
   <message level="Debug">set_interface_property mem_0 EXPORT_OF emif_0_lpddr4.mem_0</message>
   <message level="Debug">get_interface_ports mem_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_cs ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_ca ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_cke ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dq ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dqs_t ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dqs_c ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dmi ROLE</message>
   <message level="Debug">set_interface_ports_property mem_0 NAME mem_0_mem_cs mem_0_cs mem_0_mem_ca mem_0_ca mem_0_mem_cke mem_0_cke mem_0_mem_dq mem_0_dq mem_0_mem_dqs_t mem_0_dqs_t mem_0_mem_dqs_c mem_0_dqs_c mem_0_mem_dmi mem_0_dmi</message>
   <message level="Debug">add_interface mem_ck_0  </message>
   <message level="Debug">set_interface_property mem_ck_0 EXPORT_OF emif_0_lpddr4.mem_ck_0</message>
   <message level="Debug">get_interface_ports mem_ck_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_ck_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_ck_0 mem_0_ck_t ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_ck_0 mem_0_ck_c ROLE</message>
   <message level="Debug">set_interface_ports_property mem_ck_0 NAME mem_ck_0_mem_ck_t mem_0_ck_t mem_ck_0_mem_ck_c mem_0_ck_c</message>
   <message level="Debug">add_interface mem_reset_n  </message>
   <message level="Debug">set_interface_property mem_reset_n EXPORT_OF emif_0_lpddr4.mem_reset_n</message>
   <message level="Debug">get_interface_ports mem_reset_n</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_reset_n</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_reset_n mem_0_reset_n ROLE</message>
   <message level="Debug">set_interface_ports_property mem_reset_n NAME mem_reset_n_mem_reset_n mem_0_reset_n</message>
   <message level="Debug">add_interface oct_0  </message>
   <message level="Debug">set_interface_property oct_0 EXPORT_OF emif_0_lpddr4.oct_0</message>
   <message level="Debug">get_interface_ports oct_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 oct_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 oct_0 oct_rzqin_0 ROLE</message>
   <message level="Debug">set_interface_ports_property oct_0 NAME oct_0_oct_rzqin oct_rzqin_0</message>
   <message level="Debug">add_interface ref_clk  </message>
   <message level="Debug">set_interface_property ref_clk EXPORT_OF refclk_bridge.refclk_in</message>
   <message level="Debug">get_interface_ports ref_clk</message>
   <message level="Debug">get_instance_interface_ports refclk_bridge refclk_in</message>
   <message level="Debug">get_instance_interface_port_property refclk_bridge refclk_in refclk_in ROLE</message>
   <message level="Debug">set_interface_ports_property ref_clk NAME ref_clk_clk ref_clk</message>
   <message level="Debug">sync_sysinfo_parameters </message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>emif_0_lpddr4</strong>]]></message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_bridge</strong>]]></message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_gpio</strong>]]></message>
   <message level="Debug">validate_system </message>
   <message level="Debug">save_system </message>
   <message level="Debug">All modules have been converted to Generic Components.</message>
   <message level="Debug">send_message Debug RESULT:messages {} | cmds {{set_instance_package_parameter_property emif_0_lpddr4 PHY_AC_PLACEMENT DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 MEM_NUM_CHANNELS DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 PHY_MAINBAND_ACCESS_MODE DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 PHY_MAINBAND_ACCESS_MODE DISABLED false} {set_instance_package_parameter_property refclk_bridge CONNECTIONS DISABLED true} {set_instance_package_parameter_property refclk_bridge CUSTOM_ELABORATION_COMMANDS DISABLED true} {set_instance_package_parameter_property refclk_bridge INTERFACES DISABLED true} {set_instance_package_parameter_property refclk_bridge PORTS DISABLED true}} | PHY_TERM_X_R_T_REFCLK_INPUT_OHM RT_DIFF MEM_CHANNEL_CAPACITY_GBITS 8.0 PHY_TERM_X_REFCLK_IO_STD_TYPE TRUE_DIFF</message>
   <message level="Debug" culprit="emif_io96b_hps">elaboration time: 1.76 s</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: qsys-generate emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys --synthesis=VERILOG --package-subsystem --generate-all-simulation-scripts --part=A5EB013BB23BE4SCS --search-path=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/**/*,/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/**/*,$ --clear-output-directory</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: ***************************************************************</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: Quartus is a registered trademark of Altera Corporation in the</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: US and other countries.  Portions of the Quartus Prime software</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: code, and other portions of the code included in this download</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: or on this DVD, are licensed to Altera Corporation and are the</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: copyrighted property of third parties. For license details,</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: refer to the Altera Software License Subscription Agreements </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: on the Quartus Prime software download page.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: ***************************************************************</message>
   <message level="Warning" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:08 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:13 Info: Parallel IP Generation is enabled. </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:13 Info: Platform Designer will attempt to use 4 processors for parallel IP generation based on available number of processors and the total number of IP to be generated.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:13 Info: </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:13 Info: Starting: Platform Designer system generation</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Generating on localhost:38153</message>
   <message level="Warning" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Saving generation log to /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge_generation.rpt</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Generated by version: 26.1 build 110</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Starting: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: qsys-generate /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.ip --synthesis=VERILOG --output-directory=/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge --family="Agilex 5" --part=A5EB013BB23BE4SCS</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: "Transforming system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: "Naming system components in system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: "Processing generation queue"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge_qsys_interface_bridge_10_tos2vpi"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: Done "emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge" with 2 modules, 2 files</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Finished: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Generation of /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.ip (emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge) took 280 ms</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generating on localhost:45717</message>
   <message level="Warning" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Saving generation log to /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio_generation.rpt</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generated by version: 26.1 build 110</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Starting: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: qsys-generate /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.ip --synthesis=VERILOG --output-directory=/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio --family="Agilex 5" --part=A5EB013BB23BE4SCS</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.refclk_gpio: GPIO supports a maximum interface frequency of 250 MHZ.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Transforming system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Naming system components in system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Processing generation queue"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio_altera_gpio_2300_ctzjwfq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Generating: altera_gpio"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: Done "emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio" with 3 modules, 3 files</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Finished: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generation of /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.ip (emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio) took 368 ms</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generating on localhost:46525</message>
   <message level="Warning" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: All Generic Component instances match their respective ip files.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Saving generation log to /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_generation.rpt</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generated by version: 26.1 build 110</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Starting: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: qsys-generate /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys --synthesis=VERILOG --output-directory=/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq --family="Agilex 5" --part=A5EB013BB23BE4SCS</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Loading 0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Reading input file</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_0_ddr4comp</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_0_ddr5comp</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_0_ddr5dimm</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_0_lpddr4</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_0_lpddr5</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_1_ddr4comp</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_1_ddr5comp</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_1_ddr5dimm</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_1_lpddr4</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_1_lpddr5</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module refclk_bridge</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module refclk_gpio</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Building connections</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing connections</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Validating</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Done reading input file</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Transforming system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Naming system components in system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Processing generation queue"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: Done "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" with 4 modules, 1 files</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Finished: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generation of /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys (emif_io96b_hps_emif_io96b_hps_420_dyxenzq) took 1567 ms</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Generating on localhost:33515</message>
   <message level="Warning" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Saving generation log to /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_generation.rpt</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Generated by version: 26.1 build 110</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Starting: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: qsys-generate /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.ip --synthesis=VERILOG --output-directory=/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4 --family="Agilex 5" --part=A5EB013BB23BE4SCS</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.emif_0_lpddr4: Configuring this IP for device A5EB013BB23BE4SCS (Agilex 5). This device has speedgrade 4.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Transforming system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Naming system components in system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Processing generation queue"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_lpddr4_420_cy5n3cq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: cal_0: "Generating: cal_0"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_lpddr4_emif_io96b_cal_420_65qugki"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: jamb: "Generating: jamb"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_alt_mem_if_jtag_master_191_2xbfrbi"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: altera_avalon_st_jtag_interface"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_timing_adapter_1950_bbjt6kq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_altera_avalon_sc_fifo_1932_onpcouq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: altera_avalon_st_bytes_to_packets"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: altera_avalon_st_packets_to_bytes"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: altera_avalon_packets_to_master"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_channel_adapter_1922_rd56ufy"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_channel_adapter_1922_5vp3d5a"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: altera_reset_controller"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: Done "emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4" with 15 modules, 165 files</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Finished: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Generation of /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.ip (emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4) took 2419 ms</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Finished: Platform Designer system generation</message>
   <message level="Debug" culprit="emif_io96b_hps">quartus_synth fileset time: 21.93 s</message>
  </messages>
 </entity>
 <entity
   kind="emif_io96b_hps"
   version="4.2.0"
   name="emif_io96b_hps_emif_io96b_hps_420_dyxenzq">
  <parameter name="SYSINFO_DEVICE_SPEEDGRADE" value="4" />
  <parameter name="SYSINFO_DEVICE_DIE_REVISIONS" value="MAIN_SM4_REVB" />
  <parameter name="SYSINFO_DEVICE_GROUP" value="B" />
  <parameter name="EMIF_REF_CLK_SHARING" value="false" />
  <parameter name="EMIF_SHOW_INTERNAL_SETTINGS" value="false" />
  <parameter name="EMIF_TOPOLOGY" value="1x32" />
  <parameter name="SYSINFO_DEVICE_IOBANK_REVISION" value="IO96B_REVB1" />
  <parameter name="SYSINFO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="SYSINFO_BOARD" value="default" />
  <parameter name="SYSINFO_DEVICE_POWER_MODEL" value="STANDARD_POWER_FIXED" />
  <parameter name="EMIF_PROTOCOL" value="LPDDR4" />
  <parameter name="SYSINFO_BOARD_TRAIT" value="" />
  <parameter name="SYSINFO_DEVICE_BASE_DIE" value="SM4REVB" />
  <parameter name="EMIF_RZQ_SHARING" value="false" />
  <parameter name="SYSINFO_SUPPORTS_VID" value="0" />
  <parameter name="SYSINFO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="SYSINFO_DEVICE_TEMPERATURE_GRADE" value="EXTENDED" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qip"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.sopcinfo"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.qip"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.sopcinfo"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.qip"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.sopcinfo"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.sopcinfo"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.qip"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qip"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.sopcinfo"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.qip"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.sopcinfo"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.qip"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.sopcinfo"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.sopcinfo"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/ip/qsys_top/emif_io96b_hps/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/synth/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.qip"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles/>
  <childSourceFiles/>
  <instantiator instantiator="emif_io96b_hps" as="emif_io96b_hps" />
  <messages>
   <message level="Info" culprit="emif_io96b_hps">"Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"</message>
   <message level="Debug" culprit="emif_io96b_hps">validation time: 1.08 ms</message>
   <message level="Debug">set_validation_property AUTOMATIC_VALIDATION false</message>
   <message level="Debug">set_project_property DEVICE_FAMILY Agilex 5</message>
   <message level="Debug">The device and speed grade is changed to the defaults of the device family, Agilex 5.</message>
   <message level="Debug">set_project_property DEVICE A5EB013BB23BE4SCS</message>
   <message level="Debug">remove_dangling_connections </message>
   <message level="Debug">get_connections </message>
   <message level="Debug">remove_connections </message>
   <message level="Debug">get_interfaces </message>
   <message level="Debug">remove_interfaces </message>
   <message level="Debug">get_instances </message>
   <message level="Debug">set_instance_property emif_0_ddr4comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_ddr5comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_ddr5dimm ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr5 ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr4comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr5comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr5dimm ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_lpddr4 ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_lpddr5 ENABLED false</message>
   <message level="Debug">set_instance_property refclk_bridge ENABLED false</message>
   <message level="Debug">set_instance_property refclk_gpio ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED true</message>
   <message level="Debug">load_component emif_0_lpddr4</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">get_component_parameter_values PHY_MAINBAND_ACCESS_MODE INSTANCE_ID PHY_TERM_X_REFCLK_IO_STD_TYPE PHY_TERM_X_R_T_REFCLK_INPUT_OHM MEM_CHANNEL_CAPACITY_GBITS</message>
   <message level="Debug">set_component_parameter_values MEM_CHANNEL_DATA_DQ_WIDTH 32</message>
   <message level="Debug">set_component_parameter_value PHY_AC_PLACEMENT BOT</message>
   <message level="Debug">set_component_parameter_value MEM_NUM_CHANNELS 1</message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED true</message>
   <message level="Debug">load_component emif_0_lpddr4</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">get_component_parameters </message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_MARGIN</message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_REQ</message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_WEQ</message>
   <message level="Debug">get_component_parameter_value ANALOG_PARAM_DERIVATION_PARAM_NAME</message>
   <message level="Debug">get_component_parameter_value AXI4_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value CTRL_ALL_STRB_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_AUTO_PRECHARGE_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_DM_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_ECC_AUTOCORRECT_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_ECC_INLINE_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_PRIORITY_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_R_PRIORITY</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_W_PRIORITY</message>
   <message level="Debug">get_component_parameter_value CTRL_PERFORMANCE_PROFILE</message>
   <message level="Debug">get_component_parameter_value CTRL_PLACEMENT_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_RD_DBI_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_SCRAMBLER_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_WR_DBI_EN</message>
   <message level="Debug">get_component_parameter_value DEBUG_PRINT_LEVEL</message>
   <message level="Debug">get_component_parameter_value DEBUG_TOOLS_EN</message>
   <message level="Debug">get_component_parameter_value DIAG_EXTRA_PARAMETERS</message>
   <message level="Debug">get_component_parameter_value DIAG_FORCE_SLIM_EN</message>
   <message level="Debug">get_component_parameter_value DIAG_HMC_ADDR_SWAP_EN</message>
   <message level="Debug">get_component_parameter_value EMIF_INST_NAME</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_CDC</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_SIM</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_SYNTH</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_HDL_FORMAT</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH0_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH1_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH2_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH3_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_INTERNAL_JAMB_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_CSR_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_PROGRAM</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_WIDE_IF</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value INSTANCE_ID</message>
   <message level="Debug">get_component_parameter_value IS_HPS</message>
   <message level="Debug">get_component_parameter_value JEDEC_OVERRIDE_TABLE_PARAM_NAME</message>
   <message level="Debug">get_component_parameter_value MEM_BANK_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CA_VREF</message>
   <message level="Debug">get_component_parameter_value MEM_CA_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_ADDR_NUM_BITS</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_CAPACITY_GBITS</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_CS_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_DATA_DQ_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CKE_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CK_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CL_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_COL_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CS_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CWL_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_DIE_DENSITY_GBITS</message>
   <message level="Debug">get_component_parameter_value MEM_DQ_PER_DQS</message>
   <message level="Debug">get_component_parameter_value MEM_DQ_VREF</message>
   <message level="Debug">get_component_parameter_value MEM_MINNUMREFSREQ</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_CHANNELS</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_CHANNELS_PER_IO96</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_IO96</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CA_COMM</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CA_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CK_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CS_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_IDLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_RON</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_TGT_WR</message>
   <message level="Debug">get_component_parameter_value MEM_OPERATING_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value MEM_OPERATING_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value MEM_PER_BANK_REF_EN</message>
   <message level="Debug">get_component_parameter_value MEM_RD_POSTAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_RD_PREAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_ROW_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_TCCD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKCKEH_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKCKEL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKEHCMD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKELCK_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKELCMD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCMDCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCSCKEH_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCSCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TDQSCK_MAX_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TDQSCK_MIN_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TECH_IS_X</message>
   <message level="Debug">get_component_parameter_value MEM_TESCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TFAW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRWCKEL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TPPD_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_TRAS_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRCD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRC_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TREFI_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TREFW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRFCAB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRFCPB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRPAB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRPPB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRRD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRTP_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TSR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TWR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TWTR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TXP_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TXSR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQCAL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQLAT_NS</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_CA_X_CA_RANGE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_CA_X_CA_VALUE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_DQ_X_RANGE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_DQ_X_VALUE</message>
   <message level="Debug">get_component_parameter_value MEM_WLS</message>
   <message level="Debug">get_component_parameter_value MEM_WR_POSTAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value NUM_IO96_IN_CHIP</message>
   <message level="Debug">get_component_parameter_value PHY_AC_PLACEMENT</message>
   <message level="Debug">get_component_parameter_value PHY_AC_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_CK_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_CS_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_DQ_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_MAINBAND_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_ADVANCED_SELECT_EN</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_SIDEBAND_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_SWIZZLE_MAP</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_AC_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_AC_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CK_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CK_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CS_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CS_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQS_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_VREF</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_GPIO_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_REFCLK_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_AC_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_CK_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_CS_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_DQ_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_DQ_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_GPIO_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_REFCLK_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PLACEMENT_SCHEMES</message>
   <message level="Debug">get_component_parameter_value S0_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S1_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S2_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S3_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value SYSINFO_BOARD</message>
   <message level="Debug">get_component_parameter_value SYSINFO_BOARD_TRAIT</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_BASE_DIE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_DIE_REVISIONS</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_FAMILY</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_GROUP</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_IOBANK_REVISION</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_POWER_MODEL</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_SPEEDGRADE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_TEMPERATURE_GRADE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_SUPPORTS_VID</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2R_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2R_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2W_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2W_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2R_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2R_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2W_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2W_SAMECS_CYC</message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property refclk_bridge ENABLED true</message>
   <message level="Debug">load_component refclk_bridge</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">set_component_parameter_values INTERFACES {refclk_in        clock    sink} {refclk_out       clock    source} {refclk_in_gpio   conduit  end} {refclk_out_gpio  conduit  start} PORTS {refclk_in        refclk_in         clk      input    1} {refclk_out       refclk_out        clk      output   1} {refclk_in_gpio   refclk_in_gpio    export   output   1} {refclk_out_gpio  refclk_out_gpio   export   input    1} CONNECTIONS {refclk_in        refclk_in_gpio} {refclk_out_gpio  refclk_out} CUSTOM_ELABORATION_COMMANDS </message>
   <message level="Debug">get_component_parameters </message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property refclk_gpio ENABLED true</message>
   <message level="Debug">sync_sysinfo_parameters refclk_gpio</message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_gpio</strong>]]></message>
   <message level="Debug">add_connection refclk_gpio.dout refclk_bridge.refclk_out_gpio</message>
   <message level="Debug">add_connection refclk_bridge.refclk_in_gpio refclk_gpio.pad_in</message>
   <message level="Debug">add_connection refclk_bridge.refclk_out emif_0_lpddr4.ref_clk</message>
   <message level="Debug">get_connections </message>
   <message level="Debug">get_interfaces </message>
   <message level="Debug">get_wirelevel_expressions </message>
   <message level="Debug">get_instances </message>
   <message level="Debug">get_instance_property emif_0_ddr4comp ENABLED</message>
   <message level="Debug">get_instance_property emif_0_ddr5comp ENABLED</message>
   <message level="Debug">get_instance_property emif_0_ddr5dimm ENABLED</message>
   <message level="Debug">get_instance_property emif_0_lpddr4 ENABLED</message>
   <message level="Debug">get_instance_interfaces emif_0_lpddr4</message>
   <message level="Debug">get_instance_property emif_0_lpddr5 ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr4comp ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr5comp ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr5dimm ENABLED</message>
   <message level="Debug">get_instance_property emif_1_lpddr4 ENABLED</message>
   <message level="Debug">get_instance_property emif_1_lpddr5 ENABLED</message>
   <message level="Debug">get_instance_property refclk_bridge ENABLED</message>
   <message level="Debug">get_instance_interfaces refclk_bridge</message>
   <message level="Debug">get_instance_property refclk_gpio ENABLED</message>
   <message level="Debug">get_instance_interfaces refclk_gpio</message>
   <message level="Debug">add_interface io96b0_to_hps  </message>
   <message level="Debug">set_interface_property io96b0_to_hps EXPORT_OF emif_0_lpddr4.io96b0_to_hps</message>
   <message level="Debug">get_interface_ports io96b0_to_hps</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 io96b0_to_hps</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_clock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_reset_n ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awaddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_araddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wstrb ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awaddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awburst ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awlen ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awlock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awqos ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awsize ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awuser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_araddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arburst ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arlen ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arlock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arqos ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arsize ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_aruser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wstrb ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wlast ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rlast ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps noc_aclk_0 ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps noc_rst_n_0 ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wuser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_ruser ROLE</message>
   <message level="Debug">set_interface_ports_property io96b0_to_hps NAME io96b0_to_hps_ch0_axil_clk s0_noc_axi4lite_clock io96b0_to_hps_ch0_axil_reset_n s0_noc_axi4lite_reset_n io96b0_to_hps_ch0_axil_awaddr s0_noc_axi4lite_awaddr io96b0_to_hps_ch0_axil_awvalid s0_noc_axi4lite_awvalid io96b0_to_hps_ch0_axil_awready s0_noc_axi4lite_awready io96b0_to_hps_ch0_axil_araddr s0_noc_axi4lite_araddr io96b0_to_hps_ch0_axil_arvalid s0_noc_axi4lite_arvalid io96b0_to_hps_ch0_axil_arready s0_noc_axi4lite_arready io96b0_to_hps_ch0_axil_wdata s0_noc_axi4lite_wdata io96b0_to_hps_ch0_axil_wvalid s0_noc_axi4lite_wvalid io96b0_to_hps_ch0_axil_wready s0_noc_axi4lite_wready io96b0_to_hps_ch0_axil_rresp s0_noc_axi4lite_rresp io96b0_to_hps_ch0_axil_rdata s0_noc_axi4lite_rdata io96b0_to_hps_ch0_axil_rvalid s0_noc_axi4lite_rvalid io96b0_to_hps_ch0_axil_rready s0_noc_axi4lite_rready io96b0_to_hps_ch0_axil_bresp s0_noc_axi4lite_bresp io96b0_to_hps_ch0_axil_bvalid s0_noc_axi4lite_bvalid io96b0_to_hps_ch0_axil_bready s0_noc_axi4lite_bready io96b0_to_hps_ch0_axil_awprot s0_noc_axi4lite_awprot io96b0_to_hps_ch0_axil_arprot s0_noc_axi4lite_arprot io96b0_to_hps_ch0_axil_wstrb s0_noc_axi4lite_wstrb io96b0_to_hps_axi4_ch0_awaddr s0_axi4_awaddr io96b0_to_hps_axi4_ch0_awburst s0_axi4_awburst io96b0_to_hps_axi4_ch0_awid s0_axi4_awid io96b0_to_hps_axi4_ch0_awlen s0_axi4_awlen io96b0_to_hps_axi4_ch0_awlock s0_axi4_awlock io96b0_to_hps_axi4_ch0_awqos s0_axi4_awqos io96b0_to_hps_axi4_ch0_awsize s0_axi4_awsize io96b0_to_hps_axi4_ch0_awvalid s0_axi4_awvalid io96b0_to_hps_axi4_ch0_awuser s0_axi4_awuser io96b0_to_hps_axi4_ch0_awprot s0_axi4_awprot io96b0_to_hps_axi4_ch0_awready s0_axi4_awready io96b0_to_hps_axi4_ch0_araddr s0_axi4_araddr io96b0_to_hps_axi4_ch0_arburst s0_axi4_arburst io96b0_to_hps_axi4_ch0_arid s0_axi4_arid io96b0_to_hps_axi4_ch0_arlen s0_axi4_arlen io96b0_to_hps_axi4_ch0_arlock s0_axi4_arlock io96b0_to_hps_axi4_ch0_arqos s0_axi4_arqos io96b0_to_hps_axi4_ch0_arsize s0_axi4_arsize io96b0_to_hps_axi4_ch0_arvalid s0_axi4_arvalid io96b0_to_hps_axi4_ch0_aruser s0_axi4_aruser io96b0_to_hps_axi4_ch0_arprot s0_axi4_arprot io96b0_to_hps_axi4_ch0_arready s0_axi4_arready io96b0_to_hps_axi4_ch0_wdata s0_axi4_wdata io96b0_to_hps_axi4_ch0_wstrb s0_axi4_wstrb io96b0_to_hps_axi4_ch0_wlast s0_axi4_wlast io96b0_to_hps_axi4_ch0_wvalid s0_axi4_wvalid io96b0_to_hps_axi4_ch0_wready s0_axi4_wready io96b0_to_hps_axi4_ch0_bready s0_axi4_bready io96b0_to_hps_axi4_ch0_bid s0_axi4_bid io96b0_to_hps_axi4_ch0_bresp s0_axi4_bresp io96b0_to_hps_axi4_ch0_bvalid s0_axi4_bvalid io96b0_to_hps_axi4_ch0_rready s0_axi4_rready io96b0_to_hps_axi4_ch0_rdata s0_axi4_rdata io96b0_to_hps_axi4_ch0_rid s0_axi4_rid io96b0_to_hps_axi4_ch0_rlast s0_axi4_rlast io96b0_to_hps_axi4_ch0_rresp s0_axi4_rresp io96b0_to_hps_axi4_ch0_rvalid s0_axi4_rvalid io96b0_to_hps_axi4_ch0_clk noc_aclk_0 io96b0_to_hps_axi4_ch0_reset_n noc_rst_n_0 io96b0_to_hps_axi4_ch0_wuser s0_axi4_wuser io96b0_to_hps_axi4_ch0_ruser s0_axi4_ruser</message>
   <message level="Debug">add_interface mem_0  </message>
   <message level="Debug">set_interface_property mem_0 EXPORT_OF emif_0_lpddr4.mem_0</message>
   <message level="Debug">get_interface_ports mem_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_cs ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_ca ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_cke ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dq ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dqs_t ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dqs_c ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dmi ROLE</message>
   <message level="Debug">set_interface_ports_property mem_0 NAME mem_0_mem_cs mem_0_cs mem_0_mem_ca mem_0_ca mem_0_mem_cke mem_0_cke mem_0_mem_dq mem_0_dq mem_0_mem_dqs_t mem_0_dqs_t mem_0_mem_dqs_c mem_0_dqs_c mem_0_mem_dmi mem_0_dmi</message>
   <message level="Debug">add_interface mem_ck_0  </message>
   <message level="Debug">set_interface_property mem_ck_0 EXPORT_OF emif_0_lpddr4.mem_ck_0</message>
   <message level="Debug">get_interface_ports mem_ck_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_ck_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_ck_0 mem_0_ck_t ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_ck_0 mem_0_ck_c ROLE</message>
   <message level="Debug">set_interface_ports_property mem_ck_0 NAME mem_ck_0_mem_ck_t mem_0_ck_t mem_ck_0_mem_ck_c mem_0_ck_c</message>
   <message level="Debug">add_interface mem_reset_n  </message>
   <message level="Debug">set_interface_property mem_reset_n EXPORT_OF emif_0_lpddr4.mem_reset_n</message>
   <message level="Debug">get_interface_ports mem_reset_n</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_reset_n</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_reset_n mem_0_reset_n ROLE</message>
   <message level="Debug">set_interface_ports_property mem_reset_n NAME mem_reset_n_mem_reset_n mem_0_reset_n</message>
   <message level="Debug">add_interface oct_0  </message>
   <message level="Debug">set_interface_property oct_0 EXPORT_OF emif_0_lpddr4.oct_0</message>
   <message level="Debug">get_interface_ports oct_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 oct_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 oct_0 oct_rzqin_0 ROLE</message>
   <message level="Debug">set_interface_ports_property oct_0 NAME oct_0_oct_rzqin oct_rzqin_0</message>
   <message level="Debug">add_interface ref_clk  </message>
   <message level="Debug">set_interface_property ref_clk EXPORT_OF refclk_bridge.refclk_in</message>
   <message level="Debug">get_interface_ports ref_clk</message>
   <message level="Debug">get_instance_interface_ports refclk_bridge refclk_in</message>
   <message level="Debug">get_instance_interface_port_property refclk_bridge refclk_in refclk_in ROLE</message>
   <message level="Debug">set_interface_ports_property ref_clk NAME ref_clk_clk ref_clk</message>
   <message level="Debug">sync_sysinfo_parameters </message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>emif_0_lpddr4</strong>]]></message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_bridge</strong>]]></message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_gpio</strong>]]></message>
   <message level="Debug">validate_system </message>
   <message level="Debug">save_system </message>
   <message level="Debug">All modules have been converted to Generic Components.</message>
   <message level="Debug">send_message Debug RESULT:messages {} | cmds {{set_instance_package_parameter_property emif_0_lpddr4 PHY_AC_PLACEMENT DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 MEM_NUM_CHANNELS DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 PHY_MAINBAND_ACCESS_MODE DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 PHY_MAINBAND_ACCESS_MODE DISABLED false} {set_instance_package_parameter_property refclk_bridge CONNECTIONS DISABLED true} {set_instance_package_parameter_property refclk_bridge CUSTOM_ELABORATION_COMMANDS DISABLED true} {set_instance_package_parameter_property refclk_bridge INTERFACES DISABLED true} {set_instance_package_parameter_property refclk_bridge PORTS DISABLED true}} | PHY_TERM_X_R_T_REFCLK_INPUT_OHM RT_DIFF MEM_CHANNEL_CAPACITY_GBITS 16.0 PHY_TERM_X_REFCLK_IO_STD_TYPE TRUE_DIFF</message>
   <message level="Debug" culprit="emif_io96b_hps">elaboration time: 2.63 s</message>
   <message level="Debug">load_component emif_0_lpddr4</message>
   <message level="Debug">set_component_parameter_value PHY_CS_TX_EQUALIZATION OFF</message>
   <message level="Debug">set_component_parameter_value MEM_DIE_DENSITY_GBITS 4</message>
   <message level="Debug">set_component_parameter_value MEM_MINNUMREFSREQ 8192.0</message>
   <message level="Debug">set_component_parameter_value MEM_TREFI_NS 3904.0</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_R2W_SAMECS_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_CHANNEL_CS_WIDTH 1</message>
   <message level="Debug">set_component_parameter_value CTRL_FIXED_W_PRIORITY 0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_S_CK_OUTPUT_OHM SERIES_40_OHM_CAL</message>
   <message level="Debug">set_component_parameter_value INSTANCE_ID 0</message>
   <message level="Debug">set_component_parameter_value MEM_TCKEHCMD_NS 7.5</message>
   <message level="Debug">set_component_parameter_value MEM_TRPPB_NS 18.0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_S_DQ_OUTPUT_OHM SERIES_40_OHM_CAL</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_DQ_VREF 17.5</message>
   <message level="Debug">set_component_parameter_value MEM_TRCD_NS 18.0</message>
   <message level="Debug">set_component_parameter_value EX_DESIGN_TG_WIDE_IF false</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_DQ_X_IDLE off</message>
   <message level="Debug">set_component_parameter_value MEM_TRC_NS 63.0</message>
   <message level="Debug">set_component_parameter_value MEM_OPERATING_FREQ_MHZ 1333.333</message>
   <message level="Debug">set_component_parameter_value CTRL_FIXED_R_PRIORITY 0</message>
   <message level="Debug">set_component_parameter_value PHY_AC_PLACEMENT BOT</message>
   <message level="Debug">set_component_parameter_value CTRL_FIXED_PRIORITY_EN false</message>
   <message level="Debug">set_component_parameter_value CTRL_AUTO_PRECHARGE_EN false</message>
   <message level="Debug">set_component_parameter_value PHY_REFCLK_FREQ_MHZ_AUTOSET_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_DQ_VREF 45</message>
   <message level="Debug">set_component_parameter_value MEM_TCMDCKE_NS 2.25</message>
   <message level="Debug">set_component_parameter_value EX_DESIGN_PMON_CH2_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_NUM_CHANNELS 1</message>
   <message level="Debug">set_component_parameter_value MEM_TXSR_NS 187.5</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_W2W_SAMECS_CYC 0</message>
   <message level="Debug">set_component_parameter_value EX_DESIGN_PMON_INTERNAL_JAMB_EN true</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_GPIO_IO_STD_TYPE LVCMOS</message>
   <message level="Debug">set_component_parameter_value MEM_TRAS_NS 42.0</message>
   <message level="Debug">set_component_parameter_value ADV_CAL_ENABLE_REQ false</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_CK_SLEW_RATE FASTEST</message>
   <message level="Debug">set_component_parameter_value ADV_CAL_ENABLE_MARGIN false</message>
   <message level="Debug">set_component_parameter_value MEM_PER_BANK_REF_EN 1</message>
   <message level="Debug">set_component_parameter_value MEM_CWL_CYC 22</message>
   <message level="Debug">set_component_parameter_value JEDEC_OVERRIDE_TABLE_PARAM_NAME MEM_TCCD_NS</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_CS_SLEW_RATE FASTEST</message>
   <message level="Debug">set_component_parameter_value MEM_RD_PREAMBLE_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_TRFCAB_NS 180.0</message>
   <message level="Debug">set_component_parameter_value MEM_TSR_NS 15.0</message>
   <message level="Debug">set_component_parameter_value CTRL_WR_DBI_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_TPPD_CYC 4.0</message>
   <message level="Debug">set_component_parameter_value MEM_CA_VREF 33</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_DQS_IO_STD_TYPE DF_LVSTL</message>
   <message level="Debug">set_component_parameter_value PHY_CK_TX_EQUALIZATION OFF</message>
   <message level="Debug">set_component_parameter_value MEM_TWR_NS 18.0</message>
   <message level="Debug">set_component_parameter_value MEM_TESCKE_NS 2.25</message>
   <message level="Debug">set_component_parameter_value MEM_TXP_NS 7.5</message>
   <message level="Debug">set_component_parameter_value CTRL_DM_EN true</message>
   <message level="Debug">set_component_parameter_value ANALOG_PARAM_DERIVATION_PARAM_NAME MEM_VREF_DQ_X_VALUE MEM_VREF_CA_X_CA_VALUE MEM_VREF_CA_X_CA_RANGE</message>
   <message level="Debug">set_component_parameter_value CTRL_SCRAMBLER_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_TECH_IS_X false</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_CA_X_CA_ENABLE true</message>
   <message level="Debug">set_component_parameter_value MEM_TDQSCK_MAX_NS 3.5</message>
   <message level="Debug">set_component_parameter_value MEM_TWTR_NS 10.0</message>
   <message level="Debug">set_component_parameter_value DIAG_HMC_ADDR_SWAP_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_TRRD_NS 10.0</message>
   <message level="Debug">set_component_parameter_value MEM_TCSCKEH_NS 1.75</message>
   <message level="Debug">set_component_parameter_value MEM_TCKCKEH_NS 2.25</message>
   <message level="Debug">set_component_parameter_value MEM_VREF_CA_X_CA_RANGE 1</message>
   <message level="Debug">set_component_parameter_value MEM_VREF_CA_X_CA_VALUE 23.2</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_W2W_DIFFCS_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_TCKELCMD_NS 5.0</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_CA_X_CA_COMM 3</message>
   <message level="Debug">set_component_parameter_value MEM_TMRR_NS 6.0</message>
   <message level="Debug">set_component_parameter_value PHY_AC_TX_EQUALIZATION OFF</message>
   <message level="Debug">set_component_parameter_value CTRL_ECC_INLINE_EN false</message>
   <message level="Debug">set_component_parameter_value EX_DESIGN_PMON_CH1_EN false</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_AC_SLEW_RATE FASTEST</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_S_AC_OUTPUT_OHM SERIES_40_OHM_CAL</message>
   <message level="Debug">set_component_parameter_value MEM_TCKELCK_NS 5.0</message>
   <message level="Debug">set_component_parameter_value CTRL_PLACEMENT_EN true</message>
   <message level="Debug">set_component_parameter_value MEM_TCCD_NS 8.0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_DQ_SLEW_RATE FASTEST</message>
   <message level="Debug">set_component_parameter_value DIAG_FORCE_SLIM_EN false</message>
   <message level="Debug">set_component_parameter_value CTRL_ALL_STRB_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_TDQSCK_MIN_NS 1.5</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_W2R_SAMECS_CYC 0</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_R2R_DIFFCS_CYC 0</message>
   <message level="Debug">set_component_parameter_value PHY_REFCLK_ADVANCED_SELECT_EN true</message>
   <message level="Debug">set_component_parameter_value CTRL_RD_DBI_EN true</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_R2R_SAMECS_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_VREF_DQ_X_VALUE 28.0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_S_CS_OUTPUT_OHM SERIES_40_OHM_CAL</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_AC_OUTPUT_IO_STD_TYPE LVSTL</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_DQ_X_RON 6</message>
   <message level="Debug">set_component_parameter_value MEM_VREF_DQ_X_RANGE 1</message>
   <message level="Debug">set_component_parameter_value ADV_CAL_ENABLE_WEQ false</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_T_DQ_INPUT_OHM RT_50_OHM_CAL</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_CA_X_CK_ENABLE true</message>
   <message level="Debug">set_component_parameter_value MEM_TMRD_NS 14.0</message>
   <message level="Debug">set_component_parameter_value MEM_TFAW_NS 40.0</message>
   <message level="Debug">set_component_parameter_value MEM_TZQCKE_NS 2.25</message>
   <message level="Debug">set_component_parameter_value MEM_TMRW_NS 10.0</message>
   <message level="Debug">set_component_parameter_value MEM_RD_POSTAMBLE_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_OPERATING_FREQ_MHZ_AUTOSET_EN true</message>
   <message level="Debug">set_component_parameter_value MEM_TCSCKE_NS 1.75</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_DQ_IO_STD_TYPE LVSTL</message>
   <message level="Debug">set_component_parameter_value MEM_TRTP_NS 7.5</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_W2R_DIFFCS_CYC 0</message>
   <message level="Debug">set_component_parameter_value CTRL_PERFORMANCE_PROFILE SEQ</message>
   <message level="Debug">set_component_parameter_value EX_DESIGN_PMON_CH3_EN false</message>
   <message level="Debug">set_component_parameter_value PHY_REFCLK_FREQ_MHZ 166.6666</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_DQ_X_TGT_WR 5</message>
   <message level="Debug">set_component_parameter_value MEM_CL_CYC 28</message>
   <message level="Debug">set_component_parameter_value MEM_TREFW_NS 3.2E7</message>
   <message level="Debug">set_component_parameter_value CTRL_ECC_AUTOCORRECT_EN false</message>
   <message level="Debug">set_component_parameter_value MEM_WR_POSTAMBLE_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_TCKE_NS 7.5</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_CK_OUTPUT_IO_STD_TYPE DF_LVSTL</message>
   <message level="Debug">set_component_parameter_value PHY_DQ_TX_EQUALIZATION OFF</message>
   <message level="Debug">set_component_parameter_value MEM_TZQCAL_NS 1000.0</message>
   <message level="Debug">set_component_parameter_value MEM_ODT_CA_X_CS_ENABLE true</message>
   <message level="Debug">set_component_parameter_value MEM_TMRWCKEL_NS 14.0</message>
   <message level="Debug">set_component_parameter_value MEM_WLS 1.0</message>
   <message level="Debug">set_component_parameter_value PHY_SWIZZLE_MAP PIN_SWIZZLE_CH0_DQS0=5 4 0 7 1 6 2 3;PIN_SWIZZLE_CH0_DQS1=15 8 14 9 12 13 11 10;PIN_SWIZZLE_CH0_DQS2=18 22 19 20 21 23 16 17;PIN_SWIZZLE_CH0_DQS3=27 29 28 26 24 25 31 30;</message>
   <message level="Debug">set_component_parameter_value MEM_TRFCPB_NS 90.0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_CS_OUTPUT_IO_STD_TYPE LVSTL</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_REFCLK_IO_STD_TYPE TRUE_DIFF</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_T_REFCLK_INPUT_OHM RT_DIFF</message>
   <message level="Debug">set_component_parameter_value MEM_TCKCKEL_NS 5.0</message>
   <message level="Debug">set_component_parameter_value IS_HPS true</message>
   <message level="Debug">set_component_parameter_value TURNAROUND_R2W_DIFFCS_CYC 0</message>
   <message level="Debug">set_component_parameter_value MEM_TRPAB_NS 21.0</message>
   <message level="Debug">set_component_parameter_value PHY_TERM_X_R_T_GPIO_INPUT_OHM RT_OFF</message>
   <message level="Debug">set_component_parameter_value MEM_TZQLAT_NS 30.0</message>
   <message level="Debug">save_component </message>
   <message level="Debug">load_component refclk_bridge</message>
   <message level="Debug">set_component_parameter_value INTERFACES {refclk_in        clock    sink} {refclk_out       clock    source} {refclk_in_gpio   conduit  end} {refclk_out_gpio  conduit  start}</message>
   <message level="Debug">set_component_parameter_value CONNECTIONS {refclk_in        refclk_in_gpio} {refclk_out_gpio  refclk_out}</message>
   <message level="Debug">set_component_parameter_value PORTS {refclk_in        refclk_in         clk      input    1} {refclk_out       refclk_out        clk      output   1} {refclk_in_gpio   refclk_in_gpio    export   output   1} {refclk_out_gpio  refclk_out_gpio   export   input    1}</message>
   <message level="Debug">save_component </message>
   <message level="Debug">save_system </message>
   <message level="Debug">All modules have been converted to Generic Components.</message>
   <message level="Debug">set_validation_property AUTOMATIC_VALIDATION false</message>
   <message level="Debug">set_project_property DEVICE_FAMILY Agilex 5</message>
   <message level="Debug">set_project_property DEVICE A5EB013BB23BE4SCS</message>
   <message level="Debug">remove_dangling_connections </message>
   <message level="Debug">get_connections </message>
   <message level="Debug">remove_connections refclk_bridge.refclk_in_gpio/refclk_gpio.pad_in refclk_bridge.refclk_out/emif_0_lpddr4.ref_clk refclk_gpio.dout/refclk_bridge.refclk_out_gpio</message>
   <message level="Debug">get_interfaces </message>
   <message level="Debug">remove_interfaces io96b0_to_hps mem_0 mem_ck_0 mem_reset_n oct_0 ref_clk</message>
   <message level="Debug">get_instances </message>
   <message level="Debug">set_instance_property emif_0_ddr4comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_ddr5comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_ddr5dimm ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr5 ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr4comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr5comp ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_ddr5dimm ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_lpddr4 ENABLED false</message>
   <message level="Debug">set_instance_property emif_1_lpddr5 ENABLED false</message>
   <message level="Debug">set_instance_property refclk_bridge ENABLED false</message>
   <message level="Debug">set_instance_property refclk_gpio ENABLED false</message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED true</message>
   <message level="Debug">load_component emif_0_lpddr4</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">get_component_parameter_values PHY_MAINBAND_ACCESS_MODE INSTANCE_ID PHY_TERM_X_REFCLK_IO_STD_TYPE PHY_TERM_X_R_T_REFCLK_INPUT_OHM MEM_CHANNEL_CAPACITY_GBITS</message>
   <message level="Debug">set_component_parameter_values MEM_CHANNEL_DATA_DQ_WIDTH 32</message>
   <message level="Debug">set_component_parameter_value PHY_AC_PLACEMENT BOT</message>
   <message level="Debug">set_component_parameter_value MEM_NUM_CHANNELS 1</message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property emif_0_lpddr4 ENABLED true</message>
   <message level="Debug">load_component emif_0_lpddr4</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">get_component_parameters </message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_MARGIN</message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_REQ</message>
   <message level="Debug">get_component_parameter_value ADV_CAL_ENABLE_WEQ</message>
   <message level="Debug">get_component_parameter_value ANALOG_PARAM_DERIVATION_PARAM_NAME</message>
   <message level="Debug">get_component_parameter_value AXI4_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value CTRL_ALL_STRB_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_AUTO_PRECHARGE_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_DM_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_ECC_AUTOCORRECT_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_ECC_INLINE_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_PRIORITY_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_R_PRIORITY</message>
   <message level="Debug">get_component_parameter_value CTRL_FIXED_W_PRIORITY</message>
   <message level="Debug">get_component_parameter_value CTRL_PERFORMANCE_PROFILE</message>
   <message level="Debug">get_component_parameter_value CTRL_PLACEMENT_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_RD_DBI_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_SCRAMBLER_EN</message>
   <message level="Debug">get_component_parameter_value CTRL_WR_DBI_EN</message>
   <message level="Debug">get_component_parameter_value DEBUG_PRINT_LEVEL</message>
   <message level="Debug">get_component_parameter_value DEBUG_TOOLS_EN</message>
   <message level="Debug">get_component_parameter_value DIAG_EXTRA_PARAMETERS</message>
   <message level="Debug">get_component_parameter_value DIAG_FORCE_SLIM_EN</message>
   <message level="Debug">get_component_parameter_value DIAG_HMC_ADDR_SWAP_EN</message>
   <message level="Debug">get_component_parameter_value EMIF_INST_NAME</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_CDC</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_SIM</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_GEN_SYNTH</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_HDL_FORMAT</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_NOC_PLL_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH0_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH1_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH2_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_CH3_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_PMON_INTERNAL_JAMB_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_CSR_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_PROGRAM</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_TG_WIDE_IF</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_OUTPUT_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value EX_DESIGN_USER_PLL_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value INSTANCE_ID</message>
   <message level="Debug">get_component_parameter_value IS_HPS</message>
   <message level="Debug">get_component_parameter_value JEDEC_OVERRIDE_TABLE_PARAM_NAME</message>
   <message level="Debug">get_component_parameter_value MEM_BANK_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CA_VREF</message>
   <message level="Debug">get_component_parameter_value MEM_CA_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_ADDR_NUM_BITS</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_CAPACITY_GBITS</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_CS_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CHANNEL_DATA_DQ_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CKE_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CK_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CL_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_COL_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CS_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_CWL_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_DIE_DENSITY_GBITS</message>
   <message level="Debug">get_component_parameter_value MEM_DQ_PER_DQS</message>
   <message level="Debug">get_component_parameter_value MEM_DQ_VREF</message>
   <message level="Debug">get_component_parameter_value MEM_MINNUMREFSREQ</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_CHANNELS</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_CHANNELS_PER_IO96</message>
   <message level="Debug">get_component_parameter_value MEM_NUM_IO96</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CA_COMM</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CA_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CK_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_CA_X_CS_ENABLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_IDLE</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_RON</message>
   <message level="Debug">get_component_parameter_value MEM_ODT_DQ_X_TGT_WR</message>
   <message level="Debug">get_component_parameter_value MEM_OPERATING_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value MEM_OPERATING_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value MEM_PER_BANK_REF_EN</message>
   <message level="Debug">get_component_parameter_value MEM_RD_POSTAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_RD_PREAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_ROW_ADDR_WIDTH</message>
   <message level="Debug">get_component_parameter_value MEM_TCCD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKCKEH_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKCKEL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKEHCMD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKELCK_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKELCMD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCMDCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCSCKEH_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TCSCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TDQSCK_MAX_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TDQSCK_MIN_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TECH_IS_X</message>
   <message level="Debug">get_component_parameter_value MEM_TESCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TFAW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRWCKEL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TMRW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TPPD_CYC</message>
   <message level="Debug">get_component_parameter_value MEM_TRAS_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRCD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRC_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TREFI_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TREFW_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRFCAB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRFCPB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRPAB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRPPB_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRRD_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TRTP_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TSR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TWR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TWTR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TXP_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TXSR_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQCAL_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQCKE_NS</message>
   <message level="Debug">get_component_parameter_value MEM_TZQLAT_NS</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_CA_X_CA_RANGE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_CA_X_CA_VALUE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_DQ_X_RANGE</message>
   <message level="Debug">get_component_parameter_value MEM_VREF_DQ_X_VALUE</message>
   <message level="Debug">get_component_parameter_value MEM_WLS</message>
   <message level="Debug">get_component_parameter_value MEM_WR_POSTAMBLE_CYC</message>
   <message level="Debug">get_component_parameter_value NUM_IO96_IN_CHIP</message>
   <message level="Debug">get_component_parameter_value PHY_AC_PLACEMENT</message>
   <message level="Debug">get_component_parameter_value PHY_AC_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_CK_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_CS_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_DQ_TX_EQUALIZATION</message>
   <message level="Debug">get_component_parameter_value PHY_MAINBAND_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value PHY_MAINBAND_ACCESS_MODE_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_ADVANCED_SELECT_EN</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_FREQ_MHZ</message>
   <message level="Debug">get_component_parameter_value PHY_REFCLK_FREQ_MHZ_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_SIDEBAND_ACCESS_MODE</message>
   <message level="Debug">get_component_parameter_value PHY_SIDEBAND_ACCESS_MODE_AUTOSET_EN</message>
   <message level="Debug">get_component_parameter_value PHY_SWIZZLE_MAP</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_AC_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_AC_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CK_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CK_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CS_OUTPUT_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_CS_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQS_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_SLEW_RATE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_DQ_VREF</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_GPIO_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_REFCLK_IO_STD_TYPE</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_AC_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_CK_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_CS_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_S_DQ_OUTPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_DQ_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_GPIO_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PHY_TERM_X_R_T_REFCLK_INPUT_OHM</message>
   <message level="Debug">get_component_parameter_value PLACEMENT_SCHEMES</message>
   <message level="Debug">get_component_parameter_value S0_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S1_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S2_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value S3_AXID_WIDTH</message>
   <message level="Debug">get_component_parameter_value SYSINFO_BOARD</message>
   <message level="Debug">get_component_parameter_value SYSINFO_BOARD_TRAIT</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_BASE_DIE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_DIE_REVISIONS</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_FAMILY</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_GROUP</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_IOBANK_REVISION</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_POWER_MODEL</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_SPEEDGRADE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_DEVICE_TEMPERATURE_GRADE</message>
   <message level="Debug">get_component_parameter_value SYSINFO_SUPPORTS_VID</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2R_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2R_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2W_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_R2W_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2R_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2R_SAMECS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2W_DIFFCS_CYC</message>
   <message level="Debug">get_component_parameter_value TURNAROUND_W2W_SAMECS_CYC</message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property refclk_bridge ENABLED true</message>
   <message level="Debug">load_component refclk_bridge</message>
   <message level="Debug">sync_component_sysinfo_parameters </message>
   <message level="Debug">set_component_parameter_values INTERFACES {refclk_in        clock    sink} {refclk_out       clock    source} {refclk_in_gpio   conduit  end} {refclk_out_gpio  conduit  start} PORTS {refclk_in        refclk_in         clk      input    1} {refclk_out       refclk_out        clk      output   1} {refclk_in_gpio   refclk_in_gpio    export   output   1} {refclk_out_gpio  refclk_out_gpio   export   input    1} CONNECTIONS {refclk_in        refclk_in_gpio} {refclk_out_gpio  refclk_out} CUSTOM_ELABORATION_COMMANDS </message>
   <message level="Debug">get_component_parameters </message>
   <message level="Debug">validate_component </message>
   <message level="Debug">save_component </message>
   <message level="Debug">set_instance_property refclk_gpio ENABLED true</message>
   <message level="Debug">sync_sysinfo_parameters refclk_gpio</message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_gpio</strong>]]></message>
   <message level="Debug">add_connection refclk_gpio.dout refclk_bridge.refclk_out_gpio</message>
   <message level="Debug">add_connection refclk_bridge.refclk_in_gpio refclk_gpio.pad_in</message>
   <message level="Debug">add_connection refclk_bridge.refclk_out emif_0_lpddr4.ref_clk</message>
   <message level="Debug">get_connections </message>
   <message level="Debug">get_interfaces </message>
   <message level="Debug">get_wirelevel_expressions </message>
   <message level="Debug">get_instances </message>
   <message level="Debug">get_instance_property emif_0_ddr4comp ENABLED</message>
   <message level="Debug">get_instance_property emif_0_ddr5comp ENABLED</message>
   <message level="Debug">get_instance_property emif_0_ddr5dimm ENABLED</message>
   <message level="Debug">get_instance_property emif_0_lpddr4 ENABLED</message>
   <message level="Debug">get_instance_interfaces emif_0_lpddr4</message>
   <message level="Debug">get_instance_property emif_0_lpddr5 ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr4comp ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr5comp ENABLED</message>
   <message level="Debug">get_instance_property emif_1_ddr5dimm ENABLED</message>
   <message level="Debug">get_instance_property emif_1_lpddr4 ENABLED</message>
   <message level="Debug">get_instance_property emif_1_lpddr5 ENABLED</message>
   <message level="Debug">get_instance_property refclk_bridge ENABLED</message>
   <message level="Debug">get_instance_interfaces refclk_bridge</message>
   <message level="Debug">get_instance_property refclk_gpio ENABLED</message>
   <message level="Debug">get_instance_interfaces refclk_gpio</message>
   <message level="Debug">add_interface io96b0_to_hps  </message>
   <message level="Debug">set_interface_property io96b0_to_hps EXPORT_OF emif_0_lpddr4.io96b0_to_hps</message>
   <message level="Debug">get_interface_ports io96b0_to_hps</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 io96b0_to_hps</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_clock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_reset_n ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awaddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_araddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_rready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_bready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_awprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_arprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_noc_axi4lite_wstrb ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awaddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awburst ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awlen ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awlock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awqos ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awsize ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awuser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_awready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_araddr ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arburst ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arlen ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arlock ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arqos ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arsize ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_aruser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arprot ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_arready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wstrb ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wlast ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_bvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rready ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rdata ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rlast ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rresp ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_rvalid ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps noc_aclk_0 ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps noc_rst_n_0 ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_wuser ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 io96b0_to_hps s0_axi4_ruser ROLE</message>
   <message level="Debug">set_interface_ports_property io96b0_to_hps NAME io96b0_to_hps_ch0_axil_clk s0_noc_axi4lite_clock io96b0_to_hps_ch0_axil_reset_n s0_noc_axi4lite_reset_n io96b0_to_hps_ch0_axil_awaddr s0_noc_axi4lite_awaddr io96b0_to_hps_ch0_axil_awvalid s0_noc_axi4lite_awvalid io96b0_to_hps_ch0_axil_awready s0_noc_axi4lite_awready io96b0_to_hps_ch0_axil_araddr s0_noc_axi4lite_araddr io96b0_to_hps_ch0_axil_arvalid s0_noc_axi4lite_arvalid io96b0_to_hps_ch0_axil_arready s0_noc_axi4lite_arready io96b0_to_hps_ch0_axil_wdata s0_noc_axi4lite_wdata io96b0_to_hps_ch0_axil_wvalid s0_noc_axi4lite_wvalid io96b0_to_hps_ch0_axil_wready s0_noc_axi4lite_wready io96b0_to_hps_ch0_axil_rresp s0_noc_axi4lite_rresp io96b0_to_hps_ch0_axil_rdata s0_noc_axi4lite_rdata io96b0_to_hps_ch0_axil_rvalid s0_noc_axi4lite_rvalid io96b0_to_hps_ch0_axil_rready s0_noc_axi4lite_rready io96b0_to_hps_ch0_axil_bresp s0_noc_axi4lite_bresp io96b0_to_hps_ch0_axil_bvalid s0_noc_axi4lite_bvalid io96b0_to_hps_ch0_axil_bready s0_noc_axi4lite_bready io96b0_to_hps_ch0_axil_awprot s0_noc_axi4lite_awprot io96b0_to_hps_ch0_axil_arprot s0_noc_axi4lite_arprot io96b0_to_hps_ch0_axil_wstrb s0_noc_axi4lite_wstrb io96b0_to_hps_axi4_ch0_awaddr s0_axi4_awaddr io96b0_to_hps_axi4_ch0_awburst s0_axi4_awburst io96b0_to_hps_axi4_ch0_awid s0_axi4_awid io96b0_to_hps_axi4_ch0_awlen s0_axi4_awlen io96b0_to_hps_axi4_ch0_awlock s0_axi4_awlock io96b0_to_hps_axi4_ch0_awqos s0_axi4_awqos io96b0_to_hps_axi4_ch0_awsize s0_axi4_awsize io96b0_to_hps_axi4_ch0_awvalid s0_axi4_awvalid io96b0_to_hps_axi4_ch0_awuser s0_axi4_awuser io96b0_to_hps_axi4_ch0_awprot s0_axi4_awprot io96b0_to_hps_axi4_ch0_awready s0_axi4_awready io96b0_to_hps_axi4_ch0_araddr s0_axi4_araddr io96b0_to_hps_axi4_ch0_arburst s0_axi4_arburst io96b0_to_hps_axi4_ch0_arid s0_axi4_arid io96b0_to_hps_axi4_ch0_arlen s0_axi4_arlen io96b0_to_hps_axi4_ch0_arlock s0_axi4_arlock io96b0_to_hps_axi4_ch0_arqos s0_axi4_arqos io96b0_to_hps_axi4_ch0_arsize s0_axi4_arsize io96b0_to_hps_axi4_ch0_arvalid s0_axi4_arvalid io96b0_to_hps_axi4_ch0_aruser s0_axi4_aruser io96b0_to_hps_axi4_ch0_arprot s0_axi4_arprot io96b0_to_hps_axi4_ch0_arready s0_axi4_arready io96b0_to_hps_axi4_ch0_wdata s0_axi4_wdata io96b0_to_hps_axi4_ch0_wstrb s0_axi4_wstrb io96b0_to_hps_axi4_ch0_wlast s0_axi4_wlast io96b0_to_hps_axi4_ch0_wvalid s0_axi4_wvalid io96b0_to_hps_axi4_ch0_wready s0_axi4_wready io96b0_to_hps_axi4_ch0_bready s0_axi4_bready io96b0_to_hps_axi4_ch0_bid s0_axi4_bid io96b0_to_hps_axi4_ch0_bresp s0_axi4_bresp io96b0_to_hps_axi4_ch0_bvalid s0_axi4_bvalid io96b0_to_hps_axi4_ch0_rready s0_axi4_rready io96b0_to_hps_axi4_ch0_rdata s0_axi4_rdata io96b0_to_hps_axi4_ch0_rid s0_axi4_rid io96b0_to_hps_axi4_ch0_rlast s0_axi4_rlast io96b0_to_hps_axi4_ch0_rresp s0_axi4_rresp io96b0_to_hps_axi4_ch0_rvalid s0_axi4_rvalid io96b0_to_hps_axi4_ch0_clk noc_aclk_0 io96b0_to_hps_axi4_ch0_reset_n noc_rst_n_0 io96b0_to_hps_axi4_ch0_wuser s0_axi4_wuser io96b0_to_hps_axi4_ch0_ruser s0_axi4_ruser</message>
   <message level="Debug">add_interface mem_0  </message>
   <message level="Debug">set_interface_property mem_0 EXPORT_OF emif_0_lpddr4.mem_0</message>
   <message level="Debug">get_interface_ports mem_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_cs ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_ca ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_cke ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dq ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dqs_t ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dqs_c ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_0 mem_0_dmi ROLE</message>
   <message level="Debug">set_interface_ports_property mem_0 NAME mem_0_mem_cs mem_0_cs mem_0_mem_ca mem_0_ca mem_0_mem_cke mem_0_cke mem_0_mem_dq mem_0_dq mem_0_mem_dqs_t mem_0_dqs_t mem_0_mem_dqs_c mem_0_dqs_c mem_0_mem_dmi mem_0_dmi</message>
   <message level="Debug">add_interface mem_ck_0  </message>
   <message level="Debug">set_interface_property mem_ck_0 EXPORT_OF emif_0_lpddr4.mem_ck_0</message>
   <message level="Debug">get_interface_ports mem_ck_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_ck_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_ck_0 mem_0_ck_t ROLE</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_ck_0 mem_0_ck_c ROLE</message>
   <message level="Debug">set_interface_ports_property mem_ck_0 NAME mem_ck_0_mem_ck_t mem_0_ck_t mem_ck_0_mem_ck_c mem_0_ck_c</message>
   <message level="Debug">add_interface mem_reset_n  </message>
   <message level="Debug">set_interface_property mem_reset_n EXPORT_OF emif_0_lpddr4.mem_reset_n</message>
   <message level="Debug">get_interface_ports mem_reset_n</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 mem_reset_n</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 mem_reset_n mem_0_reset_n ROLE</message>
   <message level="Debug">set_interface_ports_property mem_reset_n NAME mem_reset_n_mem_reset_n mem_0_reset_n</message>
   <message level="Debug">add_interface oct_0  </message>
   <message level="Debug">set_interface_property oct_0 EXPORT_OF emif_0_lpddr4.oct_0</message>
   <message level="Debug">get_interface_ports oct_0</message>
   <message level="Debug">get_instance_interface_ports emif_0_lpddr4 oct_0</message>
   <message level="Debug">get_instance_interface_port_property emif_0_lpddr4 oct_0 oct_rzqin_0 ROLE</message>
   <message level="Debug">set_interface_ports_property oct_0 NAME oct_0_oct_rzqin oct_rzqin_0</message>
   <message level="Debug">add_interface ref_clk  </message>
   <message level="Debug">set_interface_property ref_clk EXPORT_OF refclk_bridge.refclk_in</message>
   <message level="Debug">get_interface_ports ref_clk</message>
   <message level="Debug">get_instance_interface_ports refclk_bridge refclk_in</message>
   <message level="Debug">get_instance_interface_port_property refclk_bridge refclk_in refclk_in ROLE</message>
   <message level="Debug">set_interface_ports_property ref_clk NAME ref_clk_clk ref_clk</message>
   <message level="Debug">sync_sysinfo_parameters </message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>emif_0_lpddr4</strong>]]></message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_bridge</strong>]]></message>
   <message level="Debug"><![CDATA[Synchronizing System Information for <strong>refclk_gpio</strong>]]></message>
   <message level="Debug">validate_system </message>
   <message level="Debug">save_system </message>
   <message level="Debug">All modules have been converted to Generic Components.</message>
   <message level="Debug">send_message Debug RESULT:messages {} | cmds {{set_instance_package_parameter_property emif_0_lpddr4 PHY_AC_PLACEMENT DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 MEM_NUM_CHANNELS DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 PHY_MAINBAND_ACCESS_MODE DISABLED true} {set_instance_package_parameter_property emif_0_lpddr4 PHY_MAINBAND_ACCESS_MODE DISABLED false} {set_instance_package_parameter_property refclk_bridge CONNECTIONS DISABLED true} {set_instance_package_parameter_property refclk_bridge CUSTOM_ELABORATION_COMMANDS DISABLED true} {set_instance_package_parameter_property refclk_bridge INTERFACES DISABLED true} {set_instance_package_parameter_property refclk_bridge PORTS DISABLED true}} | PHY_TERM_X_R_T_REFCLK_INPUT_OHM RT_DIFF MEM_CHANNEL_CAPACITY_GBITS 8.0 PHY_TERM_X_REFCLK_IO_STD_TYPE TRUE_DIFF</message>
   <message level="Debug" culprit="emif_io96b_hps">elaboration time: 1.76 s</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: qsys-generate emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys --synthesis=VERILOG --package-subsystem --generate-all-simulation-scripts --part=A5EB013BB23BE4SCS --search-path=/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/**/*,/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/**/*,$ --clear-output-directory</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: ***************************************************************</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: Quartus is a registered trademark of Altera Corporation in the</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: US and other countries.  Portions of the Quartus Prime software</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: code, and other portions of the code included in this download</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: or on this DVD, are licensed to Altera Corporation and are the</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: copyrighted property of third parties. For license details,</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: refer to the Altera Software License Subscription Agreements </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: on the Quartus Prime software download page.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: ***************************************************************</message>
   <message level="Warning" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:08 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:13 Info: Parallel IP Generation is enabled. </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:13 Info: Platform Designer will attempt to use 4 processors for parallel IP generation based on available number of processors and the total number of IP to be generated.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:13 Info: </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:13 Info: Starting: Platform Designer system generation</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Generating on localhost:38153</message>
   <message level="Warning" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Saving generation log to /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge_generation.rpt</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Generated by version: 26.1 build 110</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Starting: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: qsys-generate /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.ip --synthesis=VERILOG --output-directory=/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge --family="Agilex 5" --part=A5EB013BB23BE4SCS</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: "Transforming system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: "Naming system components in system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: "Processing generation queue"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge_qsys_interface_bridge_10_tos2vpi"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge: Done "emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge" with 2 modules, 2 files</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Finished: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:22 Info: Generation of /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge.ip (emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge) took 280 ms</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generating on localhost:45717</message>
   <message level="Warning" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Saving generation log to /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio_generation.rpt</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generated by version: 26.1 build 110</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Starting: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: qsys-generate /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.ip --synthesis=VERILOG --output-directory=/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio --family="Agilex 5" --part=A5EB013BB23BE4SCS</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.refclk_gpio: GPIO supports a maximum interface frequency of 250 MHZ.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Transforming system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Naming system components in system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Processing generation queue"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio_altera_gpio_2300_ctzjwfq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: "Generating: altera_gpio"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio: Done "emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio" with 3 modules, 3 files</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Finished: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generation of /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio.ip (emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio) took 368 ms</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generating on localhost:46525</message>
   <message level="Warning" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: All Generic Component instances match their respective ip files.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Saving generation log to /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_generation.rpt</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generated by version: 26.1 build 110</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Starting: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: qsys-generate /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys --synthesis=VERILOG --output-directory=/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq --family="Agilex 5" --part=A5EB013BB23BE4SCS</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Loading 0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Reading input file</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_0_ddr4comp</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_0_ddr5comp</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_0_ddr5dimm</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_0_lpddr4</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_0_lpddr5</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_1_ddr4comp</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_1_ddr5comp</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_1_ddr5dimm</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_1_lpddr4</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module emif_1_lpddr5</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module refclk_bridge</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing module refclk_gpio</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Building connections</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Parameterizing connections</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Validating</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Done reading input file</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Transforming system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Naming system components in system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Processing generation queue"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_bridge"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_refclk_gpio"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq: Done "emif_io96b_hps_emif_io96b_hps_420_dyxenzq" with 4 modules, 1 files</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Finished: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:23 Info: Generation of /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/emif_io96b_hps_emif_io96b_hps_420_dyxenzq.qsys (emif_io96b_hps_emif_io96b_hps_420_dyxenzq) took 1567 ms</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: </message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Generating on localhost:33515</message>
   <message level="Warning" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Warning: Quartus project not specified. Use --quartus-project and --rev to specify a Quartus project and revision.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Saving generation log to /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_generation.rpt</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Generated by version: 26.1 build 110</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Starting: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: qsys-generate /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.ip --synthesis=VERILOG --output-directory=/tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4 --family="Agilex 5" --part=A5EB013BB23BE4SCS</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.emif_0_lpddr4: Configuring this IP for device A5EB013BB23BE4SCS (Agilex 5). This device has speedgrade 4.</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Transforming system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Naming system components in system: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Processing generation queue"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_lpddr4_420_cy5n3cq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: cal_0: "Generating: cal_0"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_lpddr4_emif_io96b_cal_420_65qugki"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_232_s5h5wki"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: jamb: "Generating: jamb"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_emif_io96b_cal_alt_mem_if_jtag_master_232_ch65psa"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_alt_mem_if_jtag_master_191_2xbfrbi"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: altera_avalon_st_jtag_interface"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_timing_adapter_1950_bbjt6kq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_altera_avalon_sc_fifo_1932_onpcouq"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: altera_avalon_st_bytes_to_packets"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: altera_avalon_st_packets_to_bytes"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: altera_avalon_packets_to_master"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_channel_adapter_1922_rd56ufy"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4_channel_adapter_1922_5vp3d5a"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: "Generating: altera_reset_controller"</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4: Done "emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4" with 15 modules, 165 files</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Finished: Create HDL design files for synthesis</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Generation of /tmp/alt0585_15730755167497342377.dir/0012_packageGeneration/ip/emif_io96b_hps_emif_io96b_hps_420_dyxenzq/emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4.ip (emif_io96b_hps_emif_io96b_hps_420_dyxenzq_emif_0_lpddr4) took 2419 ms</message>
   <message level="Info" culprit="emif_io96b_hps">generate_all_instances: 2026.05.11.21:04:29 Info: Finished: Platform Designer system generation</message>
   <message level="Debug" culprit="emif_io96b_hps">quartus_synth fileset time: 21.93 s</message>
  </messages>
 </entity>
</deploy>
