// peripheral_subsys.v

// Generated using ACDS version 26.1 110

`timescale 1 ps / 1 ps
module peripheral_subsys (
		input  wire [3:0]  button_pio_external_connection_export, // button_pio_external_connection.export
		output wire        button_pio_irq_irq,                    //                 button_pio_irq.irq
		input  wire [3:0]  dipsw_pio_external_connection_export,  //  dipsw_pio_external_connection.export
		output wire        dipsw_pio_irq_irq,                     //                  dipsw_pio_irq.irq
		input  wire [2:0]  led_pio_external_connection_in_port,   //    led_pio_external_connection.in_port
		output wire [2:0]  led_pio_external_connection_out_port,  //                               .out_port
		output wire        pb_cpu_0_s0_waitrequest,               //                    pb_cpu_0_s0.waitrequest
		output wire [31:0] pb_cpu_0_s0_readdata,                  //                               .readdata
		output wire        pb_cpu_0_s0_readdatavalid,             //                               .readdatavalid
		input  wire [0:0]  pb_cpu_0_s0_burstcount,                //                               .burstcount
		input  wire [31:0] pb_cpu_0_s0_writedata,                 //                               .writedata
		input  wire [16:0] pb_cpu_0_s0_address,                   //                               .address
		input  wire        pb_cpu_0_s0_write,                     //                               .write
		input  wire        pb_cpu_0_s0_read,                      //                               .read
		input  wire [3:0]  pb_cpu_0_s0_byteenable,                //                               .byteenable
		input  wire        pb_cpu_0_s0_debugaccess,               //                               .debugaccess
		input  wire        clk_clk,                               //                            clk.clk
		input  wire        reset_reset_n                          //                          reset.reset_n
	);

	wire         periph_clk_out_clk_clk;                         // periph_clk:out_clk -> [button_pio:clk, dipsw_pio:clk, led_pio:clk, mm_interconnect_0:periph_clk_out_clk_clk, pb_cpu_0:clk, rst_controller:clk, rst_controller_001:clk, sysid:clock]
	wire         pb_cpu_0_m0_waitrequest;                        // mm_interconnect_0:pb_cpu_0_m0_waitrequest -> pb_cpu_0:m0_waitrequest
	wire  [31:0] pb_cpu_0_m0_readdata;                           // mm_interconnect_0:pb_cpu_0_m0_readdata -> pb_cpu_0:m0_readdata
	wire         pb_cpu_0_m0_debugaccess;                        // pb_cpu_0:m0_debugaccess -> mm_interconnect_0:pb_cpu_0_m0_debugaccess
	wire  [16:0] pb_cpu_0_m0_address;                            // pb_cpu_0:m0_address -> mm_interconnect_0:pb_cpu_0_m0_address
	wire         pb_cpu_0_m0_read;                               // pb_cpu_0:m0_read -> mm_interconnect_0:pb_cpu_0_m0_read
	wire   [3:0] pb_cpu_0_m0_byteenable;                         // pb_cpu_0:m0_byteenable -> mm_interconnect_0:pb_cpu_0_m0_byteenable
	wire         pb_cpu_0_m0_readdatavalid;                      // mm_interconnect_0:pb_cpu_0_m0_readdatavalid -> pb_cpu_0:m0_readdatavalid
	wire  [31:0] pb_cpu_0_m0_writedata;                          // pb_cpu_0:m0_writedata -> mm_interconnect_0:pb_cpu_0_m0_writedata
	wire         pb_cpu_0_m0_write;                              // pb_cpu_0:m0_write -> mm_interconnect_0:pb_cpu_0_m0_write
	wire   [0:0] pb_cpu_0_m0_burstcount;                         // pb_cpu_0:m0_burstcount -> mm_interconnect_0:pb_cpu_0_m0_burstcount
	wire  [31:0] mm_interconnect_0_sysid_control_slave_readdata; // sysid:readdata -> mm_interconnect_0:sysid_control_slave_readdata
	wire   [0:0] mm_interconnect_0_sysid_control_slave_address;  // mm_interconnect_0:sysid_control_slave_address -> sysid:address
	wire         mm_interconnect_0_led_pio_s1_chipselect;        // mm_interconnect_0:led_pio_s1_chipselect -> led_pio:chipselect
	wire  [31:0] mm_interconnect_0_led_pio_s1_readdata;          // led_pio:readdata -> mm_interconnect_0:led_pio_s1_readdata
	wire   [1:0] mm_interconnect_0_led_pio_s1_address;           // mm_interconnect_0:led_pio_s1_address -> led_pio:address
	wire         mm_interconnect_0_led_pio_s1_write;             // mm_interconnect_0:led_pio_s1_write -> led_pio:write_n
	wire  [31:0] mm_interconnect_0_led_pio_s1_writedata;         // mm_interconnect_0:led_pio_s1_writedata -> led_pio:writedata
	wire         mm_interconnect_0_dipsw_pio_s1_chipselect;      // mm_interconnect_0:dipsw_pio_s1_chipselect -> dipsw_pio:chipselect
	wire  [31:0] mm_interconnect_0_dipsw_pio_s1_readdata;        // dipsw_pio:readdata -> mm_interconnect_0:dipsw_pio_s1_readdata
	wire   [1:0] mm_interconnect_0_dipsw_pio_s1_address;         // mm_interconnect_0:dipsw_pio_s1_address -> dipsw_pio:address
	wire         mm_interconnect_0_dipsw_pio_s1_write;           // mm_interconnect_0:dipsw_pio_s1_write -> dipsw_pio:write_n
	wire  [31:0] mm_interconnect_0_dipsw_pio_s1_writedata;       // mm_interconnect_0:dipsw_pio_s1_writedata -> dipsw_pio:writedata
	wire         mm_interconnect_0_button_pio_s1_chipselect;     // mm_interconnect_0:button_pio_s1_chipselect -> button_pio:chipselect
	wire  [31:0] mm_interconnect_0_button_pio_s1_readdata;       // button_pio:readdata -> mm_interconnect_0:button_pio_s1_readdata
	wire   [1:0] mm_interconnect_0_button_pio_s1_address;        // mm_interconnect_0:button_pio_s1_address -> button_pio:address
	wire         mm_interconnect_0_button_pio_s1_write;          // mm_interconnect_0:button_pio_s1_write -> button_pio:write_n
	wire  [31:0] mm_interconnect_0_button_pio_s1_writedata;      // mm_interconnect_0:button_pio_s1_writedata -> button_pio:writedata
	wire         rst_controller_reset_out_reset;                 // rst_controller:reset_out -> [button_pio:reset_n, dipsw_pio:reset_n, led_pio:reset_n, pb_cpu_0:reset, sysid:reset_n]
	wire         periph_rst_in_out_reset_reset;                  // periph_rst_in:out_reset_n -> [rst_controller:reset_in0, rst_controller_001:reset_in0]
	wire         rst_controller_001_reset_out_reset;             // rst_controller_001:reset_out -> [mm_interconnect_0:pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset, mm_interconnect_0:pb_cpu_0_reset_reset_bridge_in_reset_reset]

	button_pio button_pio (
		.clk        (periph_clk_out_clk_clk),                     //   input,   width = 1,                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),            //   input,   width = 1,               reset.reset_n
		.address    (mm_interconnect_0_button_pio_s1_address),    //   input,   width = 2,                  s1.address
		.write_n    (~mm_interconnect_0_button_pio_s1_write),     //   input,   width = 1,                    .write_n
		.writedata  (mm_interconnect_0_button_pio_s1_writedata),  //   input,  width = 32,                    .writedata
		.chipselect (mm_interconnect_0_button_pio_s1_chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (mm_interconnect_0_button_pio_s1_readdata),   //  output,  width = 32,                    .readdata
		.in_port    (button_pio_external_connection_export),      //   input,   width = 4, external_connection.export
		.irq        (button_pio_irq_irq)                          //  output,   width = 1,                 irq.irq
	);

	dipsw_pio dipsw_pio (
		.clk        (periph_clk_out_clk_clk),                    //   input,   width = 1,                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),           //   input,   width = 1,               reset.reset_n
		.address    (mm_interconnect_0_dipsw_pio_s1_address),    //   input,   width = 2,                  s1.address
		.write_n    (~mm_interconnect_0_dipsw_pio_s1_write),     //   input,   width = 1,                    .write_n
		.writedata  (mm_interconnect_0_dipsw_pio_s1_writedata),  //   input,  width = 32,                    .writedata
		.chipselect (mm_interconnect_0_dipsw_pio_s1_chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (mm_interconnect_0_dipsw_pio_s1_readdata),   //  output,  width = 32,                    .readdata
		.in_port    (dipsw_pio_external_connection_export),      //   input,   width = 4, external_connection.export
		.irq        (dipsw_pio_irq_irq)                          //  output,   width = 1,                 irq.irq
	);

	led_pio led_pio (
		.clk        (periph_clk_out_clk_clk),                  //   input,   width = 1,                 clk.clk
		.reset_n    (~rst_controller_reset_out_reset),         //   input,   width = 1,               reset.reset_n
		.address    (mm_interconnect_0_led_pio_s1_address),    //   input,   width = 2,                  s1.address
		.write_n    (~mm_interconnect_0_led_pio_s1_write),     //   input,   width = 1,                    .write_n
		.writedata  (mm_interconnect_0_led_pio_s1_writedata),  //   input,  width = 32,                    .writedata
		.chipselect (mm_interconnect_0_led_pio_s1_chipselect), //   input,   width = 1,                    .chipselect
		.readdata   (mm_interconnect_0_led_pio_s1_readdata),   //  output,  width = 32,                    .readdata
		.in_port    (led_pio_external_connection_in_port),     //   input,   width = 3, external_connection.in_port
		.out_port   (led_pio_external_connection_out_port)     //  output,   width = 3,                    .out_port
	);

	pb_cpu_0 pb_cpu_0 (
		.clk              (periph_clk_out_clk_clk),         //   input,   width = 1,   clk.clk
		.reset            (rst_controller_reset_out_reset), //   input,   width = 1, reset.reset
		.s0_waitrequest   (pb_cpu_0_s0_waitrequest),        //  output,   width = 1,    s0.waitrequest
		.s0_readdata      (pb_cpu_0_s0_readdata),           //  output,  width = 32,      .readdata
		.s0_readdatavalid (pb_cpu_0_s0_readdatavalid),      //  output,   width = 1,      .readdatavalid
		.s0_burstcount    (pb_cpu_0_s0_burstcount),         //   input,   width = 1,      .burstcount
		.s0_writedata     (pb_cpu_0_s0_writedata),          //   input,  width = 32,      .writedata
		.s0_address       (pb_cpu_0_s0_address),            //   input,  width = 17,      .address
		.s0_write         (pb_cpu_0_s0_write),              //   input,   width = 1,      .write
		.s0_read          (pb_cpu_0_s0_read),               //   input,   width = 1,      .read
		.s0_byteenable    (pb_cpu_0_s0_byteenable),         //   input,   width = 4,      .byteenable
		.s0_debugaccess   (pb_cpu_0_s0_debugaccess),        //   input,   width = 1,      .debugaccess
		.m0_waitrequest   (pb_cpu_0_m0_waitrequest),        //   input,   width = 1,    m0.waitrequest
		.m0_readdata      (pb_cpu_0_m0_readdata),           //   input,  width = 32,      .readdata
		.m0_readdatavalid (pb_cpu_0_m0_readdatavalid),      //   input,   width = 1,      .readdatavalid
		.m0_burstcount    (pb_cpu_0_m0_burstcount),         //  output,   width = 1,      .burstcount
		.m0_writedata     (pb_cpu_0_m0_writedata),          //  output,  width = 32,      .writedata
		.m0_address       (pb_cpu_0_m0_address),            //  output,  width = 17,      .address
		.m0_write         (pb_cpu_0_m0_write),              //  output,   width = 1,      .write
		.m0_read          (pb_cpu_0_m0_read),               //  output,   width = 1,      .read
		.m0_byteenable    (pb_cpu_0_m0_byteenable),         //  output,   width = 4,      .byteenable
		.m0_debugaccess   (pb_cpu_0_m0_debugaccess)         //  output,   width = 1,      .debugaccess
	);

	periph_clk periph_clk (
		.in_clk  (clk_clk),                //   input,  width = 1,  in_clk.clk
		.out_clk (periph_clk_out_clk_clk)  //  output,  width = 1, out_clk.clk
	);

	periph_rst_in periph_rst_in (
		.in_reset_n  (reset_reset_n),                 //   input,  width = 1,  in_reset.reset_n
		.out_reset_n (periph_rst_in_out_reset_reset)  //  output,  width = 1, out_reset.reset_n
	);

	sysid sysid (
		.clock    (periph_clk_out_clk_clk),                         //   input,   width = 1,           clk.clk
		.reset_n  (~rst_controller_reset_out_reset),                //   input,   width = 1,         reset.reset_n
		.readdata (mm_interconnect_0_sysid_control_slave_readdata), //  output,  width = 32, control_slave.readdata
		.address  (mm_interconnect_0_sysid_control_slave_address)   //   input,   width = 1,              .address
	);

	peripheral_subsys_altera_mm_interconnect_1920_553jo7i mm_interconnect_0 (
		.pb_cpu_0_m0_address                                      (pb_cpu_0_m0_address),                            //   input,  width = 17,                                        pb_cpu_0_m0.address
		.pb_cpu_0_m0_waitrequest                                  (pb_cpu_0_m0_waitrequest),                        //  output,   width = 1,                                                   .waitrequest
		.pb_cpu_0_m0_burstcount                                   (pb_cpu_0_m0_burstcount),                         //   input,   width = 1,                                                   .burstcount
		.pb_cpu_0_m0_byteenable                                   (pb_cpu_0_m0_byteenable),                         //   input,   width = 4,                                                   .byteenable
		.pb_cpu_0_m0_read                                         (pb_cpu_0_m0_read),                               //   input,   width = 1,                                                   .read
		.pb_cpu_0_m0_readdata                                     (pb_cpu_0_m0_readdata),                           //  output,  width = 32,                                                   .readdata
		.pb_cpu_0_m0_readdatavalid                                (pb_cpu_0_m0_readdatavalid),                      //  output,   width = 1,                                                   .readdatavalid
		.pb_cpu_0_m0_write                                        (pb_cpu_0_m0_write),                              //   input,   width = 1,                                                   .write
		.pb_cpu_0_m0_writedata                                    (pb_cpu_0_m0_writedata),                          //   input,  width = 32,                                                   .writedata
		.pb_cpu_0_m0_debugaccess                                  (pb_cpu_0_m0_debugaccess),                        //   input,   width = 1,                                                   .debugaccess
		.sysid_control_slave_address                              (mm_interconnect_0_sysid_control_slave_address),  //  output,   width = 1,                                sysid_control_slave.address
		.sysid_control_slave_readdata                             (mm_interconnect_0_sysid_control_slave_readdata), //   input,  width = 32,                                                   .readdata
		.led_pio_s1_address                                       (mm_interconnect_0_led_pio_s1_address),           //  output,   width = 2,                                         led_pio_s1.address
		.led_pio_s1_write                                         (mm_interconnect_0_led_pio_s1_write),             //  output,   width = 1,                                                   .write
		.led_pio_s1_readdata                                      (mm_interconnect_0_led_pio_s1_readdata),          //   input,  width = 32,                                                   .readdata
		.led_pio_s1_writedata                                     (mm_interconnect_0_led_pio_s1_writedata),         //  output,  width = 32,                                                   .writedata
		.led_pio_s1_chipselect                                    (mm_interconnect_0_led_pio_s1_chipselect),        //  output,   width = 1,                                                   .chipselect
		.dipsw_pio_s1_address                                     (mm_interconnect_0_dipsw_pio_s1_address),         //  output,   width = 2,                                       dipsw_pio_s1.address
		.dipsw_pio_s1_write                                       (mm_interconnect_0_dipsw_pio_s1_write),           //  output,   width = 1,                                                   .write
		.dipsw_pio_s1_readdata                                    (mm_interconnect_0_dipsw_pio_s1_readdata),        //   input,  width = 32,                                                   .readdata
		.dipsw_pio_s1_writedata                                   (mm_interconnect_0_dipsw_pio_s1_writedata),       //  output,  width = 32,                                                   .writedata
		.dipsw_pio_s1_chipselect                                  (mm_interconnect_0_dipsw_pio_s1_chipselect),      //  output,   width = 1,                                                   .chipselect
		.button_pio_s1_address                                    (mm_interconnect_0_button_pio_s1_address),        //  output,   width = 2,                                      button_pio_s1.address
		.button_pio_s1_write                                      (mm_interconnect_0_button_pio_s1_write),          //  output,   width = 1,                                                   .write
		.button_pio_s1_readdata                                   (mm_interconnect_0_button_pio_s1_readdata),       //   input,  width = 32,                                                   .readdata
		.button_pio_s1_writedata                                  (mm_interconnect_0_button_pio_s1_writedata),      //  output,  width = 32,                                                   .writedata
		.button_pio_s1_chipselect                                 (mm_interconnect_0_button_pio_s1_chipselect),     //  output,   width = 1,                                                   .chipselect
		.pb_cpu_0_reset_reset_bridge_in_reset_reset               (rst_controller_001_reset_out_reset),             //   input,   width = 1,               pb_cpu_0_reset_reset_bridge_in_reset.reset
		.pb_cpu_0_m0_translator_reset_reset_bridge_in_reset_reset (rst_controller_001_reset_out_reset),             //   input,   width = 1, pb_cpu_0_m0_translator_reset_reset_bridge_in_reset.reset
		.periph_clk_out_clk_clk                                   (periph_clk_out_clk_clk)                          //   input,   width = 1,                                 periph_clk_out_clk.clk
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("deassert"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller (
		.reset_in0      (~periph_rst_in_out_reset_reset), //   input,  width = 1, reset_in0.reset
		.clk            (periph_clk_out_clk_clk),         //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                               // (terminated),                       
		.reset_req_in0  (1'b0),                           // (terminated),                       
		.reset_in1      (1'b0),                           // (terminated),                       
		.reset_req_in1  (1'b0),                           // (terminated),                       
		.reset_in2      (1'b0),                           // (terminated),                       
		.reset_req_in2  (1'b0),                           // (terminated),                       
		.reset_in3      (1'b0),                           // (terminated),                       
		.reset_req_in3  (1'b0),                           // (terminated),                       
		.reset_in4      (1'b0),                           // (terminated),                       
		.reset_req_in4  (1'b0),                           // (terminated),                       
		.reset_in5      (1'b0),                           // (terminated),                       
		.reset_req_in5  (1'b0),                           // (terminated),                       
		.reset_in6      (1'b0),                           // (terminated),                       
		.reset_req_in6  (1'b0),                           // (terminated),                       
		.reset_in7      (1'b0),                           // (terminated),                       
		.reset_req_in7  (1'b0),                           // (terminated),                       
		.reset_in8      (1'b0),                           // (terminated),                       
		.reset_req_in8  (1'b0),                           // (terminated),                       
		.reset_in9      (1'b0),                           // (terminated),                       
		.reset_req_in9  (1'b0),                           // (terminated),                       
		.reset_in10     (1'b0),                           // (terminated),                       
		.reset_req_in10 (1'b0),                           // (terminated),                       
		.reset_in11     (1'b0),                           // (terminated),                       
		.reset_req_in11 (1'b0),                           // (terminated),                       
		.reset_in12     (1'b0),                           // (terminated),                       
		.reset_req_in12 (1'b0),                           // (terminated),                       
		.reset_in13     (1'b0),                           // (terminated),                       
		.reset_req_in13 (1'b0),                           // (terminated),                       
		.reset_in14     (1'b0),                           // (terminated),                       
		.reset_req_in14 (1'b0),                           // (terminated),                       
		.reset_in15     (1'b0),                           // (terminated),                       
		.reset_req_in15 (1'b0)                            // (terminated),                       
	);

	altera_reset_controller #(
		.NUM_RESET_INPUTS          (1),
		.OUTPUT_RESET_SYNC_EDGES   ("both"),
		.SYNC_DEPTH                (2),
		.RESET_REQUEST_PRESENT     (0),
		.RESET_REQ_WAIT_TIME       (1),
		.MIN_RST_ASSERTION_TIME    (3),
		.RESET_REQ_EARLY_DSRT_TIME (1),
		.USE_RESET_REQUEST_IN0     (0),
		.USE_RESET_REQUEST_IN1     (0),
		.USE_RESET_REQUEST_IN2     (0),
		.USE_RESET_REQUEST_IN3     (0),
		.USE_RESET_REQUEST_IN4     (0),
		.USE_RESET_REQUEST_IN5     (0),
		.USE_RESET_REQUEST_IN6     (0),
		.USE_RESET_REQUEST_IN7     (0),
		.USE_RESET_REQUEST_IN8     (0),
		.USE_RESET_REQUEST_IN9     (0),
		.USE_RESET_REQUEST_IN10    (0),
		.USE_RESET_REQUEST_IN11    (0),
		.USE_RESET_REQUEST_IN12    (0),
		.USE_RESET_REQUEST_IN13    (0),
		.USE_RESET_REQUEST_IN14    (0),
		.USE_RESET_REQUEST_IN15    (0),
		.ADAPT_RESET_REQUEST       (0)
	) rst_controller_001 (
		.reset_in0      (~periph_rst_in_out_reset_reset),     //   input,  width = 1, reset_in0.reset
		.clk            (periph_clk_out_clk_clk),             //   input,  width = 1,       clk.clk
		.reset_out      (rst_controller_001_reset_out_reset), //  output,  width = 1, reset_out.reset
		.reset_req      (),                                   // (terminated),                       
		.reset_req_in0  (1'b0),                               // (terminated),                       
		.reset_in1      (1'b0),                               // (terminated),                       
		.reset_req_in1  (1'b0),                               // (terminated),                       
		.reset_in2      (1'b0),                               // (terminated),                       
		.reset_req_in2  (1'b0),                               // (terminated),                       
		.reset_in3      (1'b0),                               // (terminated),                       
		.reset_req_in3  (1'b0),                               // (terminated),                       
		.reset_in4      (1'b0),                               // (terminated),                       
		.reset_req_in4  (1'b0),                               // (terminated),                       
		.reset_in5      (1'b0),                               // (terminated),                       
		.reset_req_in5  (1'b0),                               // (terminated),                       
		.reset_in6      (1'b0),                               // (terminated),                       
		.reset_req_in6  (1'b0),                               // (terminated),                       
		.reset_in7      (1'b0),                               // (terminated),                       
		.reset_req_in7  (1'b0),                               // (terminated),                       
		.reset_in8      (1'b0),                               // (terminated),                       
		.reset_req_in8  (1'b0),                               // (terminated),                       
		.reset_in9      (1'b0),                               // (terminated),                       
		.reset_req_in9  (1'b0),                               // (terminated),                       
		.reset_in10     (1'b0),                               // (terminated),                       
		.reset_req_in10 (1'b0),                               // (terminated),                       
		.reset_in11     (1'b0),                               // (terminated),                       
		.reset_req_in11 (1'b0),                               // (terminated),                       
		.reset_in12     (1'b0),                               // (terminated),                       
		.reset_req_in12 (1'b0),                               // (terminated),                       
		.reset_in13     (1'b0),                               // (terminated),                       
		.reset_req_in13 (1'b0),                               // (terminated),                       
		.reset_in14     (1'b0),                               // (terminated),                       
		.reset_req_in14 (1'b0),                               // (terminated),                       
		.reset_in15     (1'b0),                               // (terminated),                       
		.reset_req_in15 (1'b0)                                // (terminated),                       
	);

endmodule
