module EMIF_Qsys (
		output wire         clock_310m_out_clk_clk,                   //               clock_310m_out_clk.clk
		output wire         emif_lpddr4b_s0_axi4_ctrl_ready_reset_n,  //  emif_lpddr4b_s0_axi4_ctrl_ready.reset_n
		input  wire [29:0]  emif_lpddr4b_s0_axi4_awaddr,              //             emif_lpddr4b_s0_axi4.awaddr
		input  wire [1:0]   emif_lpddr4b_s0_axi4_awburst,             //                                 .awburst
		input  wire [6:0]   emif_lpddr4b_s0_axi4_awid,                //                                 .awid
		input  wire [7:0]   emif_lpddr4b_s0_axi4_awlen,               //                                 .awlen
		input  wire         emif_lpddr4b_s0_axi4_awlock,              //                                 .awlock
		input  wire [3:0]   emif_lpddr4b_s0_axi4_awqos,               //                                 .awqos
		input  wire [2:0]   emif_lpddr4b_s0_axi4_awsize,              //                                 .awsize
		input  wire         emif_lpddr4b_s0_axi4_awvalid,             //                                 .awvalid
		input  wire [13:0]  emif_lpddr4b_s0_axi4_awuser,              //                                 .awuser
		input  wire [2:0]   emif_lpddr4b_s0_axi4_awprot,              //                                 .awprot
		output wire         emif_lpddr4b_s0_axi4_awready,             //                                 .awready
		input  wire [29:0]  emif_lpddr4b_s0_axi4_araddr,              //                                 .araddr
		input  wire [1:0]   emif_lpddr4b_s0_axi4_arburst,             //                                 .arburst
		input  wire [6:0]   emif_lpddr4b_s0_axi4_arid,                //                                 .arid
		input  wire [7:0]   emif_lpddr4b_s0_axi4_arlen,               //                                 .arlen
		input  wire         emif_lpddr4b_s0_axi4_arlock,              //                                 .arlock
		input  wire [3:0]   emif_lpddr4b_s0_axi4_arqos,               //                                 .arqos
		input  wire [2:0]   emif_lpddr4b_s0_axi4_arsize,              //                                 .arsize
		input  wire         emif_lpddr4b_s0_axi4_arvalid,             //                                 .arvalid
		input  wire [13:0]  emif_lpddr4b_s0_axi4_aruser,              //                                 .aruser
		input  wire [2:0]   emif_lpddr4b_s0_axi4_arprot,              //                                 .arprot
		output wire         emif_lpddr4b_s0_axi4_arready,             //                                 .arready
		input  wire [255:0] emif_lpddr4b_s0_axi4_wdata,               //                                 .wdata
		input  wire [31:0]  emif_lpddr4b_s0_axi4_wstrb,               //                                 .wstrb
		input  wire         emif_lpddr4b_s0_axi4_wlast,               //                                 .wlast
		input  wire         emif_lpddr4b_s0_axi4_wvalid,              //                                 .wvalid
		output wire         emif_lpddr4b_s0_axi4_wready,              //                                 .wready
		input  wire         emif_lpddr4b_s0_axi4_bready,              //                                 .bready
		output wire [6:0]   emif_lpddr4b_s0_axi4_bid,                 //                                 .bid
		output wire [1:0]   emif_lpddr4b_s0_axi4_bresp,               //                                 .bresp
		output wire         emif_lpddr4b_s0_axi4_bvalid,              //                                 .bvalid
		input  wire         emif_lpddr4b_s0_axi4_rready,              //                                 .rready
		output wire [255:0] emif_lpddr4b_s0_axi4_rdata,               //                                 .rdata
		output wire [6:0]   emif_lpddr4b_s0_axi4_rid,                 //                                 .rid
		output wire         emif_lpddr4b_s0_axi4_rlast,               //                                 .rlast
		output wire [1:0]   emif_lpddr4b_s0_axi4_rresp,               //                                 .rresp
		output wire         emif_lpddr4b_s0_axi4_rvalid,              //                                 .rvalid
		input  wire         emif_lpddr4b_s0_axi4lite_clock_clk,       //   emif_lpddr4b_s0_axi4lite_clock.clk
		input  wire         emif_lpddr4b_s0_axi4lite_reset_n_reset_n, // emif_lpddr4b_s0_axi4lite_reset_n.reset_n
		input  wire [26:0]  emif_lpddr4b_s0_axi4lite_awaddr,          //         emif_lpddr4b_s0_axi4lite.awaddr
		input  wire [2:0]   emif_lpddr4b_s0_axi4lite_awprot,          //                                 .awprot
		input  wire         emif_lpddr4b_s0_axi4lite_awvalid,         //                                 .awvalid
		output wire         emif_lpddr4b_s0_axi4lite_awready,         //                                 .awready
		input  wire [26:0]  emif_lpddr4b_s0_axi4lite_araddr,          //                                 .araddr
		input  wire [2:0]   emif_lpddr4b_s0_axi4lite_arprot,          //                                 .arprot
		input  wire         emif_lpddr4b_s0_axi4lite_arvalid,         //                                 .arvalid
		output wire         emif_lpddr4b_s0_axi4lite_arready,         //                                 .arready
		input  wire [31:0]  emif_lpddr4b_s0_axi4lite_wdata,           //                                 .wdata
		input  wire [3:0]   emif_lpddr4b_s0_axi4lite_wstrb,           //                                 .wstrb
		input  wire         emif_lpddr4b_s0_axi4lite_wvalid,          //                                 .wvalid
		output wire         emif_lpddr4b_s0_axi4lite_wready,          //                                 .wready
		input  wire         emif_lpddr4b_s0_axi4lite_bready,          //                                 .bready
		output wire [1:0]   emif_lpddr4b_s0_axi4lite_bresp,           //                                 .bresp
		output wire         emif_lpddr4b_s0_axi4lite_bvalid,          //                                 .bvalid
		input  wire         emif_lpddr4b_s0_axi4lite_rready,          //                                 .rready
		output wire [31:0]  emif_lpddr4b_s0_axi4lite_rdata,           //                                 .rdata
		output wire [1:0]   emif_lpddr4b_s0_axi4lite_rresp,           //                                 .rresp
		output wire         emif_lpddr4b_s0_axi4lite_rvalid,          //                                 .rvalid
		output wire [0:0]   emif_lpddr4b_mem_mem_cs,                  //                 emif_lpddr4b_mem.mem_cs
		output wire [5:0]   emif_lpddr4b_mem_mem_ca,                  //                                 .mem_ca
		output wire [0:0]   emif_lpddr4b_mem_mem_cke,                 //                                 .mem_cke
		inout  wire [31:0]  emif_lpddr4b_mem_mem_dq,                  //                                 .mem_dq
		inout  wire [3:0]   emif_lpddr4b_mem_mem_dqs_t,               //                                 .mem_dqs_t
		inout  wire [3:0]   emif_lpddr4b_mem_mem_dqs_c,               //                                 .mem_dqs_c
		inout  wire [3:0]   emif_lpddr4b_mem_mem_dmi,                 //                                 .mem_dmi
		output wire [0:0]   emif_lpddr4b_mem_ck_mem_ck_t,             //              emif_lpddr4b_mem_ck.mem_ck_t
		output wire [0:0]   emif_lpddr4b_mem_ck_mem_ck_c,             //                                 .mem_ck_c
		output wire         emif_lpddr4b_mem_reset_n_mem_reset_n,     //         emif_lpddr4b_mem_reset_n.mem_reset_n
		input  wire         emif_lpddr4b_oct_oct_rzqin,               //                 emif_lpddr4b_oct.oct_rzqin
		input  wire         emif_lpddr4b_ref_clk_clk,                 //             emif_lpddr4b_ref_clk.clk
		input  wire         iopll_refclk_clk,                         //                     iopll_refclk.clk
		output wire         iopll_locked_export,                      //                     iopll_locked.export
		input  wire         iopll_reset_reset,                        //                      iopll_reset.reset
		output wire         iopll_outclk_axi4_lite_clk,               //           iopll_outclk_axi4_lite.clk
		input  wire         reset_reset_n                             //                            reset.reset_n
	);
endmodule

