// retroDE_ps2 — tb_top_psmct32_tile_scissor_demo (Ch306)
//
// GS SCISSOR clipping in the tiled renderer. The Ch305 3-primitive scene
// (opaque blue bg / opaque red / translucent white, over a 2x2 grid of 16x16
// tiles) PLUS a SCISSOR_1 rectangle [6..25]x[4..20] (inclusive) that crosses
// BOTH tile seams (x=16, y=16). Effective raster bounds = primitive bbox ∩ tile
// bbox ∩ scissor rect, baked into the walker (no per-pixel test). Pixels outside
// the scissor must stay the CLEAR color (no color/Z write).
//
// PROOFS:
//   CLIP      : pixels that would be inside a primitive but are OUTSIDE the
//               scissor are GREEN (clear) — the scene is clipped, not drawn.
//   INSIDE    : pixels inside the scissor match the UNCLIPPED 3-prim reference
//               (blue / red / light-blue / occlusion regions all present).
//   EDGE      : the scissor boundary is exact (integer rect; pixels at x=SX0/SX1
//               and y=SY0/SY1 correct, and the pixel one step outside is green).
//   SEAMS     : the clip is correct across x=15|16 and y=15|16.
//   GRID      : 4 tiles cleared (256 each) + 1024 flush emits; prim list = 3.

`timescale 1ns/1ps

module tb_top_psmct32_tile_scissor_demo;

    localparam int H_ACTIVE = 32, V_ACTIVE = 32;
    localparam int TP_CLEAR = 1;
    localparam real MARG = 0.08;
    localparam int Z0 = 'h5000, Z1 = 'h6000, Z2 = 'h5800, ZCLR = 'h4000;
    // SCISSOR_1 rect (inclusive) — MUST match bake.py Ch306 (TSC_S*).
    localparam int SX0 = 9, SX1 = 22, SY0 = 6, SY1 = 20;

    logic clk, rst_n;
    initial clk = 1'b0;
    always #5 clk = ~clk;

    logic        core_go;
    logic [7:0]  r, g, b;
    logic        hsync, vsync, de;
    logic        core_halt, dma_done_seen, frame_seen, raster_overflow;
    logic        frame_toggle, dma_done_toggle;

    top_psmct32_raster_demo_bram #(
        .H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
        .VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
        .COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(2), .TILE_ROWS(2),
        .TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3), .SCISSOR_ENABLE(1'b1)
    ) dut (
        .clk(clk), .rst_n(rst_n), .core_go(core_go),
        .r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
        .core_halt(core_halt), .dma_done_seen(dma_done_seen),
        .frame_seen(frame_seen), .raster_overflow(raster_overflow),
        .frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
        .joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
    );

    function automatic int tri_cls(input real px, input real py,
                                   input real ax, input real ay,
                                   input real bx, input real by,
                                   input real cx, input real cy);
        real d, wa, wb, wc;
        begin
            d  = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
            wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
            wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
            wc = 1.0 - wa - wb;
            if (wa>MARG && wb>MARG && wc>MARG)            tri_cls = 1;
            else if (wa<-MARG || wb<-MARG || wc<-MARG)    tri_cls = 0;
            else                                          tri_cls = 2;
        end
    endfunction

    function automatic logic [7:0] blendch(input int cs, input int cd, input int aa);
        int t;
        begin
            t = ((cs - cd) * aa) >>> 7;
            t = t + cd;
            if (t < 0)   t = 0;
            if (t > 255) t = 255;
            blendch = t[7:0];
        end
    endfunction

    // ---- grid tracers ----
    int  clear_cw_tile [0:1][0:1];
    int  flush_emits;
    bit  saw_prim_count_3;
    initial begin
        for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++) clear_cw_tile[rr][cc]=0;
        flush_emits=0; saw_prim_count_3=1'b0;
    end
    always_ff @(posedge clk) if (rst_n) begin
        if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
            int cc, rr; cc=int'(dut.u_gs.tile_col_r); rr=int'(dut.u_gs.tile_row_r);
            if (cc<2 && rr<2) clear_cw_tile[rr][cc] <= clear_cw_tile[rr][cc] + 1;
        end
        if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
        if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==3)) saw_prim_count_3 <= 1'b1;
    end

    // ---- scanout capture (32x32) ----
    logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
    logic       cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
    bit capture_armed;
    initial begin
        for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
        capture_armed=1'b0;
    end
    logic [31:0] hcnt_d, vcnt_d;
    always_ff @(posedge clk) begin
        if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
        else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
    end
    always_ff @(posedge clk) begin
        if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
            cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
        end
    end

    int errors, n_match, n_check, n_seam;
    int n_clipped, n_inside_scene, n_edge_pairs;

    initial begin
        errors=0; n_match=0; n_check=0; n_seam=0;
        n_clipped=0; n_inside_scene=0; n_edge_pairs=0;
        rst_n=1'b0; core_go=1'b0;
        repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
        @(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
        wait (core_halt==1'b1); repeat(4) @(posedge clk);
        wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
        if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
        @(posedge dut.u_gs.raster_active);
        @(negedge dut.u_gs.raster_active);
        repeat(10) @(posedge clk);
        @(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
        @(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;

        // PROOF GRID
        for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++)
            if (clear_cw_tile[rr][cc] != 256) begin
                $error("[tsc] tile(col=%0d,row=%0d) cleared %0d (want 256)", cc, rr, clear_cw_tile[rr][cc]); errors++;
            end
        if (flush_emits != 4*256) begin $error("[tsc] flush emitted %0d (want %0d)", flush_emits, 4*256); errors++; end
        if (!saw_prim_count_3)     begin $error("[tsc] prim_count_r never == 3"); errors++; end

        // PROOF CLIP + INSIDE + EDGE + SEAMS — whole 32x32 vs the SCISSORED reference.
        for (int py=0; py<V_ACTIVE; py++) begin
            for (int px=0; px<H_ACTIVE; px++) begin
                int c0, c1, c2, cr, cg, cb, zz;
                bit insc, scene_here;
                logic [7:0] er, eg, eb;
                real fpx, fpy;
                fpx = real'(px); fpy = real'(py);
                c0 = tri_cls(fpx,fpy,  1, 1, 30, 1, 15,30);  // P0 blue
                c1 = tri_cls(fpx,fpy,  8, 3, 22, 3, 15,20);  // P1 red
                c2 = tri_cls(fpx,fpy,  7, 9, 23, 9, 15,28);  // P2 white
                insc = (px>=SX0)&&(px<=SX1)&&(py>=SY0)&&(py<=SY1);   // scissor is EXACT (integer)
                if (c0==2 || c1==2 || c2==2) begin er=8'hxx; eg=8'hxx; eb=8'hxx; end
                else begin
                    scene_here = (c0==1) || (c1==1) || (c2==1);
                    cr=0; cg=128; cb=0; zz=ZCLR;                          // clear green
                    if (insc) begin                                       // ONLY composite inside scissor
                        if (c0==1 && Z0>=zz) begin cr=blendch(0,cr,'h80);   cg=blendch(0,cg,'h80);   cb=blendch(255,cb,'h80); zz=Z0; end
                        if (c1==1 && Z1>=zz) begin cr=blendch(255,cr,'h80); cg=blendch(0,cg,'h80);   cb=blendch(0,cb,'h80);   zz=Z1; end
                        if (c2==1 && Z2>=zz) begin cr=blendch(255,cr,'h40); cg=blendch(255,cg,'h40); cb=blendch(255,cb,'h40); zz=Z2; end
                    end
                    er=cr[7:0]; eg=cg[7:0]; eb=cb[7:0];
                end

                if (er!==8'hxx && cap_de[py][px]) begin
                    n_check++;
                    if (!insc && scene_here) n_clipped++;       // would-be-scene pixel, clipped -> green
                    if (insc && scene_here)  n_inside_scene++;  // scene pixel kept
                    if (cap_r[py][px]===er && cap_g[py][px]===eg && cap_b[py][px]===eb) begin
                        n_match++;
                        if (px==15||px==16||py==15||py==16) n_seam++;
                    end else begin
                        if (errors<14) $error("[tsc] (%0d,%0d) insc=%0b got(%02x,%02x,%02x) exp(%02x,%02x,%02x) [c0%0d c1%0d c2%0d]",
                                              px,py,insc,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb,c0,c1,c2);
                        errors++;
                    end
                end
            end
        end

        // PROOF EDGE — explicit: just-inside vs just-outside each scissor border,
        // at a row/col through the scene, must differ correctly (drawn vs green).
        // (Sampled where the scene is clearly present so the transition is visible.)
        for (int py=SY0+1; py<=SY1-1; py++) begin
            // left border: x=SX0-1 outside (green), x=SX0 inside
            if (cap_de[py][SX0-1] && cap_de[py][SX0]) begin
                bit out_green, scn;
                scn = (tri_cls(real'(SX0),real'(py), 1,1,30,1,15,30)==1) ||
                      (tri_cls(real'(SX0),real'(py), 8,3,22,3,15,20)==1) ||
                      (tri_cls(real'(SX0),real'(py), 7,9,23,9,15,28)==1);
                out_green = (cap_r[py][SX0-1]===8'h00 && cap_g[py][SX0-1]===8'h80 && cap_b[py][SX0-1]===8'h00);
                if (scn) begin
                    n_edge_pairs++;
                    if (!out_green) begin $error("[tsc] left scissor edge: (%0d,%0d) outside not green", SX0-1, py); errors++; end
                end
            end
        end

        if (n_check < 200)        begin $error("[tsc] too few checkable pixels (%0d)", n_check); errors++; end
        if (n_match != n_check)   begin $error("[tsc] image match %0d/%0d (scissor/clip error)", n_match, n_check); errors++; end
        if (n_clipped < 20)       begin $error("[tsc] too few CLIPPED pixels (%0d) — scissor not exercised", n_clipped); errors++; end
        if (n_inside_scene < 20)  begin $error("[tsc] too few INSIDE-scene pixels (%0d)", n_inside_scene); errors++; end
        if (n_edge_pairs < 5)     begin $error("[tsc] too few scissor-edge samples (%0d)", n_edge_pairs); errors++; end
        if (n_seam < 15)          begin $error("[tsc] too few SEAM matches (%0d)", n_seam); errors++; end
        if (!core_halt)           begin $error("core_halt low"); errors++; end
        if (raster_overflow)      begin $error("raster_overflow"); errors++; end

        $display("[tb_top_psmct32_tile_scissor_demo] clears=[%0d %0d %0d %0d] flush=%0d prim3=%0b match=%0d/%0d seam=%0d | clipped=%0d inside=%0d edgePairs=%0d errors=%0d",
                 clear_cw_tile[0][0],clear_cw_tile[0][1],clear_cw_tile[1][0],clear_cw_tile[1][1],
                 flush_emits, saw_prim_count_3, n_match, n_check, n_seam,
                 n_clipped, n_inside_scene, n_edge_pairs, errors);
        if (errors==0) $display("[tb_top_psmct32_tile_scissor_demo] PASS");
        else           $display("[tb_top_psmct32_tile_scissor_demo] FAIL");
        $finish;
    end

    initial begin #300000000; $error("[tb_top_psmct32_tile_scissor_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_scissor_demo
