<?xml version="1.0" encoding="UTF-8"?>
<deploy
 date="2026.05.11.21:03:55"
 outputDirectory="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/">
 <perimeter>
  <parameter
     name="AUTO_GENERATION_ID"
     type="Integer"
     defaultValue="0"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_UNIQUE_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_FAMILY"
     type="String"
     defaultValue="Agilex 5"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE"
     type="String"
     defaultValue="A5EB013BB23BE4SCS"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_DEVICE_SPEEDGRADE"
     type="String"
     defaultValue="4"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_BOARD"
     type="String"
     defaultValue="default"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_100_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_100_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_CLK_100_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_SUBSYS_HPS_HPS2FPGA_ADDRESS_MAP"
     type="AddressMap"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_SUBSYS_HPS_HPS2FPGA_ADDRESS_WIDTH"
     type="AddressWidthType"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_F2H_IRQ1_IN_INTERRUPTS_USED"
     type="BigInteger"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_F2SDRAM_CPU_INFO_ID"
     type="String"
     defaultValue=""
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_EMIF_HPS_EMIF_REF_CLK_0_CLOCK_RATE"
     type="Long"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_EMIF_HPS_EMIF_REF_CLK_0_CLOCK_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <parameter
     name="AUTO_EMIF_HPS_EMIF_REF_CLK_0_RESET_DOMAIN"
     type="Integer"
     defaultValue="-1"
     onHdl="0"
     affectsHdl="1" />
  <interface name="clk_100" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port name="clk_100_clk" direction="input" role="clk" width="1" />
  </interface>
  <interface name="reset" kind="reset" start="0">
   <property name="associatedClock" value="" />
   <property name="synchronousEdges" value="NONE" />
   <port name="reset_reset_n" direction="input" role="reset_n" width="1" />
  </interface>
  <interface name="ninit_done" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="ninit_done_ninit_done"
       direction="output"
       role="ninit_done"
       width="1" />
  </interface>
  <interface name="h2f_reset" kind="reset" start="1">
   <property name="associatedClock" value="" />
   <property name="associatedDirectReset" value="" />
   <property name="associatedResetSinks" value="none" />
   <property name="synchronousEdges" value="NONE" />
   <port name="h2f_reset_reset" direction="output" role="reset" width="1" />
  </interface>
  <interface name="subsys_hps_hps2fpga" kind="axi4" start="1">
   <property name="associatedClock" value="clk_100" />
   <property name="associatedReset" value="reset" />
   <property name="optionalAssociatedReset" value="false" />
   <property name="trustzoneAware" value="true" />
   <property name="wakeupSignals" value="false" />
   <property name="uniqueIdSupport" value="false" />
   <property name="poison" value="false" />
   <property name="traceSignals" value="false" />
   <property name="isTranslator" value="false" />
   <property name="maximumOutstandingReads" value="1" />
   <property name="maximumOutstandingWrites" value="1" />
   <property name="maximumOutstandingTransactions" value="1" />
   <property name="dataCheck" value="false" />
   <property name="addressCheck" value="false" />
   <property name="securityAttribute" value="false" />
   <property name="userData" value="false" />
   <property name="readIssuingCapability" value="16" />
   <property name="writeIssuingCapability" value="16" />
   <property name="combinedIssuingCapability" value="16" />
   <property name="enableConcurrentSubordinateAccess" value="0" />
   <property name="noRepeatedIdsBetweenSubordinates" value="0" />
   <property name="issuesINCRBursts" value="true" />
   <property name="issuesWRAPBursts" value="true" />
   <property name="issuesFIXEDBursts" value="true" />
   <port
       name="subsys_hps_hps2fpga_awid"
       direction="output"
       role="awid"
       width="4" />
   <port
       name="subsys_hps_hps2fpga_awaddr"
       direction="output"
       role="awaddr"
       width="38" />
   <port
       name="subsys_hps_hps2fpga_awlen"
       direction="output"
       role="awlen"
       width="8" />
   <port
       name="subsys_hps_hps2fpga_awsize"
       direction="output"
       role="awsize"
       width="3" />
   <port
       name="subsys_hps_hps2fpga_awburst"
       direction="output"
       role="awburst"
       width="2" />
   <port
       name="subsys_hps_hps2fpga_awlock"
       direction="output"
       role="awlock"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_awcache"
       direction="output"
       role="awcache"
       width="4" />
   <port
       name="subsys_hps_hps2fpga_awprot"
       direction="output"
       role="awprot"
       width="3" />
   <port
       name="subsys_hps_hps2fpga_awvalid"
       direction="output"
       role="awvalid"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_awready"
       direction="input"
       role="awready"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_wdata"
       direction="output"
       role="wdata"
       width="128" />
   <port
       name="subsys_hps_hps2fpga_wstrb"
       direction="output"
       role="wstrb"
       width="16" />
   <port
       name="subsys_hps_hps2fpga_wlast"
       direction="output"
       role="wlast"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_wvalid"
       direction="output"
       role="wvalid"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_wready"
       direction="input"
       role="wready"
       width="1" />
   <port name="subsys_hps_hps2fpga_bid" direction="input" role="bid" width="4" />
   <port
       name="subsys_hps_hps2fpga_bresp"
       direction="input"
       role="bresp"
       width="2" />
   <port
       name="subsys_hps_hps2fpga_bvalid"
       direction="input"
       role="bvalid"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_bready"
       direction="output"
       role="bready"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_arid"
       direction="output"
       role="arid"
       width="4" />
   <port
       name="subsys_hps_hps2fpga_araddr"
       direction="output"
       role="araddr"
       width="38" />
   <port
       name="subsys_hps_hps2fpga_arlen"
       direction="output"
       role="arlen"
       width="8" />
   <port
       name="subsys_hps_hps2fpga_arsize"
       direction="output"
       role="arsize"
       width="3" />
   <port
       name="subsys_hps_hps2fpga_arburst"
       direction="output"
       role="arburst"
       width="2" />
   <port
       name="subsys_hps_hps2fpga_arlock"
       direction="output"
       role="arlock"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_arcache"
       direction="output"
       role="arcache"
       width="4" />
   <port
       name="subsys_hps_hps2fpga_arprot"
       direction="output"
       role="arprot"
       width="3" />
   <port
       name="subsys_hps_hps2fpga_arvalid"
       direction="output"
       role="arvalid"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_arready"
       direction="input"
       role="arready"
       width="1" />
   <port name="subsys_hps_hps2fpga_rid" direction="input" role="rid" width="4" />
   <port
       name="subsys_hps_hps2fpga_rdata"
       direction="input"
       role="rdata"
       width="128" />
   <port
       name="subsys_hps_hps2fpga_rresp"
       direction="input"
       role="rresp"
       width="2" />
   <port
       name="subsys_hps_hps2fpga_rlast"
       direction="input"
       role="rlast"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_rvalid"
       direction="input"
       role="rvalid"
       width="1" />
   <port
       name="subsys_hps_hps2fpga_rready"
       direction="output"
       role="rready"
       width="1" />
  </interface>
  <interface name="subsys_hps_h2f_warm_reset_handshake" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="subsys_hps_h2f_warm_reset_handshake_reset_req"
       direction="output"
       role="reset_req"
       width="1" />
   <port
       name="subsys_hps_h2f_warm_reset_handshake_reset_ack"
       direction="input"
       role="reset_ack"
       width="1" />
  </interface>
  <interface name="hps_io" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="hps_io_hps_osc_clk"
       direction="input"
       role="hps_osc_clk"
       width="1" />
   <port
       name="hps_io_sdmmc_data0"
       direction="bidir"
       role="sdmmc_data0"
       width="1" />
   <port
       name="hps_io_sdmmc_data1"
       direction="bidir"
       role="sdmmc_data1"
       width="1" />
   <port
       name="hps_io_sdmmc_cclk"
       direction="output"
       role="sdmmc_cclk"
       width="1" />
   <port
       name="hps_io_sdmmc_data2"
       direction="bidir"
       role="sdmmc_data2"
       width="1" />
   <port
       name="hps_io_sdmmc_data3"
       direction="bidir"
       role="sdmmc_data3"
       width="1" />
   <port name="hps_io_sdmmc_cmd" direction="bidir" role="sdmmc_cmd" width="1" />
   <port name="hps_io_usb0_clk" direction="input" role="usb0_clk" width="1" />
   <port name="hps_io_usb0_stp" direction="output" role="usb0_stp" width="1" />
   <port name="hps_io_usb0_dir" direction="input" role="usb0_dir" width="1" />
   <port
       name="hps_io_usb0_data0"
       direction="bidir"
       role="usb0_data0"
       width="1" />
   <port
       name="hps_io_usb0_data1"
       direction="bidir"
       role="usb0_data1"
       width="1" />
   <port name="hps_io_usb0_nxt" direction="input" role="usb0_nxt" width="1" />
   <port
       name="hps_io_usb0_data2"
       direction="bidir"
       role="usb0_data2"
       width="1" />
   <port
       name="hps_io_usb0_data3"
       direction="bidir"
       role="usb0_data3"
       width="1" />
   <port
       name="hps_io_usb0_data4"
       direction="bidir"
       role="usb0_data4"
       width="1" />
   <port
       name="hps_io_usb0_data5"
       direction="bidir"
       role="usb0_data5"
       width="1" />
   <port
       name="hps_io_usb0_data6"
       direction="bidir"
       role="usb0_data6"
       width="1" />
   <port
       name="hps_io_usb0_data7"
       direction="bidir"
       role="usb0_data7"
       width="1" />
   <port
       name="hps_io_emac0_tx_clk"
       direction="output"
       role="emac0_tx_clk"
       width="1" />
   <port
       name="hps_io_emac0_tx_ctl"
       direction="output"
       role="emac0_tx_ctl"
       width="1" />
   <port
       name="hps_io_emac0_rx_clk"
       direction="input"
       role="emac0_rx_clk"
       width="1" />
   <port
       name="hps_io_emac0_rx_ctl"
       direction="input"
       role="emac0_rx_ctl"
       width="1" />
   <port
       name="hps_io_emac0_txd0"
       direction="output"
       role="emac0_txd0"
       width="1" />
   <port
       name="hps_io_emac0_txd1"
       direction="output"
       role="emac0_txd1"
       width="1" />
   <port
       name="hps_io_emac0_rxd0"
       direction="input"
       role="emac0_rxd0"
       width="1" />
   <port
       name="hps_io_emac0_rxd1"
       direction="input"
       role="emac0_rxd1"
       width="1" />
   <port
       name="hps_io_emac0_txd2"
       direction="output"
       role="emac0_txd2"
       width="1" />
   <port
       name="hps_io_emac0_txd3"
       direction="output"
       role="emac0_txd3"
       width="1" />
   <port
       name="hps_io_emac0_rxd2"
       direction="input"
       role="emac0_rxd2"
       width="1" />
   <port
       name="hps_io_emac0_rxd3"
       direction="input"
       role="emac0_rxd3"
       width="1" />
   <port
       name="hps_io_mdio0_mdio"
       direction="bidir"
       role="mdio0_mdio"
       width="1" />
   <port name="hps_io_mdio0_mdc" direction="output" role="mdio0_mdc" width="1" />
   <port name="hps_io_uart1_tx" direction="output" role="uart1_tx" width="1" />
   <port name="hps_io_uart1_rx" direction="input" role="uart1_rx" width="1" />
   <port name="hps_io_i2c1_sda" direction="bidir" role="i2c1_sda" width="1" />
   <port name="hps_io_i2c1_scl" direction="bidir" role="i2c1_scl" width="1" />
   <port name="hps_io_gpio28" direction="bidir" role="gpio28" width="1" />
   <port name="hps_io_gpio34" direction="bidir" role="gpio34" width="1" />
   <port name="hps_io_gpio40" direction="bidir" role="gpio40" width="1" />
   <port name="hps_io_gpio41" direction="bidir" role="gpio41" width="1" />
  </interface>
  <interface name="f2h_irq1_in" kind="interrupt" start="1">
   <property name="associatedAddressablePoint" value="" />
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="irqMap" value="" />
   <property name="irqScheme" value="INDIVIDUAL_REQUESTS" />
   <port name="f2h_irq1_in_irq" direction="input" role="irq" width="32" />
  </interface>
  <interface name="f2sdram" kind="axi4" start="0">
   <property name="associatedClock" value="clk_100" />
   <property name="associatedReset" value="reset" />
   <property name="optionalAssociatedReset" value="false" />
   <property name="trustzoneAware" value="true" />
   <property name="wakeupSignals" value="false" />
   <property name="uniqueIdSupport" value="false" />
   <property name="poison" value="false" />
   <property name="traceSignals" value="false" />
   <property name="isTranslator" value="false" />
   <property name="maximumOutstandingReads" value="1" />
   <property name="maximumOutstandingWrites" value="1" />
   <property name="maximumOutstandingTransactions" value="1" />
   <property name="dataCheck" value="false" />
   <property name="addressCheck" value="false" />
   <property name="securityAttribute" value="false" />
   <property name="userData" value="false" />
   <property name="readAcceptanceCapability" value="16" />
   <property name="writeAcceptanceCapability" value="16" />
   <property name="combinedAcceptanceCapability" value="16" />
   <property name="readDataReorderingDepth" value="1" />
   <property name="bridgesToMaster" value="" />
   <property name="dfhFeatureGuid" value="0" />
   <property name="dfhGroupId" value="0" />
   <property name="dfhParameterId" value="" />
   <property name="dfhParameterName" value="" />
   <property name="dfhParameterVersion" value="" />
   <property name="dfhParameterData" value="" />
   <property name="dfhParameterDataLength" value="" />
   <property name="dfhFeatureMajorVersion" value="0" />
   <property name="dfhFeatureMinorVersion" value="0" />
   <property name="dfhFeatureId" value="35" />
   <property name="dfhFeatureType" value="3" />
   <property name="noNarrowTransfer" value="false" />
   <port name="f2sdram_araddr" direction="input" role="araddr" width="32" />
   <port name="f2sdram_arburst" direction="input" role="arburst" width="2" />
   <port name="f2sdram_arcache" direction="input" role="arcache" width="4" />
   <port name="f2sdram_arid" direction="input" role="arid" width="5" />
   <port name="f2sdram_arlen" direction="input" role="arlen" width="8" />
   <port name="f2sdram_arlock" direction="input" role="arlock" width="1" />
   <port name="f2sdram_arprot" direction="input" role="arprot" width="3" />
   <port name="f2sdram_arqos" direction="input" role="arqos" width="4" />
   <port name="f2sdram_arready" direction="output" role="arready" width="1" />
   <port name="f2sdram_arsize" direction="input" role="arsize" width="3" />
   <port name="f2sdram_arvalid" direction="input" role="arvalid" width="1" />
   <port name="f2sdram_awaddr" direction="input" role="awaddr" width="32" />
   <port name="f2sdram_awburst" direction="input" role="awburst" width="2" />
   <port name="f2sdram_awcache" direction="input" role="awcache" width="4" />
   <port name="f2sdram_awid" direction="input" role="awid" width="5" />
   <port name="f2sdram_awlen" direction="input" role="awlen" width="8" />
   <port name="f2sdram_awlock" direction="input" role="awlock" width="1" />
   <port name="f2sdram_awprot" direction="input" role="awprot" width="3" />
   <port name="f2sdram_awqos" direction="input" role="awqos" width="4" />
   <port name="f2sdram_awready" direction="output" role="awready" width="1" />
   <port name="f2sdram_awsize" direction="input" role="awsize" width="3" />
   <port name="f2sdram_awvalid" direction="input" role="awvalid" width="1" />
   <port name="f2sdram_bid" direction="output" role="bid" width="5" />
   <port name="f2sdram_bready" direction="input" role="bready" width="1" />
   <port name="f2sdram_bresp" direction="output" role="bresp" width="2" />
   <port name="f2sdram_bvalid" direction="output" role="bvalid" width="1" />
   <port name="f2sdram_rdata" direction="output" role="rdata" width="256" />
   <port name="f2sdram_rid" direction="output" role="rid" width="5" />
   <port name="f2sdram_rlast" direction="output" role="rlast" width="1" />
   <port name="f2sdram_rready" direction="input" role="rready" width="1" />
   <port name="f2sdram_rresp" direction="output" role="rresp" width="2" />
   <port name="f2sdram_rvalid" direction="output" role="rvalid" width="1" />
   <port name="f2sdram_wdata" direction="input" role="wdata" width="256" />
   <port name="f2sdram_wlast" direction="input" role="wlast" width="1" />
   <port name="f2sdram_wready" direction="output" role="wready" width="1" />
   <port name="f2sdram_wstrb" direction="input" role="wstrb" width="32" />
   <port name="f2sdram_wvalid" direction="input" role="wvalid" width="1" />
   <port name="f2sdram_aruser" direction="input" role="aruser" width="8" />
   <port name="f2sdram_awuser" direction="input" role="awuser" width="8" />
   <port name="f2sdram_wuser" direction="input" role="wuser" width="8" />
   <port name="f2sdram_buser" direction="output" role="buser" width="8" />
   <port name="f2sdram_arregion" direction="input" role="arregion" width="4" />
   <port name="f2sdram_ruser" direction="output" role="ruser" width="8" />
   <port name="f2sdram_awregion" direction="input" role="awregion" width="4" />
  </interface>
  <interface name="emif_hps_emif_mem_0" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="emif_hps_emif_mem_0_mem_cs"
       direction="output"
       role="mem_cs"
       width="1" />
   <port
       name="emif_hps_emif_mem_0_mem_ca"
       direction="output"
       role="mem_ca"
       width="6" />
   <port
       name="emif_hps_emif_mem_0_mem_cke"
       direction="output"
       role="mem_cke"
       width="1" />
   <port
       name="emif_hps_emif_mem_0_mem_dq"
       direction="bidir"
       role="mem_dq"
       width="32" />
   <port
       name="emif_hps_emif_mem_0_mem_dqs_t"
       direction="bidir"
       role="mem_dqs_t"
       width="4" />
   <port
       name="emif_hps_emif_mem_0_mem_dqs_c"
       direction="bidir"
       role="mem_dqs_c"
       width="4" />
   <port
       name="emif_hps_emif_mem_0_mem_dmi"
       direction="bidir"
       role="mem_dmi"
       width="4" />
  </interface>
  <interface name="emif_hps_emif_mem_ck_0" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="emif_hps_emif_mem_ck_0_mem_ck_t"
       direction="output"
       role="mem_ck_t"
       width="1" />
   <port
       name="emif_hps_emif_mem_ck_0_mem_ck_c"
       direction="output"
       role="mem_ck_c"
       width="1" />
  </interface>
  <interface name="emif_hps_emif_mem_reset_n" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="emif_hps_emif_mem_reset_n_mem_reset_n"
       direction="output"
       role="mem_reset_n"
       width="1" />
  </interface>
  <interface name="emif_hps_emif_oct_0" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="emif_hps_emif_oct_0_oct_rzqin"
       direction="input"
       role="oct_rzqin"
       width="1" />
  </interface>
  <interface name="emif_hps_emif_ref_clk_0" kind="clock" start="0">
   <property name="clockRate" value="0" />
   <property name="externallyDriven" value="false" />
   <property name="ptfSchematicName" value="" />
   <port
       name="emif_hps_emif_ref_clk_0_clk"
       direction="input"
       role="clk"
       width="1" />
  </interface>
  <interface name="button_pio_external_connection" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="button_pio_external_connection_export"
       direction="input"
       role="export"
       width="4" />
  </interface>
  <interface name="dipsw_pio_external_connection" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="dipsw_pio_external_connection_export"
       direction="input"
       role="export"
       width="4" />
  </interface>
  <interface name="led_pio_external_connection" kind="conduit" start="0">
   <property name="associatedClock" value="" />
   <property name="associatedReset" value="" />
   <property name="prSafe" value="false" />
   <port
       name="led_pio_external_connection_in_port"
       direction="input"
       role="in_port"
       width="3" />
   <port
       name="led_pio_external_connection_out_port"
       direction="output"
       role="out_port"
       width="3" />
  </interface>
 </perimeter>
 <entity kind="qsys_top" version="1.0" name="qsys_top">
  <parameter name="AUTO_F2H_IRQ1_IN_INTERRUPTS_USED" value="-1" />
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="AUTO_BOARD" value="default" />
  <parameter name="AUTO_CLK_100_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_UNIQUE_ID" value="" />
  <parameter name="AUTO_F2SDRAM_CPU_INFO_ID" value="" />
  <parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_0_CLOCK_DOMAIN" value="-1" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
  <parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_0_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_SUBSYS_HPS_HPS2FPGA_ADDRESS_WIDTH" value="-1" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="AUTO_CLK_100_RESET_DOMAIN" value="-1" />
  <parameter name="AUTO_CLK_100_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_SUBSYS_HPS_HPS2FPGA_ADDRESS_MAP" value="" />
  <parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_0_CLOCK_RATE" value="-1" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/synth/qsys_top.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/synth/qsys_top.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top.qsys" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/hps_subsys.qsys" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/peripheral_subsys.qsys" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_axi_translator/altera_merlin_axi_translator_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_axi_master_ni/altera_merlin_axi_master_ni_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </childSourceFiles>
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top"</message>
   <message level="Info" culprit="qsys_top">"Generating: clk_100"</message>
   <message level="Info" culprit="qsys_top">"Generating: rst_in"</message>
   <message level="Info" culprit="qsys_top">"Generating: user_rst_clkgate_0"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_mm_interconnect_1920_ykfyxdi"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_axi_translator_1987_lty7xoq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_slave_translator_191_xg7rzxi"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_axi_master_ni_19117_qautany"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_slave_agent_1930_jxauz3i"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_avalon_sc_fifo_1932_22gxxgi"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_router_1921_ox5xuhq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_router_1921_sxavatq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy"</message>
   <message level="Info" culprit="my_altera_avalon_st_pipeline_stage">"Generating: my_altera_avalon_st_pipeline_stage"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_multiplexer_1922_666s25q"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_demultiplexer_1921_qyizksq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_multiplexer_1922_yjgptii"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_irq_mapper_2001_lp4cnei"</message>
   <message level="Info" culprit="qsys_top">"Generating: altera_reset_controller"</message>
  </messages>
 </entity>
 <entity kind="hps_subsys" version="1.0" name="hps_subsys">
  <parameter name="AUTO_F2H_IRQ0_IN_INTERRUPTS_USED" value="3" />
  <parameter name="AUTO_LWHPS2FPGA_CLK_CLOCK_DOMAIN" value="1" />
  <parameter name="AUTO_F2H_IRQ1_IN_INTERRUPTS_USED" value="-1" />
  <parameter name="AUTO_HPS2FPGA_ADDRESS_MAP" value="" />
  <parameter
     name="AUTO_LWHPS2FPGA_ADDRESS_MAP"
     value="&lt;address-map&gt;&lt;slave name=&apos;subsys_periph.sysid.control_slave&apos; start=&apos;0x10000&apos; end=&apos;0x10008&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;subsys_periph.button_pio.s1&apos; start=&apos;0x10060&apos; end=&apos;0x10070&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;subsys_periph.dipsw_pio.s1&apos; start=&apos;0x10070&apos; end=&apos;0x10080&apos; datawidth=&apos;32&apos; /&gt;&lt;slave name=&apos;subsys_periph.led_pio.s1&apos; start=&apos;0x10080&apos; end=&apos;0x10090&apos; datawidth=&apos;32&apos; /&gt;&lt;/address-map&gt;" />
  <parameter name="AUTO_BOARD" value="default" />
  <parameter name="AUTO_HPS2FPGA_CLK_CLOCK_RATE" value="100000000" />
  <parameter name="AUTO_UNIQUE_ID" value="qsys_top_subsys_hps" />
  <parameter name="AUTO_F2SDRAM_CPU_INFO_ID" value="" />
  <parameter name="AUTO_LWHPS2FPGA_ADDRESS_WIDTH" value="17" />
  <parameter name="AUTO_F2SDRAM_CLK_CLOCK_RATE" value="100000000" />
  <parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_RESET_DOMAIN" value="2" />
  <parameter name="AUTO_HPS2FPGA_ADDRESS_WIDTH" value="-1" />
  <parameter name="AUTO_HPS2FPGA_CLK_RESET_DOMAIN" value="1" />
  <parameter name="AUTO_LWHPS2FPGA_CLK_RESET_DOMAIN" value="1" />
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="AUTO_LWHPS2FPGA_CLK_CLOCK_RATE" value="100000000" />
  <parameter name="AUTO_F2SDRAM_CLK_RESET_DOMAIN" value="1" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
  <parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_CLOCK_RATE" value="-1" />
  <parameter name="AUTO_F2SDRAM_CLK_CLOCK_DOMAIN" value="1" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="AUTO_EMIF_HPS_EMIF_REF_CLK_CLOCK_DOMAIN" value="2" />
  <parameter name="AUTO_HPS2FPGA_CLK_CLOCK_DOMAIN" value="1" />
  <generatedFiles/>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/hps_subsys/hps_subsys.qsys" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="qsys_top" as="subsys_hps" />
  <messages/>
 </entity>
 <entity kind="peripheral_subsys" version="1.0" name="peripheral_subsys">
  <parameter name="AUTO_CLK_CLOCK_RATE" value="100000000" />
  <parameter name="AUTO_GENERATION_ID" value="0" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="AUTO_BOARD" value="default" />
  <parameter name="AUTO_CLK_RESET_DOMAIN" value="1" />
  <parameter name="AUTO_PB_CPU_0_S0_CPU_INFO_ID" value="" />
  <parameter name="AUTO_CLK_CLOCK_DOMAIN" value="1" />
  <parameter name="AUTO_UNIQUE_ID" value="qsys_top_subsys_periph" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="4" />
  <generatedFiles/>
  <childGeneratedFiles/>
  <sourceFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/peripheral_subsys/peripheral_subsys.qsys" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="qsys_top" as="subsys_periph" />
  <messages/>
 </entity>
 <entity kind="altera_generic_component" version="1.0" name="clk_100">
  <parameter
     name="cpuHashInfo"
     value="&lt;cpuHashInfoDefinition&gt;
    &lt;cpuHashInfoMap/&gt;
&lt;/cpuHashInfoDefinition&gt;" />
  <parameter name="hlsFile" value="" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter
     name="defaultBoundary"
     value="&lt;boundaryDefinition&gt;
    &lt;interfaces&gt;
        &lt;interface&gt;
            &lt;name&gt;in_clk&lt;/name&gt;
            &lt;type&gt;clock&lt;/type&gt;
            &lt;isStart&gt;false&lt;/isStart&gt;
            &lt;ports&gt;
                &lt;port&gt;
                    &lt;name&gt;in_clk&lt;/name&gt;
                    &lt;role&gt;clk&lt;/role&gt;
                    &lt;direction&gt;Input&lt;/direction&gt;
                    &lt;width&gt;1&lt;/width&gt;
                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
                    &lt;terminationValue&gt;0&lt;/terminationValue&gt;
                &lt;/port&gt;
            &lt;/ports&gt;
            &lt;assignments&gt;
                &lt;assignmentValueMap/&gt;
            &lt;/assignments&gt;
            &lt;parameters&gt;
                &lt;parameterValueMap&gt;
                    &lt;entry&gt;
                        &lt;key&gt;clockRate&lt;/key&gt;
                        &lt;value&gt;0&lt;/value&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;externallyDriven&lt;/key&gt;
                        &lt;value&gt;false&lt;/value&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
                    &lt;/entry&gt;
                &lt;/parameterValueMap&gt;
            &lt;/parameters&gt;
        &lt;/interface&gt;
        &lt;interface&gt;
            &lt;name&gt;out_clk&lt;/name&gt;
            &lt;type&gt;clock&lt;/type&gt;
            &lt;isStart&gt;true&lt;/isStart&gt;
            &lt;ports&gt;
                &lt;port&gt;
                    &lt;name&gt;out_clk&lt;/name&gt;
                    &lt;role&gt;clk&lt;/role&gt;
                    &lt;direction&gt;Output&lt;/direction&gt;
                    &lt;width&gt;1&lt;/width&gt;
                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
                    &lt;terminationValue&gt;0&lt;/terminationValue&gt;
                &lt;/port&gt;
            &lt;/ports&gt;
            &lt;assignments&gt;
                &lt;assignmentValueMap/&gt;
            &lt;/assignments&gt;
            &lt;parameters&gt;
                &lt;parameterValueMap&gt;
                    &lt;entry&gt;
                        &lt;key&gt;associatedDirectClock&lt;/key&gt;
                        &lt;value&gt;in_clk&lt;/value&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;clockRate&lt;/key&gt;
                        &lt;value&gt;100000000&lt;/value&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;clockRateKnown&lt;/key&gt;
                        &lt;value&gt;true&lt;/value&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;externallyDriven&lt;/key&gt;
                        &lt;value&gt;false&lt;/value&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;ptfSchematicName&lt;/key&gt;
                    &lt;/entry&gt;
                &lt;/parameterValueMap&gt;
            &lt;/parameters&gt;
        &lt;/interface&gt;
    &lt;/interfaces&gt;
&lt;/boundaryDefinition&gt;" />
  <parameter name="bspCpu" value="false" />
  <parameter
     name="componentDefinition"
     value="&lt;componentDefinition&gt;
    &lt;boundary&gt;
        &lt;interfaces&gt;
            &lt;interface&gt;
                &lt;name&gt;in_clk&lt;/name&gt;
                &lt;type&gt;clock&lt;/type&gt;
                &lt;isStart&gt;false&lt;/isStart&gt;
                &lt;ports&gt;
                    &lt;port&gt;
                        &lt;name&gt;in_clk&lt;/name&gt;
                        &lt;role&gt;clk&lt;/role&gt;
                        &lt;direction&gt;Input&lt;/direction&gt;
                        &lt;width&gt;1&lt;/width&gt;
                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
                        &lt;terminationValue&gt;0&lt;/terminationValue&gt;
                    &lt;/port&gt;
                &lt;/ports&gt;
                &lt;assignments&gt;
                    &lt;assignmentValueMap/&gt;
                &lt;/assignments&gt;
                &lt;parameters&gt;
                    &lt;parameterValueMap&gt;
                        &lt;entry&gt;
                            &lt;key&gt;clockRate&lt;/key&gt;
                            &lt;value&gt;0&lt;/value&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;externallyDriven&lt;/key&gt;
                            &lt;value&gt;false&lt;/value&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;ptfSchematicName&lt;/key&gt;
                        &lt;/entry&gt;
                    &lt;/parameterValueMap&gt;
                &lt;/parameters&gt;
            &lt;/interface&gt;
            &lt;interface&gt;
                &lt;name&gt;out_clk&lt;/name&gt;
                &lt;type&gt;clock&lt;/type&gt;
                &lt;isStart&gt;true&lt;/isStart&gt;
                &lt;ports&gt;
                    &lt;port&gt;
                        &lt;name&gt;out_clk&lt;/name&gt;
                        &lt;role&gt;clk&lt;/role&gt;
                        &lt;direction&gt;Output&lt;/direction&gt;
                        &lt;width&gt;1&lt;/width&gt;
                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
                        &lt;terminationValue&gt;0&lt;/terminationValue&gt;
                    &lt;/port&gt;
                &lt;/ports&gt;
                &lt;assignments&gt;
                    &lt;assignmentValueMap/&gt;
                &lt;/assignments&gt;
                &lt;parameters&gt;
                    &lt;parameterValueMap&gt;
                        &lt;entry&gt;
                            &lt;key&gt;associatedDirectClock&lt;/key&gt;
                            &lt;value&gt;in_clk&lt;/value&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;clockRate&lt;/key&gt;
                            &lt;value&gt;100000000&lt;/value&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;clockRateKnown&lt;/key&gt;
                            &lt;value&gt;true&lt;/value&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;externallyDriven&lt;/key&gt;
                            &lt;value&gt;false&lt;/value&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;ptfSchematicName&lt;/key&gt;
                        &lt;/entry&gt;
                    &lt;/parameterValueMap&gt;
                &lt;/parameters&gt;
            &lt;/interface&gt;
        &lt;/interfaces&gt;
    &lt;/boundary&gt;
    &lt;originalModuleInfo&gt;
        &lt;className&gt;altera_clock_bridge&lt;/className&gt;
        &lt;version&gt;19.2.0&lt;/version&gt;
        &lt;displayName&gt;Clock Bridge IP&lt;/displayName&gt;
    &lt;/originalModuleInfo&gt;
    &lt;systemInfoParameterDescriptors&gt;
        &lt;descriptors&gt;
            &lt;descriptor&gt;
                &lt;parameterDefaultValue&gt;0&lt;/parameterDefaultValue&gt;
                &lt;parameterName&gt;DERIVED_CLOCK_RATE&lt;/parameterName&gt;
                &lt;parameterType&gt;java.lang.Long&lt;/parameterType&gt;
                &lt;systemInfoArgs&gt;in_clk&lt;/systemInfoArgs&gt;
                &lt;systemInfotype&gt;CLOCK_RATE&lt;/systemInfotype&gt;
            &lt;/descriptor&gt;
        &lt;/descriptors&gt;
    &lt;/systemInfoParameterDescriptors&gt;
    &lt;systemInfos&gt;
        &lt;connPtSystemInfos&gt;
            &lt;entry&gt;
                &lt;key&gt;in_clk&lt;/key&gt;
                &lt;value&gt;
                    &lt;connectionPointName&gt;in_clk&lt;/connectionPointName&gt;
                    &lt;suppliedSystemInfos/&gt;
                    &lt;consumedSystemInfos&gt;
                        &lt;entry&gt;
                            &lt;key&gt;CLOCK_RATE&lt;/key&gt;
                            &lt;value&gt;0&lt;/value&gt;
                        &lt;/entry&gt;
                    &lt;/consumedSystemInfos&gt;
                &lt;/value&gt;
            &lt;/entry&gt;
            &lt;entry&gt;
                &lt;key&gt;out_clk&lt;/key&gt;
                &lt;value&gt;
                    &lt;connectionPointName&gt;out_clk&lt;/connectionPointName&gt;
                    &lt;suppliedSystemInfos&gt;
                        &lt;entry&gt;
                            &lt;key&gt;CLOCK_RATE&lt;/key&gt;
                            &lt;value&gt;100000000&lt;/value&gt;
                        &lt;/entry&gt;
                    &lt;/suppliedSystemInfos&gt;
                    &lt;consumedSystemInfos/&gt;
                &lt;/value&gt;
            &lt;/entry&gt;
        &lt;/connPtSystemInfos&gt;
    &lt;/systemInfos&gt;
&lt;/componentDefinition&gt;" />
  <parameter name="DERIVED_CLOCK_RATE" value="0" />
  <parameter name="cpuInfo" value="" />
  <parameter name="logicalView" value="ip/qsys_top/clk_100.ip" />
  <parameter
     name="moduleAssignmentDefinition"
     value="&lt;assignmentDefinition&gt;
    &lt;assignmentValueMap/&gt;
&lt;/assignmentDefinition&gt;" />
  <parameter
     name="transformParameters"
     value="&lt;transformParameterDescriptorDefinitionList/&gt;" />
  <parameter name="svInterfaceDefinition" value="" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter
     name="hdlParameters"
     value="&lt;hdlParameterDescriptorDefinitionList/&gt;" />
  <parameter
     name="generationInfoDefinition"
     value="&lt;generationInfoDefinition&gt;
    &lt;hdlLibraryName&gt;clk_100&lt;/hdlLibraryName&gt;
    &lt;fileSets&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;clk_100&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;clk_100&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;QUARTUS_SYNTH&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;clk_100&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;clk_100&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;SIM_VERILOG&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;clk_100&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;clk_100&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;SIM_VHDL&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;clk_100&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;clk_100&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;CDC&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;clk_100&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;clk_100&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;CDC_VHDL&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
    &lt;/fileSets&gt;
&lt;/generationInfoDefinition&gt;" />
  <parameter name="liveModuleName" value="altera_clock_bridge_inst" />
  <generatedFiles/>
  <childGeneratedFiles/>
  <sourceFiles/>
  <childSourceFiles/>
  <instantiator instantiator="qsys_top" as="clk_100" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: clk_100"</message>
  </messages>
 </entity>
 <entity kind="altera_generic_component" version="1.0" name="rst_in">
  <parameter
     name="cpuHashInfo"
     value="&lt;cpuHashInfoDefinition&gt;
    &lt;cpuHashInfoMap/&gt;
&lt;/cpuHashInfoDefinition&gt;" />
  <parameter name="AUTO_CLK_CLOCK_RATE" value="-1" />
  <parameter name="hlsFile" value="" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter
     name="defaultBoundary"
     value="&lt;boundaryDefinition&gt;
    &lt;interfaces&gt;
        &lt;interface&gt;
            &lt;name&gt;in_reset&lt;/name&gt;
            &lt;type&gt;reset&lt;/type&gt;
            &lt;isStart&gt;false&lt;/isStart&gt;
            &lt;ports&gt;
                &lt;port&gt;
                    &lt;name&gt;in_reset_n&lt;/name&gt;
                    &lt;role&gt;reset_n&lt;/role&gt;
                    &lt;direction&gt;Input&lt;/direction&gt;
                    &lt;width&gt;1&lt;/width&gt;
                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
                    &lt;terminationValue&gt;0&lt;/terminationValue&gt;
                &lt;/port&gt;
            &lt;/ports&gt;
            &lt;assignments&gt;
                &lt;assignmentValueMap/&gt;
            &lt;/assignments&gt;
            &lt;parameters&gt;
                &lt;parameterValueMap&gt;
                    &lt;entry&gt;
                        &lt;key&gt;associatedClock&lt;/key&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;synchronousEdges&lt;/key&gt;
                        &lt;value&gt;NONE&lt;/value&gt;
                    &lt;/entry&gt;
                &lt;/parameterValueMap&gt;
            &lt;/parameters&gt;
        &lt;/interface&gt;
        &lt;interface&gt;
            &lt;name&gt;out_reset&lt;/name&gt;
            &lt;type&gt;reset&lt;/type&gt;
            &lt;isStart&gt;true&lt;/isStart&gt;
            &lt;ports&gt;
                &lt;port&gt;
                    &lt;name&gt;out_reset_n&lt;/name&gt;
                    &lt;role&gt;reset_n&lt;/role&gt;
                    &lt;direction&gt;Output&lt;/direction&gt;
                    &lt;width&gt;1&lt;/width&gt;
                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
                    &lt;terminationValue&gt;0&lt;/terminationValue&gt;
                &lt;/port&gt;
            &lt;/ports&gt;
            &lt;assignments&gt;
                &lt;assignmentValueMap/&gt;
            &lt;/assignments&gt;
            &lt;parameters&gt;
                &lt;parameterValueMap&gt;
                    &lt;entry&gt;
                        &lt;key&gt;associatedClock&lt;/key&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;associatedDirectReset&lt;/key&gt;
                        &lt;value&gt;in_reset&lt;/value&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;associatedResetSinks&lt;/key&gt;
                        &lt;value&gt;in_reset&lt;/value&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;synchronousEdges&lt;/key&gt;
                        &lt;value&gt;NONE&lt;/value&gt;
                    &lt;/entry&gt;
                &lt;/parameterValueMap&gt;
            &lt;/parameters&gt;
        &lt;/interface&gt;
    &lt;/interfaces&gt;
&lt;/boundaryDefinition&gt;" />
  <parameter name="bspCpu" value="false" />
  <parameter
     name="componentDefinition"
     value="&lt;componentDefinition&gt;
    &lt;boundary&gt;
        &lt;interfaces&gt;
            &lt;interface&gt;
                &lt;name&gt;in_reset&lt;/name&gt;
                &lt;type&gt;reset&lt;/type&gt;
                &lt;isStart&gt;false&lt;/isStart&gt;
                &lt;ports&gt;
                    &lt;port&gt;
                        &lt;name&gt;in_reset_n&lt;/name&gt;
                        &lt;role&gt;reset_n&lt;/role&gt;
                        &lt;direction&gt;Input&lt;/direction&gt;
                        &lt;width&gt;1&lt;/width&gt;
                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
                        &lt;terminationValue&gt;0&lt;/terminationValue&gt;
                    &lt;/port&gt;
                &lt;/ports&gt;
                &lt;assignments&gt;
                    &lt;assignmentValueMap/&gt;
                &lt;/assignments&gt;
                &lt;parameters&gt;
                    &lt;parameterValueMap&gt;
                        &lt;entry&gt;
                            &lt;key&gt;associatedClock&lt;/key&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;synchronousEdges&lt;/key&gt;
                            &lt;value&gt;NONE&lt;/value&gt;
                        &lt;/entry&gt;
                    &lt;/parameterValueMap&gt;
                &lt;/parameters&gt;
            &lt;/interface&gt;
            &lt;interface&gt;
                &lt;name&gt;out_reset&lt;/name&gt;
                &lt;type&gt;reset&lt;/type&gt;
                &lt;isStart&gt;true&lt;/isStart&gt;
                &lt;ports&gt;
                    &lt;port&gt;
                        &lt;name&gt;out_reset_n&lt;/name&gt;
                        &lt;role&gt;reset_n&lt;/role&gt;
                        &lt;direction&gt;Output&lt;/direction&gt;
                        &lt;width&gt;1&lt;/width&gt;
                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
                        &lt;terminationValue&gt;0&lt;/terminationValue&gt;
                    &lt;/port&gt;
                &lt;/ports&gt;
                &lt;assignments&gt;
                    &lt;assignmentValueMap/&gt;
                &lt;/assignments&gt;
                &lt;parameters&gt;
                    &lt;parameterValueMap&gt;
                        &lt;entry&gt;
                            &lt;key&gt;associatedClock&lt;/key&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;associatedDirectReset&lt;/key&gt;
                            &lt;value&gt;in_reset&lt;/value&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;associatedResetSinks&lt;/key&gt;
                            &lt;value&gt;in_reset&lt;/value&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;synchronousEdges&lt;/key&gt;
                            &lt;value&gt;NONE&lt;/value&gt;
                        &lt;/entry&gt;
                    &lt;/parameterValueMap&gt;
                &lt;/parameters&gt;
            &lt;/interface&gt;
        &lt;/interfaces&gt;
    &lt;/boundary&gt;
    &lt;originalModuleInfo&gt;
        &lt;className&gt;altera_reset_bridge&lt;/className&gt;
        &lt;version&gt;19.2.0&lt;/version&gt;
        &lt;displayName&gt;Reset Bridge IP&lt;/displayName&gt;
    &lt;/originalModuleInfo&gt;
    &lt;systemInfoParameterDescriptors&gt;
        &lt;descriptors&gt;
            &lt;descriptor&gt;
                &lt;parameterDefaultValue&gt;-1&lt;/parameterDefaultValue&gt;
                &lt;parameterName&gt;AUTO_CLK_CLOCK_RATE&lt;/parameterName&gt;
                &lt;parameterType&gt;java.lang.Long&lt;/parameterType&gt;
                &lt;systemInfoArgs&gt;clk&lt;/systemInfoArgs&gt;
                &lt;systemInfotype&gt;CLOCK_RATE&lt;/systemInfotype&gt;
            &lt;/descriptor&gt;
        &lt;/descriptors&gt;
    &lt;/systemInfoParameterDescriptors&gt;
    &lt;systemInfos&gt;
        &lt;connPtSystemInfos/&gt;
    &lt;/systemInfos&gt;
&lt;/componentDefinition&gt;" />
  <parameter name="cpuInfo" value="" />
  <parameter name="logicalView" value="ip/qsys_top/rst_in.ip" />
  <parameter
     name="moduleAssignmentDefinition"
     value="&lt;assignmentDefinition&gt;
    &lt;assignmentValueMap/&gt;
&lt;/assignmentDefinition&gt;" />
  <parameter
     name="transformParameters"
     value="&lt;transformParameterDescriptorDefinitionList/&gt;" />
  <parameter name="svInterfaceDefinition" value="" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter
     name="hdlParameters"
     value="&lt;hdlParameterDescriptorDefinitionList/&gt;" />
  <parameter
     name="generationInfoDefinition"
     value="&lt;generationInfoDefinition&gt;
    &lt;hdlLibraryName&gt;rst_in&lt;/hdlLibraryName&gt;
    &lt;fileSets&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;rst_in&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;rst_in&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;QUARTUS_SYNTH&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;rst_in&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;rst_in&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;SIM_VERILOG&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;rst_in&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;rst_in&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;SIM_VHDL&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;rst_in&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;rst_in&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;CDC&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;rst_in&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;rst_in&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;CDC_VHDL&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
    &lt;/fileSets&gt;
&lt;/generationInfoDefinition&gt;" />
  <parameter name="liveModuleName" value="altera_reset_bridge_inst" />
  <generatedFiles/>
  <childGeneratedFiles/>
  <sourceFiles/>
  <childSourceFiles/>
  <instantiator instantiator="qsys_top" as="rst_in" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: rst_in"</message>
  </messages>
 </entity>
 <entity
   kind="altera_generic_component"
   version="1.0"
   name="user_rst_clkgate_0">
  <parameter
     name="cpuHashInfo"
     value="&lt;cpuHashInfoDefinition&gt;
    &lt;cpuHashInfoMap/&gt;
&lt;/cpuHashInfoDefinition&gt;" />
  <parameter name="hlsFile" value="" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="DEVICE_FAMILY" value="Agilex 5" />
  <parameter
     name="defaultBoundary"
     value="&lt;boundaryDefinition&gt;
    &lt;interfaces&gt;
        &lt;interface&gt;
            &lt;name&gt;ninit_done&lt;/name&gt;
            &lt;type&gt;conduit&lt;/type&gt;
            &lt;isStart&gt;false&lt;/isStart&gt;
            &lt;ports&gt;
                &lt;port&gt;
                    &lt;name&gt;ninit_done&lt;/name&gt;
                    &lt;role&gt;ninit_done&lt;/role&gt;
                    &lt;direction&gt;Output&lt;/direction&gt;
                    &lt;width&gt;1&lt;/width&gt;
                    &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                    &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
                    &lt;terminationValue&gt;0&lt;/terminationValue&gt;
                &lt;/port&gt;
            &lt;/ports&gt;
            &lt;assignments&gt;
                &lt;assignmentValueMap/&gt;
            &lt;/assignments&gt;
            &lt;parameters&gt;
                &lt;parameterValueMap&gt;
                    &lt;entry&gt;
                        &lt;key&gt;associatedClock&lt;/key&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;associatedReset&lt;/key&gt;
                    &lt;/entry&gt;
                    &lt;entry&gt;
                        &lt;key&gt;prSafe&lt;/key&gt;
                        &lt;value&gt;false&lt;/value&gt;
                    &lt;/entry&gt;
                &lt;/parameterValueMap&gt;
            &lt;/parameters&gt;
        &lt;/interface&gt;
    &lt;/interfaces&gt;
&lt;/boundaryDefinition&gt;" />
  <parameter name="bspCpu" value="false" />
  <parameter
     name="componentDefinition"
     value="&lt;componentDefinition&gt;
    &lt;boundary&gt;
        &lt;interfaces&gt;
            &lt;interface&gt;
                &lt;name&gt;ninit_done&lt;/name&gt;
                &lt;type&gt;conduit&lt;/type&gt;
                &lt;isStart&gt;false&lt;/isStart&gt;
                &lt;ports&gt;
                    &lt;port&gt;
                        &lt;name&gt;ninit_done&lt;/name&gt;
                        &lt;role&gt;ninit_done&lt;/role&gt;
                        &lt;direction&gt;Output&lt;/direction&gt;
                        &lt;width&gt;1&lt;/width&gt;
                        &lt;lowerBound&gt;0&lt;/lowerBound&gt;
                        &lt;vhdlType&gt;STD_LOGIC&lt;/vhdlType&gt;
                        &lt;terminationValue&gt;0&lt;/terminationValue&gt;
                    &lt;/port&gt;
                &lt;/ports&gt;
                &lt;assignments&gt;
                    &lt;assignmentValueMap/&gt;
                &lt;/assignments&gt;
                &lt;parameters&gt;
                    &lt;parameterValueMap&gt;
                        &lt;entry&gt;
                            &lt;key&gt;associatedClock&lt;/key&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;associatedReset&lt;/key&gt;
                        &lt;/entry&gt;
                        &lt;entry&gt;
                            &lt;key&gt;prSafe&lt;/key&gt;
                            &lt;value&gt;false&lt;/value&gt;
                        &lt;/entry&gt;
                    &lt;/parameterValueMap&gt;
                &lt;/parameters&gt;
            &lt;/interface&gt;
        &lt;/interfaces&gt;
    &lt;/boundary&gt;
    &lt;originalModuleInfo&gt;
        &lt;className&gt;intel_user_rst_clkgate&lt;/className&gt;
        &lt;version&gt;1.0.1&lt;/version&gt;
        &lt;displayName&gt;Reset Release IP&lt;/displayName&gt;
    &lt;/originalModuleInfo&gt;
    &lt;systemInfoParameterDescriptors&gt;
        &lt;descriptors&gt;
            &lt;descriptor&gt;
                &lt;parameterDefaultValue&gt;&lt;/parameterDefaultValue&gt;
                &lt;parameterName&gt;DEVICE_FAMILY&lt;/parameterName&gt;
                &lt;parameterType&gt;java.lang.String&lt;/parameterType&gt;
                &lt;systemInfotype&gt;DEVICE_FAMILY&lt;/systemInfotype&gt;
            &lt;/descriptor&gt;
        &lt;/descriptors&gt;
    &lt;/systemInfoParameterDescriptors&gt;
    &lt;systemInfos&gt;
        &lt;connPtSystemInfos/&gt;
    &lt;/systemInfos&gt;
&lt;/componentDefinition&gt;" />
  <parameter name="cpuInfo" value="" />
  <parameter name="logicalView" value="ip/qsys_top/user_rst_clkgate_0.ip" />
  <parameter
     name="moduleAssignmentDefinition"
     value="&lt;assignmentDefinition&gt;
    &lt;assignmentValueMap/&gt;
&lt;/assignmentDefinition&gt;" />
  <parameter
     name="transformParameters"
     value="&lt;transformParameterDescriptorDefinitionList/&gt;" />
  <parameter name="svInterfaceDefinition" value="" />
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter
     name="hdlParameters"
     value="&lt;hdlParameterDescriptorDefinitionList/&gt;" />
  <parameter
     name="generationInfoDefinition"
     value="&lt;generationInfoDefinition&gt;
    &lt;hdlLibraryName&gt;user_rst_clkgate_0&lt;/hdlLibraryName&gt;
    &lt;fileSets&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;user_rst_clkgate_0&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;user_rst_clkgate_0&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;QUARTUS_SYNTH&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;user_rst_clkgate_0&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;user_rst_clkgate_0&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;SIM_VERILOG&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;user_rst_clkgate_0&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;user_rst_clkgate_0&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;SIM_VHDL&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;user_rst_clkgate_0&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;user_rst_clkgate_0&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;CDC&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
        &lt;fileSet&gt;
            &lt;fileSetName&gt;user_rst_clkgate_0&lt;/fileSetName&gt;
            &lt;fileSetFixedName&gt;user_rst_clkgate_0&lt;/fileSetFixedName&gt;
            &lt;fileSetKind&gt;CDC_VHDL&lt;/fileSetKind&gt;
            &lt;fileSetFiles/&gt;
            &lt;fileSetFileChangeDefs/&gt;
        &lt;/fileSet&gt;
    &lt;/fileSets&gt;
&lt;/generationInfoDefinition&gt;" />
  <parameter name="liveModuleName" value="intel_user_rst_clkgate_inst" />
  <generatedFiles/>
  <childGeneratedFiles/>
  <sourceFiles/>
  <childSourceFiles/>
  <instantiator instantiator="qsys_top" as="user_rst_clkgate_0" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: user_rst_clkgate_0"</message>
  </messages>
 </entity>
 <entity
   kind="altera_mm_interconnect"
   version="19.2.0"
   name="qsys_top_altera_mm_interconnect_1920_ykfyxdi">
  <parameter name="AUTO_DEVICE" value="A5EB013BB23BE4SCS" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="AUTO_BOARD" value="default" />
  <parameter name="AUTO_DEVICE_SPEEDGRADE" value="" />
  <parameter
     name="COMPOSE_CONTENTS"
     value="add_instance {subsys_hps_lwhps2fpga_translator} {altera_merlin_axi_translator};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWREGION} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWREGION} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWLEN} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSIZE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWBURST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWQOS} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWQOS} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WSTRB} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WLAST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WLAST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_BRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARREGION} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARREGION} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARLEN} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARSIZE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARBURST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARLOCK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARQOS} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARPROT} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARCACHE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARQOS} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RID} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RRESP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RLAST} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BUSER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_BUSER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUSER_ADDRCHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUSER_SAI} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARUSER_ADDRCHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARUSER_SAI} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER_DATACHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER_POISON} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER_DATACHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER_POISON} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WUSER_DATA} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RUSER_DATA} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWAKEUP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_BTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_WDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_RDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWUNIQUE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWAKEUP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RPOISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_BTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RTRACE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RDATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUSER_ADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUSER_SAI} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARUSER_ADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARUSER_SAI} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER_DATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER_POISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER_DATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_WUSER_DATA} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER_DATA} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_RUSER_POISON} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWUNIQUE} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWATOP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHNID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHNIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHLPID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSTASHLPIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWATOP} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHNID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHNIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHLPID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWSTASHLPIDEN} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARMMUSECSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARMMUSID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWSNOOP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARSNOOP} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_AWADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_S0_ARADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_AWADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USE_M0_ARADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_ID_WIDTH} {4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {DATA_WIDTH} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_SAI_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_SAI_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {USER_DATA_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_USER_ADDRCHK_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_USER_ADDRCHK_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_ID_WIDTH} {4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_ADDR_WIDTH} {29};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_WRITE_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_READ_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_WRITE_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_READ_ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_WRITE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_WRITE_RESPONSE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_READ_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_WRITE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_WRITE_RESPONSE_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_READ_DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_ADDR_WIDTH} {29};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_SID_WIDTH} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_SID_WIDTH} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {WRITE_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {READ_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {COMBINED_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {WRITE_ACCEPTANCE_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {READ_ACCEPTANCE_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {COMBINED_ACCEPTANCE_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {READ_DATA_REORDERING_DEPTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {M0_AXI_VERSION} {AXI4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {S0_AXI_VERSION} {AXI4};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ACE_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ACE5_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {SYNC_RESET} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {REGENERATE_ADDRCHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {ENABLE_AXI5} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {IS_TRANSLATOR} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {TERMINATE_READ_CHANNEL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator} {TERMINATE_WRITE_CHANNEL} {0};add_instance {subsys_periph_pb_cpu_0_s0_translator} {altera_merlin_slave_translator};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ADDRESS_W} {17};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_DATA_W} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_DATA_W} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BURSTCOUNT_W} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BYTEENABLE_W} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_BYTEENABLE_W} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_ADDRESS_W} {29};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_BURSTCOUNT_W} {3};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_READLATENCY} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_SETUP_WAIT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_WRITE_WAIT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_READ_WAIT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_DATA_HOLD} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_TIMING_UNITS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READDATA} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITEDATA} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READ} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITE} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BEGINBURSTTRANSFER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BEGINTRANSFER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BYTEENABLE} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_CHIPSELECT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_ADDRESS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_BURSTCOUNT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READDATAVALID} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WAITREQUEST} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITEBYTEENABLE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_LOCK} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_AV_CLKEN} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_UAV_CLKEN} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_OUTPUTENABLE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_DEBUGACCESS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_READRESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {USE_WRITERESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_SYMBOLS_PER_WORD} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ADDRESS_SYMBOLS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_CONSTANT_BURST_BEHAVIOR} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_REQUIRE_UNALIGNED_ADDRESSES} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_MAX_PENDING_READ_TRANSACTIONS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_MAX_PENDING_WRITE_TRANSACTIONS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BURSTBOUNDARIES} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_INTERLEAVEBURSTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_BITS_PER_SYMBOL} {8};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ISBIGENDIAN} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ADDRESSGROUP} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {UAV_ADDRESSGROUP} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_REGISTEROUTGOINGSIGNALS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_REGISTERINCOMINGSIGNALS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {AV_ALWAYSBURSTMAXBURST} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {CHIPSELECT_THROUGH_READLATENCY} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {WAITREQUEST_ALLOWANCE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_translator} {SYNC_RESET} {1};add_instance {subsys_hps_lwhps2fpga_agent} {altera_merlin_axi_master_ni};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ID_WIDTH} {4};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDR_WIDTH} {29};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {RDATA_WIDTH} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {WDATA_WIDTH} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDR_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {SAI_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDRCHK_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USER_DATA_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {SID_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_ADDR_USER} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_PKT_DATACHK} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_PKT_ADDRCHK} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {AXI_VERSION} {AXI4};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ACE_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ACE5_LITE_SUPPORT} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {WRITE_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {READ_ISSUING_CAPABILITY} {16};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_READ_TERMINAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_WRITE_TERMINAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_READ_UNIVERSAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {TERMINATE_WRITE_UNIVERSAL} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_CACHE_H} {113};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_CACHE_L} {110};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_SIDEBAND_H} {94};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_SIDEBAND_L} {94};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_PROTECTION_H} {109};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_PROTECTION_L} {107};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_RESPONSE_STATUS_L} {114};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_RESPONSE_STATUS_H} {115};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BURSTWRAP_L} {82};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTE_CNT_H} {81};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_EXCLUSIVE} {70};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_H} {31};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_L} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SRC_ID_H} {101};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SRC_ID_L} {101};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DEST_ID_H} {102};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DEST_ID_L} {102};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_THREAD_ID_H} {106};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_THREAD_ID_L} {103};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_QOS_L} {97};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_QOS_H} {100};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ORI_BURST_SIZE_L} {116};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ORI_BURST_SIZE_H} {118};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_SIDEBAND_H} {95};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATA_SIDEBAND_L} {95};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DOMAIN_H} {126};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DOMAIN_L} {125};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SNOOP_H} {124};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SNOOP_L} {121};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BARRIER_H} {120};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_BARRIER_L} {119};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_WUNIQUE} {127};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_EOP_OOO} {134};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SOP_OOO} {135};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ATRACE} {141};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRACE} {142};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWAKEUP} {143};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_POISON_H} {128};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_POISON_L} {128};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATACHK_H} {129};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATACHK_L} {129};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDRCHK_H} {132};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_ADDRCHK_L} {131};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SAI_H} {133};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_SAI_L} {133};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_SEQ_H} {140};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_TRANS_SEQ_L} {136};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_USER_DATA_H} {130};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_USER_DATA_L} {130};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWATOP_L} {144};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWATOP_H} {149};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHNID_L} {150};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHNID_H} {160};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHNIDEN} {161};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHLPID_L} {162};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHLPID_H} {166};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_AWSTASHLPIDEN} {167};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_MMUSECSID} {169};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_MMUSID_L} {168};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_MMUSID_H} {168};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {PKT_DATALESS} {170};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ST_DATA_W} {171};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ID} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ADDR_MAP} {&lt;?xml version=&quot;1.0&quot; encoding=&quot;UTF-8&quot;?&gt;
&lt;address_map&gt;
 &lt;slave
   id=&quot;0&quot;
   name=&quot;subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0&quot;
   start=&quot;0x0000000000000000&quot;
   end=&quot;0x00000000000020000&quot;
   responds=&quot;1&quot;
   user_default=&quot;0&quot; /&gt;
&lt;/address_map&gt;
};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {SYNC_RESET} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_TRACE} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {USE_POISON} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {ENABLE_AXI5} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {DATA_USER_WIDTH} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_agent} {RESP_USER_WIDTH} {8};add_instance {subsys_periph_pb_cpu_0_s0_agent} {altera_merlin_slave_agent};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ORI_BURST_SIZE_H} {118};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ORI_BURST_SIZE_L} {116};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_RESPONSE_STATUS_H} {115};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_RESPONSE_STATUS_L} {114};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_PROTECTION_H} {109};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_PROTECTION_L} {107};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BURSTWRAP_L} {82};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTE_CNT_H} {81};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDR_H} {64};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDR_L} {36};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_POSTED} {66};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_READ} {68};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATA_H} {31};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATA_L} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTEEN_H} {35};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_BYTEEN_L} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SRC_ID_H} {101};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SRC_ID_L} {101};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DEST_ID_H} {102};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DEST_ID_L} {102};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_POISON_H} {128};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_POISON_L} {128};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATACHK_H} {129};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATACHK_L} {129};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SAI_H} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SAI_L} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDRCHK_H} {132};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ADDRCHK_L} {131};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_EOP_OOO} {134};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SOP_OOO} {135};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_SEQ_H} {140};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRANS_SEQ_L} {136};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_USER_DATA_H} {130};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_USER_DATA_L} {130};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_ATRACE} {141};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_TRACE} {142};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWAKEUP} {143};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWATOP_H} {149};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWATOP_L} {144};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHNID_H} {160};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHNID_L} {150};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHNIDEN} {161};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHLPID_H} {166};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHLPID_L} {162};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_AWSTASHLPIDEN} {167};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_MMUSECSID} {169};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_MMUSID_H} {168};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_MMUSID_L} {168};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_DATALESS} {170};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PKT_SYMBOL_W} {8};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ST_CHANNEL_W} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ST_DATA_W} {171};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {AVS_BURSTCOUNT_SYMBOLS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {AVS_BURSTCOUNT_W} {3};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {AV_LINEWRAPBURSTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {SUPPRESS_0_BYTEEN_CMD} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {PREVENT_FIFO_OVERFLOW} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {MAX_BYTE_CNT} {4};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {MAX_BURSTWRAP} {127};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ID} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_READRESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_WRITERESPONSE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ECC_ENABLE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {SYNC_RESET} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {USE_PKT_DATACHK} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent} {ENABLE_AXI5} {0};add_instance {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {BITS_PER_SYMBOL} {172};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_PACKETS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {EMPTY_LATENCY} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {EXPLICIT_MAXCHANNEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {MEM_TYPE} {M20K};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo} {SYNC_RESET} {1};add_instance {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {altera_avalon_sc_fifo};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {BITS_PER_SYMBOL} {34};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {FIFO_DEPTH} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {CHANNEL_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {ERROR_WIDTH} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_PACKETS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_FILL_LEVEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {EMPTY_LATENCY} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_MEMORY_BLOCKS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_STORE_FORWARD} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_ALMOST_FULL_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {USE_ALMOST_EMPTY_IF} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {ENABLE_EXPLICIT_MAXCHANNEL} {false};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {EXPLICIT_MAXCHANNEL} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {MEM_TYPE} {M20K};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo} {SYNC_RESET} {1};add_instance {router} {altera_merlin_router};set_instance_parameter_value {router} {DESTINATION_ID} {0 };set_instance_parameter_value {router} {CHANNEL_ID} {1 };set_instance_parameter_value {router} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router} {START_ADDRESS} {0x0 };set_instance_parameter_value {router} {END_ADDRESS} {0x20000 };set_instance_parameter_value {router} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router} {SPAN_OFFSET} {};set_instance_parameter_value {router} {PKT_ADDR_H} {64};set_instance_parameter_value {router} {PKT_ADDR_L} {36};set_instance_parameter_value {router} {PKT_PROTECTION_H} {109};set_instance_parameter_value {router} {PKT_PROTECTION_L} {107};set_instance_parameter_value {router} {PKT_DEST_ID_H} {102};set_instance_parameter_value {router} {PKT_DEST_ID_L} {102};set_instance_parameter_value {router} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router} {PKT_TRANS_READ} {68};set_instance_parameter_value {router} {ST_DATA_W} {171};set_instance_parameter_value {router} {ST_CHANNEL_W} {2};set_instance_parameter_value {router} {DECODER_TYPE} {0};set_instance_parameter_value {router} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router} {DEFAULT_DESTID} {0};set_instance_parameter_value {router} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router} {MEMORY_ALIASING_DECODE} {0};set_instance_parameter_value {router} {HAS_USER_DEFAULT_SLAVE} {0};set_instance_parameter_value {router} {SYNC_RESET} {1};add_instance {router_001} {altera_merlin_router};set_instance_parameter_value {router_001} {DESTINATION_ID} {0 };set_instance_parameter_value {router_001} {CHANNEL_ID} {1 };set_instance_parameter_value {router_001} {TYPE_OF_TRANSACTION} {both };set_instance_parameter_value {router_001} {START_ADDRESS} {0x0 };set_instance_parameter_value {router_001} {END_ADDRESS} {0x20000 };set_instance_parameter_value {router_001} {NON_SECURED_TAG} {1 };set_instance_parameter_value {router_001} {SECURED_RANGE_PAIRS} {0 };set_instance_parameter_value {router_001} {SECURED_RANGE_LIST} {0 };set_instance_parameter_value {router_001} {SPAN_OFFSET} {};set_instance_parameter_value {router_001} {PKT_ADDR_H} {64};set_instance_parameter_value {router_001} {PKT_ADDR_L} {36};set_instance_parameter_value {router_001} {PKT_PROTECTION_H} {109};set_instance_parameter_value {router_001} {PKT_PROTECTION_L} {107};set_instance_parameter_value {router_001} {PKT_DEST_ID_H} {102};set_instance_parameter_value {router_001} {PKT_DEST_ID_L} {102};set_instance_parameter_value {router_001} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_001} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_001} {ST_DATA_W} {171};set_instance_parameter_value {router_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_001} {DECODER_TYPE} {0};set_instance_parameter_value {router_001} {DEFAULT_CHANNEL} {0};set_instance_parameter_value {router_001} {DEFAULT_WR_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_RD_CHANNEL} {-1};set_instance_parameter_value {router_001} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_001} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_001} {MEMORY_ALIASING_DECODE} {0};set_instance_parameter_value {router_001} {HAS_USER_DEFAULT_SLAVE} {0};set_instance_parameter_value {router_001} {SYNC_RESET} {1};add_instance {router_002} {altera_merlin_router};set_instance_parameter_value {router_002} {DESTINATION_ID} {0 0 };set_instance_parameter_value {router_002} {CHANNEL_ID} {01 10 };set_instance_parameter_value {router_002} {TYPE_OF_TRANSACTION} {write read };set_instance_parameter_value {router_002} {START_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {END_ADDRESS} {0x0 0x0 };set_instance_parameter_value {router_002} {NON_SECURED_TAG} {1 1 };set_instance_parameter_value {router_002} {SECURED_RANGE_PAIRS} {0 0 };set_instance_parameter_value {router_002} {SECURED_RANGE_LIST} {0 0 };set_instance_parameter_value {router_002} {SPAN_OFFSET} {};set_instance_parameter_value {router_002} {PKT_ADDR_H} {64};set_instance_parameter_value {router_002} {PKT_ADDR_L} {36};set_instance_parameter_value {router_002} {PKT_PROTECTION_H} {109};set_instance_parameter_value {router_002} {PKT_PROTECTION_L} {107};set_instance_parameter_value {router_002} {PKT_DEST_ID_H} {102};set_instance_parameter_value {router_002} {PKT_DEST_ID_L} {102};set_instance_parameter_value {router_002} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {router_002} {PKT_TRANS_READ} {68};set_instance_parameter_value {router_002} {ST_DATA_W} {171};set_instance_parameter_value {router_002} {ST_CHANNEL_W} {2};set_instance_parameter_value {router_002} {DECODER_TYPE} {1};set_instance_parameter_value {router_002} {DEFAULT_CHANNEL} {-1};set_instance_parameter_value {router_002} {DEFAULT_WR_CHANNEL} {0};set_instance_parameter_value {router_002} {DEFAULT_RD_CHANNEL} {1};set_instance_parameter_value {router_002} {DEFAULT_DESTID} {0};set_instance_parameter_value {router_002} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {router_002} {MEMORY_ALIASING_DECODE} {0};set_instance_parameter_value {router_002} {HAS_USER_DEFAULT_SLAVE} {0};set_instance_parameter_value {router_002} {SYNC_RESET} {1};add_instance {subsys_periph_pb_cpu_0_s0_burst_adapter} {altera_merlin_burst_adapter};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_ADDR_H} {64};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_ADDR_L} {36};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BEGIN_BURST} {96};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTE_CNT_H} {81};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTE_CNT_L} {71};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTEEN_H} {35};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BYTEEN_L} {32};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_SIZE_H} {91};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_SIZE_L} {89};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_TYPE_H} {93};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURST_TYPE_L} {92};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_BURSTWRAP_L} {82};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_SAI_H} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_SAI_L} {133};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ROLE_BASED_USER} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ENABLE_AXI5} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_TRANS_COMPRESSED_READ} {65};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_TRANS_WRITE} {67};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_TRANS_READ} {68};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_NARROW_SIZE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {IN_NARROW_SIZE} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_FIXED} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_COMPLETE_WRAP} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_EOP_OOO} {89};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PKT_SOP_OOO} {90};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ENABLE_OOO} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ST_DATA_W} {171};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ST_CHANNEL_W} {2};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_BYTE_CNT_H} {73};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {OUT_BURSTWRAP_H} {88};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {COMPRESSED_READ_SUPPORT} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {BYTEENABLE_SYNTHESIS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {PIPE_INPUTS} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {NO_WRAP_SUPPORT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {INCOMPLETE_WRAP_SUPPORT} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {BURSTWRAP_CONST_MASK} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {BURSTWRAP_CONST_VALUE} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {ADAPTER_VERSION} {new};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter} {SYNC_RESET} {1};add_instance {cmd_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux} {ST_DATA_W} {171};set_instance_parameter_value {cmd_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cmd_demux} {SYNC_RESET} {1};add_instance {cmd_demux_001} {altera_merlin_demultiplexer};set_instance_parameter_value {cmd_demux_001} {ST_DATA_W} {171};set_instance_parameter_value {cmd_demux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_demux_001} {NUM_OUTPUTS} {1};set_instance_parameter_value {cmd_demux_001} {VALID_WIDTH} {1};set_instance_parameter_value {cmd_demux_001} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cmd_demux_001} {SYNC_RESET} {1};add_instance {cmd_mux} {altera_merlin_multiplexer};set_instance_parameter_value {cmd_mux} {ST_DATA_W} {171};set_instance_parameter_value {cmd_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {cmd_mux} {NUM_INPUTS} {2};set_instance_parameter_value {cmd_mux} {PIPELINE_ARB} {1};set_instance_parameter_value {cmd_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {cmd_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {cmd_mux} {ARBITRATION_SCHEME} {round-robin};set_instance_parameter_value {cmd_mux} {ARBITRATION_SHARES} {1 1 };set_instance_parameter_value {cmd_mux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {cmd_mux} {SYNC_RESET} {1};set_instance_parameter_value {cmd_mux} {ENABLE_OOO_CHUNKS} {0};set_instance_parameter_value {cmd_mux} {PKT_SOP_OOO} {135};set_instance_parameter_value {cmd_mux} {PKT_EOP_OOO} {134};add_instance {rsp_demux} {altera_merlin_demultiplexer};set_instance_parameter_value {rsp_demux} {ST_DATA_W} {171};set_instance_parameter_value {rsp_demux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_demux} {NUM_OUTPUTS} {2};set_instance_parameter_value {rsp_demux} {VALID_WIDTH} {1};set_instance_parameter_value {rsp_demux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {rsp_demux} {SYNC_RESET} {1};add_instance {rsp_mux} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux} {ST_DATA_W} {171};set_instance_parameter_value {rsp_mux} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {rsp_mux} {SYNC_RESET} {1};set_instance_parameter_value {rsp_mux} {ENABLE_OOO_CHUNKS} {0};set_instance_parameter_value {rsp_mux} {PKT_SOP_OOO} {135};set_instance_parameter_value {rsp_mux} {PKT_EOP_OOO} {134};add_instance {rsp_mux_001} {altera_merlin_multiplexer};set_instance_parameter_value {rsp_mux_001} {ST_DATA_W} {171};set_instance_parameter_value {rsp_mux_001} {ST_CHANNEL_W} {2};set_instance_parameter_value {rsp_mux_001} {NUM_INPUTS} {1};set_instance_parameter_value {rsp_mux_001} {PIPELINE_ARB} {0};set_instance_parameter_value {rsp_mux_001} {USE_EXTERNAL_ARB} {0};set_instance_parameter_value {rsp_mux_001} {PKT_TRANS_LOCK} {69};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SCHEME} {no-arb};set_instance_parameter_value {rsp_mux_001} {ARBITRATION_SHARES} {1 };set_instance_parameter_value {rsp_mux_001} {MERLIN_PACKET_FORMAT} {dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)};set_instance_parameter_value {rsp_mux_001} {SYNC_RESET} {1};set_instance_parameter_value {rsp_mux_001} {ENABLE_OOO_CHUNKS} {0};set_instance_parameter_value {rsp_mux_001} {PKT_SOP_OOO} {135};set_instance_parameter_value {rsp_mux_001} {PKT_EOP_OOO} {134};add_instance {agent_pipeline} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {agent_pipeline} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {agent_pipeline} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {agent_pipeline} {USE_PACKETS} {1};set_instance_parameter_value {agent_pipeline} {USE_EMPTY} {0};set_instance_parameter_value {agent_pipeline} {CHANNEL_WIDTH} {2};set_instance_parameter_value {agent_pipeline} {MAX_CHANNEL} {0};set_instance_parameter_value {agent_pipeline} {ERROR_WIDTH} {0};set_instance_parameter_value {agent_pipeline} {PIPELINE_READY} {1};set_instance_parameter_value {agent_pipeline} {SYNC_RESET} {1};add_instance {agent_pipeline_001} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {agent_pipeline_001} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {agent_pipeline_001} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {agent_pipeline_001} {USE_PACKETS} {1};set_instance_parameter_value {agent_pipeline_001} {USE_EMPTY} {0};set_instance_parameter_value {agent_pipeline_001} {CHANNEL_WIDTH} {0};set_instance_parameter_value {agent_pipeline_001} {MAX_CHANNEL} {0};set_instance_parameter_value {agent_pipeline_001} {ERROR_WIDTH} {0};set_instance_parameter_value {agent_pipeline_001} {PIPELINE_READY} {1};set_instance_parameter_value {agent_pipeline_001} {SYNC_RESET} {1};add_instance {mux_pipeline} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline} {SYNC_RESET} {1};add_instance {mux_pipeline_001} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline_001} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline_001} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline_001} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline_001} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline_001} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline_001} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline_001} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline_001} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline_001} {SYNC_RESET} {1};add_instance {mux_pipeline_002} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline_002} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline_002} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline_002} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline_002} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline_002} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline_002} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline_002} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline_002} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline_002} {SYNC_RESET} {1};add_instance {mux_pipeline_003} {altera_avalon_st_pipeline_stage};set_instance_parameter_value {mux_pipeline_003} {SYMBOLS_PER_BEAT} {1};set_instance_parameter_value {mux_pipeline_003} {BITS_PER_SYMBOL} {171};set_instance_parameter_value {mux_pipeline_003} {USE_PACKETS} {1};set_instance_parameter_value {mux_pipeline_003} {USE_EMPTY} {0};set_instance_parameter_value {mux_pipeline_003} {CHANNEL_WIDTH} {2};set_instance_parameter_value {mux_pipeline_003} {MAX_CHANNEL} {0};set_instance_parameter_value {mux_pipeline_003} {ERROR_WIDTH} {0};set_instance_parameter_value {mux_pipeline_003} {PIPELINE_READY} {1};set_instance_parameter_value {mux_pipeline_003} {SYNC_RESET} {1};add_instance {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {USE_RESET_REQUEST} {0};set_instance_parameter_value {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge} {SYNC_RESET} {1};add_instance {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {altera_reset_bridge};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {ACTIVE_LOW_RESET} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {SYNCHRONOUS_EDGES} {deassert};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {NUM_RESET_OUTPUTS} {1};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {USE_RESET_REQUEST} {0};set_instance_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge} {SYNC_RESET} {1};add_instance {clk_100_out_clk_clock_bridge} {altera_clock_bridge};set_instance_parameter_value {clk_100_out_clk_clock_bridge} {EXPLICIT_CLOCK_RATE} {100000000};set_instance_parameter_value {clk_100_out_clk_clock_bridge} {NUM_CLOCK_OUTPUTS} {1};add_connection {subsys_hps_lwhps2fpga_translator.m0} {subsys_hps_lwhps2fpga_agent.altera_axi_slave} {avalon};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {arbitrationPriority} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {baseAddress} {0x0000};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {defaultConnection} {false};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {domainAlias} {};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_translator.m0/subsys_hps_lwhps2fpga_agent.altera_axi_slave} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {rsp_mux.src} {subsys_hps_lwhps2fpga_agent.write_rp} {avalon_streaming};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_mux.src/subsys_hps_lwhps2fpga_agent.write_rp} {qsys_mm.response};add_connection {rsp_mux_001.src} {subsys_hps_lwhps2fpga_agent.read_rp} {avalon_streaming};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_mux_001.src/subsys_hps_lwhps2fpga_agent.read_rp} {qsys_mm.response};add_connection {subsys_periph_pb_cpu_0_s0_agent.m0} {subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {avalon};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {arbitrationPriority} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {baseAddress} {0x0000};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {defaultConnection} {false};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {domainAlias} {};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.m0/subsys_periph_pb_cpu_0_s0_translator.avalon_universal_slave_0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent.rf_source} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rf_source/subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.in} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out} {subsys_periph_pb_cpu_0_s0_agent.rf_sink} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rf_sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src} {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_src/subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.in} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out} {subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.out/subsys_periph_pb_cpu_0_s0_agent.rdata_fifo_sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};add_connection {subsys_hps_lwhps2fpga_agent.write_cp} {router.sink} {avalon_streaming};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_hps_lwhps2fpga_agent.write_cp/router.sink} {qsys_mm.command};add_connection {router.src} {cmd_demux.sink} {avalon_streaming};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {router.src/cmd_demux.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {router.src/cmd_demux.sink} {qsys_mm.command};add_connection {subsys_hps_lwhps2fpga_agent.read_cp} {router_001.sink} {avalon_streaming};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_hps_lwhps2fpga_agent.read_cp/router_001.sink} {qsys_mm.command};add_connection {router_001.src} {cmd_demux_001.sink} {avalon_streaming};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {router_001.src/cmd_demux_001.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {router_001.src/cmd_demux_001.sink} {qsys_mm.command};add_connection {router_002.src} {rsp_demux.sink} {avalon_streaming};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {router_002.src/rsp_demux.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {router_002.src/rsp_demux.sink} {qsys_mm.response};add_connection {cmd_mux.src} {subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {avalon_streaming};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {cmd_mux.src/subsys_periph_pb_cpu_0_s0_burst_adapter.sink0} {qsys_mm.command};add_connection {subsys_periph_pb_cpu_0_s0_burst_adapter.source0} {agent_pipeline.sink0} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_periph_pb_cpu_0_s0_burst_adapter.source0/agent_pipeline.sink0} {qsys_mm.command};add_connection {agent_pipeline.source0} {subsys_periph_pb_cpu_0_s0_agent.cp} {avalon_streaming};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {agent_pipeline.source0/subsys_periph_pb_cpu_0_s0_agent.cp} {qsys_mm.command};add_connection {subsys_periph_pb_cpu_0_s0_agent.rp} {agent_pipeline_001.sink0} {avalon_streaming};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {subsys_periph_pb_cpu_0_s0_agent.rp/agent_pipeline_001.sink0} {qsys_mm.response};add_connection {agent_pipeline_001.source0} {router_002.sink} {avalon_streaming};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {agent_pipeline_001.source0/router_002.sink} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {agent_pipeline_001.source0/router_002.sink} {qsys_mm.response};add_connection {cmd_demux.src0} {mux_pipeline.sink0} {avalon_streaming};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {cmd_demux.src0/mux_pipeline.sink0} {qsys_mm.command};add_connection {mux_pipeline.source0} {cmd_mux.sink0} {avalon_streaming};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline.source0/cmd_mux.sink0} {qsys_mm.command};add_connection {cmd_demux_001.src0} {mux_pipeline_001.sink0} {avalon_streaming};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {cmd_demux_001.src0/mux_pipeline_001.sink0} {qsys_mm.command};add_connection {mux_pipeline_001.source0} {cmd_mux.sink1} {avalon_streaming};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline_001.source0/cmd_mux.sink1} {qsys_mm.command};add_connection {rsp_demux.src0} {mux_pipeline_002.sink0} {avalon_streaming};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_demux.src0/mux_pipeline_002.sink0} {qsys_mm.response};add_connection {mux_pipeline_002.source0} {rsp_mux.sink0} {avalon_streaming};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline_002.source0/rsp_mux.sink0} {qsys_mm.response};add_connection {rsp_demux.src1} {mux_pipeline_003.sink0} {avalon_streaming};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {rsp_demux.src1/mux_pipeline_003.sink0} {qsys_mm.response};add_connection {mux_pipeline_003.source0} {rsp_mux_001.sink0} {avalon_streaming};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.piplineType} {PIPELINE_STAGE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableAllPipelines} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.maxAdditionalLatency} {1};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.clockCrossingAdapter} {AUTO};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.fifoDepth} {8};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.insertDefaultSlave} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableInstrumentation} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.interconnectResetSource} {DEFAULT};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.burstAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.widthAdapterImplementation} {GENERIC_CONVERTER};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableEccProtection} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.interconnectType} {STANDARD};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.syncResets} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.optimizeRdFifoSize} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.responseFifoType} {REGISTER_BASED};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.enableOutOfOrderSupport} {FALSE};set_connection_parameter_value {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.splitCommandsFor4KBoundary} {FALSE};preview_set_connection_tag {mux_pipeline_003.source0/rsp_mux_001.sink0} {qsys_mm.response};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_hps_lwhps2fpga_translator.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_translator.reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_hps_lwhps2fpga_agent.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_agent.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {router.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {router_001.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {router_002.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_burst_adapter.cr0_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {cmd_demux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {cmd_demux_001.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {cmd_mux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {rsp_demux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {rsp_mux.clk_reset} {reset};add_connection {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.out_reset} {rsp_mux_001.clk_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {agent_pipeline.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {agent_pipeline_001.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline_001.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline_002.cr0_reset} {reset};add_connection {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.out_reset} {mux_pipeline_003.cr0_reset} {reset};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_hps_lwhps2fpga_translator.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_translator.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_hps_lwhps2fpga_agent.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent_rdata_fifo.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {router.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {router_001.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {router_002.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_burst_adapter.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {cmd_demux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {rsp_mux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {cmd_demux_001.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {rsp_mux_001.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {cmd_mux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {rsp_demux.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {agent_pipeline.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {agent_pipeline_001.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline_001.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline_002.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {mux_pipeline_003.cr0} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.clk} {clock};add_connection {clk_100_out_clk_clock_bridge.out_clk} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.clk} {clock};add_interface {subsys_hps_lwhps2fpga} {axi4} {slave};set_interface_property {subsys_hps_lwhps2fpga} {EXPORT_OF} {subsys_hps_lwhps2fpga_translator.s0};add_interface {subsys_periph_pb_cpu_0_s0} {avalon} {master};set_interface_property {subsys_periph_pb_cpu_0_s0} {EXPORT_OF} {subsys_periph_pb_cpu_0_s0_translator.avalon_anti_slave_0};add_interface {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge_in_reset} {EXPORT_OF} {subsys_hps_lwhps2fpga_translator_clk_reset_reset_bridge.in_reset};add_interface {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset} {reset} {slave};set_interface_property {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge_in_reset} {EXPORT_OF} {subsys_periph_pb_cpu_0_s0_agent_rsp_fifo_clk_reset_reset_bridge.in_reset};add_interface {clk_100_out_clk} {clock} {slave};set_interface_property {clk_100_out_clk} {EXPORT_OF} {clk_100_out_clk_clock_bridge.in_clk};set_module_assignment {interconnect_id.subsys_hps.lwhps2fpga} {0};set_module_assignment {interconnect_id.subsys_periph.pb_cpu_0_s0} {0};" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_mm_interconnect_1920/synth/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_mm_interconnect_1920/synth/qsys_top_altera_mm_interconnect_1920_ykfyxdi.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_mm_interconnect/altera_mm_interconnect_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_axi_translator/altera_merlin_axi_translator_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_axi_master_ni/altera_merlin_axi_master_ni_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
   <file
       path="/opt/altera_pro/26.1/ip/altera/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_hw.tcl" />
  </childSourceFiles>
  <instantiator instantiator="qsys_top" as="mm_interconnect_0" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_mm_interconnect_1920_ykfyxdi"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_axi_translator_1987_lty7xoq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_slave_translator_191_xg7rzxi"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_axi_master_ni_19117_qautany"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_slave_agent_1930_jxauz3i"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_avalon_sc_fifo_1932_22gxxgi"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_router_1921_ox5xuhq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_router_1921_sxavatq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy"</message>
   <message level="Info" culprit="my_altera_avalon_st_pipeline_stage">"Generating: my_altera_avalon_st_pipeline_stage"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_multiplexer_1922_666s25q"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_demultiplexer_1921_qyizksq"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_multiplexer_1922_yjgptii"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq"</message>
  </messages>
 </entity>
 <entity
   kind="altera_irq_mapper"
   version="20.0.1"
   name="qsys_top_altera_irq_mapper_2001_lp4cnei">
  <parameter name="NUM_RCVRS" value="2" />
  <parameter name="REMOVE_CLK_RST" value="0" />
  <parameter name="IRQ_MAP" value="0:1,1:0" />
  <parameter name="AUTO_DEVICE_FAMILY" value="Agilex 5" />
  <parameter name="SYNC_RESET" value="0" />
  <parameter name="SENDER_IRQ_WIDTH" value="32" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_irq_mapper_2001/synth/qsys_top_altera_irq_mapper_2001_lp4cnei.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_irq_mapper_2001/synth/qsys_top_altera_irq_mapper_2001_lp4cnei.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_irq_mapper/altera_irq_mapper_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="qsys_top" as="irq_mapper" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_irq_mapper_2001_lp4cnei"</message>
  </messages>
 </entity>
 <entity
   kind="altera_reset_controller"
   version="19.2.4"
   name="altera_reset_controller">
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_reset_controller_1924/synth/altera_reset_controller.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_reset_controller_1924/synth/altera_reset_synchronizer.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_reset_controller_1924/synth/altera_reset_controller.sdc"
       attributes="NO_SDC_PROMOTION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_reset_controller_1924/synth/altera_reset_controller.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_reset_controller_1924/synth/altera_reset_synchronizer.v"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_reset_controller_1924/synth/altera_reset_controller.sdc"
       attributes="NO_SDC_PROMOTION" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_reset_controller/altera_reset_controller_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator instantiator="qsys_top" as="rst_controller" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: altera_reset_controller"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_axi_translator"
   version="19.8.7"
   name="qsys_top_altera_merlin_axi_translator_1987_lty7xoq">
  <parameter name="M0_LOCK_WIDTH" value="1" />
  <parameter name="IS_TRANSLATOR" value="1" />
  <parameter name="TERMINATE_READ_CHANNEL" value="0" />
  <parameter name="M0_BURST_LENGTH_WIDTH" value="8" />
  <parameter name="S0_BURST_LENGTH_WIDTH" value="8" />
  <parameter name="S0_AWSNOOP_WIDTH" value="3" />
  <parameter name="TERMINATE_WRITE_CHANNEL" value="0" />
  <parameter name="S0_LOCK_WIDTH" value="1" />
  <parameter name="M0_AWSNOOP_WIDTH" value="3" />
  <parameter name="ENABLE_AXI5" value="0" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_axi_translator_1987/synth/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_axi_translator_1987/synth/qsys_top_altera_merlin_axi_translator_1987_lty7xoq.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_axi_translator/altera_merlin_axi_translator_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="subsys_hps_lwhps2fpga_translator" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_axi_translator_1987_lty7xoq"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_slave_translator"
   version="19.1"
   name="qsys_top_altera_merlin_slave_translator_191_xg7rzxi">
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_slave_translator_191/synth/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_slave_translator_191/synth/qsys_top_altera_merlin_slave_translator_191_xg7rzxi.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_slave_translator/altera_merlin_slave_translator_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="subsys_periph_pb_cpu_0_s0_translator" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_slave_translator_191_xg7rzxi"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_axi_master_ni"
   version="19.11.7"
   name="qsys_top_altera_merlin_axi_master_ni_19117_qautany">
  <parameter name="RESP_USER_WIDTH" value="8" />
  <parameter name="ENABLE_AXI5" value="0" />
  <parameter name="DATA_USER_WIDTH" value="1" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_axi_master_ni_19117/synth/altera_merlin_address_alignment.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_axi_master_ni_19117/synth/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_axi_master_ni_19117/synth/altera_merlin_address_alignment.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_axi_master_ni_19117/synth/qsys_top_altera_merlin_axi_master_ni_19117_qautany.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_axi_master_ni/altera_merlin_axi_master_ni_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="subsys_hps_lwhps2fpga_agent" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_axi_master_ni_19117_qautany"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_slave_agent"
   version="19.3.0"
   name="qsys_top_altera_merlin_slave_agent_1930_jxauz3i">
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_slave_agent_1930/synth/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_slave_agent_1930/synth/qsys_top_altera_merlin_slave_agent_1930_jxauz3i.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_slave_agent_1930/synth/altera_merlin_burst_uncompressor.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_slave_agent/altera_merlin_slave_agent_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="subsys_periph_pb_cpu_0_s0_agent" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_slave_agent_1930_jxauz3i"</message>
  </messages>
 </entity>
 <entity
   kind="altera_avalon_sc_fifo"
   version="19.3.2"
   name="qsys_top_altera_avalon_sc_fifo_1932_22gxxgi">
  <parameter name="EXPLICIT_MAXCHANNEL" value="0" />
  <parameter name="EMPTY_WIDTH" value="1" />
  <parameter name="SYNC_RESET" value="1" />
  <parameter name="ENABLE_EXPLICIT_MAXCHANNEL" value="false" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_avalon_sc_fifo_1932/synth/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_avalon_sc_fifo_1932/synth/qsys_top_altera_avalon_sc_fifo_1932_22gxxgi.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/sopc_builder_ip/altera_avalon_sc_fifo/altera_avalon_sc_fifo_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="subsys_periph_pb_cpu_0_s0_agent_rsp_fifo,subsys_periph_pb_cpu_0_s0_agent_rdata_fifo" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_avalon_sc_fifo_1932_22gxxgi"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_router"
   version="19.2.1"
   name="qsys_top_altera_merlin_router_1921_ox5xuhq">
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="DEFAULT_WR_CHANNEL" value="-1" />
  <parameter name="PKT_TRANS_READ" value="68" />
  <parameter name="START_ADDRESS" value="0x0" />
  <parameter name="DEFAULT_CHANNEL" value="0" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter name="HAS_USER_DEFAULT_SLAVE" value="0" />
  <parameter name="SLAVES_INFO" value="0:1:0x0:0x20000:both:1:0:0:1" />
  <parameter name="DEFAULT_RD_CHANNEL" value="-1" />
  <parameter name="PKT_ADDR_H" value="64" />
  <parameter name="PKT_DEST_ID_H" value="102" />
  <parameter name="PKT_ADDR_L" value="36" />
  <parameter name="PKT_DEST_ID_L" value="102" />
  <parameter name="CHANNEL_ID" value="1" />
  <parameter name="TYPE_OF_TRANSACTION" value="both" />
  <parameter name="SECURED_RANGE_PAIRS" value="0" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="ST_DATA_W" value="171" />
  <parameter name="SECURED_RANGE_LIST" value="0" />
  <parameter name="DECODER_TYPE" value="0" />
  <parameter name="PKT_PROTECTION_H" value="109" />
  <parameter name="END_ADDRESS" value="0x20000" />
  <parameter name="PKT_PROTECTION_L" value="107" />
  <parameter name="PKT_TRANS_WRITE" value="67" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="DESTINATION_ID" value="0" />
  <parameter name="NON_SECURED_TAG" value="1" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_router_1921/synth/qsys_top_altera_merlin_router_1921_ox5xuhq.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_router_1921/synth/qsys_top_altera_merlin_router_1921_ox5xuhq.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="router,router_001" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_router_1921_ox5xuhq"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_router"
   version="19.2.1"
   name="qsys_top_altera_merlin_router_1921_sxavatq">
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="DEFAULT_WR_CHANNEL" value="0" />
  <parameter name="PKT_TRANS_READ" value="68" />
  <parameter name="START_ADDRESS" value="0x0,0x0" />
  <parameter name="DEFAULT_CHANNEL" value="-1" />
  <parameter name="MEMORY_ALIASING_DECODE" value="0" />
  <parameter name="HAS_USER_DEFAULT_SLAVE" value="0" />
  <parameter
     name="SLAVES_INFO"
     value="0:01:0x0:0x0:write:1:0:0:1,0:10:0x0:0x0:read:1:0:0:1" />
  <parameter name="DEFAULT_RD_CHANNEL" value="1" />
  <parameter name="PKT_ADDR_H" value="64" />
  <parameter name="PKT_DEST_ID_H" value="102" />
  <parameter name="PKT_ADDR_L" value="36" />
  <parameter name="PKT_DEST_ID_L" value="102" />
  <parameter name="CHANNEL_ID" value="01,10" />
  <parameter name="TYPE_OF_TRANSACTION" value="write,read" />
  <parameter name="SECURED_RANGE_PAIRS" value="0,0" />
  <parameter name="SPAN_OFFSET" value="" />
  <parameter name="ST_DATA_W" value="171" />
  <parameter name="SECURED_RANGE_LIST" value="0,0" />
  <parameter name="DECODER_TYPE" value="1" />
  <parameter name="PKT_PROTECTION_H" value="109" />
  <parameter name="END_ADDRESS" value="0x0,0x0" />
  <parameter name="PKT_PROTECTION_L" value="107" />
  <parameter name="PKT_TRANS_WRITE" value="67" />
  <parameter name="DEFAULT_DESTID" value="0" />
  <parameter name="DESTINATION_ID" value="0,0" />
  <parameter name="NON_SECURED_TAG" value="1,1" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_router_1921/synth/qsys_top_altera_merlin_router_1921_sxavatq.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_router_1921/synth/qsys_top_altera_merlin_router_1921_sxavatq.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_router/altera_merlin_router_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="router_002" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_router_1921_sxavatq"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_burst_adapter"
   version="19.4.0"
   name="qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy">
  <parameter name="PKT_SAI_L" value="133" />
  <parameter
     name="MERLIN_PACKET_FORMAT"
     value="dataless(170) mmusecsid(169) mmusid(168) awstashlpiden(167) awstashlpid(166:162) awstashniden(161) awstashnid(160:150) awatop(149:144) awakeup(143) trace(142) atrace(141) trans_seq(140:136) sop_ooo(135) eop_ooo(134) sai(133) addrchk(132:131) user_data(130) datachk(129) poison(128) wunique(127) domain(126:125) snoop(124:121) barrier(120:119) ori_burst_size(118:116) response_status(115:114) cache(113:110) protection(109:107) thread_id(106:103) dest_id(102) src_id(101) qos(100:97) begin_burst(96) data_sideband(95) addr_sideband(94) burst_type(93:92) burst_size(91:89) burstwrap(88:82) byte_cnt(81:71) trans_exclusive(70) trans_lock(69) trans_read(68) trans_write(67) trans_posted(66) trans_compressed_read(65) addr(64:36) byteen(35:32) data(31:0)" />
  <parameter name="PKT_TRANS_COMPRESSED_READ" value="65" />
  <parameter name="ENABLE_OOO" value="0" />
  <parameter name="PKT_SAI_H" value="133" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_uncmpr.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_13_1.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_new.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_incr_burst_converter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_wrap_burst_converter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_default_burst_converter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_address_alignment.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_uncmpr.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_13_1.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_burst_adapter_new.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_incr_burst_converter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_wrap_burst_converter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_default_burst_converter.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/altera_merlin_address_alignment.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_burst_adapter/altera_merlin_burst_adapter_hw.tcl" />
  </sourceFiles>
  <childSourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_hw.tcl" />
  </childSourceFiles>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="subsys_periph_pb_cpu_0_s0_burst_adapter" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy"</message>
   <message level="Info" culprit="my_altera_avalon_st_pipeline_stage">"Generating: my_altera_avalon_st_pipeline_stage"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_demultiplexer"
   version="19.2.1"
   name="qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q">
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="VALID_WIDTH" value="1" />
  <parameter name="ST_DATA_W" value="171" />
  <parameter name="NUM_OUTPUTS" value="1" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="cmd_demux,cmd_demux_001" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_demultiplexer_1921_2v2lw6q"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_multiplexer"
   version="19.2.2"
   name="qsys_top_altera_merlin_multiplexer_1922_666s25q">
  <parameter name="PKT_EOP_OOO" value="134" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="ARBITRATION_SHARES" value="1,1" />
  <parameter name="NUM_INPUTS" value="2" />
  <parameter name="PIPELINE_ARB" value="1" />
  <parameter name="ARBITRATION_SCHEME" value="round-robin" />
  <parameter name="ST_DATA_W" value="171" />
  <parameter name="PKT_SOP_OOO" value="135" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="PKT_TRANS_LOCK" value="69" />
  <parameter name="SYNC_RESET" value="1" />
  <parameter name="ENABLE_OOO_CHUNKS" value="0" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_666s25q.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="cmd_mux" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_multiplexer_1922_666s25q"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_demultiplexer"
   version="19.2.1"
   name="qsys_top_altera_merlin_demultiplexer_1921_qyizksq">
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="VALID_WIDTH" value="1" />
  <parameter name="ST_DATA_W" value="171" />
  <parameter name="NUM_OUTPUTS" value="2" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_demultiplexer_1921/synth/qsys_top_altera_merlin_demultiplexer_1921_qyizksq.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_demultiplexer/altera_merlin_demultiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="rsp_demux" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_demultiplexer_1921_qyizksq"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_multiplexer"
   version="19.2.2"
   name="qsys_top_altera_merlin_multiplexer_1922_yjgptii">
  <parameter name="PKT_EOP_OOO" value="134" />
  <parameter name="ST_CHANNEL_W" value="2" />
  <parameter name="ARBITRATION_SHARES" value="1" />
  <parameter name="NUM_INPUTS" value="1" />
  <parameter name="PIPELINE_ARB" value="0" />
  <parameter name="ARBITRATION_SCHEME" value="no-arb" />
  <parameter name="ST_DATA_W" value="171" />
  <parameter name="PKT_SOP_OOO" value="135" />
  <parameter name="USE_EXTERNAL_ARB" value="0" />
  <parameter name="PKT_TRANS_LOCK" value="69" />
  <parameter name="SYNC_RESET" value="1" />
  <parameter name="ENABLE_OOO_CHUNKS" value="0" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_multiplexer_1922/synth/qsys_top_altera_merlin_multiplexer_1922_yjgptii.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_multiplexer_1922/synth/altera_merlin_arbitrator.sv"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/merlin/altera_merlin_multiplexer/altera_merlin_multiplexer_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="rsp_mux,rsp_mux_001" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_multiplexer_1922_yjgptii"</message>
  </messages>
 </entity>
 <entity
   kind="altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage"
   version="19.4.0"
   name="qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di">
  <parameter name="USE_EMPTY" value="0" />
  <parameter name="PACKET_WIDTH" value="2" />
  <parameter name="USE_PACKETS" value="1" />
  <parameter name="SYMBOLS_PER_BEAT" value="1" />
  <parameter name="BITS_PER_SYMBOL" value="171" />
  <parameter name="MAX_CHANNEL" value="0" />
  <parameter name="ERROR_WIDTH" value="0" />
  <parameter name="EMPTY_WIDTH" value="0" />
  <parameter name="PIPELINE_READY" value="1" />
  <parameter name="CHANNEL_WIDTH" value="2" />
  <parameter name="SYNC_RESET" value="1" />
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_merlin_burst_adapter_1940/synth/qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di.v"
       attributes="CONTAINS_INLINE_CONFIGURATION" />
  </childGeneratedFiles>
  <sourceFiles/>
  <childSourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_hw.tcl" />
  </childSourceFiles>
  <instantiator
     instantiator="qsys_top_altera_merlin_burst_adapter_1940_6zvwdfy"
     as="my_altera_avalon_st_pipeline_stage" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di"</message>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq"</message>
  </messages>
 </entity>
 <entity
   kind="altera_avalon_st_pipeline_stage"
   version="19.3.0"
   name="qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq">
  <generatedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_avalon_st_pipeline_stage_1930/synth/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_avalon_st_pipeline_stage_1930/synth/altera_avalon_st_pipeline_base.v"
       attributes="" />
  </generatedFiles>
  <childGeneratedFiles>
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_avalon_st_pipeline_stage_1930/synth/qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq.sv"
       attributes="" />
   <file
       path="/home/ubuntu/FPGA_Projects/retroDE_ps2/synth/de25_nano/top_psmct32_raster_demo/qsys/qsys_top/altera_avalon_st_pipeline_stage_1930/synth/altera_avalon_st_pipeline_base.v"
       attributes="" />
  </childGeneratedFiles>
  <sourceFiles>
   <file
       path="/opt/altera_pro/26.1/ip/altera/avalon_st/altera_avalon_st_pipeline_stage/altera_avalon_st_pipeline_stage_hw.tcl" />
  </sourceFiles>
  <childSourceFiles/>
  <instantiator
     instantiator="qsys_top_altera_mm_interconnect_1920_ykfyxdi"
     as="agent_pipeline,agent_pipeline_001,mux_pipeline,mux_pipeline_001,mux_pipeline_002,mux_pipeline_003" />
  <instantiator
     instantiator="qsys_top_altera_merlin_burst_adapter_altera_avalon_st_pipeline_stage_1940_ykdw6di"
     as="my_altera_avalon_st_pipeline_stage" />
  <messages>
   <message level="Info" culprit="qsys_top">"Generating: qsys_top_altera_avalon_st_pipeline_stage_1930_oiupeiq"</message>
  </messages>
 </entity>
</deploy>
