// retroDE_ps2 — tb_ee_core_psubb
//
// Ch280 — Focused TB for R5900 EE MMI0/PSUBB (Parallel Subtract
// Byte). Primary opcode 0x1C, funct 0x08 (MMI0), sa 0x09 (PSUBB).
// qbert.elf hits `psubb $v0, $t1, $t2` (instr 0x712A1248) at PC
// 0x00112C90.
//
// In our 32-bit GPR model: 4 parallel byte subtracts on the low
// 32 bits, no carry/borrow between byte lanes.
//
//   rd[ 7: 0] = rs[ 7: 0] - rt[ 7: 0]
//   rd[15: 8] = rs[15: 8] - rt[15: 8]
//   rd[23:16] = rs[23:16] - rt[23:16]
//   rd[31:24] = rs[31:24] - rt[31:24]
//
// Cases:
//   1. Exact qbert encoding: enc_rtype shape asserted == 0x712A1248.
//   2. Distinct lane sub: 0x10203040 - 0x01020304 = 0x0F1E2D3C.
//   3. Wrap-all: 0x00000000 - 0x01020304 = 0xFFFEFDFC (each lane
//      underflows independently).
//   4. No cross-byte borrow: 0x12345600 - 0x00000001 = 0x123456FF
//      (low byte borrows but it MUST NOT propagate up to byte 1).
//
// Strict mode ON.

`timescale 1ns/1ps

module tb_ee_core_psubb;

    localparam int BIOS_BYTES    = 4 * 1024 * 1024;
    localparam int EE_RAM_BYTES  = 4 * 1024;
    localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);

    localparam logic [31:0] RESET_VECTOR   = 32'hBFC0_0000;
    localparam logic [31:0] BOOTSTRAP_VA   = 32'hBFC0_0100;
    localparam int          RESET_SLOT     = 0;
    localparam int          BOOTSTRAP_SLOT = 32'h100 >> 2;

    // ---- Slots ----
    // Case 1: $t1 = 0x10203040; $t2 = 0x01020304; psubb $v0,$t1,$t2 → 0x0F1E2D3C
    localparam int B_LUI_T1A    = BOOTSTRAP_SLOT + 0;
    localparam int B_ORI_T1A    = BOOTSTRAP_SLOT + 1;
    localparam int B_LUI_T2A    = BOOTSTRAP_SLOT + 2;
    localparam int B_ORI_T2A    = BOOTSTRAP_SLOT + 3;
    localparam int B_PSUBB_A    = BOOTSTRAP_SLOT + 4;   // qbert encoding
    localparam int B_LUI_TMP_A  = BOOTSTRAP_SLOT + 5;
    localparam int B_ORI_TMP_A  = BOOTSTRAP_SLOT + 6;
    localparam int B_BNE_A      = BOOTSTRAP_SLOT + 7;
    localparam int B_DS_A       = BOOTSTRAP_SLOT + 8;

    // Case 2: $t3 = 0x00000000; $t4 = 0x01020304; psubb $t5,$t3,$t4 → 0xFFFEFDFC
    localparam int B_ORI_T3_0   = BOOTSTRAP_SLOT + 9;
    localparam int B_LUI_T4     = BOOTSTRAP_SLOT + 10;
    localparam int B_ORI_T4     = BOOTSTRAP_SLOT + 11;
    localparam int B_PSUBB_B    = BOOTSTRAP_SLOT + 12;
    localparam int B_LUI_TMP_B  = BOOTSTRAP_SLOT + 13;
    localparam int B_ORI_TMP_B  = BOOTSTRAP_SLOT + 14;
    localparam int B_BNE_B      = BOOTSTRAP_SLOT + 15;
    localparam int B_DS_B       = BOOTSTRAP_SLOT + 16;

    // Case 3: no cross-byte borrow. $t6=0x12345600; $t7=0x00000001 → $t8=0x123456FF
    localparam int B_LUI_T6     = BOOTSTRAP_SLOT + 17;
    localparam int B_ORI_T6     = BOOTSTRAP_SLOT + 18;
    localparam int B_ORI_T7_1   = BOOTSTRAP_SLOT + 19;
    localparam int B_PSUBB_C    = BOOTSTRAP_SLOT + 20;
    localparam int B_LUI_TMP_C  = BOOTSTRAP_SLOT + 21;
    localparam int B_ORI_TMP_C  = BOOTSTRAP_SLOT + 22;
    localparam int B_BNE_C      = BOOTSTRAP_SLOT + 23;
    localparam int B_DS_C       = BOOTSTRAP_SLOT + 24;

    localparam int B_PASS       = BOOTSTRAP_SLOT + 25;
    localparam int B_FAIL       = BOOTSTRAP_SLOT + 26;

    localparam logic [5:0] OP_J     = 6'h02;
    localparam logic [5:0] OP_BNE   = 6'h05;
    localparam logic [5:0] OP_ORI   = 6'h0D;
    localparam logic [5:0] OP_LUI   = 6'h0F;
    localparam logic [5:0] OP_MMI   = 6'h1C;
    localparam logic [5:0] FUNC_MMI0 = 6'h08;
    localparam logic [4:0] SA_PSUBB  = 5'h09;

    // GPRs
    localparam int RV0 = 2;
    localparam int RT1 = 9;
    localparam int RT2 = 10;
    localparam int RT3 = 11;
    localparam int RT4 = 12;
    localparam int RT5 = 13;
    localparam int RT6 = 14;
    localparam int RT7 = 15;
    localparam int RT8 = 24;
    localparam int RTMP = 25;

    logic clk, rst_n;
    initial clk = 1'b0;
    always #5 clk = ~clk;

    // ----- EE core -----
    logic        core_go, core_halt, core_trap;
    logic [31:0] core_pc, core_trap_pc, core_trap_instr;
    logic        ee_rd_en, ee_rd_valid, ee_wr_en;
    logic [31:0] ee_rd_addr, ee_rd_data, ee_wr_addr, ee_wr_data;
    logic [3:0]  ee_wr_be;

    logic                core_ev_valid;
    trace_pkg::subsys_e  core_ev_subsys;
    trace_pkg::event_e   core_ev_event;
    logic [63:0]         core_ev_arg0, core_ev_arg1, core_ev_arg2, core_ev_arg3;
    logic [31:0]         core_ev_flags;

    ee_core_stub #(.STRICT_UNSUPPORTED(1'b1)) u_core (
        .clk(clk), .rst_n(rst_n), .go_i(core_go),
        .map_rd_en(ee_rd_en), .map_rd_addr(ee_rd_addr),
        .map_rd_data(ee_rd_data), .map_rd_valid(ee_rd_valid),
        .map_wr_en(ee_wr_en), .map_wr_addr(ee_wr_addr),
        .map_wr_data(ee_wr_data), .map_wr_be(ee_wr_be),
        .cpu_irq(1'b0),
        .halt_o(core_halt), .pc_o(core_pc),
        .trap_o(core_trap), .trap_pc_o(core_trap_pc),
        .trap_instr_o(core_trap_instr),
        .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
        .ev_event(core_ev_event),
        .ev_arg0(core_ev_arg0), .ev_arg1(core_ev_arg1),
        .ev_arg2(core_ev_arg2), .ev_arg3(core_ev_arg3),
        .ev_flags(core_ev_flags)
    );

    // ----- Map + RAM + BIOS -----
    logic         bios_rd_en, bios_rd_valid;
    logic [21:0]  bios_rd_addr;
    logic [31:0]  bios_rd_data;
    logic         ee_ram_rd_en, ee_ram_rd_valid, ee_ram_wr_en;
    logic [24:0]  ee_ram_rd_addr, ee_ram_wr_addr;
    logic [127:0] ee_ram_rd_data, ee_ram_wr_data;
    logic [15:0]  ee_ram_wr_be;
    logic [7:0]   ee_ram_master_id;

    ee_memory_map_stub u_ee_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
        .ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
        .ee_wr_en(ee_wr_en), .ee_wr_addr(ee_wr_addr),
        .ee_wr_data(ee_wr_data), .ee_wr_be(ee_wr_be),
        .dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
        .dmac_rd_data(), .dmac_rd_valid(),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .bios_rd_en(bios_rd_en), .bios_rd_addr(bios_rd_addr),
        .bios_rd_data(bios_rd_data), .bios_rd_valid(bios_rd_valid),
        .ram_rd_en(ee_ram_rd_en), .ram_rd_addr(ee_ram_rd_addr),
        .ram_rd_data(ee_ram_rd_data), .ram_rd_valid(ee_ram_rd_valid),
        .ram_wr_en(ee_ram_wr_en), .ram_wr_addr(ee_ram_wr_addr),
        .ram_wr_data(ee_ram_wr_data), .ram_wr_be(ee_ram_wr_be),
        .ram_master_id(ee_ram_master_id),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ee_ram_rd_en), .rd_addr(ee_ram_rd_addr[EE_RAM_ADDR_W-1:0]),
        .rd_data(ee_ram_rd_data), .rd_valid(ee_ram_rd_valid),
        .wr_en(ee_ram_wr_en), .wr_addr(ee_ram_wr_addr[EE_RAM_ADDR_W-1:0]),
        .wr_data(ee_ram_wr_data), .wr_be(ee_ram_wr_be),
        .master_id(ee_ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    bios_rom_stub #(.SIZE_BYTES(BIOS_BYTES)) u_bios (
        .clk(clk), .rst_n(rst_n),
        .rd_en(bios_rd_en), .rd_addr(bios_rd_addr),
        .rd_data(bios_rd_data), .rd_valid(bios_rd_valid),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("ee_core_psubb_core.trace"), .SINK_LABEL("ee_core"))
        u_trace_core (.clk(clk), .rst_n(rst_n),
            .ev_valid(core_ev_valid), .ev_subsys(core_ev_subsys),
            .ev_event(core_ev_event), .ev_arg0(core_ev_arg0),
            .ev_arg1(core_ev_arg1), .ev_arg2(core_ev_arg2),
            .ev_arg3(core_ev_arg3), .ev_flags(core_ev_flags));

    int core_retired_events, core_halt_events, core_trap_events, errors;
    initial begin
        core_retired_events = 0; core_halt_events = 0;
        core_trap_events = 0; errors = 0;
    end
    always_ff @(posedge clk) begin
        if (rst_n && core_ev_valid) begin
            core_retired_events <= core_retired_events + 1;
            if ((core_ev_flags & 32'h08) != 32'd0) core_halt_events <= core_halt_events + 1;
            if ((core_ev_flags & 32'h80) != 32'd0) core_trap_events <= core_trap_events + 1;
        end
    end

    task automatic bios_word(input int slot, input logic [31:0] word);
        u_bios.mem[slot] = word;
    endtask
    function automatic logic [31:0] enc_i(input logic [5:0] op,
                                          input int rs, input int rt,
                                          input logic [15:0] imm);
        return {op, rs[4:0], rt[4:0], imm};
    endfunction
    function automatic logic [31:0] enc_j(input logic [31:0] target_addr);
        return {OP_J, target_addr[27:2]};
    endfunction
    function automatic logic [31:0] enc_rtype(input logic [5:0] op,
                                              input int rs, input int rt,
                                              input int rd, input int sa,
                                              input logic [5:0] funct);
        return {op, rs[4:0], rt[4:0], rd[4:0], sa[4:0], funct};
    endfunction
    function automatic logic [15:0] branch_imm(input int branch_slot,
                                               input int target_slot);
        int diff;
        diff = target_slot - branch_slot - 1;
        return diff[15:0];
    endfunction

    initial begin
        logic [31:0] qbert_psubb_raw;

        rst_n = 1'b0; core_go = 1'b0;
        repeat (4) @(posedge clk);
        rst_n = 1'b1;
        repeat (2) @(posedge clk);

        bios_word(RESET_SLOT,     enc_j(BOOTSTRAP_VA));
        bios_word(RESET_SLOT + 1, 32'd0);

        // ===== Case 1: distinct lanes (qbert encoding shape) =====
        // $t1 = 0x10203040; $t2 = 0x01020304; psubb $v0,$t1,$t2 → 0x0F1E2D3C
        bios_word(B_LUI_T1A, enc_i(OP_LUI, 0, RT1, 16'h1020));
        bios_word(B_ORI_T1A, enc_i(OP_ORI, RT1, RT1, 16'h3040));
        bios_word(B_LUI_T2A, enc_i(OP_LUI, 0, RT2, 16'h0102));
        bios_word(B_ORI_T2A, enc_i(OP_ORI, RT2, RT2, 16'h0304));
        // qbert exact encoding shape (rs=$t1=9, rt=$t2=10, rd=$v0=2)
        qbert_psubb_raw = enc_rtype(OP_MMI, RT1, RT2, RV0, SA_PSUBB, FUNC_MMI0);
        if (qbert_psubb_raw !== 32'h712A_1248) begin
            $error("[tb_ee_core_psubb] enc_rtype mismatch: produced 0x%08h, expected 0x712A1248",
                   qbert_psubb_raw);
            errors = errors + 1;
        end
        bios_word(B_PSUBB_A, qbert_psubb_raw);
        // Verify $v0 == 0x0F1E2D3C
        bios_word(B_LUI_TMP_A, enc_i(OP_LUI, 0, RTMP, 16'h0F1E));
        bios_word(B_ORI_TMP_A, enc_i(OP_ORI, RTMP, RTMP, 16'h2D3C));
        bios_word(B_BNE_A,     enc_i(OP_BNE, RV0, RTMP, branch_imm(B_BNE_A, B_FAIL)));
        bios_word(B_DS_A,      32'd0);

        // ===== Case 2: all-wrap. $t3=0; $t4=0x01020304 → $t5=0xFFFEFDFC
        bios_word(B_ORI_T3_0,  enc_i(OP_ORI, 0, RT3, 16'h0000));
        bios_word(B_LUI_T4,    enc_i(OP_LUI, 0, RT4, 16'h0102));
        bios_word(B_ORI_T4,    enc_i(OP_ORI, RT4, RT4, 16'h0304));
        bios_word(B_PSUBB_B,   enc_rtype(OP_MMI, RT3, RT4, RT5, SA_PSUBB, FUNC_MMI0));
        bios_word(B_LUI_TMP_B, enc_i(OP_LUI, 0, RTMP, 16'hFFFE));
        bios_word(B_ORI_TMP_B, enc_i(OP_ORI, RTMP, RTMP, 16'hFDFC));
        bios_word(B_BNE_B,     enc_i(OP_BNE, RT5, RTMP, branch_imm(B_BNE_B, B_FAIL)));
        bios_word(B_DS_B,      32'd0);

        // ===== Case 3: no cross-byte borrow. $t6=0x12345600; $t7=0x00000001 → $t8=0x123456FF
        bios_word(B_LUI_T6,    enc_i(OP_LUI, 0, RT6, 16'h1234));
        bios_word(B_ORI_T6,    enc_i(OP_ORI, RT6, RT6, 16'h5600));
        bios_word(B_ORI_T7_1,  enc_i(OP_ORI, 0, RT7, 16'h0001));
        bios_word(B_PSUBB_C,   enc_rtype(OP_MMI, RT6, RT7, RT8, SA_PSUBB, FUNC_MMI0));
        bios_word(B_LUI_TMP_C, enc_i(OP_LUI, 0, RTMP, 16'h1234));
        bios_word(B_ORI_TMP_C, enc_i(OP_ORI, RTMP, RTMP, 16'h56FF));
        bios_word(B_BNE_C,     enc_i(OP_BNE, RT8, RTMP, branch_imm(B_BNE_C, B_FAIL)));
        bios_word(B_DS_C,      32'd0);

        bios_word(B_PASS, 32'h0000_000C);
        bios_word(B_FAIL, 32'h0000_000C);

        @(negedge clk); core_go = 1'b1;
        @(negedge clk); core_go = 1'b0;

        while (!core_halt) @(posedge clk);
        repeat (4) @(posedge clk);

        // ---- Checks ----
        if (core_trap_events != 0) begin
            $error("[tb_ee_core_psubb] unexpected trap: %0d pc=0x%08h instr=0x%08h",
                   core_trap_events, core_trap_pc, core_trap_instr);
            errors = errors + 1;
        end
        if (core_halt_events != 1) begin
            $error("[tb_ee_core_psubb] expected 1 halt, got %0d", core_halt_events);
            errors = errors + 1;
        end
        if (core_pc !== BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2)) begin
            $error("[tb_ee_core_psubb] final pc mismatch: got 0x%08h expected PASS 0x%08h",
                   core_pc, BOOTSTRAP_VA + ((B_PASS - BOOTSTRAP_SLOT) << 2));
            errors = errors + 1;
        end

        if (u_core.regfile[RV0] !== 32'h0F1E_2D3C) begin
            $error("[tb_ee_core_psubb] CASE 1: $v0 = 0x%08h (expected 0x0F1E2D3C)",
                   u_core.regfile[RV0]);
            errors = errors + 1;
        end
        if (u_core.regfile[RT5] !== 32'hFFFE_FDFC) begin
            $error("[tb_ee_core_psubb] CASE 2: $t5 = 0x%08h (expected 0xFFFEFDFC — all-wrap)",
                   u_core.regfile[RT5]);
            errors = errors + 1;
        end
        if (u_core.regfile[RT8] !== 32'h1234_56FF) begin
            $error("[tb_ee_core_psubb] CASE 3: $t8 = 0x%08h (expected 0x123456FF — no cross-byte borrow)",
                   u_core.regfile[RT8]);
            errors = errors + 1;
        end

        $display("[tb_ee_core_psubb] retired=%0d halt=%0d trap=%0d pc=0x%08h errors=%0d",
                 core_retired_events, core_halt_events,
                 core_trap_events, core_pc, errors);
        $display("[tb_ee_core_psubb]   $v0=0x%08h $t5=0x%08h $t8=0x%08h",
                 u_core.regfile[RV0], u_core.regfile[RT5], u_core.regfile[RT8]);

        if (errors == 0)
            $display("[tb_ee_core_psubb] PASS");
        else
            $display("[tb_ee_core_psubb] FAIL");
        $finish;
    end

    initial begin
        #2000000;
        $error("[tb_ee_core_psubb] timeout");
        $finish;
    end

endmodule : tb_ee_core_psubb
