// retroDE_ps2 — tb_ee_core_gif_primitive (Ch75)
//
// First end-to-end exercise of a primitive-shaped GIF PACKED packet
// using the **real PS2 GIF A+D register namespace** (per PCSX2's
// GSRegs.h). Replaces Ch74's tb_ee_core_gif_real_regs, which had
// confused GIF A+D reg numbers with privileged CRTC/MMIO offsets:
//   Ch74 (wrong): 0x14 → PMODE, 0x15 → SMODE2, 0x1A → BGCOLOR,
//                 0x4F → ZBUF_1
//   Ch75 (real):  0x14 = TEX1_1,  0x15 = TEX1_2,  0x1A = PRMODECONT
//                 0x4E = ZBUF_1   0x4F = ZBUF_2
//
// gif_packed_stub now drives gs_stub's separate GIF-A+D port
// (gif_reg_*) when REAL_AD_REG_MAP=1. gs_stub keeps its privileged
// MMIO port (reg_wr_*, BGCOLOR-only today) untouched.
//
// Stream (6 qwords):
//   q0 = GIFtag NLOOP=1 NREG=5 EOP=1 PACKED, REGS=[A+D ×5]
//   q1 = A+D reg# 0x00 (PRIM)    data=0x0000_0000_0000_0006     (TRIANGLE_FAN)
//   q2 = A+D reg# 0x01 (RGBAQ)   data=0x3F80_0000_FF00_30FF     (Q + RGBA)
//   q3 = A+D reg# 0x05 (XYZ2)    data=0x0000_0000_0080_0080     (X=0x80,Y=0x80,Z=0)
//   q4 = A+D reg# 0x4C (FRAME_1) data=0x0000_0000_001A_0014     (FBP=0x14, FBW=0x1A)
//   q5 = A+D reg# 0x4E (ZBUF_1)  data=0x0000_0000_0000_0028     (ZBP=0x28)
//
// Pass criteria:
//   - DMAC: 1 START / 6 BEATs / 1 DONE
//   - GIF:  1 GIFTAG, 5 EV_WRITEs (one per A+D entry; all known regs)
//   - GS:   5 EV_WRITE on gif_reg port; 0 EV_BGCOLOR / 0 EV_MODE
//           (BGCOLOR is privileged-only and not in this packet)
//   - latched values match exactly:
//       prim_q     = 0x0000_0000_0000_0006
//       rgbaq_q    = 0x3F80_0000_FF00_30FF
//       xyz2_q     = 0x0000_0000_0080_0080
//       frame_1_q  = 0x0000_0000_001A_0014
//       zbuf_1_q   = 0x0000_0000_0000_0028

`timescale 1ns/1ps

module tb_ee_core_gif_primitive;

    localparam int H_ACTIVE = 8;
    localparam int H_FRONT  = 2;
    localparam int H_SYNC   = 2;
    localparam int H_BACK   = 2;
    localparam int V_ACTIVE = 4;
    localparam int V_FRONT  = 1;
    localparam int V_SYNC   = 2;
    localparam int V_BACK   = 1;

    localparam int RAM_SIZE_BYTES = 4 * 1024;
    localparam int RAM_ADDR_W     = $clog2(RAM_SIZE_BYTES);

    logic clk;
    logic rst_n;
    initial clk = 1'b0;
    always #5 clk = ~clk;

    // ee_ram_stub
    logic                  ram_rd_en;
    logic [RAM_ADDR_W-1:0] ram_rd_addr;
    logic [127:0]          ram_rd_data;
    logic                  ram_rd_valid;
    logic                  ram_wr_en;
    logic [RAM_ADDR_W-1:0] ram_wr_addr;
    logic [127:0]          ram_wr_data;
    logic [15:0]           ram_wr_be;
    logic [7:0]            ram_master_id;

    ee_ram_stub #(.SIZE_BYTES(RAM_SIZE_BYTES)) u_ram (
        .clk(clk), .rst_n(rst_n),
        .rd_en(ram_rd_en), .rd_addr(ram_rd_addr),
        .rd_data(ram_rd_data), .rd_valid(ram_rd_valid),
        .wr_en(ram_wr_en), .wr_addr(ram_wr_addr),
        .wr_data(ram_wr_data), .wr_be(ram_wr_be),
        .master_id(ram_master_id),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );
    assign ram_master_id = ram_rd_en ? 8'd1 : 8'd0;

    // DMAC + map
    logic        dmac_reg_wr_en;
    logic [7:0]  dmac_reg_offset;
    logic [31:0] dmac_reg_wr_data;
    logic        dmac_mem_rd_en;
    logic [31:0] dmac_mem_rd_addr;
    logic         dmac_gif_valid;
    logic [127:0] dmac_gif_data;
    logic         dmac_gif_last;
    logic         dmac_gif_ready;

    logic                dmac_ev_valid;
    trace_pkg::subsys_e  dmac_ev_subsys;
    trace_pkg::event_e   dmac_ev_event;
    logic [63:0]         dmac_ev_arg0, dmac_ev_arg1, dmac_ev_arg2, dmac_ev_arg3;
    logic [31:0]         dmac_ev_flags;

    logic [127:0] map_to_dmac_rd_data;
    logic         map_to_dmac_rd_valid;

    dmac_reg_stub u_dmac (
        .clk(clk), .rst_n(rst_n),
        .reg_wr_en(dmac_reg_wr_en), .reg_offset(dmac_reg_offset),
        .reg_wr_data(dmac_reg_wr_data),
        .reg_rd_en(1'b0), .reg_rd_data(), .reg_rd_valid(),
        .mem_rd_en(dmac_mem_rd_en), .mem_rd_addr(dmac_mem_rd_addr),
        .mem_rd_data(map_to_dmac_rd_data), .mem_rd_valid(map_to_dmac_rd_valid),
        .ep_valid(dmac_gif_valid), .ep_data(dmac_gif_data),
        .ep_last(dmac_gif_last), .ep_ready(dmac_gif_ready),
        .irq_completion_o(),
        .ev_valid(dmac_ev_valid), .ev_subsys(dmac_ev_subsys),
        .ev_event(dmac_ev_event),
        .ev_arg0(dmac_ev_arg0), .ev_arg1(dmac_ev_arg1),
        .ev_arg2(dmac_ev_arg2), .ev_arg3(dmac_ev_arg3),
        .ev_flags(dmac_ev_flags)
    );

    logic         map_ram_rd_en;
    logic [24:0]  map_ram_rd_addr;

    ee_memory_map_stub u_map (
        .clk(clk), .rst_n(rst_n),
        .ee_rd_en(1'b0), .ee_rd_addr(32'd0),
        .ee_rd_data(), .ee_rd_valid(),
        .ee_wr_en(1'b0), .ee_wr_addr(32'd0),
        .ee_wr_data(32'd0), .ee_wr_be(4'd0),
        .dmac_rd_en(dmac_mem_rd_en), .dmac_rd_addr(dmac_mem_rd_addr),
        .dmac_rd_data(map_to_dmac_rd_data),
        .dmac_rd_valid(map_to_dmac_rd_valid),
        .bios_rd_en(), .bios_rd_addr(),
        .bios_rd_data(32'd0), .bios_rd_valid(1'b0),
        .ram_rd_en(map_ram_rd_en), .ram_rd_addr(map_ram_rd_addr),
        .ram_rd_data(ram_rd_data), .ram_rd_valid(ram_rd_valid),
        .bridge_wr_en(1'b0), .bridge_wr_addr(32'd0),
        .bridge_wr_data(128'd0), .bridge_wr_be(16'd0),
        .bridge_master_id(8'd0),
        .ram_wr_en(), .ram_wr_addr(), .ram_wr_data(),
        .ram_wr_be(), .ram_master_id(),
        .ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
        .ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
        .ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
        .ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
        .ee_intc_rd_en(), .ee_intc_rd_addr(),
        .ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
        .ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
        .ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
        .ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
        .ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
        .ee_biu_rd_en(), .ee_biu_rd_addr(),
        .ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    assign ram_rd_en   = map_ram_rd_en;
    assign ram_rd_addr = map_ram_rd_addr[RAM_ADDR_W-1:0];

    // gif_packed_stub — Ch75 REAL_AD_REG_MAP=1
    logic        gif_gs_wr_en;
    logic [15:0] gif_gs_wr_addr;
    logic [63:0] gif_gs_wr_data;
    logic        gif_gif_reg_wr_en;
    logic [7:0]  gif_gif_reg_num;
    logic [63:0] gif_gif_reg_data;

    logic                gif_ev_valid;
    trace_pkg::subsys_e  gif_ev_subsys;
    trace_pkg::event_e   gif_ev_event;
    logic [63:0]         gif_ev_arg0, gif_ev_arg1, gif_ev_arg2, gif_ev_arg3;
    logic [31:0]         gif_ev_flags;

    gif_packed_stub #(.REAL_AD_REG_MAP(1'b1)) u_gif (
        .clk(clk), .rst_n(rst_n),
        .in_valid(dmac_gif_valid), .in_data(dmac_gif_data),
        .in_last(dmac_gif_last), .in_ready(dmac_gif_ready),
        .image_data_ready(1'b1),
        .raster_fifo_full(1'b0),
        .gs_wr_en(gif_gs_wr_en), .gs_wr_addr(gif_gs_wr_addr),
        .gs_wr_data(gif_gs_wr_data),
        .gif_reg_wr_en(gif_gif_reg_wr_en),
        .gif_reg_num(gif_gif_reg_num),
        .gif_reg_data(gif_gif_reg_data),
        .ev_valid(gif_ev_valid), .ev_subsys(gif_ev_subsys),
        .ev_event(gif_ev_event),
        .ev_arg0(gif_ev_arg0), .ev_arg1(gif_ev_arg1),
        .ev_arg2(gif_ev_arg2), .ev_arg3(gif_ev_arg3),
        .ev_flags(gif_ev_flags)
    );

    // gs_stub
    logic [7:0]          bg_r, bg_g, bg_b;
    logic [63:0]         prim_q, rgbaq_q, xyz2_q, xyzf2_q, frame_1_q, zbuf_1_q;
    logic                gs_ev_valid;
    trace_pkg::subsys_e  gs_ev_subsys;
    trace_pkg::event_e   gs_ev_event;
    logic [63:0]         gs_ev_arg0, gs_ev_arg1, gs_ev_arg2, gs_ev_arg3;
    logic [31:0]         gs_ev_flags;

    gs_stub u_gs (
        .clk(clk), .rst_n(rst_n),
        .reg_wr_en(gif_gs_wr_en), .reg_wr_addr(gif_gs_wr_addr),
        .reg_wr_data(gif_gs_wr_data),
        .gif_reg_wr_en(gif_gif_reg_wr_en),
        .gif_reg_num(gif_gif_reg_num),
        .gif_reg_data(gif_gif_reg_data),
        .bg_r(bg_r), .bg_g(bg_g), .bg_b(bg_b),
        .prim_q(prim_q), .rgbaq_q(rgbaq_q),
        .xyz2_q(xyz2_q), .xyzf2_q(xyzf2_q),
        .frame_1_q(frame_1_q), .zbuf_1_q(zbuf_1_q),
        .prim_complete(), .prim_complete_count(),
        .prim_v0_q(), .prim_v1_q(), .prim_v2_q(),
        .prim_color_q(),
        .prim_color_v0_q(), .prim_color_v1_q(), .prim_color_v2_q(),
        .prim_v0_decoded_q(), .prim_v1_decoded_q(), .prim_v2_decoded_q(),
        .prim_v0_color_decoded_q(), .prim_v1_color_decoded_q(), .prim_v2_color_decoded_q(),
        .pixel_emit(), .pixel_emit_count(),
        .pixel_x_q(), .pixel_y_q(),
        .pixel_color_q(),
        .pixel_fbp_q(), .pixel_fbw_q(), .pixel_psm_q(),
        .pixel_fb_addr_q(),
        .raster_pixel_emit(), .raster_pixel_emit_count(),
        .raster_pixel_x_q(), .raster_pixel_y_q(),
        .raster_pixel_color_q(),
        .raster_pixel_fb_addr_q(),
        .raster_active(), .raster_overflow(),
        .raster_degenerate(),
        .ev_valid(gs_ev_valid), .ev_subsys(gs_ev_subsys),
        .ev_event(gs_ev_event),
        .ev_arg0(gs_ev_arg0), .ev_arg1(gs_ev_arg1),
        .ev_arg2(gs_ev_arg2), .ev_arg3(gs_ev_arg3),
        .ev_flags(gs_ev_flags)
    );

    logic       hsync, vsync, de;
    logic [7:0] r, g, b;
    platform_video_stub #(
        .H_ACTIVE(H_ACTIVE), .H_FRONT(H_FRONT), .H_SYNC(H_SYNC), .H_BACK(H_BACK),
        .V_ACTIVE(V_ACTIVE), .V_FRONT(V_FRONT), .V_SYNC(V_SYNC), .V_BACK(V_BACK)
    ) u_plat (
        .clk(clk), .rst_n(rst_n),
        .bg_r(bg_r), .bg_g(bg_g), .bg_b(bg_b),
        .hsync(hsync), .vsync(vsync), .de(de),
        .r(r), .g(g), .b(b),
        .ev_valid(), .ev_subsys(), .ev_event(),
        .ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
    );

    trace_sink_stub #(.FILENAME("gif_primitive_dmac.trace"), .SINK_LABEL("dmac"))
        u_trace_dmac (.clk(clk), .rst_n(rst_n),
            .ev_valid(dmac_ev_valid), .ev_subsys(dmac_ev_subsys),
            .ev_event(dmac_ev_event),
            .ev_arg0(dmac_ev_arg0), .ev_arg1(dmac_ev_arg1),
            .ev_arg2(dmac_ev_arg2), .ev_arg3(dmac_ev_arg3),
            .ev_flags(dmac_ev_flags));
    trace_sink_stub #(.FILENAME("gif_primitive_gif.trace"), .SINK_LABEL("gif"))
        u_trace_gif (.clk(clk), .rst_n(rst_n),
            .ev_valid(gif_ev_valid), .ev_subsys(gif_ev_subsys),
            .ev_event(gif_ev_event),
            .ev_arg0(gif_ev_arg0), .ev_arg1(gif_ev_arg1),
            .ev_arg2(gif_ev_arg2), .ev_arg3(gif_ev_arg3),
            .ev_flags(gif_ev_flags));
    trace_sink_stub #(.FILENAME("gif_primitive_gs.trace"), .SINK_LABEL("gs"))
        u_trace_gs (.clk(clk), .rst_n(rst_n),
            .ev_valid(gs_ev_valid), .ev_subsys(gs_ev_subsys),
            .ev_event(gs_ev_event),
            .ev_arg0(gs_ev_arg0), .ev_arg1(gs_ev_arg1),
            .ev_arg2(gs_ev_arg2), .ev_arg3(gs_ev_arg3),
            .ev_flags(gs_ev_flags));

    // Counters
    int dma_start_count, dma_beat_count, dma_done_count;
    int gif_giftag_count, gif_write_count, gif_mode_count;
    int gs_bgcolor_count, gs_write_count, gs_mode_count;
    int errors;
    logic dma_done_seen;

    initial begin
        dma_start_count = 0; dma_beat_count = 0; dma_done_count = 0;
        gif_giftag_count = 0; gif_write_count = 0; gif_mode_count = 0;
        gs_bgcolor_count = 0; gs_write_count = 0; gs_mode_count = 0;
        errors = 0; dma_done_seen = 1'b0;
    end

    always_ff @(posedge clk) begin
        if (rst_n && dmac_ev_valid) begin
            unique case (dmac_ev_event)
                trace_pkg::EV_DMA_START: dma_start_count <= dma_start_count + 1;
                trace_pkg::EV_DMA_BEAT:  dma_beat_count  <= dma_beat_count  + 1;
                trace_pkg::EV_DMA_DONE: begin
                    dma_done_count <= dma_done_count + 1;
                    dma_done_seen  <= 1'b1;
                end
                default: ;
            endcase
        end
        if (rst_n && gif_ev_valid) begin
            if (gif_ev_event == trace_pkg::EV_GIFTAG) gif_giftag_count <= gif_giftag_count + 1;
            if (gif_ev_event == trace_pkg::EV_WRITE)  gif_write_count  <= gif_write_count  + 1;
            if (gif_ev_event == trace_pkg::EV_MODE)   gif_mode_count   <= gif_mode_count   + 1;
        end
        if (rst_n && gs_ev_valid) begin
            if (gs_ev_event == trace_pkg::EV_BGCOLOR) gs_bgcolor_count <= gs_bgcolor_count + 1;
            if (gs_ev_event == trace_pkg::EV_WRITE)   gs_write_count   <= gs_write_count   + 1;
            if (gs_ev_event == trace_pkg::EV_MODE)    gs_mode_count    <= gs_mode_count    + 1;
        end
    end

    // Stimulus
    localparam logic [7:0]  CHCR_OFF = 8'h00;
    localparam logic [7:0]  MADR_OFF = 8'h10;
    localparam logic [7:0]  QWC_OFF  = 8'h20;
    localparam logic [31:0] PAYLOAD_MADR = 32'h0000_0100;

    task automatic write_dmac(input logic [7:0] offset, input logic [31:0] data);
        @(negedge clk); dmac_reg_wr_en = 1'b1; dmac_reg_offset = offset; dmac_reg_wr_data = data;
        @(negedge clk); dmac_reg_wr_en = 1'b0; dmac_reg_offset = 8'd0; dmac_reg_wr_data = 32'd0;
    endtask

    task automatic preload_qword(input logic [RAM_ADDR_W-1:0] addr,
                                 input logic [127:0] data);
        @(negedge clk); ram_wr_en = 1'b1; ram_wr_addr = addr; ram_wr_data = data; ram_wr_be = 16'hFFFF;
        @(negedge clk); ram_wr_en = 1'b0; ram_wr_addr = '0; ram_wr_data = 128'd0; ram_wr_be = 16'd0;
    endtask

    function automatic logic [127:0] giftag(
        input logic [14:0] nloop, input logic eop,
        input logic [1:0] flg, input logic [3:0] nreg, input logic [63:0] regs);
        logic [63:0] lower;
        lower = {nreg, flg, 42'd0, eop, nloop};
        return {regs, lower};
    endfunction

    // Real-PS2 PACKED A+D entry
    function automatic logic [127:0] aplusd_real(input logic [7:0]  reg_num,
                                                 input logic [63:0] data64);
        return {56'd0, reg_num, data64};
    endfunction

    // Constants for real GIF A+D reg numbers (per PCSX2 GSRegs.h)
    localparam logic [7:0] R_PRIM    = 8'h00;
    localparam logic [7:0] R_RGBAQ   = 8'h01;
    localparam logic [7:0] R_XYZ2    = 8'h05;
    localparam logic [7:0] R_FRAME_1 = 8'h4C;
    localparam logic [7:0] R_ZBUF_1  = 8'h4E;

    // Expected data
    localparam logic [63:0] EXP_PRIM    = 64'h0000_0000_0000_0006;
    localparam logic [63:0] EXP_RGBAQ   = 64'h3F80_0000_FF00_30FF;
    localparam logic [63:0] EXP_XYZ2    = 64'h0000_0000_0080_0080;
    localparam logic [63:0] EXP_FRAME_1 = 64'h0000_0000_001A_0014;
    localparam logic [63:0] EXP_ZBUF_1  = 64'h0000_0000_0000_0028;

    initial begin
        rst_n = 1'b0;
        dmac_reg_wr_en = 1'b0; dmac_reg_offset = 8'd0; dmac_reg_wr_data = 32'd0;
        ram_wr_en = 1'b0; ram_wr_addr = '0; ram_wr_data = 128'd0; ram_wr_be = 16'd0;

        repeat (4) @(posedge clk); rst_n = 1'b1; repeat (8) @(posedge clk);

        begin : preload_block
            logic [RAM_ADDR_W-1:0] addr_q;
            // q0 — GIFtag NLOOP=1 NREG=5 EOP=1 PACKED, REGS=[A+D × 5]
            addr_q = PAYLOAD_MADR + 32'd0;
            preload_qword(addr_q, giftag(15'd1, 1'b1, 2'd0, 4'd5,
                                         64'h0000_0000_000E_EEEE));
            // q1 — A+D PRIM
            addr_q = PAYLOAD_MADR + 32'd16;
            preload_qword(addr_q, aplusd_real(R_PRIM, EXP_PRIM));
            // q2 — A+D RGBAQ
            addr_q = PAYLOAD_MADR + 32'd32;
            preload_qword(addr_q, aplusd_real(R_RGBAQ, EXP_RGBAQ));
            // q3 — A+D XYZ2
            addr_q = PAYLOAD_MADR + 32'd48;
            preload_qword(addr_q, aplusd_real(R_XYZ2, EXP_XYZ2));
            // q4 — A+D FRAME_1
            addr_q = PAYLOAD_MADR + 32'd64;
            preload_qword(addr_q, aplusd_real(R_FRAME_1, EXP_FRAME_1));
            // q5 — A+D ZBUF_1 (reg# 0x4E — verifies the Ch74 0x4F→0x4E fix)
            addr_q = PAYLOAD_MADR + 32'd80;
            preload_qword(addr_q, aplusd_real(R_ZBUF_1, EXP_ZBUF_1));
        end

        write_dmac(MADR_OFF, PAYLOAD_MADR);
        write_dmac(QWC_OFF,  32'd6);
        write_dmac(CHCR_OFF, 32'h0000_0001);

        wait (dma_done_seen == 1'b1);
        repeat (40) @(posedge clk);

        $display("[tb_ee_core_gif_primitive] dma=(%0d,%0d,%0d)  gif=(tag=%0d,wr=%0d,mode=%0d)  gs=(bg=%0d,wr=%0d,mode=%0d)",
                 dma_start_count, dma_beat_count, dma_done_count,
                 gif_giftag_count, gif_write_count, gif_mode_count,
                 gs_bgcolor_count, gs_write_count, gs_mode_count);
        $display("[tb_ee_core_gif_primitive] gif-context latches: prim=0x%016h rgbaq=0x%016h xyz2=0x%016h frame_1=0x%016h zbuf_1=0x%016h",
                 prim_q, rgbaq_q, xyz2_q, frame_1_q, zbuf_1_q);

        if (dma_start_count != 1)  begin $error("dma_start"); errors = errors + 1; end
        if (dma_beat_count  != 6)  begin $error("dma_beat=%0d (expected 6)", dma_beat_count); errors = errors + 1; end
        if (dma_done_count  != 1)  begin $error("dma_done"); errors = errors + 1; end
        if (gif_giftag_count != 1) begin $error("gif_giftag=%0d (expected 1)", gif_giftag_count); errors = errors + 1; end
        if (gif_write_count != 5)  begin $error("gif_write=%0d (expected 5: 5 A+D entries)", gif_write_count); errors = errors + 1; end
        if (gif_mode_count  != 0)  begin $error("gif_mode=%0d (expected 0)", gif_mode_count); errors = errors + 1; end
        if (gs_bgcolor_count != 0) begin $error("gs_bgcolor=%0d (expected 0; BGCOLOR is privileged-only)", gs_bgcolor_count); errors = errors + 1; end
        if (gs_write_count  != 5)  begin $error("gs_write=%0d (expected 5: PRIM+RGBAQ+XYZ2+FRAME_1+ZBUF_1)", gs_write_count); errors = errors + 1; end
        if (gs_mode_count   != 0)  begin $error("gs_mode=%0d (expected 0; all reg#s known)", gs_mode_count); errors = errors + 1; end
        if (prim_q    !== EXP_PRIM)    begin $error("prim_q=0x%016h",    prim_q);    errors = errors + 1; end
        if (rgbaq_q   !== EXP_RGBAQ)   begin $error("rgbaq_q=0x%016h",   rgbaq_q);   errors = errors + 1; end
        if (xyz2_q    !== EXP_XYZ2)    begin $error("xyz2_q=0x%016h",    xyz2_q);    errors = errors + 1; end
        if (frame_1_q !== EXP_FRAME_1) begin $error("frame_1_q=0x%016h", frame_1_q); errors = errors + 1; end
        if (zbuf_1_q  !== EXP_ZBUF_1)  begin $error("zbuf_1_q=0x%016h",  zbuf_1_q);  errors = errors + 1; end

        if (errors == 0) $display("[tb_ee_core_gif_primitive] PASS");
        else             $display("[tb_ee_core_gif_primitive] FAIL");
        $finish;
    end

    initial begin
        #200000;
        $error("[tb_ee_core_gif_primitive] timeout");
        $finish;
    end

endmodule : tb_ee_core_gif_primitive
