thejayman77
27dfd0b0cf
Ch442's fit exposed two failing setup families (plus a stale max-skew). Attack both structurally; no reseeding. Family 1 - AWREADY -> Z-FSM (-0.410): gen_p2c_ff[23] (EMIF AWREADY) reached u_zc_emit|u_z's S_SFLUSH_AW/S_FILL_R next-state combinationally. Ch441 registered only the W channel; add the AW twin: - new gs_axi_aw_regbuf (one-entry fully-registered AW buffer), inserted in zc_emit between u_z's AW output and the arbiter s2 AW port. The FSM now sees registered occupancy, never EMIF's combinational AWREADY. Family 2 - texcache drain_idx_q -> tex_mem (-0.370, x7): a single index fanned across the whole 65536x32, 128-M20K macro. Split by WIDTH into four 65536x8 banks, each with its own (* preserve, dont_merge *) write- address launch register; write the four byte lanes together in F_WRITE; reconstruct the sample word by concatenating four registered read bytes. Selector structure and 1-cycle read latency unchanged; total M20Ks unchanged (4x32 == 128); fill_crc still sums the full 32-bit word. Max-skew: relax ONLY the Ch357 tile-write CDC set_max_skew 2.0 -> 2.5 (quasi-static bundle, >=2 dclk stability window); retain set_net_delay 2.0 (the real arrival bound). SDC comment updated. Tests: new tb_gs_axi_aw_regbuf (AW scoreboard: exactly-once/order/no- combinational-AWREADY-bypass/stable-while-stalled); tb_gs_texture_cache strengthened to distinct-per-byte-bank data + per-bank + full-word checks. All pass: aw/w regbuf, texture_cache, texture_psmt8_clut, scanout_diag, ps2_hps_bridge, and the complete f52 replay BYTE-IDENTICAL (Z 0/307200, COLOR 0/245760). No Quartus, board, or push from here. Ready for one owner GUI fit. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
89 lines
3.9 KiB
Systemverilog
89 lines
3.9 KiB
Systemverilog
// retroDE_ps2 — gs_axi_aw_regbuf (Ch443)
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//
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// Fully-registered ONE-ENTRY AXI AW-channel (write-address) buffer. The AW twin
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// of gs_axi_w_regbuf. Inserted between the Z RMW master's (gs_lpddr_z_rmw) AW
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// OUTPUT and the write arbiter's s2 AW INPUT to cut the combinational path
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// EMIF gen_p2c_ff[23] (AWREADY) -> wr_arb s2_awready -> gs_lpddr_z_rmw
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// next-state (`st`, S_SFLUSH_AW / S_FILL_R) — the -0.410 ns EMIF setup family.
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//
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// Ch441 registered the W channel (gs_axi_w_regbuf u_z_wbuf) but left AW running
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// straight from the FSM to the arbiter, so EMIF AWREADY still reached the FSM
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// combinationally. This buffer applies the identical structural cut to AW.
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//
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// CONTRACT (identical to gs_axi_w_regbuf, must hold exactly):
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// - FULLY REGISTERED, not a fall-through skid: u_awready depends ONLY on the
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// registered occupancy `full`, never on d_awready. Downstream (EMIF) AWREADY
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// therefore can never propagate combinationally back into the upstream FSM.
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// (i.e. NOT `u_awready = !full || d_awready`.)
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// - Buffers the complete {AWADDR, AWLEN, AWSIZE, AWBURST} payload and holds it
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// stable downstream until the arbiter accepts it.
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// - Exactly-once: an address accepted upstream is delivered downstream exactly
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// once. One in flight (the Z RMW issues single-beat writes, AWLEN=0).
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// - W and B channels are NOT touched here (W is separately buffered by
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// gs_axi_w_regbuf; B passes through). AXI permits AW and W in either order,
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// and each one-entry buffer holds its beat until the arbiter accepts it, so
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// the AW/W pair still reaches the slave together.
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`timescale 1ns/1ps
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module gs_axi_aw_regbuf #(
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parameter int ADDR_W = 32,
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parameter int LEN_W = 8,
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parameter int SIZE_W = 3,
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parameter int BURST_W = 2
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) (
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input logic clk,
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input logic rst_n,
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// upstream — from the Z RMW master's AW output
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input logic [ADDR_W-1:0] u_awaddr,
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input logic [LEN_W-1:0] u_awlen,
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input logic [SIZE_W-1:0] u_awsize,
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input logic [BURST_W-1:0] u_awburst,
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input logic u_awvalid,
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output logic u_awready,
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// downstream — to the write arbiter's s2 AW input
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output logic [ADDR_W-1:0] d_awaddr,
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output logic [LEN_W-1:0] d_awlen,
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output logic [SIZE_W-1:0] d_awsize,
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output logic [BURST_W-1:0] d_awburst,
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output logic d_awvalid,
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input logic d_awready
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);
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logic full;
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logic [ADDR_W-1:0] awaddr_q;
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logic [LEN_W-1:0] awlen_q;
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logic [SIZE_W-1:0] awsize_q;
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logic [BURST_W-1:0] awburst_q;
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// Upstream ready = registered occupancy ONLY (no d_awready term) -> EMIF AWREADY
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// never reaches the upstream FSM combinationally.
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assign u_awready = !full;
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// Downstream presents the held address, stable until the arbiter accepts it.
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assign d_awvalid = full;
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assign d_awaddr = awaddr_q;
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assign d_awlen = awlen_q;
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assign d_awsize = awsize_q;
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assign d_awburst = awburst_q;
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// One-entry register. Accept an offered upstream address only while empty;
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// release only when the arbiter accepts the held address. When full and
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// accepted in the same cycle, u_awready is still 0 (full is registered), so
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// the next address waits one cycle -> a swap/drop/dup is impossible. Payload
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// registers deliberately have no reset (qualified by `full`/d_awvalid; the
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// writer cannot present an address until reset releases).
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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full <= 1'b0;
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end else if (!full) begin
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if (u_awvalid) begin
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full <= 1'b1;
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awaddr_q <= u_awaddr;
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awlen_q <= u_awlen;
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awsize_q <= u_awsize;
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awburst_q <= u_awburst;
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end
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end else begin
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if (d_awready) full <= 1'b0;
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end
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end
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endmodule : gs_axi_aw_regbuf
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