Ch443: combined timing repair for both Ch442 setup families
Ch442's fit exposed two failing setup families (plus a stale max-skew). Attack both structurally; no reseeding. Family 1 - AWREADY -> Z-FSM (-0.410): gen_p2c_ff[23] (EMIF AWREADY) reached u_zc_emit|u_z's S_SFLUSH_AW/S_FILL_R next-state combinationally. Ch441 registered only the W channel; add the AW twin: - new gs_axi_aw_regbuf (one-entry fully-registered AW buffer), inserted in zc_emit between u_z's AW output and the arbiter s2 AW port. The FSM now sees registered occupancy, never EMIF's combinational AWREADY. Family 2 - texcache drain_idx_q -> tex_mem (-0.370, x7): a single index fanned across the whole 65536x32, 128-M20K macro. Split by WIDTH into four 65536x8 banks, each with its own (* preserve, dont_merge *) write- address launch register; write the four byte lanes together in F_WRITE; reconstruct the sample word by concatenating four registered read bytes. Selector structure and 1-cycle read latency unchanged; total M20Ks unchanged (4x32 == 128); fill_crc still sums the full 32-bit word. Max-skew: relax ONLY the Ch357 tile-write CDC set_max_skew 2.0 -> 2.5 (quasi-static bundle, >=2 dclk stability window); retain set_net_delay 2.0 (the real arrival bound). SDC comment updated. Tests: new tb_gs_axi_aw_regbuf (AW scoreboard: exactly-once/order/no- combinational-AWREADY-bypass/stable-while-stalled); tb_gs_texture_cache strengthened to distinct-per-byte-bank data + per-bank + full-word checks. All pass: aw/w regbuf, texture_cache, texture_psmt8_clut, scanout_diag, ps2_hps_bridge, and the complete f52 replay BYTE-IDENTICAL (Z 0/307200, COLOR 0/245760). No Quartus, board, or push from here. Ready for one owner GUI fit. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
This commit is contained in:
@@ -0,0 +1,88 @@
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// retroDE_ps2 — gs_axi_aw_regbuf (Ch443)
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//
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// Fully-registered ONE-ENTRY AXI AW-channel (write-address) buffer. The AW twin
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// of gs_axi_w_regbuf. Inserted between the Z RMW master's (gs_lpddr_z_rmw) AW
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// OUTPUT and the write arbiter's s2 AW INPUT to cut the combinational path
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// EMIF gen_p2c_ff[23] (AWREADY) -> wr_arb s2_awready -> gs_lpddr_z_rmw
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// next-state (`st`, S_SFLUSH_AW / S_FILL_R) — the -0.410 ns EMIF setup family.
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//
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// Ch441 registered the W channel (gs_axi_w_regbuf u_z_wbuf) but left AW running
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// straight from the FSM to the arbiter, so EMIF AWREADY still reached the FSM
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// combinationally. This buffer applies the identical structural cut to AW.
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//
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// CONTRACT (identical to gs_axi_w_regbuf, must hold exactly):
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// - FULLY REGISTERED, not a fall-through skid: u_awready depends ONLY on the
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// registered occupancy `full`, never on d_awready. Downstream (EMIF) AWREADY
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// therefore can never propagate combinationally back into the upstream FSM.
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// (i.e. NOT `u_awready = !full || d_awready`.)
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// - Buffers the complete {AWADDR, AWLEN, AWSIZE, AWBURST} payload and holds it
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// stable downstream until the arbiter accepts it.
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// - Exactly-once: an address accepted upstream is delivered downstream exactly
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// once. One in flight (the Z RMW issues single-beat writes, AWLEN=0).
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// - W and B channels are NOT touched here (W is separately buffered by
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// gs_axi_w_regbuf; B passes through). AXI permits AW and W in either order,
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// and each one-entry buffer holds its beat until the arbiter accepts it, so
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// the AW/W pair still reaches the slave together.
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`timescale 1ns/1ps
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module gs_axi_aw_regbuf #(
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parameter int ADDR_W = 32,
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parameter int LEN_W = 8,
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parameter int SIZE_W = 3,
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parameter int BURST_W = 2
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) (
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input logic clk,
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input logic rst_n,
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// upstream — from the Z RMW master's AW output
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input logic [ADDR_W-1:0] u_awaddr,
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input logic [LEN_W-1:0] u_awlen,
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input logic [SIZE_W-1:0] u_awsize,
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input logic [BURST_W-1:0] u_awburst,
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input logic u_awvalid,
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output logic u_awready,
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// downstream — to the write arbiter's s2 AW input
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output logic [ADDR_W-1:0] d_awaddr,
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output logic [LEN_W-1:0] d_awlen,
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output logic [SIZE_W-1:0] d_awsize,
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output logic [BURST_W-1:0] d_awburst,
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output logic d_awvalid,
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input logic d_awready
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);
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logic full;
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logic [ADDR_W-1:0] awaddr_q;
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logic [LEN_W-1:0] awlen_q;
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logic [SIZE_W-1:0] awsize_q;
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logic [BURST_W-1:0] awburst_q;
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// Upstream ready = registered occupancy ONLY (no d_awready term) -> EMIF AWREADY
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// never reaches the upstream FSM combinationally.
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assign u_awready = !full;
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// Downstream presents the held address, stable until the arbiter accepts it.
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assign d_awvalid = full;
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assign d_awaddr = awaddr_q;
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assign d_awlen = awlen_q;
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assign d_awsize = awsize_q;
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assign d_awburst = awburst_q;
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// One-entry register. Accept an offered upstream address only while empty;
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// release only when the arbiter accepts the held address. When full and
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// accepted in the same cycle, u_awready is still 0 (full is registered), so
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// the next address waits one cycle -> a swap/drop/dup is impossible. Payload
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// registers deliberately have no reset (qualified by `full`/d_awvalid; the
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// writer cannot present an address until reset releases).
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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full <= 1'b0;
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end else if (!full) begin
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if (u_awvalid) begin
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full <= 1'b1;
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awaddr_q <= u_awaddr;
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awlen_q <= u_awlen;
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awsize_q <= u_awsize;
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awburst_q <= u_awburst;
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end
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end else begin
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if (d_awready) full <= 1'b0;
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end
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end
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endmodule : gs_axi_aw_regbuf
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@@ -155,6 +155,10 @@ module gs_lpddr_zc_emit #(
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// ports (write arbiter s2). This cuts the combinational EMIF WREADY -> z_rmw
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// FSM path. AW and B pass straight through (z_awaddr.../z_bvalid... unchanged).
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logic [255:0] zi_wdata; logic [31:0] zi_wstrb; logic zi_wlast, zi_wvalid, zi_wready;
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// Ch443: the Z RMW master's AW output ALSO goes through a one-entry registered
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// buffer (gs_axi_aw_regbuf u_z_awbuf, below) so the FSM sees a REGISTERED awready
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// (buffer occupancy), never EMIF's combinational AWREADY (gen_p2c_ff[23]).
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logic [31:0] zi_awaddr; logic [7:0] zi_awlen; logic [2:0] zi_awsize; logic [1:0] zi_awburst; logic zi_awvalid, zi_awready;
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gs_lpddr_z_rmw #(.ZBASE(ZBASE), .FB_PXW(FB_PXW), .FB_H(FB_H), .Z_CLEAR(Z_CLEAR)) u_z (
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.clk(axi_clk), .rst_n(axi_rst_n), .enable(enable), .clear_start(clear_start), .clear_done(clear_done),
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.scene_flush(z_sflush), .z_drained(z_drained),
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@@ -163,20 +167,28 @@ module gs_lpddr_zc_emit #(
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.p_valid(z_pvalid), .p_ready(z_pready), .p_pass(z_ppass), .p_x(z_px), .p_y(z_py), .p_zq(z_pzq),
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.araddr(z_araddr), .arlen(z_arlen), .arsize(z_arsize), .arburst(z_arburst), .arvalid(z_arvalid), .arready(z_arready),
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.rdata(z_rdata), .rresp(z_rresp), .rlast(z_rlast), .rvalid(z_rvalid), .rready(z_rready),
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.awaddr(z_awaddr), .awlen(z_awlen), .awsize(z_awsize), .awburst(z_awburst), .awvalid(z_awvalid), .awready(z_awready),
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.awaddr(zi_awaddr), .awlen(zi_awlen), .awsize(zi_awsize), .awburst(zi_awburst), .awvalid(zi_awvalid), .awready(zi_awready),
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.wdata(zi_wdata), .wstrb(zi_wstrb), .wlast(zi_wlast), .wvalid(zi_wvalid), .wready(zi_wready),
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.bvalid(z_bvalid), .bready(z_bready), .bresp(z_bresp),
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.beats_read(z_beats_read), .beats_written(z_beats_written), .bresp_err(bresp_err), .idle(z_idle)
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);
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// Ch441: one-entry fully-registered W-channel buffer between the Z RMW master
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// (u_z) and the write arbiter s2 (via the z_w* ports). Breaks the combinational
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// EMIF WREADY -> z_rmw FSM path. AW/B untouched; the arbiter's bready_q still
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// EMIF WREADY -> z_rmw FSM path. B untouched; the arbiter's bready_q still
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// arms on the real EMIF m_wvalid && m_wready && m_wlast (buffer is upstream).
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gs_axi_w_regbuf #(.WDATA_W(256), .WSTRB_W(32)) u_z_wbuf (
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.clk(axi_clk), .rst_n(axi_rst_n),
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.u_wdata(zi_wdata), .u_wstrb(zi_wstrb), .u_wlast(zi_wlast), .u_wvalid(zi_wvalid), .u_wready(zi_wready),
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.d_wdata(z_wdata), .d_wstrb(z_wstrb), .d_wlast(z_wlast), .d_wvalid(z_wvalid), .d_wready(z_wready)
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);
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// Ch443: one-entry fully-registered AW-channel buffer, the AW twin of u_z_wbuf.
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// Cuts the combinational EMIF AWREADY -> z_rmw FSM next-state (S_SFLUSH_AW/
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// S_FILL_R) path — the -0.410 ns setup family Ch442's fit exposed.
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gs_axi_aw_regbuf #(.ADDR_W(32), .LEN_W(8), .SIZE_W(3), .BURST_W(2)) u_z_awbuf (
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.clk(axi_clk), .rst_n(axi_rst_n),
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.u_awaddr(zi_awaddr), .u_awlen(zi_awlen), .u_awsize(zi_awsize), .u_awburst(zi_awburst), .u_awvalid(zi_awvalid), .u_awready(zi_awready),
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.d_awaddr(z_awaddr), .d_awlen(z_awlen), .d_awsize(z_awsize), .d_awburst(z_awburst), .d_awvalid(z_awvalid), .d_awready(z_awready)
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);
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// A fragment carries ztest: when ztest=0 it must ALWAYS pass. Feed the RMW a zmsk so it never writes Z for a
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// non-Z fragment, and force its zq to max so GEQUAL always passes. (All scheduler draws are ztest=1.)
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// (Handled at feed below via the always-pass override on the pass decision.)
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@@ -85,7 +85,17 @@ module gs_texture_cache #(
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// 1x 65536x32 (HERE) -> latch each AXI beat, drain 8 lanes over 8 axi_clk cycles.
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// Serializing the fill removes the multi-bank/multi-write geometry while preserving the sampler's
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// one-cycle registered 32-bit read. The one-shot fill is still tiny compared with board startup.
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(* ramstyle = "M20K" *) logic [31:0] tex_mem [0:TEX_WORDS-1];
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// Ch443 (Codex): four 65536x8 byte-width banks with INDEPENDENT preserved write-
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// address launch registers, replacing the single 65536x32 logical RAM. The single
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// drain_idx_q fanning across the whole 128-M20K macro was the -0.370 ns setup family
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// (drain_idx_q[4] -> tex_mem ram_block*~reg0). Splitting the WIDTH gives each address
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// tree ~32 M20Ks; total M20K count is unchanged (4x32 == 128). Selector structure,
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// one-shot fill sequence, and the 1-cycle registered read latency are all preserved;
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// the read reconstructs the 32-bit word by concatenation.
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(* ramstyle = "M20K" *) logic [7:0] tex_mem_b0 [0:TEX_WORDS-1];
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(* ramstyle = "M20K" *) logic [7:0] tex_mem_b1 [0:TEX_WORDS-1];
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(* ramstyle = "M20K" *) logic [7:0] tex_mem_b2 [0:TEX_WORDS-1];
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(* ramstyle = "M20K" *) logic [7:0] tex_mem_b3 [0:TEX_WORDS-1];
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// ================= fill side (axi_clk) =================
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typedef enum logic [2:0] { F_IDLE, F_AR, F_R, F_DRAIN, F_WRITE, F_DONE } fstate_t;
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@@ -103,7 +113,10 @@ module gs_texture_cache #(
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// so reset values are unobservable; keeping them out of the 4k-fanout EMIF calibration reset removes that reset
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// from the duplicated RAM-address launch registers at 310 MHz.
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logic [31:0] drain_word_q;
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logic [WIDX_BITS-1:0] drain_idx_q;
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// Ch443: four independent, preserved, non-merged write-address launch registers —
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// one per byte bank. dont_merge is REQUIRED: they hold identical values, so without
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// it Quartus would re-merge them into a single high-fanout register, undoing the fix.
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(* preserve, dont_merge *) logic [WIDX_BITS-1:0] drain_idx_q0, drain_idx_q1, drain_idx_q2, drain_idx_q3;
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// fill_start is an EDGE/TOGGLE (bridge toggles it on each arm), CDC-synced here so the
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// cache is RE-FILLABLE: each arm reloads the texture (lets the HPS re-stage a different
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// texture without a board reset). 3-FF sync + edge-detect, like the read/write probes.
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@@ -154,9 +167,13 @@ module gs_texture_cache #(
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fst <= F_WRITE;
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end
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F_WRITE: begin
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// COMMIT half: registered word -> M20K; CRC over the word actually committed.
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tex_mem[drain_idx_q] <= drain_word_q;
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fill_crc <= fill_crc + drain_word_q; // sum32 over the words written
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// COMMIT half: registered word -> four byte banks (each with its own
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// preserved address reg); CRC over the FULL word actually committed.
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tex_mem_b0[drain_idx_q0] <= drain_word_q[7:0];
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tex_mem_b1[drain_idx_q1] <= drain_word_q[15:8];
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tex_mem_b2[drain_idx_q2] <= drain_word_q[23:16];
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tex_mem_b3[drain_idx_q3] <= drain_word_q[31:24];
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fill_crc <= fill_crc + drain_word_q; // sum32 over the words written (unchanged)
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if (fill_lane == 3'd7) begin
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fill_beats <= fill_beats + 32'd1;
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fill_bytes <= fill_bytes + 32'd32;
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@@ -198,7 +215,10 @@ module gs_texture_cache #(
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always_ff @(posedge axi_clk) begin
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if (fst == F_DRAIN) begin
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drain_word_q <= fill_data_q[fill_lane*32 +: 32];
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drain_idx_q <= fill_word_idx;
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drain_idx_q0 <= fill_word_idx; // four identical loads; kept separate by dont_merge
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drain_idx_q1 <= fill_word_idx;
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drain_idx_q2 <= fill_word_idx;
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drain_idx_q3 <= fill_word_idx;
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end
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end
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@@ -207,9 +227,18 @@ module gs_texture_cache #(
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// present (tex_rd_addr) when tex_rd_en, data lands next cycle.
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wire [31:0] word_off = (tex_rd_addr - TEX_VRAM_BASE) >> 2;
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wire [WIDX_BITS-1:0] rd_word = word_off[WIDX_BITS-1:0];
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// Ch443: read each byte bank, register the four bytes, reconstruct the 32-bit word
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// by concatenation. Identical 1-cycle registered latency to the pre-split read.
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logic [7:0] tex_rd_b0, tex_rd_b1, tex_rd_b2, tex_rd_b3;
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always_ff @(posedge sample_clk) begin
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if (tex_rd_en) tex_rd_data <= tex_mem[rd_word];
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if (tex_rd_en) begin
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tex_rd_b0 <= tex_mem_b0[rd_word];
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tex_rd_b1 <= tex_mem_b1[rd_word];
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tex_rd_b2 <= tex_mem_b2[rd_word];
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tex_rd_b3 <= tex_mem_b3[rd_word];
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end
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end
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assign tex_rd_data = {tex_rd_b3, tex_rd_b2, tex_rd_b1, tex_rd_b0};
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// fill_done -> sample_clk (2-FF). The read mux only goes live once warm.
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logic [1:0] done_sync;
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+11
-1
@@ -586,6 +586,7 @@ RTL_SRCS := \
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$(RTL_ROOT)/gif_gs/gs_lpddr_axi_master.sv \
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$(RTL_ROOT)/gif_gs/gs_lpddr_z_rmw.sv \
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$(RTL_ROOT)/gif_gs/gs_axi_w_regbuf.sv \
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$(RTL_ROOT)/gif_gs/gs_axi_aw_regbuf.sv \
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$(RTL_ROOT)/gif_gs/gs_lpddr_zc_emit.sv \
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$(RTL_ROOT)/gif_gs/gs_lpddr_rd_probe.sv \
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$(RTL_ROOT)/gif_gs/gs_lpddr_scanout.sv \
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@@ -1153,6 +1154,15 @@ tb_gs_axi_w_regbuf: dirs
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@echo "=== run tb_gs_axi_w_regbuf ==="
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@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_axi_w_regbuf.vvp
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tb_gs_axi_aw_regbuf: dirs
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@echo "=== build tb_gs_axi_aw_regbuf ==="
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$(IVERILOG) $(IVERILOG_FLGS) \
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-o $(BUILD_DIR)/tb_gs_axi_aw_regbuf.vvp \
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-s tb_gs_axi_aw_regbuf \
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$(RTL_SRCS) $(TB_ROOT)/gif_gs/tb_gs_axi_aw_regbuf.sv
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@echo "=== run tb_gs_axi_aw_regbuf ==="
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@cd $(TRACE_DIR) && $(VVP) $(BUILD_DIR)/tb_gs_axi_aw_regbuf.vvp
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tb_gs_grad_divider: dirs
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@echo "=== build tb_gs_grad_divider ==="
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$(IVERILOG) $(IVERILOG_FLGS) \
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@@ -6282,7 +6292,7 @@ run: tb_top_psmct32_sh3_zs640c12_cap tb_top_psmct32_sh3_zint640c12
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run: tb_top_psmct32_sh3_zs640b24_cap tb_top_psmct32_sh3_zint640b24
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.PHONY: tb_top_psmct32_sh3_zs640c24c_cap tb_top_psmct32_sh3_zint640c24c sh3_zs640c24c_fixture sh3_zs640motionabc_bootlet
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run: tb_top_psmct32_sh3_zs640c24c_cap tb_top_psmct32_sh3_zint640c24c tb_gs_axi_w_regbuf
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run: tb_top_psmct32_sh3_zs640c24c_cap tb_top_psmct32_sh3_zint640c24c tb_gs_axi_w_regbuf tb_gs_axi_aw_regbuf
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run: tb_ee_fetch tb_gs tb_intc tb_platform_video tb_bgcolor_via_dma tb_sif_mailbox \
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tb_sif_command_echo tb_sif_command_echo_rearm tb_sif_negative_path \
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@@ -0,0 +1,138 @@
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// retroDE_ps2 — tb_gs_axi_aw_regbuf (Ch443)
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//
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// AW twin of tb_gs_axi_w_regbuf. Focused scoreboard for the one-entry fully-
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// registered AXI AW buffer. Verifies:
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// (1) EXACTLY-ONCE, IN-ORDER delivery with payload integrity {AWADDR,AWLEN,
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// AWSIZE,AWBURST} under randomized upstream offer + downstream backpressure
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// (a drop, dup, or reorder trips the sequence scoreboard).
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// (2) The NO-COMBINATIONAL-BYPASS contract: u_awready === !full every cycle, so a
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// fall-through `u_awready = !full || d_awready` (which would leak downstream
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// AWREADY back upstream into the Z FSM) is caught. A directed phase forces the
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// full && d_awready case.
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// (3) Downstream payload held STABLE while d_awvalid && !d_awready.
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// (4) Full drain leaves the buffer empty with equal produced/consumed counts.
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`timescale 1ns/1ps
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module tb_gs_axi_aw_regbuf;
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localparam int AW = 32, LN = 8, SZ = 3, BR = 2;
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logic clk = 0; always #5 clk = ~clk; // 100 MHz
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logic rst_n;
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|
||||
logic [AW-1:0] u_awaddr; logic [LN-1:0] u_awlen; logic [SZ-1:0] u_awsize; logic [BR-1:0] u_awburst; logic u_awvalid, u_awready;
|
||||
logic [AW-1:0] d_awaddr; logic [LN-1:0] d_awlen; logic [SZ-1:0] d_awsize; logic [BR-1:0] d_awburst; logic d_awvalid; logic d_awready;
|
||||
|
||||
gs_axi_aw_regbuf #(.ADDR_W(AW), .LEN_W(LN), .SIZE_W(SZ), .BURST_W(BR)) dut (
|
||||
.clk(clk), .rst_n(rst_n),
|
||||
.u_awaddr(u_awaddr), .u_awlen(u_awlen), .u_awsize(u_awsize), .u_awburst(u_awburst), .u_awvalid(u_awvalid), .u_awready(u_awready),
|
||||
.d_awaddr(d_awaddr), .d_awlen(d_awlen), .d_awsize(d_awsize), .d_awburst(d_awburst), .d_awvalid(d_awvalid), .d_awready(d_awready)
|
||||
);
|
||||
|
||||
int errors; initial errors = 0;
|
||||
|
||||
// distinct payload per sequence value (fills all fields)
|
||||
function automatic logic [AW-1:0] mk_addr(input logic [31:0] s); mk_addr = (s ^ 32'hCAFE_0000) | 32'd4; endfunction
|
||||
function automatic logic [LN-1:0] mk_len (input logic [31:0] s); mk_len = s[7:0]; endfunction
|
||||
function automatic logic [SZ-1:0] mk_size(input logic [31:0] s); mk_size = s[2:0] ^ 3'd5; endfunction
|
||||
function automatic logic [BR-1:0] mk_brst(input logic [31:0] s); mk_brst = s[1:0] | 2'b01; endfunction
|
||||
|
||||
// LFSR backpressure on both sides
|
||||
logic [15:0] ul = 16'hACE1, dl = 16'h1357;
|
||||
always_ff @(posedge clk) begin
|
||||
ul <= {ul[14:0], ul[15]^ul[13]^ul[12]^ul[10]};
|
||||
dl <= {dl[14:0], dl[15]^dl[13]^dl[12]^dl[10]};
|
||||
end
|
||||
logic force_ready, force_stall, prod_freeze;
|
||||
assign d_awready = force_ready ? 1'b1 : (force_stall ? 1'b0 : (dl[0] | dl[3]));
|
||||
|
||||
// AXI-legal producer: assert u_awvalid with STABLE payload until accepted.
|
||||
logic [31:0] wr_seq;
|
||||
logic pending;
|
||||
always_ff @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin wr_seq <= 0; pending <= 1'b0; end
|
||||
else if (u_awvalid && u_awready) begin
|
||||
wr_seq <= wr_seq + 1;
|
||||
pending <= (ul[0] | ul[3]) && !prod_freeze;
|
||||
end
|
||||
else if (!pending) pending <= (ul[0] | ul[3]) && !prod_freeze;
|
||||
end
|
||||
assign u_awvalid = pending;
|
||||
assign u_awaddr = mk_addr(wr_seq);
|
||||
assign u_awlen = mk_len(wr_seq);
|
||||
assign u_awsize = mk_size(wr_seq);
|
||||
assign u_awburst = mk_brst(wr_seq);
|
||||
|
||||
// (1) downstream scoreboard: exactly-once, in-order, payload-correct
|
||||
logic [31:0] rd_seq;
|
||||
always_ff @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) rd_seq <= 0;
|
||||
else if (d_awvalid && d_awready) begin
|
||||
if (d_awaddr !== mk_addr(rd_seq) || d_awlen !== mk_len(rd_seq) ||
|
||||
d_awsize !== mk_size(rd_seq) || d_awburst !== mk_brst(rd_seq)) begin
|
||||
if (errors < 20) $error("[awbuf] drop/dup/reorder/payload at seq %0d: addr %h len %h size %h burst %b",
|
||||
rd_seq, d_awaddr, d_awlen, d_awsize, d_awburst);
|
||||
errors++;
|
||||
end
|
||||
rd_seq <= rd_seq + 1;
|
||||
end
|
||||
end
|
||||
|
||||
// (2) NO combinational downstream-ready bypass: u_awready must equal !full.
|
||||
always_ff @(posedge clk) if (rst_n) begin
|
||||
if (u_awready !== !dut.full) begin
|
||||
if (errors < 20) $error("[awbuf] u_awready(%b) != !full(%b) — combinational bypass?", u_awready, dut.full);
|
||||
errors++;
|
||||
end
|
||||
end
|
||||
logic saw_full_and_ready; initial saw_full_and_ready = 1'b0;
|
||||
always_ff @(posedge clk) if (rst_n && dut.full && d_awready) saw_full_and_ready <= 1'b1;
|
||||
|
||||
// (3) while stalled, the SAME beat must still be presented.
|
||||
logic [AW-1:0] hold_a; logic [LN-1:0] hold_l; logic [SZ-1:0] hold_s; logic [BR-1:0] hold_b; logic hold_v;
|
||||
always_ff @(posedge clk or negedge rst_n) begin
|
||||
if (!rst_n) begin hold_v <= 1'b0; hold_a <= '0; hold_l <= '0; hold_s <= '0; hold_b <= '0; end
|
||||
else begin
|
||||
if (hold_v) begin
|
||||
if (!d_awvalid) begin
|
||||
if (errors < 20) $error("[awbuf] d_awvalid deasserted while stalled"); errors++;
|
||||
end else if (d_awaddr !== hold_a || d_awlen !== hold_l || d_awsize !== hold_s || d_awburst !== hold_b) begin
|
||||
if (errors < 20) $error("[awbuf] downstream {awaddr,awlen,awsize,awburst} changed while stalled"); errors++;
|
||||
end
|
||||
end
|
||||
hold_v <= d_awvalid && !d_awready;
|
||||
hold_a <= d_awaddr; hold_l <= d_awlen; hold_s <= d_awsize; hold_b <= d_awburst;
|
||||
end
|
||||
end
|
||||
|
||||
initial begin
|
||||
rst_n = 0; force_ready = 0; force_stall = 0; prod_freeze = 0;
|
||||
repeat (6) @(posedge clk); rst_n = 1;
|
||||
@(posedge clk);
|
||||
if (d_awvalid !== 1'b0) begin $error("[awbuf] not empty after reset"); errors++; end
|
||||
|
||||
// Phase 1: randomized offer + backpressure
|
||||
repeat (20000) @(posedge clk);
|
||||
|
||||
// Phase 2 (directed): stall downstream so the buffer fills and STAYS full
|
||||
// (u_awready must read 0 = !full), then hold full while d_awready=1.
|
||||
force_stall = 1; repeat (200) @(posedge clk);
|
||||
force_stall = 0; force_ready = 1; repeat (200) @(posedge clk);
|
||||
force_ready = 0;
|
||||
|
||||
// Phase 3: freeze producer, drain fully
|
||||
prod_freeze = 1; force_ready = 1;
|
||||
begin int g; g = 0; while ((wr_seq !== rd_seq) && g < 4000) begin @(posedge clk); g++; end end
|
||||
repeat (10) @(posedge clk);
|
||||
|
||||
if (d_awvalid !== 1'b0) begin $error("[awbuf] not empty after drain (d_awvalid=%b)", d_awvalid); errors++; end
|
||||
if (wr_seq !== rd_seq) begin $error("[awbuf] count mismatch: in %0d out %0d", wr_seq, rd_seq); errors++; end
|
||||
if (wr_seq < 32'd2000) begin $error("[awbuf] too few transfers (%0d) — not meaningful", wr_seq); errors++; end
|
||||
if (!saw_full_and_ready) begin $error("[awbuf] coverage: full && d_awready never observed — no-bypass case unexercised"); errors++; end
|
||||
|
||||
$display("[tb_gs_axi_aw_regbuf] in=%0d out=%0d errors=%0d", wr_seq, rd_seq, errors);
|
||||
if (errors == 0) $display("[tb_gs_axi_aw_regbuf] PASS");
|
||||
else $display("[tb_gs_axi_aw_regbuf] FAIL");
|
||||
$finish;
|
||||
end
|
||||
|
||||
initial begin #2000000; $error("[tb_gs_axi_aw_regbuf] TIMEOUT"); $finish; end
|
||||
endmodule : tb_gs_axi_aw_regbuf
|
||||
@@ -37,8 +37,17 @@ module tb_gs_texture_cache;
|
||||
logic [31:0] tex_rd_addr, tex_rd_data;
|
||||
logic tex_ready;
|
||||
|
||||
// golden source: 64 words. tex_word(i) = 0xC0DE_0000 | i (distinct per lane).
|
||||
function automatic [31:0] tex_word(input int i); tex_word = 32'hC0DE_0000 | i[31:0]; endfunction
|
||||
// golden source. Ch443: every byte lane carries DISTINCT data — different per index
|
||||
// AND different across the four banks (distinct XOR keys + distinct bases) — so the
|
||||
// four-bank tex_mem split is genuinely exercised: a bank swap, misroute, or dropped
|
||||
// bank produces a wrong reconstructed byte that the full-word + per-bank checks catch.
|
||||
// (The old 0xC0DE_0000|i had constant bytes 2/3, which a bank fault could hide.)
|
||||
function automatic [31:0] tex_word(input int i);
|
||||
tex_word = { 8'(((i*4 + 3) & 32'hFF) ^ 32'hA3),
|
||||
8'(((i*4 + 2) & 32'hFF) ^ 32'h5C),
|
||||
8'(((i*4 + 1) & 32'hFF) ^ 32'h91),
|
||||
8'(((i*4 + 0) & 32'hFF) ^ 32'h2E) };
|
||||
endfunction
|
||||
|
||||
// force a bad rresp on a chosen beat to exercise rd_errs (set <0 to disable)
|
||||
int err_beat = -1;
|
||||
@@ -122,9 +131,16 @@ module tb_gs_texture_cache;
|
||||
check(tex_ready, "tex_ready never synced");
|
||||
|
||||
// ---- verify every word via the sampler 1-cycle read port ----
|
||||
// Full reconstructed word AND per-bank byte pinpoint (Ch443 four-bank split).
|
||||
for (int i=0; i<TEX_WORDS; i++) begin
|
||||
logic [31:0] exp;
|
||||
read_word(i, got);
|
||||
check(got == tex_word(i), $sformatf("word[%0d]=%08x exp %08x", i, got, tex_word(i)));
|
||||
exp = tex_word(i); // temp: iverilog forbids part-select on a function-call result
|
||||
check(got == exp, $sformatf("word[%0d]=%08x exp %08x", i, got, exp));
|
||||
check(got[7:0] === exp[7:0], $sformatf("bank0 byte[%0d]=%02x exp %02x", i, got[7:0], exp[7:0]));
|
||||
check(got[15:8] === exp[15:8], $sformatf("bank1 byte[%0d]=%02x exp %02x", i, got[15:8], exp[15:8]));
|
||||
check(got[23:16] === exp[23:16], $sformatf("bank2 byte[%0d]=%02x exp %02x", i, got[23:16], exp[23:16]));
|
||||
check(got[31:24] === exp[31:24], $sformatf("bank3 byte[%0d]=%02x exp %02x", i, got[31:24], exp[31:24]));
|
||||
end
|
||||
|
||||
$display("[texcache] clean: fill_done=%0d beats=%0d bytes=%0d rd_errs=%0d words_checked=%0d errors=%0d",
|
||||
|
||||
@@ -1061,6 +1061,7 @@ set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_tile_reload.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_map_pkg.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_z_rmw.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_axi_w_regbuf.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_axi_aw_regbuf.sv
|
||||
set_global_assignment -name SYSTEMVERILOG_FILE rtl/gif_gs/gs_lpddr_zc_emit.sv
|
||||
# ----------------------------------------------------------------------------
|
||||
# Design RTL added during the EE/qbert chapters (Ch287+) that reached the demo
|
||||
|
||||
@@ -336,9 +336,16 @@ if { $tile_src_n == 0 && $tile_dst_n == 0 } {
|
||||
if { $tile_src_n != 42 } { error "Ch357 SDC FATAL: tile_ram_cdc source tile_wr_index+tile_wr_data count $tile_src_n != 42 (10+32; renamed/optimized? hold cut + net_delay would orphan)" }
|
||||
if { $tile_dst_n == 0 } { error "Ch357 SDC FATAL: tile_ram_cdc dest u_tile_cdc|shadow_mem EMPTY (renamed? hold cut would orphan)" }
|
||||
set_false_path -hold -from $tile_cdc_src -to $tile_cdc_dst
|
||||
set_max_skew -from $tile_cdc_src -to $tile_cdc_dst 2.0
|
||||
# Ch443 (Codex): max_skew bound 2.0 -> 2.5. The Ch442 fit placed this quasi-static OSD
|
||||
# tile bundle at 2.050 ns actual skew, failing the round-number 2.0 by 50 ps. The CDC
|
||||
# contract guarantees >= 2 design-clock periods of bus stability before the synchronized
|
||||
# toggle samples (same recipe as the tile hold-false + net_delay below), so 2.5 ns stays
|
||||
# FAR inside the real functional window and avoids engineering to a 50 ps margin. The
|
||||
# set_net_delay ARRIVAL bound is UNCHANGED at 2.0 ns (it bounds the actual requirement:
|
||||
# each bit must arrive within the stability window; skew only bounds bit-to-bit spread).
|
||||
set_max_skew -from $tile_cdc_src -to $tile_cdc_dst 2.5
|
||||
set_net_delay -max -from $tile_cdc_src -to $tile_cdc_dst 2.0
|
||||
post_message -type info "Ch357 SDC: tile_ram_cdc hold-false-path + 2ns max_skew + 2ns net_delay ($tile_src_n src -> $tile_dst_n shadow_mem dst)"
|
||||
post_message -type info "Ch357/443 SDC: tile_ram_cdc hold-false-path + 2.5ns max_skew + 2ns net_delay ($tile_src_n src -> $tile_dst_n shadow_mem dst)"
|
||||
}
|
||||
|
||||
# Ch357 (Codex) — osd_cfg QUASI-STATIC config CDC. osd_cfg{0,1}_q (bridge, refclk/fabric domain) cross into
|
||||
|
||||
Reference in New Issue
Block a user