thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
487 lines
19 KiB
Systemverilog
487 lines
19 KiB
Systemverilog
// retroDE_ps2 — tb_iop_autonomous_two_xfers
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//
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// First autonomous multi-transaction flow. Extends tb_iop_self_driven
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// one architectural level higher: the RAM-resident control program
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// now contains a BNE back-edge that loops the DMA+IRQ+ack body until
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// DMAC.DONE_COUNT reaches 2. A single `go_i` pulse produces TWO full
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// DMA transactions, two interrupt assertions, and two acks — all
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// fabric-driven, no TB steering between transactions.
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//
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// Chain identical to tb_iop_self_driven (same map, DMAC, INTC, exec
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// stub, ep_ready-on-the-floor endpoint). The only difference is the
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// script: a BNE at the loop tail wires two transactions together.
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//
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// Script (9 ops, laid out in IOP RAM at SCRIPT_BASE):
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// pc=0 WRITE INTC_MASK = 1 (enable bit 0)
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// pc=1 WRITE DMAC_MADR = payload (loop entry)
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// pc=2 WRITE DMAC_BCR = 4
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// pc=3 WRITE DMAC_CHCR = 1 (start transfer)
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// pc=4 WAIT_IRQ (block until completion)
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// pc=5 WRITE INTC_STAT = 1 (W1C ack through real map)
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// pc=6 READ DMAC_DONE_COUNT (latches into last_read_data)
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// pc=7 BNE target=1, expected=2 (branch back if DONE_COUNT != 2)
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// pc=8 HALT
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//
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// Acceptance:
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// - Exactly one go_i pulse from the TB; no orchestration after.
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// - Two DMA_DONE events, two INTC assertions, two INTC acks.
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// - Exactly two WAIT_IRQ exits and exactly one BNE taken (the first
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// time, when DONE_COUNT == 1). On the second iteration DONE_COUNT
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// reads 2, so BNE falls through to HALT.
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// - halt_o asserts exactly once.
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// - Full causal chain reconstructible from the trace.
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`timescale 1ns/1ps
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module tb_iop_autonomous_two_xfers;
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localparam int IOP_RAM_BYTES = 4 * 1024;
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localparam int IOP_RAM_ADDR_W = $clog2(IOP_RAM_BYTES);
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localparam logic [31:0] SCRIPT_BASE = 32'h0000_0400;
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localparam logic [31:0] PAYLOAD_BASE = 32'h0000_0200;
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localparam logic [31:0] DMAC_MADR_ADDR = 32'h1F80_1520;
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localparam logic [31:0] DMAC_BCR_ADDR = 32'h1F80_1524;
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localparam logic [31:0] DMAC_CHCR_ADDR = 32'h1F80_1528;
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localparam logic [31:0] DMAC_DONECOUNT_ADDR = 32'h1F80_152C;
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localparam logic [31:0] INTC_STAT_ADDR = 32'h1F80_1070;
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localparam logic [31:0] INTC_MASK_ADDR = 32'h1F80_1074;
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localparam logic [31:0] OP_HALT = 32'h0000_0000;
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localparam logic [31:0] OP_WRITE = 32'h0000_0001;
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localparam logic [31:0] OP_READ = 32'h0000_0002;
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localparam logic [31:0] OP_WAIT_IRQ = 32'h0000_0003;
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localparam logic [31:0] OP_BNE = 32'h0000_0004;
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logic clk;
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logic rst_n;
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ------------------------------------------------------------------
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// IOP exec stub
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// ------------------------------------------------------------------
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logic exec_go;
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logic exec_halt;
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logic [7:0] exec_pc;
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logic map_cpu_rd_en;
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logic [31:0] map_cpu_rd_addr;
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logic [31:0] map_cpu_rd_data;
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logic map_cpu_rd_valid;
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logic map_cpu_wr_en;
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logic [31:0] map_cpu_wr_addr;
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logic [31:0] map_cpu_wr_data;
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logic [3:0] map_cpu_wr_be;
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logic iop_cpu_irq;
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logic exec_ev_valid;
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trace_pkg::subsys_e exec_ev_subsys;
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trace_pkg::event_e exec_ev_event;
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logic [63:0] exec_ev_arg0, exec_ev_arg1, exec_ev_arg2, exec_ev_arg3;
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logic [31:0] exec_ev_flags;
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iop_exec_stub #(.SCRIPT_BASE(SCRIPT_BASE)) u_exec (
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.clk(clk), .rst_n(rst_n),
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.go_i(exec_go),
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.map_rd_en(map_cpu_rd_en), .map_rd_addr(map_cpu_rd_addr),
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.map_rd_data(map_cpu_rd_data), .map_rd_valid(map_cpu_rd_valid),
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.map_wr_en(map_cpu_wr_en), .map_wr_addr(map_cpu_wr_addr),
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.map_wr_data(map_cpu_wr_data), .map_wr_be(map_cpu_wr_be),
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.cpu_irq(iop_cpu_irq),
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.halt_o(exec_halt), .pc_o(exec_pc),
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.ev_valid(exec_ev_valid), .ev_subsys(exec_ev_subsys),
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.ev_event(exec_ev_event),
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.ev_arg0(exec_ev_arg0), .ev_arg1(exec_ev_arg1),
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.ev_arg2(exec_ev_arg2), .ev_arg3(exec_ev_arg3),
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.ev_flags(exec_ev_flags)
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);
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// ------------------------------------------------------------------
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// IOP map + IOP RAM (TB drives bridge_wr_* for preload)
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// ------------------------------------------------------------------
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logic iop_ram_rd_en;
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logic [20:0] iop_ram_rd_addr;
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logic [31:0] iop_ram_rd_data;
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logic iop_ram_rd_valid;
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logic iop_ram_wr_en;
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logic [20:0] iop_ram_wr_addr;
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logic [31:0] iop_ram_wr_data;
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logic [3:0] iop_ram_wr_be;
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logic [7:0] iop_ram_master_id;
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logic map_dmac_rd_en;
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logic [3:0] map_dmac_rd_addr;
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logic [31:0] map_dmac_rd_data;
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logic map_dmac_rd_valid;
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logic map_dmac_wr_en;
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logic [3:0] map_dmac_wr_addr;
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logic [31:0] map_dmac_wr_data;
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logic map_intc_rd_en;
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logic [7:0] map_intc_rd_addr;
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logic [31:0] map_intc_rd_data;
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logic map_intc_rd_valid;
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logic map_intc_wr_en;
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logic [7:0] map_intc_wr_addr;
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logic [31:0] map_intc_wr_data;
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logic dma_rd_en;
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logic [31:0] dma_rd_addr;
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logic [7:0] dma_master_id;
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logic [31:0] dma_rd_data;
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logic dma_rd_valid;
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logic tb_br_wr_en;
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logic [31:0] tb_br_wr_addr;
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logic [31:0] tb_br_wr_data;
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logic [3:0] tb_br_wr_be;
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logic iop_map_ev_valid;
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trace_pkg::subsys_e iop_map_ev_subsys;
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trace_pkg::event_e iop_map_ev_event;
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logic [63:0] iop_map_ev_arg0, iop_map_ev_arg1, iop_map_ev_arg2, iop_map_ev_arg3;
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logic [31:0] iop_map_ev_flags;
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iop_memory_map_stub u_iop_map (
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.clk(clk), .rst_n(rst_n),
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.iop_rd_en(map_cpu_rd_en), .iop_rd_addr(map_cpu_rd_addr),
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.iop_rd_data(map_cpu_rd_data), .iop_rd_valid(map_cpu_rd_valid),
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.iop_wr_en(map_cpu_wr_en), .iop_wr_addr(map_cpu_wr_addr),
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.iop_wr_data(map_cpu_wr_data), .iop_wr_be(map_cpu_wr_be),
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.master_id(8'd2),
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.bridge_wr_en(tb_br_wr_en), .bridge_wr_addr(tb_br_wr_addr),
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.bridge_wr_data(tb_br_wr_data), .bridge_wr_be(tb_br_wr_be),
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.bridge_master_id(8'd0),
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.dma_rd_en(dma_rd_en), .dma_rd_addr(dma_rd_addr),
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.dma_master_id(dma_master_id),
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.dma_rd_data(dma_rd_data), .dma_rd_valid(dma_rd_valid),
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.sif_rd_en(), .sif_rd_addr(),
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.sif_rd_data(32'd0), .sif_rd_valid(1'b0),
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.sif_wr_en(), .sif_wr_addr(), .sif_wr_data(),
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.iop_dmac_rd_en(map_dmac_rd_en), .iop_dmac_rd_addr(map_dmac_rd_addr),
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.iop_dmac_rd_data(map_dmac_rd_data), .iop_dmac_rd_valid(map_dmac_rd_valid),
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.iop_dmac_wr_en(map_dmac_wr_en), .iop_dmac_wr_addr(map_dmac_wr_addr),
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.iop_dmac_wr_data(map_dmac_wr_data),
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.iop_intc_rd_en(map_intc_rd_en), .iop_intc_rd_addr(map_intc_rd_addr),
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.iop_intc_rd_data(map_intc_rd_data), .iop_intc_rd_valid(map_intc_rd_valid),
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.iop_intc_wr_en(map_intc_wr_en), .iop_intc_wr_addr(map_intc_wr_addr),
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.iop_intc_wr_data(map_intc_wr_data),
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.input_p1(32'd0), .input_p2(32'd0),
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// BIOS ROM port — unused by this TB
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.bios_rd_en(), .bios_rd_addr(),
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.bios_rd_data(32'd0), .bios_rd_valid(1'b0),
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.ram_rd_en(iop_ram_rd_en), .ram_rd_addr(iop_ram_rd_addr),
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.ram_rd_data(iop_ram_rd_data), .ram_rd_valid(iop_ram_rd_valid),
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.ram_wr_en(iop_ram_wr_en), .ram_wr_addr(iop_ram_wr_addr),
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.ram_wr_data(iop_ram_wr_data), .ram_wr_be(iop_ram_wr_be),
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.ram_master_id(iop_ram_master_id),
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.ev_valid(iop_map_ev_valid), .ev_subsys(iop_map_ev_subsys),
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.ev_event(iop_map_ev_event),
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.ev_arg0(iop_map_ev_arg0), .ev_arg1(iop_map_ev_arg1),
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.ev_arg2(iop_map_ev_arg2), .ev_arg3(iop_map_ev_arg3),
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.ev_flags(iop_map_ev_flags)
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);
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iop_ram_stub #(.SIZE_BYTES(IOP_RAM_BYTES)) u_iop_ram (
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.clk(clk), .rst_n(rst_n),
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.rd_en(iop_ram_rd_en), .rd_addr(iop_ram_rd_addr[IOP_RAM_ADDR_W-1:0]),
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.rd_data(iop_ram_rd_data), .rd_valid(iop_ram_rd_valid),
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.wr_en(iop_ram_wr_en), .wr_addr(iop_ram_wr_addr[IOP_RAM_ADDR_W-1:0]),
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.wr_data(iop_ram_wr_data), .wr_be(iop_ram_wr_be),
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.master_id(iop_ram_master_id),
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.ev_valid(), .ev_subsys(), .ev_event(),
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.ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
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);
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// ------------------------------------------------------------------
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// IOP DMAC ch9 — endpoint drained (no stall in this TB)
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// ------------------------------------------------------------------
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logic ep_valid;
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logic [31:0] ep_data;
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logic ep_last;
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logic ep_ready;
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assign ep_ready = 1'b1;
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logic dmac_irq_completion;
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logic dmac_busy;
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logic [31:0] dmac_done_count;
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logic dmac_ev_valid;
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trace_pkg::subsys_e dmac_ev_subsys;
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trace_pkg::event_e dmac_ev_event;
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logic [63:0] dmac_ev_arg0, dmac_ev_arg1, dmac_ev_arg2, dmac_ev_arg3;
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logic [31:0] dmac_ev_flags;
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iop_dmac_reg_stub u_dmac (
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.clk(clk), .rst_n(rst_n),
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.reg_wr_en(map_dmac_wr_en), .reg_rd_en(map_dmac_rd_en),
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.reg_offset(map_dmac_wr_en ? map_dmac_wr_addr : map_dmac_rd_addr),
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.reg_wr_data(map_dmac_wr_data),
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.reg_rd_data(map_dmac_rd_data), .reg_rd_valid(map_dmac_rd_valid),
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.mem_rd_en(dma_rd_en), .mem_rd_addr(dma_rd_addr),
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.mem_master_id(dma_master_id),
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.mem_rd_data(dma_rd_data), .mem_rd_valid(dma_rd_valid),
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.ep_valid(ep_valid), .ep_data(ep_data), .ep_last(ep_last),
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.ep_ready(ep_ready),
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.irq_completion_o(dmac_irq_completion),
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.busy_o(dmac_busy), .done_count_o(dmac_done_count),
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.ev_valid(dmac_ev_valid), .ev_subsys(dmac_ev_subsys),
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.ev_event(dmac_ev_event),
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.ev_arg0(dmac_ev_arg0), .ev_arg1(dmac_ev_arg1),
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.ev_arg2(dmac_ev_arg2), .ev_arg3(dmac_ev_arg3),
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.ev_flags(dmac_ev_flags)
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);
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// ------------------------------------------------------------------
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// IOP INTC
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// ------------------------------------------------------------------
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logic [15:0] iop_irq_src;
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assign iop_irq_src = {15'd0, dmac_irq_completion};
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logic intc_ev_valid;
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trace_pkg::subsys_e intc_ev_subsys;
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trace_pkg::event_e intc_ev_event;
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logic [63:0] intc_ev_arg0, intc_ev_arg1, intc_ev_arg2, intc_ev_arg3;
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logic [31:0] intc_ev_flags;
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intc_stub #(
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.INTC_STAT_OFFSET(8'h70),
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.INTC_MASK_OFFSET(8'h74)
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) u_intc (
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.clk(clk), .rst_n(rst_n),
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.reg_wr_en(map_intc_wr_en), .reg_rd_en(map_intc_rd_en),
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.reg_addr(map_intc_wr_en ? map_intc_wr_addr : map_intc_rd_addr),
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.reg_wr_data(map_intc_wr_data),
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.reg_rd_data(map_intc_rd_data), .reg_rd_valid(map_intc_rd_valid),
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.irq_src(iop_irq_src), .cpu_irq(iop_cpu_irq),
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.ev_valid(intc_ev_valid), .ev_subsys(intc_ev_subsys),
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.ev_event(intc_ev_event),
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.ev_arg0(intc_ev_arg0), .ev_arg1(intc_ev_arg1),
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.ev_arg2(intc_ev_arg2), .ev_arg3(intc_ev_arg3),
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.ev_flags(intc_ev_flags)
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);
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// ------------------------------------------------------------------
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// Trace sinks
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// ------------------------------------------------------------------
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trace_sink_stub #(.FILENAME("iop_two_xfers_exec.trace"), .SINK_LABEL("iop_exec"))
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u_trace_exec (.clk(clk), .rst_n(rst_n),
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.ev_valid(exec_ev_valid), .ev_subsys(exec_ev_subsys),
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.ev_event(exec_ev_event), .ev_arg0(exec_ev_arg0),
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.ev_arg1(exec_ev_arg1), .ev_arg2(exec_ev_arg2),
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.ev_arg3(exec_ev_arg3), .ev_flags(exec_ev_flags));
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trace_sink_stub #(.FILENAME("iop_two_xfers_map.trace"), .SINK_LABEL("iop_map"))
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u_trace_map (.clk(clk), .rst_n(rst_n),
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.ev_valid(iop_map_ev_valid), .ev_subsys(iop_map_ev_subsys),
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.ev_event(iop_map_ev_event), .ev_arg0(iop_map_ev_arg0),
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.ev_arg1(iop_map_ev_arg1), .ev_arg2(iop_map_ev_arg2),
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.ev_arg3(iop_map_ev_arg3), .ev_flags(iop_map_ev_flags));
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trace_sink_stub #(.FILENAME("iop_two_xfers_dmac.trace"), .SINK_LABEL("iop_dmac"))
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u_trace_dmac (.clk(clk), .rst_n(rst_n),
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.ev_valid(dmac_ev_valid), .ev_subsys(dmac_ev_subsys),
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.ev_event(dmac_ev_event), .ev_arg0(dmac_ev_arg0),
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.ev_arg1(dmac_ev_arg1), .ev_arg2(dmac_ev_arg2),
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.ev_arg3(dmac_ev_arg3), .ev_flags(dmac_ev_flags));
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trace_sink_stub #(.FILENAME("iop_two_xfers_intc.trace"), .SINK_LABEL("iop_intc"))
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u_trace_intc (.clk(clk), .rst_n(rst_n),
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.ev_valid(intc_ev_valid), .ev_subsys(intc_ev_subsys),
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.ev_event(intc_ev_event), .ev_arg0(intc_ev_arg0),
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.ev_arg1(intc_ev_arg1), .ev_arg2(intc_ev_arg2),
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.ev_arg3(intc_ev_arg3), .ev_flags(intc_ev_flags));
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// ------------------------------------------------------------------
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// Observers
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// ------------------------------------------------------------------
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int dmac_done_events;
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int intc_assert_events;
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int intc_ack_events;
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int exec_op_events;
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int wait_irq_exit_events;
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int bne_taken_events;
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int halt_events;
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int errors;
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initial begin
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dmac_done_events = 0;
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intc_assert_events = 0;
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intc_ack_events = 0;
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exec_op_events = 0;
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wait_irq_exit_events = 0;
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bne_taken_events = 0;
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halt_events = 0;
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errors = 0;
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end
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always_ff @(posedge clk) begin
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if (rst_n && dmac_ev_valid &&
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dmac_ev_subsys == trace_pkg::SUBSYS_DMAC &&
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dmac_ev_event == trace_pkg::EV_DMA_DONE)
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dmac_done_events <= dmac_done_events + 1;
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if (rst_n && intc_ev_valid &&
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intc_ev_subsys == trace_pkg::SUBSYS_INTC &&
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intc_ev_event == trace_pkg::EV_IRQ) begin
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if (intc_ev_arg3 == 64'd0 && (intc_ev_flags & 32'h1) == 32'd0)
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intc_assert_events <= intc_assert_events + 1;
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else if (intc_ev_arg3 == 64'd1)
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intc_ack_events <= intc_ack_events + 1;
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end
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if (rst_n && exec_ev_valid) begin
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exec_op_events <= exec_op_events + 1;
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if ((exec_ev_flags & 32'h2) != 32'd0)
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wait_irq_exit_events <= wait_irq_exit_events + 1;
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if ((exec_ev_flags & 32'h4) != 32'd0)
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halt_events <= halt_events + 1;
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if ((exec_ev_flags & 32'h8) != 32'd0)
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bne_taken_events <= bne_taken_events + 1;
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end
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end
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// ------------------------------------------------------------------
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// Preload helpers
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// ------------------------------------------------------------------
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task automatic bridge_write(input logic [31:0] addr, input logic [31:0] data);
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@(negedge clk);
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tb_br_wr_en = 1'b1;
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tb_br_wr_addr = addr;
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tb_br_wr_data = data;
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tb_br_wr_be = 4'b1111;
|
|
@(negedge clk);
|
|
tb_br_wr_en = 1'b0;
|
|
tb_br_wr_addr = 32'd0;
|
|
tb_br_wr_data = 32'd0;
|
|
tb_br_wr_be = 4'd0;
|
|
endtask
|
|
|
|
task automatic emit_op(input int slot,
|
|
input logic [31:0] opcode,
|
|
input logic [31:0] addr_or_tgt,
|
|
input logic [31:0] data_or_exp);
|
|
logic [31:0] base;
|
|
base = SCRIPT_BASE + (slot << 4);
|
|
bridge_write(base + 32'd0, opcode);
|
|
bridge_write(base + 32'd4, addr_or_tgt);
|
|
bridge_write(base + 32'd8, data_or_exp);
|
|
bridge_write(base + 32'd12, 32'd0);
|
|
endtask
|
|
|
|
// ------------------------------------------------------------------
|
|
// Stimulus — single go_i pulse; loop-tail BNE drives two transactions
|
|
// ------------------------------------------------------------------
|
|
|
|
initial begin
|
|
rst_n = 1'b0;
|
|
exec_go = 1'b0;
|
|
tb_br_wr_en = 1'b0;
|
|
tb_br_wr_addr = 32'd0;
|
|
tb_br_wr_data = 32'd0;
|
|
tb_br_wr_be = 4'd0;
|
|
|
|
repeat (4) @(posedge clk);
|
|
rst_n = 1'b1;
|
|
repeat (2) @(posedge clk);
|
|
|
|
// Payload (reused by both transactions — exec stub doesn't
|
|
// rewrite between iterations)
|
|
bridge_write(PAYLOAD_BASE + 32'h00, 32'hCAFE_0000);
|
|
bridge_write(PAYLOAD_BASE + 32'h04, 32'hCAFE_0001);
|
|
bridge_write(PAYLOAD_BASE + 32'h08, 32'hCAFE_0002);
|
|
bridge_write(PAYLOAD_BASE + 32'h0C, 32'hCAFE_0003);
|
|
|
|
// Control program
|
|
emit_op( 0, OP_WRITE, INTC_MASK_ADDR, 32'h0000_0001);
|
|
// loop_start @ pc=1
|
|
emit_op( 1, OP_WRITE, DMAC_MADR_ADDR, PAYLOAD_BASE);
|
|
emit_op( 2, OP_WRITE, DMAC_BCR_ADDR, 32'h0000_0004);
|
|
emit_op( 3, OP_WRITE, DMAC_CHCR_ADDR, 32'h0000_0001);
|
|
emit_op( 4, OP_WAIT_IRQ, 32'd0, 32'd0);
|
|
emit_op( 5, OP_WRITE, INTC_STAT_ADDR, 32'h0000_0001);
|
|
emit_op( 6, OP_READ, DMAC_DONECOUNT_ADDR, 32'd0);
|
|
// BNE: branch back to loop_start (pc=1) if DONE_COUNT != 2
|
|
emit_op( 7, OP_BNE, 32'h0000_0001, 32'h0000_0002);
|
|
emit_op( 8, OP_HALT, 32'd0, 32'd0);
|
|
|
|
// Single go_i pulse
|
|
@(negedge clk);
|
|
exec_go = 1'b1;
|
|
@(negedge clk);
|
|
exec_go = 1'b0;
|
|
|
|
while (!exec_halt) @(posedge clk);
|
|
repeat (4) @(posedge clk);
|
|
|
|
// Post-halt checks
|
|
if (dmac_done_events != 2) begin
|
|
$error("[tb_iop_autonomous_two_xfers] expected 2 DMA_DONE, got %0d",
|
|
dmac_done_events);
|
|
errors = errors + 1;
|
|
end
|
|
if (intc_assert_events != 2) begin
|
|
$error("[tb_iop_autonomous_two_xfers] expected 2 INTC asserts, got %0d",
|
|
intc_assert_events);
|
|
errors = errors + 1;
|
|
end
|
|
if (intc_ack_events != 2) begin
|
|
$error("[tb_iop_autonomous_two_xfers] expected 2 INTC acks, got %0d",
|
|
intc_ack_events);
|
|
errors = errors + 1;
|
|
end
|
|
if (wait_irq_exit_events != 2) begin
|
|
$error("[tb_iop_autonomous_two_xfers] expected 2 WAIT_IRQ exits, got %0d",
|
|
wait_irq_exit_events);
|
|
errors = errors + 1;
|
|
end
|
|
if (bne_taken_events != 1) begin
|
|
$error("[tb_iop_autonomous_two_xfers] expected 1 BNE taken, got %0d",
|
|
bne_taken_events);
|
|
errors = errors + 1;
|
|
end
|
|
if (halt_events != 1) begin
|
|
$error("[tb_iop_autonomous_two_xfers] expected 1 halt event, got %0d",
|
|
halt_events);
|
|
errors = errors + 1;
|
|
end
|
|
|
|
$display("[tb_iop_autonomous_two_xfers] ops=%0d wait_irq_exit=%0d bne_taken=%0d halt=%0d done=%0d asserts=%0d acks=%0d errors=%0d",
|
|
exec_op_events, wait_irq_exit_events, bne_taken_events,
|
|
halt_events, dmac_done_events,
|
|
intc_assert_events, intc_ack_events, errors);
|
|
|
|
if (errors == 0 &&
|
|
dmac_done_events == 2 &&
|
|
intc_assert_events == 2 &&
|
|
intc_ack_events == 2 &&
|
|
wait_irq_exit_events == 2 &&
|
|
bne_taken_events == 1 &&
|
|
halt_events == 1)
|
|
$display("[tb_iop_autonomous_two_xfers] PASS");
|
|
else
|
|
$display("[tb_iop_autonomous_two_xfers] FAIL");
|
|
|
|
$finish;
|
|
end
|
|
|
|
initial begin
|
|
#2000000;
|
|
$error("[tb_iop_autonomous_two_xfers] timeout");
|
|
$finish;
|
|
end
|
|
|
|
endmodule : tb_iop_autonomous_two_xfers
|