thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
328 lines
12 KiB
Systemverilog
328 lines
12 KiB
Systemverilog
// retroDE_ps2 — tb_ee_install_agent_smoke (Ch55)
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//
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// Ch55 unit verification: the boot_install_agent_stub, when driven once,
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// streams its Ch54-image payload through sif_dma_ee_ram_bridge_stub into
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// the EE memory map, where the new bridge→useg_shadow shadowing path
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// deposits the image into useg_shadow_mem. The EE CPU read port reads
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// the image back byte-exact.
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//
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// Chain (no IOP, no DMAC — install agent is the dumb producer):
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// boot_install_agent_stub (32-bit beats)
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// └─► sif_dma_ee_ram_bridge_stub (4×32 → 128 qword)
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// └─► ee_memory_map_stub (bridge_wr_* → useg_shadow_mem)
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// └─► ee_ram_stub (also written; verified via readback
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// through the EE CPU port)
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//
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// PASS criteria:
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// 1. boot agent asserts done_o.
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// 2. sif bridge's last_seen_o asserts.
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// 3. Reading useg addresses 0x80..0x1FC via the EE CPU read port
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// returns the exact Ch54 image word-for-word (96 words).
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// 4. No FAIL prints, no timeout.
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`timescale 1ns/1ps
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module tb_ee_install_agent_smoke;
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import trace_pkg::*;
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localparam int EE_RAM_BYTES = 8 * 1024;
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localparam int EE_RAM_ADDR_W = $clog2(EE_RAM_BYTES);
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localparam int TOTAL_WORDS = 96;
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localparam logic [31:0] DEST_BASE_BYTES = 32'h0000_0080;
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localparam logic [31:0] USEG_BASE_ADDR = 32'h0000_0080; // kuseg phys 0x80
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logic clk;
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logic rst_n;
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// ------------------------------------------------------------------
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// Expected payload mirror (built the same way boot_install_agent_stub
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// builds its ROM). Used purely for post-install comparison.
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// ------------------------------------------------------------------
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logic [31:0] expected [0:TOTAL_WORDS-1];
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initial begin
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expected[0] = 32'h401A7000;
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expected[1] = 32'h275A0004;
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expected[2] = 32'h03400008;
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expected[3] = 32'h42000010;
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for (int i = 4; i < TOTAL_WORDS; i = i + 2) begin
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expected[i] = 32'h03E00008;
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expected[i + 1] = 32'h00000000;
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end
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end
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// ------------------------------------------------------------------
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// Install agent
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// ------------------------------------------------------------------
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logic go;
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logic agent_valid;
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logic [31:0] agent_data;
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logic agent_last;
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logic agent_ready;
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logic agent_busy;
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logic agent_done;
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logic agent_ev_valid;
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subsys_e agent_ev_subsys;
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event_e agent_ev_event;
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logic [63:0] agent_ev_arg0, agent_ev_arg1, agent_ev_arg2, agent_ev_arg3;
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logic [31:0] agent_ev_flags;
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boot_install_agent_stub #(
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.TOTAL_WORDS(TOTAL_WORDS),
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.MASTER_ID(8'd6)
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) u_agent (
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.clk(clk), .rst_n(rst_n),
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.go_i(go),
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.out_valid(agent_valid), .out_data(agent_data),
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.out_last(agent_last), .out_ready(agent_ready),
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.busy_o(agent_busy), .done_o(agent_done),
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.ev_valid(agent_ev_valid), .ev_subsys(agent_ev_subsys),
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.ev_event(agent_ev_event),
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.ev_arg0(agent_ev_arg0), .ev_arg1(agent_ev_arg1),
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.ev_arg2(agent_ev_arg2), .ev_arg3(agent_ev_arg3),
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.ev_flags(agent_ev_flags)
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);
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// ------------------------------------------------------------------
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// SIF EE-RAM bridge (agent → 128-bit map write)
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// ------------------------------------------------------------------
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logic br_wr_en;
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logic [31:0] br_wr_addr;
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logic [127:0] br_wr_data;
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logic [15:0] br_wr_be;
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logic [7:0] br_master_id;
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logic br_last_seen;
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sif_dma_ee_ram_bridge_stub #(
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.DEST_BASE_ADDR(DEST_BASE_BYTES),
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.MASTER_ID(8'd5)
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) u_bridge (
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.clk(clk), .rst_n(rst_n),
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.in_valid(agent_valid), .in_data(agent_data),
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.in_last(agent_last), .in_ready(agent_ready),
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.bridge_wr_en(br_wr_en), .bridge_wr_addr(br_wr_addr),
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.bridge_wr_data(br_wr_data), .bridge_wr_be(br_wr_be),
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.bridge_master_id(br_master_id),
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.last_seen_o(br_last_seen)
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);
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// ------------------------------------------------------------------
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// EE memory map + EE RAM
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// ------------------------------------------------------------------
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logic ee_rd_en;
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logic [31:0] ee_rd_addr;
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logic [31:0] ee_rd_data;
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logic ee_rd_valid;
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logic ram_rd_en;
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logic [24:0] ram_rd_addr;
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logic [127:0] ram_rd_data;
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logic ram_rd_valid;
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logic ram_wr_en;
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logic [24:0] ram_wr_addr;
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logic [127:0] ram_wr_data;
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logic [15:0] ram_wr_be;
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logic [7:0] ram_master_id;
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logic map_ev_valid;
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subsys_e map_ev_subsys;
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event_e map_ev_event;
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logic [63:0] map_ev_arg0, map_ev_arg1, map_ev_arg2, map_ev_arg3;
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logic [31:0] map_ev_flags;
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ee_memory_map_stub u_ee_map (
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.clk(clk), .rst_n(rst_n),
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.ee_rd_en(ee_rd_en), .ee_rd_addr(ee_rd_addr),
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.ee_rd_data(ee_rd_data), .ee_rd_valid(ee_rd_valid),
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.ee_wr_en(1'b0), .ee_wr_addr(32'd0),
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.ee_wr_data(32'd0), .ee_wr_be(4'd0),
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.dmac_rd_en(1'b0), .dmac_rd_addr(32'd0),
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.dmac_rd_data(), .dmac_rd_valid(),
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.bridge_wr_en(br_wr_en), .bridge_wr_addr(br_wr_addr),
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.bridge_wr_data(br_wr_data), .bridge_wr_be(br_wr_be),
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.bridge_master_id(br_master_id),
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.bios_rd_en(), .bios_rd_addr(),
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.bios_rd_data(32'd0), .bios_rd_valid(1'b0),
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.ram_rd_en(ram_rd_en), .ram_rd_addr(ram_rd_addr),
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.ram_rd_data(ram_rd_data), .ram_rd_valid(ram_rd_valid),
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.ram_wr_en(ram_wr_en), .ram_wr_addr(ram_wr_addr),
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.ram_wr_data(ram_wr_data), .ram_wr_be(ram_wr_be),
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.ram_master_id(ram_master_id),
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.ee_dmac_ch2_wr_en(), .ee_dmac_ch2_wr_addr(), .ee_dmac_ch2_wr_data(),
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.ee_dmac_ch2_rd_en(), .ee_dmac_ch2_rd_addr(),
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.ee_dmac_ch2_rd_data(32'd0), .ee_dmac_ch2_rd_valid(1'b0),
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.ee_intc_wr_en(), .ee_intc_wr_addr(), .ee_intc_wr_data(),
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.ee_intc_rd_en(), .ee_intc_rd_addr(),
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.ee_intc_rd_data(32'd0), .ee_intc_rd_valid(1'b0),
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.ee_misc_mmio_wr_en(), .ee_misc_mmio_wr_addr(), .ee_misc_mmio_wr_data(), .ee_misc_mmio_wr_be(),
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.ee_misc_mmio_rd_en(), .ee_misc_mmio_rd_addr(),
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.ee_misc_mmio_rd_data(32'd0), .ee_misc_mmio_rd_valid(1'b0),
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.ee_biu_wr_en(), .ee_biu_wr_addr(), .ee_biu_wr_data(), .ee_biu_wr_be(),
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.ee_biu_rd_en(), .ee_biu_rd_addr(),
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.ee_biu_rd_data(32'd0), .ee_biu_rd_valid(1'b0),
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.ev_valid(map_ev_valid), .ev_subsys(map_ev_subsys),
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.ev_event(map_ev_event),
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.ev_arg0(map_ev_arg0), .ev_arg1(map_ev_arg1),
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.ev_arg2(map_ev_arg2), .ev_arg3(map_ev_arg3),
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.ev_flags(map_ev_flags)
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);
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ee_ram_stub #(.SIZE_BYTES(EE_RAM_BYTES)) u_ee_ram (
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.clk(clk), .rst_n(rst_n),
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.rd_en(ram_rd_en), .rd_addr(ram_rd_addr[EE_RAM_ADDR_W-1:0]),
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.rd_data(ram_rd_data), .rd_valid(ram_rd_valid),
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.wr_en(ram_wr_en), .wr_addr(ram_wr_addr[EE_RAM_ADDR_W-1:0]),
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.wr_data(ram_wr_data), .wr_be(ram_wr_be),
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.master_id(ram_master_id),
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.ev_valid(), .ev_subsys(), .ev_event(),
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.ev_arg0(), .ev_arg1(), .ev_arg2(), .ev_arg3(), .ev_flags()
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);
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// ------------------------------------------------------------------
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// Counters / observation
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// ------------------------------------------------------------------
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int agent_start_count;
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int agent_beat_count;
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int agent_done_count;
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int map_useg_writes;
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initial begin
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agent_start_count = 0;
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agent_beat_count = 0;
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agent_done_count = 0;
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map_useg_writes = 0;
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end
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always_ff @(posedge clk) begin
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if (rst_n && agent_ev_valid && agent_ev_subsys == SUBSYS_SIF) begin
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case (agent_ev_event)
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EV_DMA_START: agent_start_count <= agent_start_count + 1;
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EV_DMA_BEAT: agent_beat_count <= agent_beat_count + 1;
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EV_DMA_DONE: agent_done_count <= agent_done_count + 1;
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default: ;
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endcase
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end
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if (rst_n && map_ev_valid && map_ev_subsys == SUBSYS_MEM &&
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map_ev_event == EV_WRITE && map_ev_arg3[7:0] == 8'd1) begin
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// bridge writes to ee_ram emit REGION_EE_RAM; the shadowing
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// side-effect is internal (no separate ev tag). Count these
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// as evidence that bridge actually drove the map.
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map_useg_writes <= map_useg_writes + 1;
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end
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end
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// ------------------------------------------------------------------
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// Readback via EE CPU port (1-cycle latency)
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// ------------------------------------------------------------------
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task automatic ee_read_word(input logic [31:0] addr,
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output logic [31:0] data);
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@(negedge clk);
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ee_rd_en = 1'b1;
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ee_rd_addr = addr;
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@(negedge clk);
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ee_rd_en = 1'b0;
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ee_rd_addr = 32'd0;
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@(posedge clk);
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data = ee_rd_data;
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endtask
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// ------------------------------------------------------------------
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// Main
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// ------------------------------------------------------------------
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int errors;
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int timeout_cycles;
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initial begin
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rst_n = 1'b0;
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go = 1'b0;
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ee_rd_en = 1'b0;
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ee_rd_addr = 32'd0;
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errors = 0;
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timeout_cycles = 0;
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// Reset
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repeat (4) @(posedge clk);
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rst_n = 1'b1;
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repeat (2) @(posedge clk);
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// Kick the installer
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@(negedge clk);
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go = 1'b1;
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@(negedge clk);
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go = 1'b0;
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// Wait for done or timeout
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while (!agent_done && timeout_cycles < 2000) begin
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@(posedge clk);
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timeout_cycles = timeout_cycles + 1;
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end
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if (!agent_done) begin
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$display("[tb_ee_install_agent_smoke] FAIL: timeout waiting for agent done (cyc=%0d)",
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timeout_cycles);
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errors = errors + 1;
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end
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// Drain any in-flight bridge beats (the last qword emit takes
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// one extra cycle after the accumulator fills).
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repeat (8) @(posedge clk);
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if (!br_last_seen) begin
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$display("[tb_ee_install_agent_smoke] FAIL: bridge last_seen never asserted");
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errors = errors + 1;
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end
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// Byte-compare all 96 words through the EE CPU read port.
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for (int i = 0; i < TOTAL_WORDS; i++) begin
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logic [31:0] got;
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ee_read_word(USEG_BASE_ADDR + i * 4, got);
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if (got !== expected[i]) begin
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$display("[tb_ee_install_agent_smoke] FAIL word %0d @0x%08x: got %08x exp %08x",
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i, USEG_BASE_ADDR + i * 4, got, expected[i]);
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errors = errors + 1;
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end
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end
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$display("[tb_ee_install_agent_smoke] start_events=%0d beat_events=%0d done_events=%0d bridge_writes=%0d",
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agent_start_count, agent_beat_count, agent_done_count, map_useg_writes);
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if (agent_start_count != 1) begin
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$display("[tb_ee_install_agent_smoke] FAIL: expected 1 start event, got %0d", agent_start_count);
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errors = errors + 1;
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end
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if (agent_beat_count != TOTAL_WORDS) begin
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$display("[tb_ee_install_agent_smoke] FAIL: expected %0d beat events, got %0d",
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TOTAL_WORDS, agent_beat_count);
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errors = errors + 1;
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end
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if (agent_done_count != 1) begin
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$display("[tb_ee_install_agent_smoke] FAIL: expected 1 done event, got %0d", agent_done_count);
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errors = errors + 1;
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end
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// 96 words / 4 words per qword = 24 bridge qword writes expected
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if (map_useg_writes != TOTAL_WORDS / 4) begin
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$display("[tb_ee_install_agent_smoke] FAIL: expected %0d bridge qword writes, got %0d",
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TOTAL_WORDS / 4, map_useg_writes);
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errors = errors + 1;
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end
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if (errors == 0)
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$display("[tb_ee_install_agent_smoke] PASS");
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else
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$display("[tb_ee_install_agent_smoke] FAIL total=%0d", errors);
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$finish;
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end
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initial begin
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#200000;
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$display("[tb_ee_install_agent_smoke] FAIL: absolute timeout");
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$finish;
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end
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endmodule : tb_ee_install_agent_smoke
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