RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
3.5 KiB
Source Log — Supplemental Pass
Research pass date: 2026-04-16 Pass author: Claude (second research pass, after Codex)
This log covers sources introduced by the supplemental pass. It does not
re-list sources from ../source_log.md; see that file for the Codex pass.
Official Sony manuals
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GS User's Manual v6.0— Sony Computer Entertainment Inc. URL: https://usermanual.wiki/Pdf/GSUsersManual.1012076781/html Notes: primary register reference for the Graphics Synthesizer. Authoritative for0x12000000privileged block and GS packet-form registers. Confidential in origin. -
VU User's Manual (Emotion Engine Vector Operation Unit Guide)— Sony. URL: https://studylib.net/doc/25815876/vuusersmanual.158394566 Notes: primary reference for VU0/VU1 pipeline, register files, memories, micro/macro modes, and VIF coupling. Confidential in origin.
FPGA prior art (adjacent consoles)
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MiSTer-devel/PSX_MiSTer— Robert Peip (FPGAzumSpass) URL: https://github.com/MiSTer-devel/PSX_MiSTer Notes: closest real-world methodology template. Methodology = cycle-accurate software emulator first, RTL second, with emulator as golden model. -
PS-FPGA/ps-fpgaURL: https://github.com/PS-FPGA/ps-fpga Notes: alternate PSX FPGA project. Useful for comparing module decomposition. -
pgate1/PlayStation_on_FPGAURL: https://github.com/pgate1/PlayStation_on_FPGA Notes: smaller-scale PSX FPGA. Reference for minimal scaffold shape.
Architecture studies
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Rodrigo Copetti — "PlayStation 2 Architecture: A Practical Analysis" URL: https://www.copetti.org/writings/consoles/playstation-2/ Notes: high-level pedagogical writeup. Onboarding reading, not a spec.
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psdevwikiPS2 section URL: https://www.psdevwiki.com/ps2/ Notes: community-maintained counterpart tops2tek. Strong on IOP modules, SPU2, peripheral protocols, and hardware revisions. -
VPU Thesis — "A Study on the Feasibility of ... VU [on FPGA]" URL: https://gamehacking.org/faqs/VPUThesis.pdf Notes: academic FPGA-feasibility study specifically on the VU. Directly relevant to Codex workstream 4.
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Wikipedia — PS2 / Emotion Engine URLs: https://en.wikipedia.org/wiki/PlayStation_2_technical_specifications https://en.wikipedia.org/wiki/Emotion_Engine Notes: orientation only.
Community consensus threads
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MiSTer Forum —
Advanced cores for MiSTer future FPGA hardwareURL: https://misterfpga.org/viewtopic.php?t=4884 -
MiSTer Forum —
What Do You Think Will Happen Once MiSTer Reaches Its Limits?URL: https://misterfpga.org/viewtopic.php?t=2512 -
Time Extension —
MiSTer Pi and next-generation FPGA gamingURL: https://www.timeextension.com/news/2025/03/the-next-generation-of-fpga-gaming-could-be-just-around-the-corner-thanks-to-mister-pi
Notes: capture the current community baseline. No public PS2 FPGA core exists; consensus view places PS2 beyond current MiSTer-class fabric; only active public effort is a hybrid PCIe-FPGA + host-CPU arrangement.
Search deltas vs Codex pass
Sources Codex covered and this pass does not re-log:
ps2tek, DobieStationFrom Bits to Pixelswiki,ps2dev,ps2sdk,gsKit,PCSX2,DobieStation,Play-,pcsx2/Memory.cpp.
Sources this pass added that were absent from the Codex log:
- Sony GS User's Manual.
- Sony VU User's Manual.
- PSX_MiSTer, PS-FPGA, PlayStation_on_FPGA (adjacent-console FPGA prior art).
- Copetti architecture writeup.
psdevwikiPS2 section.- VPU thesis.
- MiSTer community consensus threads on PS2 feasibility.