thejayman77
ba74bbd5aa
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog TBs, fidelity attribution tooling. Functional baseline before removing the dead bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
68 lines
3.2 KiB
Markdown
68 lines
3.2 KiB
Markdown
# Ch424 — restore the full scene population under native 12.4 coverage
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## Root cause
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Ch416 was described as a one-variable native-subpixel conversion of Ch415,
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but its fixture was regenerated from only 113 draw IDs. Ch415 actually fed
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766 captured draws grouped into 254 compatible state runs. The 113 IDs were
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only the surviving groups' representative indices, so treating them as the
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source draw list silently discarded most of the scene. The resulting
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software reference already contained the long spike/band geometry later seen
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bit-exactly in simulation and on the board; this was not an FPGA timing fault.
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The `--legacy-strip-kicks` compatibility switch also ignored captured ADC
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kick suppression. Ch424 uses the parsed kick semantics and does not enable
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that switch.
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## Fixture repair
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`sh3_zsrt139f19` starts from the audited 766-draw / 254-group plan in
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`/tmp/sh3_opaque_qclip_plan.json`, retains authentic chronological grouping,
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and enables the already-proven production feature set:
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- authentic Z, color modulation, zero-color fog fold, and bilinear reference;
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- native GS XYZ 12.4 coordinates and pixel-center coverage;
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- authentic scissor clipping and normalized full-region clamp;
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- runtime CLUT staging and 14,500-fragment capacity epochs;
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- parsed ADC/kick behavior, with no legacy strip override.
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The repaired fixture schedules 125 epochs. Its software reference restores
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the coherent booth, floor, lamp, character, fence, and bench geometry. With
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the accepted Ch418 scanout mapping, comparison against the PCSX2 224139 frame
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is MAE 18.5560 / RMSE 26.2740. The raw 640x480 buffer is MAE 21.0802 / RMSE
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32.3348.
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## Acceptance gates
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- Production-gradient full RTL replay must finish all 125 epochs with zero
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drops and exact final Z/color comparisons.
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- The unchanged, timing-clean Ch423 RBF must pass the same fixture on hardware.
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- The board framebuffer must match the production-gradient RTL framebuffer
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bit for bit before Ch424 becomes the visible baseline.
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## Production RTL acceptance
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The production registered-gradient Verilator replay completed all 125 epochs:
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157,208 fragments were fed, 138,825 passed Z, fragment drops remained zero,
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and the final comparisons reported 0/307,200 Z mismatches and 0/114,550 color
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mismatches. Marker/drain counts were complete, `col_ovf=0`,
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`bresp_err=0`, and the testbench finished PASS.
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The raw RTL frame measures MAE 22.9740 / RMSE 33.6203 against PCSX2. Through
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the accepted Ch418 scanout mapping it measures MAE 20.9469 / RMSE 29.7626.
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Unlike the lower scalar score previously claimed for Ch416, this frame also
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passes the essential visual gate: its scene topology is coherent rather than
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dominated by false long triangles.
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## Board acceptance
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No new fit was required. The timing-clean Ch423 RBF ran the new assets and
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passed every one of the 125 texture CRC, runtime-palette, staging-record,
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drain, and zero-drop gates. The board dumped 307,200 words with 114,504
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nonzero pixels, bounds `(0,10)..(511,479)`, sum32 `0x42ee1faa`, and xor32
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`0x0dc19c66`; HDMI was switched to the resulting line-buffer scanout.
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The board and production RTL framebuffer dumps are byte-identical. Both have
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SHA-256 `2bd7a81d3650c00b1397d5196713634bbd4c87a5e607b75bcf0df346cb7b3126`.
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Ch424 is accepted as the new visible baseline.
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