thejayman77/retroDE_ps2
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity

Initial commit: retroDE_ps2 — first-of-its-kind PS2 GS FPGA core (DE25-Nano / Agilex 5)

Browse Source 
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression
(272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps,
and all dump-derived textures/traces) is excluded via .gitignore and stays local.

Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
This commit is contained in:
thejayman77
2026-06-29 20:10:50 -04:00
commit ec82764bef
2462 changed files with 2174303 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files
sim/tb/top/tb_de25_nano_psmct32_raster_demo_top.sv
+383
View File
@@ -0,0 +1,383 @@
// retroDE_ps2 — tb_de25_nano_psmct32_raster_demo_top (Ch149)
//
// Smoke TB for the DE25-Nano board wrapper. Exercises the
// board-shaped path end-to-end:
//
// 1. Drive CLOCK2_50 (the only used clock).
// 2. Hold KEY[0] LOW (active-low push button "pressed") for a
// handful of cycles, then release HIGH.
// 3. Verify the board top's reset-release sequencer pulses
// `core_go` exactly once after the reset deassert + GO_DELAY
// cycles.
// 4. Verify the three sticky status outputs (LED[2:0]) all
// eventually latch. (The fall-edge order is actually
// frame_seen → core_halt → dma_done_seen because frame_seen
// fires on the first empty PCRTC frame after reset; the TB
// doesn't lock the order — see the rationale below.)
// 5. Verify the raw video pins are driven (DE goes high inside
// the active region).
//
// This is NOT a re-verification of the Ch146 wrapper — that's
// already covered by tb_top_psmct32_raster_demo. The Ch149 TB only
// validates the BOARD plumbing (clock/reset/core_go sequencer +
// LED polarity + raw video pass-through).
`timescale 1ns/1ps
module tb_de25_nano_psmct32_raster_demo_top;
// ----------------------------------------------------------------
// Board-shaped DUT inputs.
// ----------------------------------------------------------------
logic CLOCK0_50;
logic CLOCK1_50;
logic CLOCK2_50;
logic [1:0] KEY;
logic [3:0] SW;
// Tied off — only CLOCK2_50 + KEY[0] are exercised.
initial CLOCK0_50 = 1'b0;
initial CLOCK1_50 = 1'b0;
always #10 CLOCK2_50 = ~CLOCK2_50; // 50 MHz
initial CLOCK2_50 = 1'b0;
initial SW = 4'b0000;
// ----------------------------------------------------------------
// Board-shaped DUT outputs.
// ----------------------------------------------------------------
logic [7:0] LED;
logic [7:0] VIDEO_R;
logic [7:0] VIDEO_G;
logic [7:0] VIDEO_B;
logic VIDEO_HSYNC;
logic VIDEO_VSYNC;
logic VIDEO_DE;
// Ch164 HDMI data path (board-real outputs); TB doesn't
// observe them — just elaborates them so the wrapper is
// valid.
logic HDMI_TX_CLK;
logic [23:0] HDMI_TX_D;
logic HDMI_TX_HS;
logic HDMI_TX_VS;
logic HDMI_TX_DE;
// Ch165 ADV7513 control bus. Sim doesn't model the I²C
// pull-ups or the chip's slave-side ACK; the bus floats and
// the wake-up FSM walks the LUT taking many milliseconds of
// sim time (the 5 ms TB timeout doesn't cover full LUT
// completion — that's intentional, this TB pre-dates the
// wake-up FSM and only smoke-tests the wrapper). HDMI_TX_INT
// is held high (deasserted active-low interrupt) so the FSM
// doesn't retrigger init mid-walk.
wire HDMI_I2C_SCL;
wire HDMI_I2C_SDA;
logic HDMI_TX_INT;
logic HDMI_MCLK;
initial HDMI_TX_INT = 1'b1;
// Ch170 — HPS + LPDDR4A ports the qsys platform shell needs.
// Sim doesn't model the HPS hard IP behavior; all inputs hold a
// safe constant and all outputs/inouts are just elaborated so the
// wrapper is valid. The qsys_top instance still sits inside the
// DUT — if anything breaks elaboration we see it here.
logic LPDDR4A_REFCLK_p;
wire LPDDR4A_CS_n;
wire [5:0] LPDDR4A_CA;
wire LPDDR4A_CK;
wire LPDDR4A_CKE;
wire LPDDR4A_CK_n;
wire [3:0] LPDDR4A_DM;
wire [31:0] LPDDR4A_DQ;
wire [3:0] LPDDR4A_DQS;
wire [3:0] LPDDR4A_DQS_n;
wire LPDDR4A_RESET_n;
logic LPDDR4A_RZQ;
initial LPDDR4A_REFCLK_p = 1'b0;
initial LPDDR4A_RZQ = 1'b0;
logic HPS_CLK_25;
wire HPS_ENET_MDC;
wire HPS_ENET_MDIO;
logic HPS_ENET_RX_CLK;
logic HPS_ENET_RX_CTL;
logic [3:0] HPS_ENET_RX_DATA;
wire HPS_ENET_TX_CLK;
wire HPS_ENET_TX_CTL;
wire [3:0] HPS_ENET_TX_DATA;
wire HPS_GSENSOR_I2C_EN;
wire HPS_GSENSOR_INT;
wire HPS_I2C_SCL;
wire HPS_I2C_SDA;
wire HPS_KEY;
wire HPS_LED;
wire HPS_SD_CLK;
wire HPS_SD_CMD;
wire [3:0] HPS_SD_DATA;
logic HPS_UART_RX;
wire HPS_UART_TX;
logic HPS_USB_CLK;
wire [7:0] HPS_USB_DATA;
logic HPS_USB_DIR;
logic HPS_USB_NXT;
wire HPS_USB_STP;
initial begin
HPS_CLK_25 = 1'b0;
HPS_ENET_RX_CLK = 1'b0;
HPS_ENET_RX_CTL = 1'b0;
HPS_ENET_RX_DATA = 4'b0;
HPS_UART_RX = 1'b1;
HPS_USB_CLK = 1'b0;
HPS_USB_DIR = 1'b0;
HPS_USB_NXT = 1'b0;
end
de25_nano_psmct32_raster_demo_top dut (
.CLOCK0_50(CLOCK0_50),
.CLOCK1_50(CLOCK1_50),
.CLOCK2_50(CLOCK2_50),
.KEY(KEY),
.SW(SW),
.LED(LED),
.VIDEO_R(VIDEO_R),
.VIDEO_G(VIDEO_G),
.VIDEO_B(VIDEO_B),
.VIDEO_HSYNC(VIDEO_HSYNC),
.VIDEO_VSYNC(VIDEO_VSYNC),
.VIDEO_DE(VIDEO_DE),
.HDMI_TX_CLK(HDMI_TX_CLK),
.HDMI_TX_D(HDMI_TX_D),
.HDMI_TX_HS(HDMI_TX_HS),
.HDMI_TX_VS(HDMI_TX_VS),
.HDMI_TX_DE(HDMI_TX_DE),
.HDMI_I2C_SCL(HDMI_I2C_SCL),
.HDMI_I2C_SDA(HDMI_I2C_SDA),
.HDMI_TX_INT(HDMI_TX_INT),
.HDMI_MCLK(HDMI_MCLK),
// Ch170 — HPS/LPDDR4A pass-through to qsys_top inside DUT.
.LPDDR4A_REFCLK_p (LPDDR4A_REFCLK_p),
.LPDDR4A_CS_n (LPDDR4A_CS_n),
.LPDDR4A_CA (LPDDR4A_CA),
.LPDDR4A_CK (LPDDR4A_CK),
.LPDDR4A_CKE (LPDDR4A_CKE),
.LPDDR4A_CK_n (LPDDR4A_CK_n),
.LPDDR4A_DM (LPDDR4A_DM),
.LPDDR4A_DQ (LPDDR4A_DQ),
.LPDDR4A_DQS (LPDDR4A_DQS),
.LPDDR4A_DQS_n (LPDDR4A_DQS_n),
.LPDDR4A_RESET_n (LPDDR4A_RESET_n),
.LPDDR4A_RZQ (LPDDR4A_RZQ),
.HPS_CLK_25 (HPS_CLK_25),
.HPS_ENET_MDC (HPS_ENET_MDC),
.HPS_ENET_MDIO (HPS_ENET_MDIO),
.HPS_ENET_RX_CLK (HPS_ENET_RX_CLK),
.HPS_ENET_RX_CTL (HPS_ENET_RX_CTL),
.HPS_ENET_RX_DATA (HPS_ENET_RX_DATA),
.HPS_ENET_TX_CLK (HPS_ENET_TX_CLK),
.HPS_ENET_TX_CTL (HPS_ENET_TX_CTL),
.HPS_ENET_TX_DATA (HPS_ENET_TX_DATA),
.HPS_GSENSOR_I2C_EN (HPS_GSENSOR_I2C_EN),
.HPS_GSENSOR_INT (HPS_GSENSOR_INT),
.HPS_I2C_SCL (HPS_I2C_SCL),
.HPS_I2C_SDA (HPS_I2C_SDA),
.HPS_KEY (HPS_KEY),
.HPS_LED (HPS_LED),
.HPS_SD_CLK (HPS_SD_CLK),
.HPS_SD_CMD (HPS_SD_CMD),
.HPS_SD_DATA (HPS_SD_DATA),
.HPS_UART_RX (HPS_UART_RX),
.HPS_UART_TX (HPS_UART_TX),
.HPS_USB_CLK (HPS_USB_CLK),
.HPS_USB_DATA (HPS_USB_DATA),
.HPS_USB_DIR (HPS_USB_DIR),
.HPS_USB_NXT (HPS_USB_NXT),
.HPS_USB_STP (HPS_USB_STP)
);
// ----------------------------------------------------------------
// Observers.
// ----------------------------------------------------------------
int core_go_pulse_count;
int errors;
bit saw_video_de;
// Latch the falling-edge time of each status LED so the
// post-test order check is real (the sequential `wait` block
// below would pass even if the LEDs lit out of order — the
// test would just block on the slowest one).
time t_led0_fall, t_led1_fall, t_led2_fall;
logic [2:0] led_d;
// Ch151 — capture the rising-edge times of pll_locked,
// core_rst_n, and core_go. The hardware contract is:
// pll_locked rises < core_rst_n rises < core_go fires
// i.e., the PLL must lock before the reset bridge can release,
// and core_go can only pulse after reset deasserts.
time t_pll_locked_rise, t_core_rst_n_rise, t_core_go_rise;
logic pll_locked_d, core_rst_n_d, core_go_dbg_d;
initial begin
core_go_pulse_count = 0;
errors = 0;
saw_video_de = 1'b0;
t_led0_fall = 64'h0;
t_led1_fall = 64'h0;
t_led2_fall = 64'h0;
t_pll_locked_rise = 64'h0;
t_core_rst_n_rise = 64'h0;
t_core_go_rise = 64'h0;
end
// Count rising edges of dut.core_go to verify exactly one pulse.
logic core_go_d;
always_ff @(posedge CLOCK2_50) begin
core_go_d <= dut.core_go;
if (dut.core_go && !core_go_d)
core_go_pulse_count <= core_go_pulse_count + 1;
end
// Capture rising-edge timestamps for the Ch151 PLL contract.
always_ff @(posedge CLOCK2_50) begin
pll_locked_d <= dut.pll_locked;
core_rst_n_d <= dut.core_rst_n;
core_go_dbg_d <= dut.core_go;
if (dut.pll_locked && !pll_locked_d && t_pll_locked_rise == 0)
t_pll_locked_rise <= $time;
if (dut.core_rst_n && !core_rst_n_d && t_core_rst_n_rise == 0)
t_core_rst_n_rise <= $time;
if (dut.core_go && !core_go_dbg_d && t_core_go_rise == 0)
t_core_go_rise <= $time;
end
// Watch for video DE — proves the wrapper's PCRTC scanned
// out at least one active pixel.
always_ff @(posedge CLOCK2_50) begin
if (VIDEO_DE) saw_video_de <= 1'b1;
end
// Capture the first falling edge of each status LED.
always_ff @(posedge CLOCK2_50) begin
led_d <= LED[2:0];
if (led_d[0] && !LED[0] && t_led0_fall == 0) t_led0_fall <= $time;
if (led_d[1] && !LED[1] && t_led1_fall == 0) t_led1_fall <= $time;
if (led_d[2] && !LED[2] && t_led2_fall == 0) t_led2_fall <= $time;
end
// ----------------------------------------------------------------
// Drive sequence.
// ----------------------------------------------------------------
initial begin
// Reset: KEY[0] LOW (button "pressed").
KEY = 2'b10;
// Wait for ninit_done to drop (the inline stub's 16-cycle
// timer) + a few extra cycles, then release the button.
repeat (32) @(posedge CLOCK2_50);
KEY[0] = 1'b1; // release
// Ch251 — the production bootlet now LOOPS FOREVER instead of
// SYSCALL-halting after one DMAC kick. The boot-success
// indicators changed accordingly:
// - LED[1] (dma_done_seen) — DMAC completed at least one
// transfer, same as before.
// - LED[2] (frame_seen) — PCRTC produced a frame, same.
// - LED[0] (core_halt) — **stays unlit** in steady state for
// the animated demo. We don't wait on it here.
// The TB lets the loop run long enough that we observe both
// LED[1] and LED[2] latch, then samples final state. The
// EE-loop liveness assertion in CORE_STATUS via the bridge is
// outside this TB's scope.
wait (LED[1] == 1'b0);
$display("[tb_de25_nano] LED[1] (dma_done_seen) lit");
wait (LED[2] == 1'b0);
$display("[tb_de25_nano] LED[2] (frame_seen) lit");
// Settle a few more cycles, then check status / counters.
repeat (50) @(posedge CLOCK2_50);
// Exactly one core_go pulse fired.
if (core_go_pulse_count != 1) begin
$error("core_go pulse_count=%0d (expected 1)", core_go_pulse_count);
errors = errors + 1;
end
// Ch251 — LED[1:2] light during the animated demo; LED[0]
// must STAY UNLIT (core_halt=0, loop running). LED[7:3] are
// expected OFF (no DS2/HDMI alarms in the sim path, no
// gamepad buttons held).
if (LED[0] !== 1'b1) begin
$error("LED[0]=%b (expected 1=unlit: animated bootlet loops, core_halt=0)", LED[0]);
errors = errors + 1;
end
if (LED[7:3] !== 5'b11111) begin
$error("LED[7:3]=%b (expected 5'b11111 = all OFF)", LED[7:3]);
errors = errors + 1;
end
// LED[1] and LED[2] must have latched at least once. LED[0]
// is intentionally not in this check (Ch251: loop runs, never
// halts — see LED ledger in the runbook).
if (t_led1_fall == 0 || t_led2_fall == 0) begin
$error("status LEDs LED[1]/LED[2] did not latch (t_led1=%0t t_led2=%0t)",
t_led1_fall, t_led2_fall);
errors = errors + 1;
end
// Ch151 PLL contract: pll_locked rises < core_rst_n rises < core_go.
if (t_pll_locked_rise == 0) begin
$error("pll_locked never rose");
errors = errors + 1;
end
if (t_core_rst_n_rise == 0) begin
$error("core_rst_n never deasserted");
errors = errors + 1;
end
if (t_core_go_rise == 0) begin
$error("core_go never pulsed");
errors = errors + 1;
end
if (t_pll_locked_rise != 0 && t_core_rst_n_rise != 0
&& t_pll_locked_rise >= t_core_rst_n_rise) begin
$error("PLL contract: pll_locked (%0t) must rise before core_rst_n (%0t)",
t_pll_locked_rise, t_core_rst_n_rise);
errors = errors + 1;
end
if (t_core_rst_n_rise != 0 && t_core_go_rise != 0
&& t_core_rst_n_rise >= t_core_go_rise) begin
$error("PLL contract: core_rst_n (%0t) must rise before core_go (%0t)",
t_core_rst_n_rise, t_core_go_rise);
errors = errors + 1;
end
// Video pipe drove DE at some point.
if (!saw_video_de) begin
$error("VIDEO_DE never asserted");
errors = errors + 1;
end
$display("[tb_de25_nano_psmct32_raster_demo_top] LED=0b%b core_go_pulses=%0d saw_video_de=%0b t_led=(%0t,%0t,%0t) t_pll/rstn/go=(%0t,%0t,%0t) errors=%0d",
LED, core_go_pulse_count, saw_video_de,
t_led0_fall, t_led1_fall, t_led2_fall,
t_pll_locked_rise, t_core_rst_n_rise, t_core_go_rise, errors);
if (errors == 0)
$display("[tb_de25_nano_psmct32_raster_demo_top] PASS");
else
$display("[tb_de25_nano_psmct32_raster_demo_top] FAIL");
$finish;
end
// Watchdog. Ch169 — bumped from 20 ms to 30 ms because the board
// wrapper now overrides PCRTC timing to VGA 640x480@60Hz; a full
// frame is H_TOTAL*V_TOTAL = 800*525 = 420k pixels, which at the
// sim clock (50 MHz, since the sim pass-through PLL stub mirrors
// CLOCK2_50) takes ~8.4 ms simulated. `frame_seen` is sticky and
// latches only on end-of-frame, so we need to leave room for that
// plus the post-frame checks.
initial begin
#30000000;
$error("[tb_de25_nano_psmct32_raster_demo_top] TIMEOUT");
$finish;
end
endmodule : tb_de25_nano_psmct32_raster_demo_top
sim/tb/top/tb_gs_raster_backpressure_stress.sv
+362
View File
@@ -0,0 +1,362 @@
// retroDE_ps2 — tb_gs_raster_backpressure_stress
// =============================================================================
// Ch172 backpressure acceptance TB. Demonstrates that:
//
// 1. A GIF stream with more sprites than the raster command FIFO depth
// now completes WITHOUT dropping any primitive (in Ch171 this would
// have been a `push_drop` silent loss).
// 2. While the FIFO is full, `gif_in_ready` (= `dmac_gif_ready`) goes
// LOW for at least one cycle — the upstream stall actually happens.
// 3. The final VRAM contents match the per-sprite expected colors at
// every probed coordinate.
// 4. `raster_overflow` stays LOW the entire run.
// 5. The DMA still asserts done after backpressure clears.
//
// Strategy: build an 8-SPRITE payload procedurally inside the TB (rather
// than `$readmemh` from baked .mem files) and shove it through the same
// `top_psmct32_raster_demo_bram` instance the board uses, with backpressure
// hooked up. 8 sprites × FIFO_DEPTH=2 means 6 of the 8 sprites would have
// dropped under Ch171's no-backpressure regime — under Ch172 backpressure
// all 8 complete.
//
// We use a smaller per-sprite raster footprint (40×30 pixels each, 8 sprites
// tiled across the 320×240 paint area) so the sim watchdog is comfortable.
// =============================================================================
`timescale 1ns/1ps
module tb_gs_raster_backpressure_stress;
// Match the board-wrapper Ch169 + Ch171 + Ch172 overrides.
localparam int H_ACTIVE = 640;
localparam int V_ACTIVE = 480;
localparam int H_FRONT = 16;
localparam int H_SYNC_W = 96;
localparam int H_BACK = 48;
localparam int V_FRONT = 10;
localparam int V_SYNC_W = 2;
localparam int V_BACK = 33;
localparam int VRAM_BYTES = 512 * 1024;
localparam int N_SPRITES = 8;
localparam int SPRITE_W = 40;
localparam int SPRITE_H = 30;
// Per-sprite tile layout: 4 across × 2 down, each tile 80×60 of the
// 320×240 paint region. Within each tile, fill the upper-left 40×30
// (the sprite) so adjacent tiles don't overlap.
function automatic int sprite_x0(input int s); return (s % 4) * 80; endfunction
function automatic int sprite_y0(input int s); return (s / 4) * 60; endfunction
function automatic int sprite_x1(input int s); return sprite_x0(s) + SPRITE_W - 1; endfunction
function automatic int sprite_y1(input int s); return sprite_y0(s) + SPRITE_H - 1; endfunction
// 8 distinct colors so every sprite is identifiable on a VRAM probe.
function automatic logic [7:0] sprite_r(input int s);
case (s)
0: return 8'hFF; 1: return 8'h00; 2: return 8'h00; 3: return 8'hFF;
4: return 8'hFF; 5: return 8'h00; 6: return 8'hFF; 7: return 8'h80;
default: return 8'h00;
endcase
endfunction
function automatic logic [7:0] sprite_g(input int s);
case (s)
0: return 8'h00; 1: return 8'hFF; 2: return 8'h00; 3: return 8'hFF;
4: return 8'h00; 5: return 8'hFF; 6: return 8'h80; 7: return 8'h80;
default: return 8'h00;
endcase
endfunction
function automatic logic [7:0] sprite_b(input int s);
case (s)
0: return 8'h00; 1: return 8'h00; 2: return 8'hFF; 3: return 8'h00;
4: return 8'hFF; 5: return 8'hFF; 6: return 8'h00; 7: return 8'h80;
default: return 8'h00;
endcase
endfunction
// =========================================================
// DUT
// =========================================================
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.H_FRONT (H_FRONT),
.H_SYNC (H_SYNC_W),
.H_BACK (H_BACK),
.V_FRONT (V_FRONT),
.V_SYNC (V_SYNC_W),
.V_BACK (V_BACK),
.VRAM_BYTES (VRAM_BYTES),
// Ch252 — mirror the hardware build profile (PSMCT32 only,
// no PSMT4 RMW) to clear the replication-tripwire $fatal.
.VRAM_ENABLE_READ2 (1'b0)
) dut (
// Ch255 — heartbeat override inputs are dormant in this
// stress TB; coverage of the override path itself lives in
// tb_top_psmct32_raster_demo_bram_ch171.
.joy_a_pressed_i (1'b0),
.joy_b_pressed_i (1'b0),
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen)
);
// =========================================================
// Observers
// =========================================================
bit saw_in_ready_low; // backpressure asserted at least once
int in_ready_low_cycles; // total cycles in_ready was LOW
bit saw_raster_overflow; // should NEVER fire under Ch172
always_ff @(posedge clk) begin
if (rst_n) begin
if (!dut.u_gif.in_ready) begin
saw_in_ready_low <= 1'b1;
in_ready_low_cycles <= in_ready_low_cycles + 1;
end
if (dut.u_gs.raster_overflow)
saw_raster_overflow <= 1'b1;
end
end
// =========================================================
// PSMCT32 page/block address reference (FBW=5 for 320-wide
// framebuffer, matches Ch171 bake.py + board wrapper).
// =========================================================
function automatic int ref_block_idx_ct32(input int by, input int bx);
case ({by[1:0], bx[2:0]})
5'd0: return 0; 5'd1: return 1; 5'd2: return 4; 5'd3: return 5;
5'd4: return 16; 5'd5: return 17; 5'd6: return 20; 5'd7: return 21;
5'd8: return 2; 5'd9: return 3; 5'd10: return 6; 5'd11: return 7;
5'd12: return 18; 5'd13: return 19; 5'd14: return 22; 5'd15: return 23;
5'd16: return 8; 5'd17: return 9; 5'd18: return 12; 5'd19: return 13;
5'd20: return 24; 5'd21: return 25; 5'd22: return 28; 5'd23: return 29;
5'd24: return 10; 5'd25: return 11; 5'd26: return 14; 5'd27: return 15;
5'd28: return 26; 5'd29: return 27; 5'd30: return 30; default: return 31;
endcase
endfunction
function automatic int ref_addr_psmct32(input int x_v, input int y_v);
int page_x, page_y, page_idx, page_base;
int by, bx, blk_idx, xb, yb;
page_x = x_v / 64;
page_y = y_v / 32;
page_idx = page_y * 5 + page_x; // fbw=5
page_base = page_idx * 8192;
by = (y_v % 32) / 8;
bx = (x_v % 64) / 8;
blk_idx = ref_block_idx_ct32(by, bx);
xb = x_v % 8;
yb = y_v % 8;
return page_base + blk_idx * 256 + yb * 32 + xb * 4;
endfunction
// =========================================================
// Procedural bootlet + payload preload. The board path uses
// $readmemh; here we bypass that by writing directly into the
// ee_ram and bios_rom backings via hierarchical refs at time 0
// (before reset deasserts). This keeps the TB self-contained:
// 8-sprite GIF payload built in SystemVerilog without a baked
// .mem.
//
// Module-scope ints for the build loop (iverilog 12 quirk —
// declarations-with-initializers inside loop bodies silently
// zero-out; Ch171 caught this in tb_top_..._bram_ch171).
// =========================================================
localparam int QWC_TOTAL = N_SPRITES * 6; // 6 qwords per sprite (1 tag + 5 A+D)
int build_i;
int build_qw_base;
int build_s;
int build_eop;
int probe_x_v, probe_y_v, probe_addr;
logic [31:0] probe_got, probe_expected;
int errors;
// Helper: assemble a 128-bit qword via SystemVerilog concatenation.
function automatic logic [127:0] mk_giftag(input int nloop, input int eop);
// {regs[63:0]=0xE_EEEE, NREG=5 in [63:60], FLG=0 in [59:58],
// 42'd0, EOP at bit 15, NLOOP at [14:0]} -> lower 64 bits
// Upper 64 bits = REGS = 5 nibbles of 0xE.
logic [63:0] lower;
lower = '0;
lower[63:60] = 4'd5; // NREG = 5
lower[59:58] = 2'd0; // FLG = PACKED
lower[15] = eop[0]; // EOP
lower[14:0] = nloop[14:0]; // NLOOP
return {64'h0000_0000_000E_EEEE, lower};
endfunction
function automatic logic [127:0] mk_aplusd(input int reg_num, input logic [63:0] data64);
return { 56'd0, reg_num[7:0], data64 };
endfunction
function automatic logic [63:0] mk_xyz2(input int x, input int y);
logic [63:0] v;
v = '0;
v[15:4] = x[11:0];
v[31:20] = y[11:0];
return v;
endfunction
function automatic logic [63:0] mk_rgbaq(input logic [7:0] rr, input logic [7:0] gg, input logic [7:0] bb);
return {32'd0, 8'hFF, bb, gg, rr};
endfunction
// GIF register-number constants (match bake.py).
localparam int RN_PRIM = 8'h00;
localparam int RN_RGBAQ = 8'h01;
localparam int RN_XYZ2 = 8'h05;
localparam int RN_FRAME_1 = 8'h4C;
localparam logic [63:0] FRAME_1_PSMCT32_FBW5 = 64'h0000_0000_0005_0000; // FBW=5 in bits[21:16]
localparam logic [63:0] PRIM_SPRITE = 64'd6;
// EE bootlet: same shape as bake.py's Ch171 bootlet (with
// DISPLAY1_hi for 320×240, DISPFB1 FBW=5, kick DMAC ch2 with
// QWC = N_SPRITES * 6). Encoded as 32-bit MIPS words.
function automatic logic [31:0] enc_lui(input int rt, input int imm);
return (32'h0F << 26) | (rt[4:0] << 16) | imm[15:0];
endfunction
function automatic logic [31:0] enc_ori(input int rt, input int rs, input int imm);
return (32'h0D << 26) | (rs[4:0] << 21) | (rt[4:0] << 16) | imm[15:0];
endfunction
function automatic logic [31:0] enc_sw(input int rt, input int rs, input int imm);
return (32'h2B << 26) | (rs[4:0] << 21) | (rt[4:0] << 16) | imm[15:0];
endfunction
initial begin
// ---- Build the 8-sprite payload directly into ee_ram_stub ----
// PAYLOAD_MADR = 0x100 = qword index 16 (16-byte qwords).
build_qw_base = 16;
for (build_s = 0; build_s < N_SPRITES; build_s++) begin
build_eop = (build_s == N_SPRITES - 1) ? 1 : 0;
dut.u_ram.mem[build_qw_base + build_s*6 + 0] = mk_giftag(1, build_eop);
dut.u_ram.mem[build_qw_base + build_s*6 + 1] = mk_aplusd(RN_PRIM, PRIM_SPRITE);
dut.u_ram.mem[build_qw_base + build_s*6 + 2] = mk_aplusd(RN_FRAME_1, FRAME_1_PSMCT32_FBW5);
dut.u_ram.mem[build_qw_base + build_s*6 + 3] = mk_aplusd(RN_RGBAQ,
mk_rgbaq(sprite_r(build_s), sprite_g(build_s), sprite_b(build_s)));
dut.u_ram.mem[build_qw_base + build_s*6 + 4] = mk_aplusd(RN_XYZ2,
mk_xyz2(sprite_x0(build_s), sprite_y0(build_s)));
dut.u_ram.mem[build_qw_base + build_s*6 + 5] = mk_aplusd(RN_XYZ2,
mk_xyz2(sprite_x1(build_s), sprite_y1(build_s)));
end
// ---- Build the EE bootlet directly into bios_rom_stub ----
// (Mirrors bake.py's bootlet_for_display1_hi() with FBW=5 +
// DW=319/DH=239 and QWC=N_SPRITES*6.)
dut.u_bios.mem[0] = enc_lui( 1, 16'h1200); // r1 = 0x1200_0000
dut.u_bios.mem[1] = enc_lui( 2, 16'h0000); // r2 = 0
dut.u_bios.mem[2] = enc_ori( 2, 2, 16'h0A00); // DISPFB1 = FBW=5, PSM=PSMCT32
dut.u_bios.mem[3] = enc_sw ( 2, 1, 16'h0070); // *DISPFB1 = r2
dut.u_bios.mem[4] = enc_sw ( 0, 1, 16'h0080); // *DISPLAY1_lo = 0
dut.u_bios.mem[5] = enc_lui( 2, 16'h000E); // DISPLAY1_hi upper
dut.u_bios.mem[6] = enc_ori( 2, 2, 16'hF13F); // DISPLAY1_hi lower (DW=319/DH=239)
dut.u_bios.mem[7] = enc_sw ( 2, 1, 16'h0084); // *DISPLAY1_hi = r2
dut.u_bios.mem[8] = enc_ori( 2, 0, 16'h0001); // r2 = PMODE.EN1
dut.u_bios.mem[9] = enc_sw ( 2, 1, 16'h0000); // *PMODE = r2
dut.u_bios.mem[10] = enc_lui(10, 16'h1000); // r10 = 0x1000_0000
dut.u_bios.mem[11] = enc_ori(10, 10, 16'hA000); // r10 = DMAC ch2 base
dut.u_bios.mem[12] = enc_ori(11, 0, 16'h0100); // r11 = PAYLOAD_MADR
dut.u_bios.mem[13] = enc_sw (11, 10, 16'h0010); // *MADR = r11
dut.u_bios.mem[14] = enc_ori(11, 0, QWC_TOTAL[15:0]); // r11 = QWC = N_SPRITES*6
dut.u_bios.mem[15] = enc_sw (11, 10, 16'h0020); // *QWC = r11
dut.u_bios.mem[16] = enc_ori(11, 0, 16'h0001); // r11 = CHCR.start
dut.u_bios.mem[17] = enc_sw (11, 10, 16'h0000); // *CHCR = r11
dut.u_bios.mem[18] = 32'h0000_000C; // syscall (halt)
// Zero pad the rest so undefined memory reads stay quiet.
for (build_i = 19; build_i < 1024; build_i++)
dut.u_bios.mem[build_i] = 32'h0000_0000;
errors = 0;
saw_in_ready_low = 1'b0;
in_ready_low_cycles = 0;
saw_raster_overflow = 1'b0;
rst_n = 1'b0;
core_go = 1'b0;
repeat (10) @(posedge clk);
rst_n = 1'b1;
repeat (4) @(posedge clk);
@(negedge clk); core_go = 1'b1;
@(negedge clk); core_go = 1'b0;
// Wait for the EE bootlet to finish + DMAC/GIF/raster to drain.
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1) wait (dut.xfer_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1) wait (dut.u_gs.raster_active == 1'b0);
repeat (40) @(posedge clk);
// -----------------------------------------------------
// Acceptance check 1 — backpressure was observed.
// -----------------------------------------------------
if (!saw_in_ready_low) begin
$error("[bp] in_ready never went low — backpressure did not assert despite 8 sprites in flight");
errors = errors + 1;
end
if (in_ready_low_cycles == 0) begin
// Same as above but counted explicitly so the
// pass-message can report the stall duration.
errors = errors + 1;
end
// -----------------------------------------------------
// Acceptance check 2 — no raster_overflow.
// -----------------------------------------------------
if (saw_raster_overflow) begin
$error("[bp] raster_overflow latched during stress — at least one primitive was dropped");
errors = errors + 1;
end
// -----------------------------------------------------
// Acceptance check 3 — every sprite's center pixel
// landed in VRAM with the right color.
// -----------------------------------------------------
for (build_s = 0; build_s < N_SPRITES; build_s++) begin
probe_x_v = sprite_x0(build_s) + SPRITE_W/2;
probe_y_v = sprite_y0(build_s) + SPRITE_H/2;
probe_addr = ref_addr_psmct32(probe_x_v, probe_y_v);
probe_expected = {8'hFF, sprite_b(build_s), sprite_g(build_s), sprite_r(build_s)};
probe_got = dut.u_vram.mem[probe_addr >> 2];
if (probe_got !== probe_expected) begin
$error("[bp] sprite %0d center (%0d,%0d) got 0x%08x expected 0x%08x",
build_s, probe_x_v, probe_y_v, probe_got, probe_expected);
errors = errors + 1;
end
end
// -----------------------------------------------------
// Status latches.
// -----------------------------------------------------
if (!core_halt) begin $error("[bp] core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("[bp] dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("[bp] frame_seen never latched"); errors = errors + 1; end
$display("[tb_gs_raster_backpressure_stress] sprites=%0d FIFO_DEPTH=%0d in_ready_low_cycles=%0d errors=%0d",
N_SPRITES, dut.u_gs.FIFO_DEPTH, in_ready_low_cycles, errors);
if (errors == 0) $display("[tb_gs_raster_backpressure_stress] PASS");
else $display("[tb_gs_raster_backpressure_stress] FAIL");
$finish;
end
// Watchdog — 8 sprites × 1200 raster cycles each + scanout + slack.
initial begin
#30_000_000;
$error("[tb_gs_raster_backpressure_stress] TIMEOUT");
$finish;
end
endmodule : tb_gs_raster_backpressure_stress
sim/tb/top/tb_gs_tile_spill_grid8x8_lpddr.sv
+231
View File
@@ -0,0 +1,231 @@
// ============================================================================
// tb_gs_tile_spill_grid8x8_lpddr.sv (Ch324 — 4x4 multi-tile two-batch spill/reload)
//
// Scales the Ch323 single-tile integration proof (tb_gs_tile_spill_lpddr) to a
// 8x8 grid = 128x128 raster framebuffer (FBW=2). Wires the SAME real modules the
// de25 wires — bram-top gs_stub -> 2x gs_z_flush_writer (color/Z) -> behavioral
// 256-bit RASTER EMIF -> gs_tile_reload (RUNTIME per-tile reload_base) -> gs_stub
// serve port — across an async emif clock, driven by the bios/payload_tile_spill4x4
// fixture (P1 near color1 spills, P2 mid color2 reloads + depth-tests).
//
// The behavioral EMIF is the RASTER framebuffer: spill writes land at the global
// screen address each tile's flush produces, and gs_tile_reload gathers each tile
// back from COLOR/Z_BASE + reload_base. After the render we read the color region
// straight out of `mem` (= the LPDDR raster FB) and categorize the regions:
// overlap (P1 region, x+y<64): reloaded Z=0x8000 -> P2 fails -> color1 (red), in
// MULTIPLE tiles (depth survival > 1 tile)
// region B (64<=x+y<80, P2 only): reloaded clear -> P2 passes -> color2 (blue)
// empty tiles (top row, bottom-right): clear
// Also traces per-tile reload_base values + spill/reload counters. This TB is the
// EMPIRICAL answer to "does the gs_stub tile FSM produce a grid two-batch
// spill/reload?" — it dumps the behavior before asserting.
// ============================================================================
`timescale 1ns/1ps
module tb_gs_tile_spill_grid8x8_lpddr;
localparam int H_ACTIVE = 128, V_ACTIVE = 128;
localparam logic [31:0] COLOR1 = 32'hFF0000FF, COLOR2 = 32'hFFFF0000; // red / blue (ABGR)
localparam [29:0] C_BASE = 30'h0000_0000, Z_BASE = 30'h0001_0000; // 16KiB color, then Z
localparam logic [31:0] GARB = 32'h7EED7EED;
logic clk=0; always #5 clk = ~clk;
logic eclk=0; always #3 eclk = ~eclk;
logic rst_n, erst_n, core_go;
logic [7:0] r,g,b; logic hsync,vsync,de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow, frame_toggle, dma_done_toggle;
logic z_flush_emit; logic [31:0] z_flush_addr, z_flush_data;
logic flush_emit; logic [31:0] flush_addr, flush_color32;
logic cflush_emit; logic [31:0] cflush_addr, cflush_data;
logic reload_start; logic [7:0] tile_reload_raddr; logic [29:0] reload_base;
logic [31:0] tile_reload_color, tile_reload_z; logic tile_reload_ready;
logic [2:0] tile_phase_o;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(8*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(8), .TILE_ROWS(8),
.TILE_SPILL_ENABLE(1'b1), .FB_LPDDR_ONLY(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.flush_emit_o(flush_emit), .flush_addr_o(flush_addr), .flush_color32_o(flush_color32),
.tile_color_flush_emit_o(cflush_emit), .tile_color_flush_addr_o(cflush_addr), .tile_color_flush_data_o(cflush_data),
.z_flush_emit_o(z_flush_emit), .z_flush_addr_o(z_flush_addr), .z_flush_data_o(z_flush_data),
.reload_start_o(reload_start), .tile_reload_raddr_o(tile_reload_raddr), .reload_base_o(reload_base),
.tile_reload_ready_i(tile_reload_ready), .tile_reload_color_i(tile_reload_color),
.tile_reload_z_i(tile_reload_z), .tile_phase_o(tile_phase_o)
);
// ================= REAL spill writers (color + Z) =================
wire [29:0] cw_aa, zw_aa; wire [1:0] cw_ab, zw_ab; wire [6:0] cw_id, zw_id;
wire [7:0] cw_al, zw_al; wire [2:0] cw_as, zw_as; wire cw_av, zw_av, cw_ar, zw_ar;
wire [255:0] cw_wd, zw_wd; wire [31:0] cw_ws, zw_ws; wire cw_wl, zw_wl, cw_wv, zw_wv, cw_wr, zw_wr;
wire [1:0] cw_br, zw_br; wire cw_bv, zw_bv, cw_brd, zw_brd;
wire [31:0] c_beats, c_errs, z_beats, z_errs; wire c_ovf, z_ovf;
gs_z_flush_writer #(.Z_BASE(C_BASE), .FB_BASE(30'h20000), .FB_BYTES(32'h1000),
.TEX_BASE(30'h22000), .TEX_BYTES(32'h1000)) u_color (
.gs_clk(clk), .gs_rst_n(rst_n), .enable(1'b1), .trace_clear(1'b0),
.z_flush_emit(cflush_emit), .z_flush_addr(cflush_addr), .z_flush_data(cflush_data),
.z_write_beats(c_beats), .z_wr_errs(c_errs), .fifo_overflow(c_ovf),
.axi_clk(eclk), .axi_rst_n(erst_n),
.awaddr(cw_aa), .awburst(cw_ab), .awid(cw_id), .awlen(cw_al), .awsize(cw_as),
.awvalid(cw_av), .awready(cw_ar), .wdata(cw_wd), .wstrb(cw_ws), .wlast(cw_wl),
.wvalid(cw_wv), .wready(cw_wr), .bresp(cw_br), .bvalid(cw_bv), .bready(cw_brd)
);
gs_z_flush_writer #(.Z_BASE(Z_BASE), .FB_BASE(30'h20000), .FB_BYTES(32'h1000),
.TEX_BASE(30'h22000), .TEX_BYTES(32'h1000)) u_z (
.gs_clk(clk), .gs_rst_n(rst_n), .enable(1'b1), .trace_clear(1'b0),
.z_flush_emit(z_flush_emit), .z_flush_addr(z_flush_addr), .z_flush_data(z_flush_data),
.z_write_beats(z_beats), .z_wr_errs(z_errs), .fifo_overflow(z_ovf),
.axi_clk(eclk), .axi_rst_n(erst_n),
.awaddr(zw_aa), .awburst(zw_ab), .awid(zw_id), .awlen(zw_al), .awsize(zw_as),
.awvalid(zw_av), .awready(zw_ar), .wdata(zw_wd), .wstrb(zw_ws), .wlast(zw_wl),
.wvalid(zw_wv), .wready(zw_wr), .bresp(zw_br), .bvalid(zw_bv), .bready(zw_brd)
);
// ================= REAL reload engine (per-tile base) =================
wire [29:0] rl_aa; wire [1:0] rl_ab; wire [6:0] rl_id; wire [7:0] rl_al; wire [2:0] rl_as;
wire rl_av, rl_ar; wire [255:0] rl_rd; wire [1:0] rl_rr; wire rl_rl, rl_rv, rl_rrdy;
wire [31:0] rl_cbeats, rl_zbeats, rl_rderrs;
gs_tile_reload #(.COLOR_BASE(C_BASE), .Z_BASE(Z_BASE), .TILE_W(16), .TILE_H(16),
.STRIDE_BYTES(512), .ROW_BEATS(2), .COLOR_W(32)) u_reload (
.axi_clk(eclk), .axi_rst_n(erst_n),
.reload_start(reload_start), .reload_base(reload_base), .reload_done(),
.color_beats(rl_cbeats), .z_beats(rl_zbeats), .rd_errs(rl_rderrs),
.araddr(rl_aa), .arburst(rl_ab), .arid(rl_id), .arlen(rl_al), .arsize(rl_as),
.arvalid(rl_av), .arready(rl_ar), .rdata(rl_rd), .rresp(rl_rr), .rlast(rl_rl),
.rvalid(rl_rv), .rready(rl_rrdy),
.serve_clk(clk), .raddr(tile_reload_raddr),
.color_o(tile_reload_color), .z_o(tile_reload_z), .reload_ready(tile_reload_ready)
);
// ================= behavioral 256-bit RASTER EMIF =================
logic [255:0] mem [0:4095];
typedef enum logic [1:0] {WA,WD,WB} ws_t;
ws_t cws; logic [29:0] cbeat;
assign cw_ar=(cws==WA); assign cw_wr=(cws==WD); assign cw_bv=(cws==WB); assign cw_br=2'b00;
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) cws<=WA;
else case (cws)
WA: if (cw_av) begin cbeat<=cw_aa[29:5]; cws<=WD; end
WD: if (cw_wv) begin for (int by=0;by<32;by++) if (cw_ws[by]) mem[cbeat[11:0]][by*8+:8]<=cw_wd[by*8+:8]; cws<=WB; end
WB: if (cw_brd) cws<=WA;
endcase
end
ws_t zws; logic [29:0] zbeat;
assign zw_ar=(zws==WA); assign zw_wr=(zws==WD); assign zw_bv=(zws==WB); assign zw_br=2'b00;
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) zws<=WA;
else case (zws)
WA: if (zw_av) begin zbeat<=zw_aa[29:5]; zws<=WD; end
WD: if (zw_wv) begin for (int by=0;by<32;by++) if (zw_ws[by]) mem[zbeat[11:0]][by*8+:8]<=zw_wd[by*8+:8]; zws<=WB; end
WB: if (zw_brd) zws<=WA;
endcase
end
typedef enum logic [1:0] {RA,RL,RV} rs_t;
rs_t rs; logic [29:0] rbeat; logic [2:0] rlat;
assign rl_ar=(rs==RA); assign rl_rv=(rs==RV); assign rl_rl=(rs==RV); assign rl_rr=2'b00;
assign rl_rd = mem[rbeat[11:0]];
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) begin rs<=RA; rlat<=0; end
else case (rs)
RA: if (rl_av) begin rbeat<=rl_aa[29:5]; rlat<=3'd4; rs<=RL; end
RL: if (rlat==0) rs<=RV; else rlat<=rlat-1'b1;
RV: if (rl_rrdy) rs<=RA;
endcase
end
// ---- witnesses: reload arms, per-tile reload_base values seen ----
bit saw_reload_ready, saw_reload_start;
int reload_pass; logic [29:0] base_seen [0:63]; int base_n;
always_ff @(posedge clk) begin
if (!rst_n) begin saw_reload_ready<=0; saw_reload_start<=0; reload_pass<=0; base_n<=0; end
else begin
if (reload_start) begin
saw_reload_start<=1'b1; reload_pass<=reload_pass+1;
if (base_n<64) begin base_seen[base_n]<=reload_base; base_n<=base_n+1; end
end
if (tile_reload_ready) saw_reload_ready<=1'b1;
end
end
// ---- read the raster FB color region straight out of mem ----
function automatic logic [23:0] cpx(input int gx, input int gy);
logic [29:0] a; a = C_BASE + 30'((gy*128+gx)*4);
cpx = mem[a >> 5][((a>>2)&3'd7)*32 +: 24];
endfunction
function automatic logic [31:0] zpx(input int gx, input int gy);
logic [29:0] a; a = Z_BASE + 30'((gy*128+gx)*4);
zpx = mem[a >> 5][((a>>2)&3'd7)*32 +: 32];
endfunction
int errors;
task automatic chk(input bit c, input string m); if (!c) begin errors++; $display("[grid] FAIL: %s", m); end endtask
int n_red, n_blue, n_clear, n_garb, n_other;
int ovl_red, regB_blue; // overlap pixels that are red; regionB pixels that are blue
int empty_nonclear; // top-row/empty-tile pixels that are NOT clear
initial begin
errors=0; core_go=0;
for (int i=0;i<4096;i++) mem[i]={8{GARB}}; // clean-boot from garbage
rst_n=0; erst_n=0; repeat(8) @(posedge eclk); erst_n=1; repeat(4) @(posedge clk); rst_n=1; repeat(8) @(posedge clk);
@(negedge clk); core_go<=1'b1; @(negedge clk); core_go<=1'b0;
$display("[grid] @%0t booted", $time);
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
wait (dut.u_gs.raster_active==1'b1);
$display("[grid] @%0t raster_active high", $time);
wait (dut.u_gs.raster_active==1'b0); repeat(20) @(posedge clk);
// counters + reload behavior
$display("[grid] writers: c_beats=%0d z_beats=%0d c_ovf=%0d z_ovf=%0d reload: cbeats=%0d zbeats=%0d rderrs=%0d",
c_beats, z_beats, c_ovf, z_ovf, rl_cbeats, rl_zbeats, rl_rderrs);
$display("[grid] saw_reload_start=%0d saw_reload_ready=%0d reload_passes=%0d distinct bases seen=%0d",
saw_reload_start, saw_reload_ready, reload_pass, base_n);
for (int i=0;i<base_n && i<64;i++) $display("[grid] reload pass %0d base=0x%06x", i, base_seen[i]);
// categorize the whole 128x128 color FB (8x8 grid). P1 (40,40)-(88,40)-(40,88) x+y<128;
// P2 (40,40)-(120,40)-(40,120) x+y<160. Overlap (x+y<128) -> red; region B (128<x+y<160)
// -> blue; top tile-rows (y<32) empty.
n_red=0; n_blue=0; n_clear=0; n_garb=0; n_other=0; ovl_red=0; regB_blue=0; empty_nonclear=0;
for (int gy=0; gy<128; gy++) for (int gx=0; gx<128; gx++) begin
logic [23:0] c; c = cpx(gx,gy);
if (c==COLOR1[23:0]) n_red++;
else if (c==COLOR2[23:0]) n_blue++;
else if (c==24'd0) n_clear++;
else if (c==GARB[23:0]) n_garb++;
else n_other++;
// overlap = strictly inside P1 (x+y<120 inner, x>=40,y>=40) ; expect red
if (gx>=40 && gy>=40 && (gx+gy)<120) if (c==COLOR1[23:0]) ovl_red++;
// region B = inside P2 but outside P1 (132<x+y<156, x>=40,y>=40); expect blue
if (gx>=40 && gy>=40 && (gx+gy)>132 && (gx+gy)<156) if (c==COLOR2[23:0]) regB_blue++;
// empty top tile-rows (gy<32): must be clear-or-untouched (not red/blue)
if (gy<32) if (c==COLOR1[23:0] || c==COLOR2[23:0]) empty_nonclear++;
end
$display("[grid] FB color census: red=%0d blue=%0d clear=%0d garbage=%0d other=%0d", n_red,n_blue,n_clear,n_garb,n_other);
$display("[grid] overlap-red(depth-survived)=%0d regionB-blue=%0d empty-toprow-painted=%0d", ovl_red, regB_blue, empty_nonclear);
// sample a few tiles' overlap pixels to show depth survival spans >1 tile
$display("[grid] sample px: (48,48)=%06x (72,48)=%06x (48,72)=%06x | regB (80,80)=%06x (100,56)=%06x | empty (8,8)=%06x (112,112)=%06x",
cpx(48,48), cpx(72,48), cpx(48,72), cpx(80,80), cpx(100,56), cpx(8,8), cpx(112,112));
// ---- assertions (Codex Brick acceptance) ----
chk(saw_reload_start && saw_reload_ready, "reload never armed/readied across the grid");
chk(!c_ovf && !z_ovf, "spill FIFO overflow");
chk(c_beats>0 && z_beats>0 && rl_cbeats>0 && rl_zbeats>0, "spill/reload wrote/read 0 beats");
chk(ovl_red >= 3, $sformatf("depth survival weak: only %0d overlap pixels kept color1 (expect across >1 tile)", ovl_red));
chk(regB_blue >= 3, $sformatf("region B weak: only %0d pixels accepted color2", regB_blue));
chk(empty_nonclear==0, $sformatf("%0d empty top-row pixels were painted (should stay clear)", empty_nonclear));
if (errors==0) $display("[tb_gs_tile_spill_grid8x8_lpddr] PASS");
else $display("[tb_gs_tile_spill_grid8x8_lpddr] FAIL (errors=%0d)", errors);
$finish;
end
initial begin #80000000; $display("[tb_gs_tile_spill_grid8x8_lpddr] TIMEOUT"); $display("[tb_gs_tile_spill_grid8x8_lpddr] FAIL"); $finish; end
endmodule
sim/tb/top/tb_gs_tile_spill_grid_lpddr.sv
+229
View File
@@ -0,0 +1,229 @@
// ============================================================================
// tb_gs_tile_spill_grid_lpddr.sv (Ch324 — 4x4 multi-tile two-batch spill/reload)
//
// Scales the Ch323 single-tile integration proof (tb_gs_tile_spill_lpddr) to a
// 4x4 grid = 64x64 raster framebuffer (FBW=1). Wires the SAME real modules the
// de25 wires — bram-top gs_stub -> 2x gs_z_flush_writer (color/Z) -> behavioral
// 256-bit RASTER EMIF -> gs_tile_reload (RUNTIME per-tile reload_base) -> gs_stub
// serve port — across an async emif clock, driven by the bios/payload_tile_spill4x4
// fixture (P1 near color1 spills, P2 mid color2 reloads + depth-tests).
//
// The behavioral EMIF is the RASTER framebuffer: spill writes land at the global
// screen address each tile's flush produces, and gs_tile_reload gathers each tile
// back from COLOR/Z_BASE + reload_base. After the render we read the color region
// straight out of `mem` (= the LPDDR raster FB) and categorize the regions:
// overlap (P1 region, x+y<64): reloaded Z=0x8000 -> P2 fails -> color1 (red), in
// MULTIPLE tiles (depth survival > 1 tile)
// region B (64<=x+y<80, P2 only): reloaded clear -> P2 passes -> color2 (blue)
// empty tiles (top row, bottom-right): clear
// Also traces per-tile reload_base values + spill/reload counters. This TB is the
// EMPIRICAL answer to "does the gs_stub tile FSM produce a grid two-batch
// spill/reload?" — it dumps the behavior before asserting.
// ============================================================================
`timescale 1ns/1ps
module tb_gs_tile_spill_grid_lpddr;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam logic [31:0] COLOR1 = 32'hFF0000FF, COLOR2 = 32'hFFFF0000; // red / blue (ABGR)
localparam [29:0] C_BASE = 30'h0000_0000, Z_BASE = 30'h0000_4000; // 16KiB color, then Z
localparam logic [31:0] GARB = 32'h7EED7EED;
logic clk=0; always #5 clk = ~clk;
logic eclk=0; always #3 eclk = ~eclk;
logic rst_n, erst_n, core_go;
logic [7:0] r,g,b; logic hsync,vsync,de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow, frame_toggle, dma_done_toggle;
logic z_flush_emit; logic [31:0] z_flush_addr, z_flush_data;
logic flush_emit; logic [31:0] flush_addr, flush_color32;
logic cflush_emit; logic [31:0] cflush_addr, cflush_data;
logic reload_start; logic [7:0] tile_reload_raddr; logic [29:0] reload_base;
logic [31:0] tile_reload_color, tile_reload_z; logic tile_reload_ready;
logic [2:0] tile_phase_o;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_SPILL_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.flush_emit_o(flush_emit), .flush_addr_o(flush_addr), .flush_color32_o(flush_color32),
.tile_color_flush_emit_o(cflush_emit), .tile_color_flush_addr_o(cflush_addr), .tile_color_flush_data_o(cflush_data),
.z_flush_emit_o(z_flush_emit), .z_flush_addr_o(z_flush_addr), .z_flush_data_o(z_flush_data),
.reload_start_o(reload_start), .tile_reload_raddr_o(tile_reload_raddr), .reload_base_o(reload_base),
.tile_reload_ready_i(tile_reload_ready), .tile_reload_color_i(tile_reload_color),
.tile_reload_z_i(tile_reload_z), .tile_phase_o(tile_phase_o)
);
// ================= REAL spill writers (color + Z) =================
wire [29:0] cw_aa, zw_aa; wire [1:0] cw_ab, zw_ab; wire [6:0] cw_id, zw_id;
wire [7:0] cw_al, zw_al; wire [2:0] cw_as, zw_as; wire cw_av, zw_av, cw_ar, zw_ar;
wire [255:0] cw_wd, zw_wd; wire [31:0] cw_ws, zw_ws; wire cw_wl, zw_wl, cw_wv, zw_wv, cw_wr, zw_wr;
wire [1:0] cw_br, zw_br; wire cw_bv, zw_bv, cw_brd, zw_brd;
wire [31:0] c_beats, c_errs, z_beats, z_errs; wire c_ovf, z_ovf;
gs_z_flush_writer #(.Z_BASE(C_BASE), .FB_BASE(30'h10000), .FB_BYTES(32'h1000),
.TEX_BASE(30'h12000), .TEX_BYTES(32'h1000)) u_color (
.gs_clk(clk), .gs_rst_n(rst_n), .enable(1'b1), .trace_clear(1'b0),
.z_flush_emit(cflush_emit), .z_flush_addr(cflush_addr), .z_flush_data(cflush_data),
.z_write_beats(c_beats), .z_wr_errs(c_errs), .fifo_overflow(c_ovf),
.axi_clk(eclk), .axi_rst_n(erst_n),
.awaddr(cw_aa), .awburst(cw_ab), .awid(cw_id), .awlen(cw_al), .awsize(cw_as),
.awvalid(cw_av), .awready(cw_ar), .wdata(cw_wd), .wstrb(cw_ws), .wlast(cw_wl),
.wvalid(cw_wv), .wready(cw_wr), .bresp(cw_br), .bvalid(cw_bv), .bready(cw_brd)
);
gs_z_flush_writer #(.Z_BASE(Z_BASE), .FB_BASE(30'h10000), .FB_BYTES(32'h1000),
.TEX_BASE(30'h12000), .TEX_BYTES(32'h1000)) u_z (
.gs_clk(clk), .gs_rst_n(rst_n), .enable(1'b1), .trace_clear(1'b0),
.z_flush_emit(z_flush_emit), .z_flush_addr(z_flush_addr), .z_flush_data(z_flush_data),
.z_write_beats(z_beats), .z_wr_errs(z_errs), .fifo_overflow(z_ovf),
.axi_clk(eclk), .axi_rst_n(erst_n),
.awaddr(zw_aa), .awburst(zw_ab), .awid(zw_id), .awlen(zw_al), .awsize(zw_as),
.awvalid(zw_av), .awready(zw_ar), .wdata(zw_wd), .wstrb(zw_ws), .wlast(zw_wl),
.wvalid(zw_wv), .wready(zw_wr), .bresp(zw_br), .bvalid(zw_bv), .bready(zw_brd)
);
// ================= REAL reload engine (per-tile base) =================
wire [29:0] rl_aa; wire [1:0] rl_ab; wire [6:0] rl_id; wire [7:0] rl_al; wire [2:0] rl_as;
wire rl_av, rl_ar; wire [255:0] rl_rd; wire [1:0] rl_rr; wire rl_rl, rl_rv, rl_rrdy;
wire [31:0] rl_cbeats, rl_zbeats, rl_rderrs;
gs_tile_reload #(.COLOR_BASE(C_BASE), .Z_BASE(Z_BASE), .TILE_W(16), .TILE_H(16),
.STRIDE_BYTES(256), .ROW_BEATS(2), .COLOR_W(32)) u_reload (
.axi_clk(eclk), .axi_rst_n(erst_n),
.reload_start(reload_start), .reload_base(reload_base), .reload_done(),
.color_beats(rl_cbeats), .z_beats(rl_zbeats), .rd_errs(rl_rderrs),
.araddr(rl_aa), .arburst(rl_ab), .arid(rl_id), .arlen(rl_al), .arsize(rl_as),
.arvalid(rl_av), .arready(rl_ar), .rdata(rl_rd), .rresp(rl_rr), .rlast(rl_rl),
.rvalid(rl_rv), .rready(rl_rrdy),
.serve_clk(clk), .raddr(tile_reload_raddr),
.color_o(tile_reload_color), .z_o(tile_reload_z), .reload_ready(tile_reload_ready)
);
// ================= behavioral 256-bit RASTER EMIF =================
logic [255:0] mem [0:2047];
typedef enum logic [1:0] {WA,WD,WB} ws_t;
ws_t cws; logic [29:0] cbeat;
assign cw_ar=(cws==WA); assign cw_wr=(cws==WD); assign cw_bv=(cws==WB); assign cw_br=2'b00;
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) cws<=WA;
else case (cws)
WA: if (cw_av) begin cbeat<=cw_aa[29:5]; cws<=WD; end
WD: if (cw_wv) begin for (int by=0;by<32;by++) if (cw_ws[by]) mem[cbeat[10:0]][by*8+:8]<=cw_wd[by*8+:8]; cws<=WB; end
WB: if (cw_brd) cws<=WA;
endcase
end
ws_t zws; logic [29:0] zbeat;
assign zw_ar=(zws==WA); assign zw_wr=(zws==WD); assign zw_bv=(zws==WB); assign zw_br=2'b00;
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) zws<=WA;
else case (zws)
WA: if (zw_av) begin zbeat<=zw_aa[29:5]; zws<=WD; end
WD: if (zw_wv) begin for (int by=0;by<32;by++) if (zw_ws[by]) mem[zbeat[10:0]][by*8+:8]<=zw_wd[by*8+:8]; zws<=WB; end
WB: if (zw_brd) zws<=WA;
endcase
end
typedef enum logic [1:0] {RA,RL,RV} rs_t;
rs_t rs; logic [29:0] rbeat; logic [2:0] rlat;
assign rl_ar=(rs==RA); assign rl_rv=(rs==RV); assign rl_rl=(rs==RV); assign rl_rr=2'b00;
assign rl_rd = mem[rbeat[10:0]];
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) begin rs<=RA; rlat<=0; end
else case (rs)
RA: if (rl_av) begin rbeat<=rl_aa[29:5]; rlat<=3'd4; rs<=RL; end
RL: if (rlat==0) rs<=RV; else rlat<=rlat-1'b1;
RV: if (rl_rrdy) rs<=RA;
endcase
end
// ---- witnesses: reload arms, per-tile reload_base values seen ----
bit saw_reload_ready, saw_reload_start;
int reload_pass; logic [29:0] base_seen [0:63]; int base_n;
always_ff @(posedge clk) begin
if (!rst_n) begin saw_reload_ready<=0; saw_reload_start<=0; reload_pass<=0; base_n<=0; end
else begin
if (reload_start) begin
saw_reload_start<=1'b1; reload_pass<=reload_pass+1;
if (base_n<64) begin base_seen[base_n]<=reload_base; base_n<=base_n+1; end
end
if (tile_reload_ready) saw_reload_ready<=1'b1;
end
end
// ---- read the raster FB color region straight out of mem ----
function automatic logic [23:0] cpx(input int gx, input int gy);
logic [29:0] a; a = C_BASE + 30'((gy*64+gx)*4);
cpx = mem[a >> 5][((a>>2)&3'd7)*32 +: 24];
endfunction
function automatic logic [31:0] zpx(input int gx, input int gy);
logic [29:0] a; a = Z_BASE + 30'((gy*64+gx)*4);
zpx = mem[a >> 5][((a>>2)&3'd7)*32 +: 32];
endfunction
int errors;
task automatic chk(input bit c, input string m); if (!c) begin errors++; $display("[grid] FAIL: %s", m); end endtask
int n_red, n_blue, n_clear, n_garb, n_other;
int ovl_red, regB_blue; // overlap pixels that are red; regionB pixels that are blue
int empty_nonclear; // top-row/empty-tile pixels that are NOT clear
initial begin
errors=0; core_go=0;
for (int i=0;i<2048;i++) mem[i]={8{GARB}}; // clean-boot from garbage
rst_n=0; erst_n=0; repeat(8) @(posedge eclk); erst_n=1; repeat(4) @(posedge clk); rst_n=1; repeat(8) @(posedge clk);
@(negedge clk); core_go<=1'b1; @(negedge clk); core_go<=1'b0;
$display("[grid] @%0t booted", $time);
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
wait (dut.u_gs.raster_active==1'b1);
$display("[grid] @%0t raster_active high", $time);
wait (dut.u_gs.raster_active==1'b0); repeat(20) @(posedge clk);
// counters + reload behavior
$display("[grid] writers: c_beats=%0d z_beats=%0d c_ovf=%0d z_ovf=%0d reload: cbeats=%0d zbeats=%0d rderrs=%0d",
c_beats, z_beats, c_ovf, z_ovf, rl_cbeats, rl_zbeats, rl_rderrs);
$display("[grid] saw_reload_start=%0d saw_reload_ready=%0d reload_passes=%0d distinct bases seen=%0d",
saw_reload_start, saw_reload_ready, reload_pass, base_n);
for (int i=0;i<base_n && i<32;i++) $display("[grid] reload pass %0d base=0x%06x", i, base_seen[i]);
// categorize the whole 64x64 color FB
n_red=0; n_blue=0; n_clear=0; n_garb=0; n_other=0; ovl_red=0; regB_blue=0; empty_nonclear=0;
for (int gy=0; gy<64; gy++) for (int gx=0; gx<64; gx++) begin
logic [23:0] c; c = cpx(gx,gy);
if (c==COLOR1[23:0]) n_red++;
else if (c==COLOR2[23:0]) n_blue++;
else if (c==24'd0) n_clear++;
else if (c==GARB[23:0]) n_garb++;
else n_other++;
// overlap = strictly inside P1 (x+y<64, x>=20,y>=20) ; expect red
if (gx>=20 && gy>=20 && (gx+gy)<60) if (c==COLOR1[23:0]) ovl_red++;
// region B = inside P2 but outside P1 (64<=x+y<78, x>=20,y>=20); expect blue
if (gx>=20 && gy>=20 && (gx+gy)>66 && (gx+gy)<78) if (c==COLOR2[23:0]) regB_blue++;
// empty top tile-row (gy<16): must be clear-or-untouched (not red/blue)
if (gy<16) if (c==COLOR1[23:0] || c==COLOR2[23:0]) empty_nonclear++;
end
$display("[grid] FB color census: red=%0d blue=%0d clear=%0d garbage=%0d other=%0d", n_red,n_blue,n_clear,n_garb,n_other);
$display("[grid] overlap-red(depth-survived)=%0d regionB-blue=%0d empty-toprow-painted=%0d", ovl_red, regB_blue, empty_nonclear);
// sample a few tiles' overlap pixels to show depth survival spans >1 tile
$display("[grid] sample px: (24,24)=%06x (36,24)=%06x (24,36)=%06x | regB (40,40)=%06x (50,28)=%06x | empty (4,4)=%06x (56,56)=%06x",
cpx(24,24), cpx(36,24), cpx(24,36), cpx(40,40), cpx(50,28), cpx(4,4), cpx(56,56));
// ---- assertions (Codex Brick acceptance) ----
chk(saw_reload_start && saw_reload_ready, "reload never armed/readied across the grid");
chk(!c_ovf && !z_ovf, "spill FIFO overflow");
chk(c_beats>0 && z_beats>0 && rl_cbeats>0 && rl_zbeats>0, "spill/reload wrote/read 0 beats");
chk(ovl_red >= 3, $sformatf("depth survival weak: only %0d overlap pixels kept color1 (expect across >1 tile)", ovl_red));
chk(regB_blue >= 3, $sformatf("region B weak: only %0d pixels accepted color2", regB_blue));
chk(empty_nonclear==0, $sformatf("%0d empty top-row pixels were painted (should stay clear)", empty_nonclear));
if (errors==0) $display("[tb_gs_tile_spill_grid_lpddr] PASS");
else $display("[tb_gs_tile_spill_grid_lpddr] FAIL (errors=%0d)", errors);
$finish;
end
initial begin #20000000; $display("[tb_gs_tile_spill_grid_lpddr] TIMEOUT"); $display("[tb_gs_tile_spill_grid_lpddr] FAIL"); $finish; end
endmodule
sim/tb/top/tb_gs_tile_spill_lpddr.sv
+259
View File
@@ -0,0 +1,259 @@
// retroDE_ps2 — tb_gs_tile_spill_lpddr (Ch323 Brick 2 — REAL LPDDR-path integration proof)
//
// The gap that let the board bugs through: tb_gs_tile_spill_reload (Brick 1) forced
// tile_reload_ready=1 and served an on-chip backing — it NEVER exercised the real
// gs_z_flush_writer / gs_tile_reload / EMIF round-trip, and gs_stub PULSES reload_start
// while gs_tile_reload edge-detects it (pulse-vs-toggle). This TB wires the SAME modules
// the de25 wires — gs_stub -> 2x gs_z_flush_writer (color/Z) -> behavioral 256-bit EMIF
// -> gs_tile_reload -> gs_stub serve port — across an ASYNC emif clock, and proves the
// two-batch depth result (region A = red color1, region B = blue color2) THROUGH THE REAL
// DATA PATH. Small LPDDR bases (C=0, Z=0x1000) keep the behavioral mem tiny.
`timescale 1ns/1ps
module tb_gs_tile_spill_lpddr;
localparam int H_ACTIVE = 16, V_ACTIVE = 16;
localparam logic [31:0] COLOR1 = 32'hFF0000FF, COLOR2 = 32'hFFFF0000; // red / blue (ABGR)
localparam [29:0] C_BASE = 30'h0000_0000, Z_BASE = 30'h0000_1000;
logic clk=0; always #5 clk = ~clk; // design clock
logic eclk=0; always #3 eclk = ~eclk; // emif clock (faster, async)
logic rst_n, erst_n, core_go;
logic [7:0] r,g,b; logic hsync,vsync,de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow, frame_toggle, dma_done_toggle;
logic z_flush_emit; logic [31:0] z_flush_addr, z_flush_data;
logic flush_emit; logic [31:0] flush_addr, flush_color32;
logic cflush_emit; logic [31:0] cflush_addr, cflush_data;
logic reload_start; logic [7:0] tile_reload_raddr; logic [29:0] reload_base;
logic [31:0] tile_reload_color, tile_reload_z; logic tile_reload_ready;
logic [2:0] tile_phase_o;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(8*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_SPILL_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.flush_emit_o(flush_emit), .flush_addr_o(flush_addr), .flush_color32_o(flush_color32),
.tile_color_flush_emit_o(cflush_emit), .tile_color_flush_addr_o(cflush_addr), .tile_color_flush_data_o(cflush_data),
.z_flush_emit_o(z_flush_emit), .z_flush_addr_o(z_flush_addr), .z_flush_data_o(z_flush_data),
.reload_start_o(reload_start), .tile_reload_raddr_o(tile_reload_raddr), .reload_base_o(reload_base),
.tile_reload_ready_i(tile_reload_ready), .tile_reload_color_i(tile_reload_color),
.tile_reload_z_i(tile_reload_z), .tile_phase_o(tile_phase_o)
);
// ================= REAL spill writers (color + Z) =================
wire [29:0] cw_aa, zw_aa; wire [1:0] cw_ab, zw_ab; wire [6:0] cw_id, zw_id;
wire [7:0] cw_al, zw_al; wire [2:0] cw_as, zw_as; wire cw_av, zw_av, cw_ar, zw_ar;
wire [255:0] cw_wd, zw_wd; wire [31:0] cw_ws, zw_ws; wire cw_wl, zw_wl, cw_wv, zw_wv, cw_wr, zw_wr;
wire [1:0] cw_br, zw_br; wire cw_bv, zw_bv, cw_brd, zw_brd;
wire [31:0] c_beats, c_errs, z_beats, z_errs; wire c_ovf, z_ovf;
gs_z_flush_writer #(.Z_BASE(C_BASE), .FB_BASE(30'h8000), .FB_BYTES(32'h1000),
.TEX_BASE(30'h9000), .TEX_BYTES(32'h1000)) u_color (
.gs_clk(clk), .gs_rst_n(rst_n), .enable(1'b1), .trace_clear(1'b0),
.z_flush_emit(cflush_emit), .z_flush_addr(cflush_addr), .z_flush_data(cflush_data),
.z_write_beats(c_beats), .z_wr_errs(c_errs), .fifo_overflow(c_ovf),
.axi_clk(eclk), .axi_rst_n(erst_n),
.awaddr(cw_aa), .awburst(cw_ab), .awid(cw_id), .awlen(cw_al), .awsize(cw_as),
.awvalid(cw_av), .awready(cw_ar), .wdata(cw_wd), .wstrb(cw_ws), .wlast(cw_wl),
.wvalid(cw_wv), .wready(cw_wr), .bresp(cw_br), .bvalid(cw_bv), .bready(cw_brd)
);
gs_z_flush_writer #(.Z_BASE(Z_BASE), .FB_BASE(30'h8000), .FB_BYTES(32'h1000),
.TEX_BASE(30'h9000), .TEX_BYTES(32'h1000)) u_z (
.gs_clk(clk), .gs_rst_n(rst_n), .enable(1'b1), .trace_clear(1'b0),
.z_flush_emit(z_flush_emit), .z_flush_addr(z_flush_addr), .z_flush_data(z_flush_data),
.z_write_beats(z_beats), .z_wr_errs(z_errs), .fifo_overflow(z_ovf),
.axi_clk(eclk), .axi_rst_n(erst_n),
.awaddr(zw_aa), .awburst(zw_ab), .awid(zw_id), .awlen(zw_al), .awsize(zw_as),
.awvalid(zw_av), .awready(zw_ar), .wdata(zw_wd), .wstrb(zw_ws), .wlast(zw_wl),
.wvalid(zw_wv), .wready(zw_wr), .bresp(zw_br), .bvalid(zw_bv), .bready(zw_brd)
);
// ================= REAL reload engine =================
wire [29:0] rl_aa; wire [1:0] rl_ab; wire [6:0] rl_id; wire [7:0] rl_al; wire [2:0] rl_as;
wire rl_av, rl_ar; wire [255:0] rl_rd; wire [1:0] rl_rr; wire rl_rl, rl_rv, rl_rrdy;
wire [31:0] rl_cbeats, rl_zbeats, rl_rderrs;
gs_tile_reload #(.COLOR_BASE(C_BASE), .Z_BASE(Z_BASE), .TILE_W(16), .TILE_H(16),
.STRIDE_BYTES(256), .ROW_BEATS(2), .COLOR_W(32)) u_reload (
.axi_clk(eclk), .axi_rst_n(erst_n),
.reload_start(reload_start), .reload_base(reload_base), .reload_done(),
.color_beats(rl_cbeats), .z_beats(rl_zbeats), .rd_errs(rl_rderrs),
.araddr(rl_aa), .arburst(rl_ab), .arid(rl_id), .arlen(rl_al), .arsize(rl_as),
.arvalid(rl_av), .arready(rl_ar), .rdata(rl_rd), .rresp(rl_rr), .rlast(rl_rl),
.rvalid(rl_rv), .rready(rl_rrdy),
.serve_clk(clk), .raddr(tile_reload_raddr),
.color_o(tile_reload_color), .z_o(tile_reload_z), .reload_ready(tile_reload_ready)
);
// ================= behavioral 256-bit EMIF (shared mem; eclk) =================
// Two independent write slaves (color/Z regions disjoint) + one read slave (reload).
logic [255:0] mem [0:1023];
// ---- color write slave ----
typedef enum logic [1:0] {WA,WD,WB} ws_t;
ws_t cws; logic [29:0] cbeat;
assign cw_ar = (cws==WA);
assign cw_wr = (cws==WD);
assign cw_bv = (cws==WB); assign cw_br = 2'b00;
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) cws<=WA;
else case (cws)
WA: if (cw_av) begin cbeat<=cw_aa[29:5]; cws<=WD; end
WD: if (cw_wv) begin for (int by=0;by<32;by++) if (cw_ws[by]) mem[cbeat[9:0]][by*8+:8]<=cw_wd[by*8+:8]; cws<=WB; end
WB: if (cw_brd) cws<=WA;
endcase
end
// ---- Z write slave ----
ws_t zws; logic [29:0] zbeat;
assign zw_ar = (zws==WA);
assign zw_wr = (zws==WD);
assign zw_bv = (zws==WB); assign zw_br = 2'b00;
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) zws<=WA;
else case (zws)
WA: if (zw_av) begin zbeat<=zw_aa[29:5]; zws<=WD; end
WD: if (zw_wv) begin for (int by=0;by<32;by++) if (zw_ws[by]) mem[zbeat[9:0]][by*8+:8]<=zw_wd[by*8+:8]; zws<=WB; end
WB: if (zw_brd) zws<=WA;
endcase
end
// ---- reload read slave (a few-cycle latency to exercise async timing) ----
typedef enum logic [1:0] {RA,RL,RV} rs_t;
rs_t rs; logic [29:0] rbeat; logic [2:0] rlat;
assign rl_ar = (rs==RA);
assign rl_rv = (rs==RV); assign rl_rl = (rs==RV); assign rl_rr = 2'b00;
assign rl_rd = mem[rbeat[9:0]];
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) begin rs<=RA; rlat<=0; end
else case (rs)
RA: if (rl_av) begin rbeat<=rl_aa[29:5]; rlat<=3'd4; rs<=RL; end
RL: if (rlat==0) rs<=RV; else rlat<=rlat-1'b1;
RV: if (rl_rrdy) rs<=RA;
endcase
end
// ================= scanout capture (from Brick-1 TB) =================
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed; logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; end
function automatic logic [23:0] px(input int y, input int x); px={cap_b[y][x],cap_g[y][x],cap_r[y][x]}; endfunction
// reload handshake witnesses
bit saw_reload_ready, saw_reload_start;
always_ff @(posedge clk) begin
if (!rst_n) begin saw_reload_ready<=0; saw_reload_start<=0; end
else begin
if (reload_start) saw_reload_start<=1'b1;
if (tile_reload_ready) saw_reload_ready<=1'b1;
end
end
// ---- DEBUG: trace region-A pixel (1,1) Z through the chain ----
// tile-local index for (lx=1,ly=1) = ly*16+lx = 17. screen Z byte = (1*64+1)*4=0x104.
// Z block in mem = (Z_BASE+0x104)>>5 = 0x88, lane = 0x104[4:2] = 1 (bits 63:32).
int reload_pass, zflush_evict;
logic [31:0] zA_spilled_data [0:3]; // z_flush_data emitted for region-A screen addr 0x104, per eviction
logic zA_spilled_seen [0:3];
logic [31:0] zA_reload_seen [0:3]; // tile_reload_z_i written into tile RAM idx 17, per reload pass
logic [31:0] zA_mem_at_reload [0:3];
bit mem_has_8000; // did 0x8000 ever appear anywhere in the Z region after batch1?
// emif-domain: each time the reload fill completes a read of the region-A Z block (0x88),
// capture what rdata word1 it got + how many fills ran.
logic [31:0] fillZ_blk88 [0:7]; int fill_blk88_n; int fill_done_edges; logic rdone_d;
always_ff @(posedge eclk) begin
if (!erst_n) begin fill_blk88_n<=0; fill_done_edges<=0; rdone_d<=0; end
else begin
if (rl_rv && rl_rrdy && rl_aa==30'h0000_1100 && fill_blk88_n<8) begin
fillZ_blk88[fill_blk88_n[2:0]]<=rl_rd[63:32]; fill_blk88_n<=fill_blk88_n+1;
end
rdone_d <= u_reload.reload_done;
if (u_reload.reload_done && !rdone_d) fill_done_edges<=fill_done_edges+1;
end
end
always_ff @(posedge clk) begin
if (!rst_n) begin reload_pass<=0; zflush_evict<=0;
zA_spilled_seen[0]<=0; zA_spilled_seen[1]<=0; zA_spilled_seen[2]<=0; zA_spilled_seen[3]<=0; end
else begin
if (reload_start) reload_pass<=reload_pass+1;
// region A screen Z byte addr = (1*64+1)*4 = 0x104. Capture what's emitted for it.
if (z_flush_emit && z_flush_addr[15:0]==16'h0104 && zflush_evict<4) begin
zA_spilled_data[zflush_evict[1:0]]<=z_flush_data; zA_spilled_seen[zflush_evict[1:0]]<=1'b1;
end
// count evictions: a rising edge of TP_ZFLUSH entry (phase 6)
if (tile_phase_o==3'd6 && dut.u_gs.tile_sweep_r==9'd0) zflush_evict<=zflush_evict+1;
if (dut.u_gs.reload_wr_we && dut.u_gs.reload_wr_addr==8'd17 && reload_pass<4) begin
zA_reload_seen[reload_pass[1:0]] <= tile_reload_z;
zA_mem_at_reload[reload_pass[1:0]] <= mem[10'h088][63:32];
end
end
end
int errors;
task automatic chk(input bit c, input string m); if (!c) begin errors++; $display("[lpddr] FAIL: %s", m); end endtask
logic [23:0] rA, rB;
initial begin
errors=0; core_go=0;
// Ch323 — simulate a CLEAN BOOT from SCRUB LPDDR: fill the backing with GARBAGE (high Z).
// The clean-Z bootstrap must still produce red-on-blue: batch-1 renders from the local
// CLEAR (it does NOT reload this garbage), spills, and batch-2 reloads batch-1's spill.
for (int i=0;i<1024;i++) mem[i]=256'h7EED7EED_7EED7EED_7EED7EED_7EED7EED_7EED7EED_7EED7EED_7EED7EED_7EED7EED;
rst_n=0; erst_n=0; repeat(8) @(posedge eclk); erst_n=1; repeat(4) @(posedge clk); rst_n=1; repeat(8) @(posedge clk);
@(negedge clk); core_go<=1'b1; @(negedge clk); core_go<=1'b0;
$display("[lpddr] @%0t booted, waiting core_halt", $time);
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
$display("[lpddr] @%0t waiting raster_active", $time);
wait (dut.u_gs.raster_active==1'b1);
wait (dut.u_gs.raster_active==1'b0); repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed<=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed<=1'b0;
rA = px(1,1); rB = px(10,2);
$display("[lpddr] regionA(1,1)=%06x regionB(10,2)=%06x", rA, rB);
$display("[lpddr] writers: c_beats=%0d z_beats=%0d c_ovf=%0d z_ovf=%0d reload: cbeats=%0d zbeats=%0d rderrs=%0d",
c_beats, z_beats, c_ovf, z_ovf, rl_cbeats, rl_zbeats, rl_rderrs);
$display("[lpddr] handshake: saw_reload_start=%0d saw_reload_ready=%0d reload_passes=%0d", saw_reload_start, saw_reload_ready, reload_pass);
$display("[lpddr] DEBUG region-A(idx17,screen 0x104) Z trace (evicts=%0d, reload passes=%0d):", zflush_evict, reload_pass);
for (int p=0;p<4;p++) if (zA_spilled_seen[p]) $display("[lpddr] evict %0d: z_flush emitted Z=0x%08x for region-A addr", p, zA_spilled_data[p]);
for (int p=0;p<4;p++) $display("[lpddr] reload slot %0d: idx17 served Z=0x%08x (mem lane1 was 0x%08x)", p, zA_reload_seen[p], zA_mem_at_reload[p]);
// scan the whole Z region in mem for any 0x8000 word
mem_has_8000 = 1'b0;
for (int bk=10'h080; bk<10'h0F0; bk++) for (int wd=0; wd<8; wd++)
if (mem[bk][wd*32+:32]==32'h0000_8000) mem_has_8000 = 1'b1;
$display("[lpddr] mem Z-region contains a 0x8000 word anywhere: %0d", mem_has_8000);
$display("[lpddr] fills completed (reload_done edges)=%0d, region-A Z-block reads=%0d:", fill_done_edges, fill_blk88_n);
for (int p=0;p<fill_blk88_n && p<8;p++) $display("[lpddr] fill read#%0d of block 0x88 word1 = 0x%08x", p, fillZ_blk88[p]);
$display("[lpddr] u_reload.z_ram[16..19] = %08x %08x %08x %08x (idx17 should be 0x8000)",
u_reload.z_ram[16], u_reload.z_ram[17], u_reload.z_ram[18], u_reload.z_ram[19]);
$display("[lpddr] u_reload final fill state rst_q=%0d row=%0d beat=%0d", u_reload.rst_q, u_reload.row, u_reload.beat);
// The integration proof THROUGH the real LPDDR path:
chk(saw_reload_start, "gs_stub never pulsed reload_start");
chk(saw_reload_ready, "gs_tile_reload never asserted reload_ready (pulse-vs-toggle / fill hang)");
chk(!c_ovf && !z_ovf, "spill FIFO overflow");
chk(c_beats>0 && z_beats>0, "spill writers wrote 0 beats");
// Color MUST match Z (both are 256 tile px / 8 = 32 beats per eviction). A color>Z mismatch
// means the color writer is over-fed (e.g. from generic raster_pixel_emit, not the dedicated
// TP_FLUSH color stream) — the Ch323 board "108 vs 64 + overflow" bug.
chk(c_beats==z_beats, $sformatf("color beats (%0d) != Z beats (%0d) — color writer over-fed (wrong flush stream)", c_beats, z_beats));
chk(rl_cbeats>0 && rl_zbeats>0, "reload read 0 beats");
chk(rA==COLOR1[23:0], $sformatf("region A = %06x, expected red color1 %06x (reload failed depth)", rA, COLOR1[23:0]));
chk(rB==COLOR2[23:0], $sformatf("region B = %06x, expected blue color2 %06x", rB, COLOR2[23:0]));
if (errors==0) $display("[tb_gs_tile_spill_lpddr] PASS");
else $display("[tb_gs_tile_spill_lpddr] FAIL (errors=%0d)", errors);
$finish;
end
initial begin #5000000; $display("[tb_gs_tile_spill_lpddr] TIMEOUT"); $display("[tb_gs_tile_spill_lpddr] FAIL"); $finish; end
endmodule
sim/tb/top/tb_gs_tile_spill_lpddr_neg.sv
+255
View File
@@ -0,0 +1,255 @@
// retroDE_ps2 — tb_gs_tile_spill_lpddr (Ch323 Brick 2 — REAL LPDDR-path integration proof)
//
// The gap that let the board bugs through: tb_gs_tile_spill_reload (Brick 1) forced
// tile_reload_ready=1 and served an on-chip backing — it NEVER exercised the real
// gs_z_flush_writer / gs_tile_reload / EMIF round-trip, and gs_stub PULSES reload_start
// while gs_tile_reload edge-detects it (pulse-vs-toggle). This TB wires the SAME modules
// the de25 wires — gs_stub -> 2x gs_z_flush_writer (color/Z) -> behavioral 256-bit EMIF
// -> gs_tile_reload -> gs_stub serve port — across an ASYNC emif clock, and proves the
// two-batch depth result (region A = red color1, region B = blue color2) THROUGH THE REAL
// DATA PATH. Small LPDDR bases (C=0, Z=0x1000) keep the behavioral mem tiny.
`timescale 1ns/1ps
module tb_gs_tile_spill_lpddr_neg;
localparam int H_ACTIVE = 16, V_ACTIVE = 16;
localparam logic [31:0] COLOR1 = 32'hFF0000FF, COLOR2 = 32'hFFFF0000; // red / blue (ABGR)
localparam [29:0] C_BASE = 30'h0000_0000, Z_BASE = 30'h0000_1000;
logic clk=0; always #5 clk = ~clk; // design clock
logic eclk=0; always #3 eclk = ~eclk; // emif clock (faster, async)
logic rst_n, erst_n, core_go;
logic [7:0] r,g,b; logic hsync,vsync,de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow, frame_toggle, dma_done_toggle;
logic z_flush_emit; logic [31:0] z_flush_addr, z_flush_data;
logic flush_emit; logic [31:0] flush_addr, flush_color32;
logic cflush_emit; logic [31:0] cflush_addr, cflush_data;
logic reload_start; logic [7:0] tile_reload_raddr; logic [29:0] reload_base;
logic [31:0] tile_reload_color, tile_reload_z; logic tile_reload_ready;
logic [2:0] tile_phase_o;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(8*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_SPILL_ENABLE(1'b1), .SPILL_FORCE_VALID(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.flush_emit_o(flush_emit), .flush_addr_o(flush_addr), .flush_color32_o(flush_color32),
.tile_color_flush_emit_o(cflush_emit), .tile_color_flush_addr_o(cflush_addr), .tile_color_flush_data_o(cflush_data),
.z_flush_emit_o(z_flush_emit), .z_flush_addr_o(z_flush_addr), .z_flush_data_o(z_flush_data),
.reload_start_o(reload_start), .tile_reload_raddr_o(tile_reload_raddr), .reload_base_o(reload_base),
.tile_reload_ready_i(tile_reload_ready), .tile_reload_color_i(tile_reload_color),
.tile_reload_z_i(tile_reload_z), .tile_phase_o(tile_phase_o)
);
// ================= REAL spill writers (color + Z) =================
wire [29:0] cw_aa, zw_aa; wire [1:0] cw_ab, zw_ab; wire [6:0] cw_id, zw_id;
wire [7:0] cw_al, zw_al; wire [2:0] cw_as, zw_as; wire cw_av, zw_av, cw_ar, zw_ar;
wire [255:0] cw_wd, zw_wd; wire [31:0] cw_ws, zw_ws; wire cw_wl, zw_wl, cw_wv, zw_wv, cw_wr, zw_wr;
wire [1:0] cw_br, zw_br; wire cw_bv, zw_bv, cw_brd, zw_brd;
wire [31:0] c_beats, c_errs, z_beats, z_errs; wire c_ovf, z_ovf;
gs_z_flush_writer #(.Z_BASE(C_BASE), .FB_BASE(30'h8000), .FB_BYTES(32'h1000),
.TEX_BASE(30'h9000), .TEX_BYTES(32'h1000)) u_color (
.gs_clk(clk), .gs_rst_n(rst_n), .enable(1'b1), .trace_clear(1'b0),
.z_flush_emit(cflush_emit), .z_flush_addr(cflush_addr), .z_flush_data(cflush_data),
.z_write_beats(c_beats), .z_wr_errs(c_errs), .fifo_overflow(c_ovf),
.axi_clk(eclk), .axi_rst_n(erst_n),
.awaddr(cw_aa), .awburst(cw_ab), .awid(cw_id), .awlen(cw_al), .awsize(cw_as),
.awvalid(cw_av), .awready(cw_ar), .wdata(cw_wd), .wstrb(cw_ws), .wlast(cw_wl),
.wvalid(cw_wv), .wready(cw_wr), .bresp(cw_br), .bvalid(cw_bv), .bready(cw_brd)
);
gs_z_flush_writer #(.Z_BASE(Z_BASE), .FB_BASE(30'h8000), .FB_BYTES(32'h1000),
.TEX_BASE(30'h9000), .TEX_BYTES(32'h1000)) u_z (
.gs_clk(clk), .gs_rst_n(rst_n), .enable(1'b1), .trace_clear(1'b0),
.z_flush_emit(z_flush_emit), .z_flush_addr(z_flush_addr), .z_flush_data(z_flush_data),
.z_write_beats(z_beats), .z_wr_errs(z_errs), .fifo_overflow(z_ovf),
.axi_clk(eclk), .axi_rst_n(erst_n),
.awaddr(zw_aa), .awburst(zw_ab), .awid(zw_id), .awlen(zw_al), .awsize(zw_as),
.awvalid(zw_av), .awready(zw_ar), .wdata(zw_wd), .wstrb(zw_ws), .wlast(zw_wl),
.wvalid(zw_wv), .wready(zw_wr), .bresp(zw_br), .bvalid(zw_bv), .bready(zw_brd)
);
// ================= REAL reload engine =================
wire [29:0] rl_aa; wire [1:0] rl_ab; wire [6:0] rl_id; wire [7:0] rl_al; wire [2:0] rl_as;
wire rl_av, rl_ar; wire [255:0] rl_rd; wire [1:0] rl_rr; wire rl_rl, rl_rv, rl_rrdy;
wire [31:0] rl_cbeats, rl_zbeats, rl_rderrs;
gs_tile_reload #(.COLOR_BASE(C_BASE), .Z_BASE(Z_BASE), .TILE_W(16), .TILE_H(16),
.STRIDE_BYTES(256), .ROW_BEATS(2), .COLOR_W(32)) u_reload (
.axi_clk(eclk), .axi_rst_n(erst_n),
.reload_start(reload_start), .reload_base(reload_base), .reload_done(),
.color_beats(rl_cbeats), .z_beats(rl_zbeats), .rd_errs(rl_rderrs),
.araddr(rl_aa), .arburst(rl_ab), .arid(rl_id), .arlen(rl_al), .arsize(rl_as),
.arvalid(rl_av), .arready(rl_ar), .rdata(rl_rd), .rresp(rl_rr), .rlast(rl_rl),
.rvalid(rl_rv), .rready(rl_rrdy),
.serve_clk(clk), .raddr(tile_reload_raddr),
.color_o(tile_reload_color), .z_o(tile_reload_z), .reload_ready(tile_reload_ready)
);
// ================= behavioral 256-bit EMIF (shared mem; eclk) =================
// Two independent write slaves (color/Z regions disjoint) + one read slave (reload).
logic [255:0] mem [0:1023];
// ---- color write slave ----
typedef enum logic [1:0] {WA,WD,WB} ws_t;
ws_t cws; logic [29:0] cbeat;
assign cw_ar = (cws==WA);
assign cw_wr = (cws==WD);
assign cw_bv = (cws==WB); assign cw_br = 2'b00;
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) cws<=WA;
else case (cws)
WA: if (cw_av) begin cbeat<=cw_aa[29:5]; cws<=WD; end
WD: if (cw_wv) begin for (int by=0;by<32;by++) if (cw_ws[by]) mem[cbeat[9:0]][by*8+:8]<=cw_wd[by*8+:8]; cws<=WB; end
WB: if (cw_brd) cws<=WA;
endcase
end
// ---- Z write slave ----
ws_t zws; logic [29:0] zbeat;
assign zw_ar = (zws==WA);
assign zw_wr = (zws==WD);
assign zw_bv = (zws==WB); assign zw_br = 2'b00;
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) zws<=WA;
else case (zws)
WA: if (zw_av) begin zbeat<=zw_aa[29:5]; zws<=WD; end
WD: if (zw_wv) begin for (int by=0;by<32;by++) if (zw_ws[by]) mem[zbeat[9:0]][by*8+:8]<=zw_wd[by*8+:8]; zws<=WB; end
WB: if (zw_brd) zws<=WA;
endcase
end
// ---- reload read slave (a few-cycle latency to exercise async timing) ----
typedef enum logic [1:0] {RA,RL,RV} rs_t;
rs_t rs; logic [29:0] rbeat; logic [2:0] rlat;
assign rl_ar = (rs==RA);
assign rl_rv = (rs==RV); assign rl_rl = (rs==RV); assign rl_rr = 2'b00;
assign rl_rd = mem[rbeat[9:0]];
always_ff @(posedge eclk or negedge erst_n) begin
if (!erst_n) begin rs<=RA; rlat<=0; end
else case (rs)
RA: if (rl_av) begin rbeat<=rl_aa[29:5]; rlat<=3'd4; rs<=RL; end
RL: if (rlat==0) rs<=RV; else rlat<=rlat-1'b1;
RV: if (rl_rrdy) rs<=RA;
endcase
end
// ================= scanout capture (from Brick-1 TB) =================
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed; logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; end
function automatic logic [23:0] px(input int y, input int x); px={cap_b[y][x],cap_g[y][x],cap_r[y][x]}; endfunction
// reload handshake witnesses
bit saw_reload_ready, saw_reload_start;
always_ff @(posedge clk) begin
if (!rst_n) begin saw_reload_ready<=0; saw_reload_start<=0; end
else begin
if (reload_start) saw_reload_start<=1'b1;
if (tile_reload_ready) saw_reload_ready<=1'b1;
end
end
// ---- DEBUG: trace region-A pixel (1,1) Z through the chain ----
// tile-local index for (lx=1,ly=1) = ly*16+lx = 17. screen Z byte = (1*64+1)*4=0x104.
// Z block in mem = (Z_BASE+0x104)>>5 = 0x88, lane = 0x104[4:2] = 1 (bits 63:32).
int reload_pass, zflush_evict;
logic [31:0] zA_spilled_data [0:3]; // z_flush_data emitted for region-A screen addr 0x104, per eviction
logic zA_spilled_seen [0:3];
logic [31:0] zA_reload_seen [0:3]; // tile_reload_z_i written into tile RAM idx 17, per reload pass
logic [31:0] zA_mem_at_reload [0:3];
bit mem_has_8000; // did 0x8000 ever appear anywhere in the Z region after batch1?
// emif-domain: each time the reload fill completes a read of the region-A Z block (0x88),
// capture what rdata word1 it got + how many fills ran.
logic [31:0] fillZ_blk88 [0:7]; int fill_blk88_n; int fill_done_edges; logic rdone_d;
always_ff @(posedge eclk) begin
if (!erst_n) begin fill_blk88_n<=0; fill_done_edges<=0; rdone_d<=0; end
else begin
if (rl_rv && rl_rrdy && rl_aa==30'h0000_1100 && fill_blk88_n<8) begin
fillZ_blk88[fill_blk88_n[2:0]]<=rl_rd[63:32]; fill_blk88_n<=fill_blk88_n+1;
end
rdone_d <= u_reload.reload_done;
if (u_reload.reload_done && !rdone_d) fill_done_edges<=fill_done_edges+1;
end
end
always_ff @(posedge clk) begin
if (!rst_n) begin reload_pass<=0; zflush_evict<=0;
zA_spilled_seen[0]<=0; zA_spilled_seen[1]<=0; zA_spilled_seen[2]<=0; zA_spilled_seen[3]<=0; end
else begin
if (reload_start) reload_pass<=reload_pass+1;
// region A screen Z byte addr = (1*64+1)*4 = 0x104. Capture what's emitted for it.
if (z_flush_emit && z_flush_addr[15:0]==16'h0104 && zflush_evict<4) begin
zA_spilled_data[zflush_evict[1:0]]<=z_flush_data; zA_spilled_seen[zflush_evict[1:0]]<=1'b1;
end
// count evictions: a rising edge of TP_ZFLUSH entry (phase 6)
if (tile_phase_o==3'd6 && dut.u_gs.tile_sweep_r==9'd0) zflush_evict<=zflush_evict+1;
if (dut.u_gs.reload_wr_we && dut.u_gs.reload_wr_addr==8'd17 && reload_pass<4) begin
zA_reload_seen[reload_pass[1:0]] <= tile_reload_z;
zA_mem_at_reload[reload_pass[1:0]] <= mem[10'h088][63:32];
end
end
end
int errors;
task automatic chk(input bit c, input string m); if (!c) begin errors++; $display("[lpddr] FAIL: %s", m); end endtask
logic [23:0] rA, rB;
initial begin
errors=0; core_go=0;
// Ch323 — simulate a CLEAN BOOT from SCRUB LPDDR: fill the backing with GARBAGE (high Z).
// The clean-Z bootstrap must still produce red-on-blue: batch-1 renders from the local
// CLEAR (it does NOT reload this garbage), spills, and batch-2 reloads batch-1's spill.
for (int i=0;i<1024;i++) mem[i]=256'h7EED7EED_7EED7EED_7EED7EED_7EED7EED_7EED7EED_7EED7EED_7EED7EED_7EED7EED;
rst_n=0; erst_n=0; repeat(8) @(posedge eclk); erst_n=1; repeat(4) @(posedge clk); rst_n=1; repeat(8) @(posedge clk);
@(negedge clk); core_go<=1'b1; @(negedge clk); core_go<=1'b0;
$display("[lpddr] @%0t booted, waiting core_halt", $time);
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
$display("[lpddr] @%0t waiting raster_active", $time);
wait (dut.u_gs.raster_active==1'b1);
wait (dut.u_gs.raster_active==1'b0); repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed<=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed<=1'b0;
rA = px(1,1); rB = px(10,2);
$display("[lpddr] regionA(1,1)=%06x regionB(10,2)=%06x", rA, rB);
$display("[lpddr] writers: c_beats=%0d z_beats=%0d c_ovf=%0d z_ovf=%0d reload: cbeats=%0d zbeats=%0d rderrs=%0d",
c_beats, z_beats, c_ovf, z_ovf, rl_cbeats, rl_zbeats, rl_rderrs);
$display("[lpddr] handshake: saw_reload_start=%0d saw_reload_ready=%0d reload_passes=%0d", saw_reload_start, saw_reload_ready, reload_pass);
$display("[lpddr] DEBUG region-A(idx17,screen 0x104) Z trace (evicts=%0d, reload passes=%0d):", zflush_evict, reload_pass);
for (int p=0;p<4;p++) if (zA_spilled_seen[p]) $display("[lpddr] evict %0d: z_flush emitted Z=0x%08x for region-A addr", p, zA_spilled_data[p]);
for (int p=0;p<4;p++) $display("[lpddr] reload slot %0d: idx17 served Z=0x%08x (mem lane1 was 0x%08x)", p, zA_reload_seen[p], zA_mem_at_reload[p]);
// scan the whole Z region in mem for any 0x8000 word
mem_has_8000 = 1'b0;
for (int bk=10'h080; bk<10'h0F0; bk++) for (int wd=0; wd<8; wd++)
if (mem[bk][wd*32+:32]==32'h0000_8000) mem_has_8000 = 1'b1;
$display("[lpddr] mem Z-region contains a 0x8000 word anywhere: %0d", mem_has_8000);
$display("[lpddr] fills completed (reload_done edges)=%0d, region-A Z-block reads=%0d:", fill_done_edges, fill_blk88_n);
for (int p=0;p<fill_blk88_n && p<8;p++) $display("[lpddr] fill read#%0d of block 0x88 word1 = 0x%08x", p, fillZ_blk88[p]);
$display("[lpddr] u_reload.z_ram[16..19] = %08x %08x %08x %08x (idx17 should be 0x8000)",
u_reload.z_ram[16], u_reload.z_ram[17], u_reload.z_ram[18], u_reload.z_ram[19]);
$display("[lpddr] u_reload final fill state rst_q=%0d row=%0d beat=%0d", u_reload.rst_q, u_reload.row, u_reload.beat);
// NEGATIVE bootstrap proof: SPILL_FORCE_VALID=1 forces batch-1 to RELOAD the GARBAGE
// (high-Z 0x7EED) backing instead of booting from clear. That garbage Z is enormous, so
// the GEQUAL depth test rejects EVERY fragment -> region A is NOT painted red. This proves
// the clean-Z bootstrap (skip reload on the first batch) is what makes the demo work.
chk(rA!==COLOR1[23:0],
$sformatf("NEG: region A = %06x but should NOT be red %06x — forced-valid garbage reload should defeat the render",
rA, COLOR1[23:0]));
$display("[neg] region A=%06x region B=%06x (forced-valid + garbage backing: render defeated as expected)", rA, rB);
if (errors==0) $display("[tb_gs_tile_spill_lpddr_neg] PASS");
else $display("[tb_gs_tile_spill_lpddr_neg] FAIL (errors=%0d)", errors);
$finish;
end
initial begin #5000000; $display("[tb_gs_tile_spill_lpddr_neg] TIMEOUT"); $display("[tb_gs_tile_spill_lpddr_neg] FAIL"); $finish; end
endmodule
sim/tb/top/tb_gs_tile_spill_reload.sv
+196
View File
@@ -0,0 +1,196 @@
// retroDE_ps2 — tb_gs_tile_spill_reload (Ch323 Brick 1c — two-batch DEPTH-survival proof)
//
// THE acceptance proof: tile-local color+Z can leave the chip and come back, and
// the reloaded Z affects a LATER render. Two TME+ABE+ZTE triangles (payload_tile_spill)
// render as two tile batches (single-prim mode); batch 2 reloads batch 1's flushed
// color+Z before rendering. The TB models the LPDDR backing (captured FROM the actual
// z_flush_* + color-flush streams — round-trip, not preloaded) and serves it on reload.
//
// Z scheme (CLEAR=0x4000, GEQUAL): P1 region A (top-left tri) Z=0x8000 color1(red);
// P2 region A+B (large tri) Z=0x6000 color2(blue). Region A pixel (1,1) overlaps both;
// region B pixel (10,2) is P2-only.
//
// NEGATIVE/POSITIVE flip (the real proof — Codex): two render passes via CORE_CTRL
// re-render. POSITIVE: batch-2 reload serves the captured backing → region A reloads
// P1's Z=0x8000 → P2(0x6000) FAILS → region A = color1. NEGATIVE: batch-2 reload serves
// CLEAR (0x4000) → P2 PASSES → region A = color2. The color1<->color2 flip in region A,
// with region B = color2 in BOTH, proves the result depends on Z reload, not stale state.
`timescale 1ns/1ps
module tb_gs_tile_spill_reload;
localparam int H_ACTIVE = 16, V_ACTIVE = 16;
localparam logic [2:0] TP_CLEAR=3'd1, TP_RENDER=3'd2, TP_FLUSH=3'd3, TP_RELOAD=3'd5, TP_ZFLUSH=3'd6;
localparam logic [31:0] CLEAR_Z = 32'h0000_4000, CLEAR_COLOR = 32'hFF00_8000;
localparam logic [31:0] COLOR1 = 32'hFF0000FF, COLOR2 = 32'hFFFF0000; // red / blue (ABGR)
logic clk=0; always #5 clk=~clk;
logic rst_n, core_go;
logic [7:0] r,g,b; logic hsync,vsync,de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow, frame_toggle, dma_done_toggle;
logic z_flush_emit; logic [31:0] z_flush_addr, z_flush_data;
logic flush_emit; logic [31:0] flush_addr, flush_color32;
logic reload_start; logic [7:0] tile_reload_raddr;
logic [31:0] tile_reload_color, tile_reload_z;
logic tile_reload_ready; // TB staging always warm (de25 adds fill latency in Brick 2)
// ---- behavioral LPDDR backing, captured FROM the flush streams (round-trip) ----
logic [31:0] z_backing [0:2047];
logic [31:0] c_backing [0:2047];
logic seen [0:2047];
logic neg_mode; // 1 = serve CLEAR (negative control)
// reload serve: register the raddr 1 cyc (gs_stub writes the tile RAM the cycle AFTER
// presenting raddr). map tile index -> screen index = y*64 + x (single tile @ origin, fbw=1).
// Procedural (not continuous `&&`) to avoid an iverilog vvp gate-elaboration quirk.
logic [7:0] sreg_raddr;
always_ff @(posedge clk) sreg_raddr <= tile_reload_raddr;
always_comb begin
logic [10:0] sidx;
logic ub;
tile_reload_ready = 1'b1;
sidx = (11'(sreg_raddr[7:4]) << 6) + 11'(sreg_raddr[3:0]); // screen index = y*64 + x
ub = (!neg_mode) && (seen[sidx] === 1'b1);
tile_reload_z = ub ? z_backing[sidx] : CLEAR_Z;
tile_reload_color = ub ? c_backing[sidx] : CLEAR_COLOR;
end
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(8*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_SPILL_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.flush_emit_o(flush_emit), .flush_addr_o(flush_addr), .flush_color32_o(flush_color32),
.z_flush_emit_o(z_flush_emit), .z_flush_addr_o(z_flush_addr), .z_flush_data_o(z_flush_data),
.reload_start_o(reload_start), .tile_reload_raddr_o(tile_reload_raddr),
.tile_reload_ready_i(tile_reload_ready), .tile_reload_color_i(tile_reload_color),
.tile_reload_z_i(tile_reload_z)
);
// ---- phase + counter snoops (per pass; reset by clr_counters) ----
int col_reload_w, z_reload_w, col_flush_e, z_flush_e, clear_z_w;
bit saw_reload, saw_flush, saw_zflush, backing_before_2nd_reload;
int z_flush_seen_count, reload_starts;
bit clr_counters;
always_ff @(posedge clk) begin
if (clr_counters) begin
col_reload_w<=0; z_reload_w<=0; col_flush_e<=0; z_flush_e<=0; clear_z_w<=0;
saw_reload<=0; saw_flush<=0; saw_zflush<=0; backing_before_2nd_reload<=0;
z_flush_seen_count<=0; reload_starts<=0;
end else if (rst_n) begin
// capture flush streams into the backing (round-trip).
if (z_flush_emit) begin z_backing[z_flush_addr[12:2]]<=z_flush_data; seen[z_flush_addr[12:2]]<=1'b1;
z_flush_e<=z_flush_e+1; z_flush_seen_count<=z_flush_seen_count+1; end
if (flush_emit) begin c_backing[flush_addr[12:2]]<=flush_color32; col_flush_e<=col_flush_e+1; end
// tile-RAM write attribution by phase.
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_z_we) clear_z_w<=clear_z_w+1;
if (dut.u_gs.tile_phase==TP_RELOAD) begin
saw_reload<=1'b1;
if (dut.u_gs.tile_color_we) col_reload_w<=col_reload_w+1;
if (dut.u_gs.tile_z_we) z_reload_w<=z_reload_w+1;
end
if (dut.u_gs.tile_phase==TP_FLUSH) saw_flush<=1'b1;
if (dut.u_gs.tile_phase==TP_ZFLUSH) saw_zflush<=1'b1;
// Ch323 clean-Z BOOTSTRAP: batch-1 (no valid backing) does NOT reload — it renders
// from the local CLEAR. Only batch-2 reloads, and by then batch-1's spill must have
// populated the backing. So there is exactly ONE reload_start, and z_flush has fired.
if (reload_start) begin
reload_starts <= reload_starts + 1;
if (z_flush_seen_count>0) backing_before_2nd_reload<=1'b1;
end
end
end
// ---- scanout capture ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed; logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; end
int errors;
task automatic chk(input bit c, input string m);
if (!c) begin errors++; $display("[spill] FAIL: %s", m); end endtask
function automatic logic [23:0] px(input int y, input int x); px={cap_b[y][x],cap_g[y][x],cap_r[y][x]}; endfunction
// run one render pass: full DUT reset + fresh boot (the bootlet re-uploads the texture
// and re-renders both prims), then capture region A/B. seen[] is cleared so batch-1's
// reload serves clear; the backing is repopulated from THIS pass's batch-1 flush.
task automatic run_pass(output logic [23:0] rA, output logic [23:0] rB);
for (int i=0;i<2048;i++) seen[i]=1'b0;
rst_n<=1'b0; repeat(4) @(posedge clk); rst_n<=1'b1; repeat(8) @(posedge clk);
clr_counters<=1'b1; @(posedge clk); clr_counters<=1'b0;
@(negedge clk); core_go<=1'b1; @(negedge clk); core_go<=1'b0;
$display("[spill] @%0t booted, waiting core_halt", $time);
wait (core_halt==1'b1); repeat(4) @(posedge clk);
$display("[spill] @%0t core_halt, waiting dma_done", $time);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
$display("[spill] @%0t dma_done, xfer_busy=%0d", $time, dut.xfer_busy);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
$display("[spill] @%0t waiting raster_active rise", $time);
wait (dut.u_gs.raster_active==1'b1); // level-sensitive (robust to an already-passed edge)
$display("[spill] @%0t raster_active high, waiting fall", $time);
wait (dut.u_gs.raster_active==1'b0); repeat(10) @(posedge clk);
$display("[spill] @%0t raster done, waiting end_of_frame", $time);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed<=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed<=1'b0;
$display("[spill] @%0t frame captured", $time);
rA = px(1,1); rB = px(10,2);
endtask
logic [23:0] posA, posB, negA, negB;
int p_creload, p_zreload, p_cflush, p_zflush;
initial begin
errors=0; rst_n=1; core_go=0; neg_mode=0; clr_counters=0;
// ---- POSITIVE pass: batch-2 reload serves the captured backing ----
$display("[spill] starting POSITIVE pass ...");
neg_mode<=1'b0;
run_pass(posA, posB);
$display("[spill] POSITIVE pass done: regionA=%06x regionB=%06x", posA, posB);
p_creload=col_reload_w; p_zreload=z_reload_w; p_cflush=col_flush_e; p_zflush=z_flush_e;
chk(saw_reload, "FSM never entered TP_RELOAD");
chk(saw_flush, "FSM never entered TP_FLUSH");
chk(saw_zflush, "FSM never entered TP_ZFLUSH");
chk(backing_before_2nd_reload, "backing not populated before batch-2 reload");
chk(clear_z_w >= 256, $sformatf("batch-2 CLEAR didn't clobber tile Z (clear_z_w=%0d)", clear_z_w));
// BOOTSTRAP: only batch-2 reloads (batch-1 renders from clear) -> 256 reload writes, not 512.
chk(p_creload==256, $sformatf("color reload writes=%0d exp 256 (batch-2 only; batch-1 boots from clear)", p_creload));
chk(p_zreload==256, $sformatf("Z reload writes=%0d exp 256", p_zreload));
chk(p_cflush ==512, $sformatf("color flush emits=%0d exp 512 (both batches flush)", p_cflush));
chk(p_zflush ==512, $sformatf("Z flush emits=%0d exp 512", p_zflush));
// ---- NEGATIVE pass: batch-2 reload serves CLEAR (control) ----
$display("[spill] starting NEGATIVE pass ...");
neg_mode<=1'b1;
run_pass(negA, negB);
$display("[spill] NEGATIVE pass done: regionA=%06x regionB=%06x", negA, negB);
// ---- the flip: region A must change with reload, region B stays P2 ----
chk(posA===COLOR1[23:0], $sformatf("POSITIVE region A=%06x exp color1 %06x (Z reload should make P2 fail)", posA, COLOR1[23:0]));
chk(negA===COLOR2[23:0], $sformatf("NEGATIVE region A=%06x exp color2 %06x (no reload -> P2 passes)", negA, COLOR2[23:0]));
chk(posB===COLOR2[23:0], $sformatf("POSITIVE region B=%06x exp color2 %06x (control)", posB, COLOR2[23:0]));
chk(negB===COLOR2[23:0], $sformatf("NEGATIVE region B=%06x exp color2 %06x (control)", negB, COLOR2[23:0]));
chk(posA!==negA, "region A did NOT flip between reload-on and reload-off (proof void)");
$display("=== Ch323 tile spill/reload two-batch proof ===");
$display(" counts(positive): color_reload=%0d Z_reload=%0d (exp 256, batch-2 only) color_flush=%0d Z_flush=%0d (exp 512)",
p_creload, p_zreload, p_cflush, p_zflush);
$display(" FSM: reload=%0d flush=%0d zflush=%0d backing_before_2nd_reload=%0d clear_clobber=%0d",
saw_reload, saw_flush, saw_zflush, backing_before_2nd_reload, clear_z_w);
$display(" region A: positive=%06x negative=%06x (exp color1=%06x / color2=%06x)", posA, negA, COLOR1[23:0], COLOR2[23:0]);
$display(" region B: positive=%06x negative=%06x (exp color2=%06x both)", posB, negB, COLOR2[23:0]);
if (errors==0) $display("[tb_gs_tile_spill_reload] PASS");
else $display("[tb_gs_tile_spill_reload] FAIL (%0d errors)", errors);
$finish;
end
initial begin #100000000; $display("[tb_gs_tile_spill_reload] TIMEOUT"); $finish; end
endmodule
sim/tb/top/tb_gs_tile_zflush.sv
+137
View File
@@ -0,0 +1,137 @@
// retroDE_ps2 — tb_gs_tile_zflush (Ch323 Brick 1b — focused FSM-sequencing TB)
//
// Proves the Ch323 TP_ZFLUSH phase BEFORE the big two-batch proof (Codex: fast failure
// surface for state-sequencing bugs). Renders ONE 16x16 combined-TAZ tile with
// TILE_SPILL_ENABLE=1 and checks the Z-flush stream:
// - exactly 256 Z emits (one per tile pixel — no missing last / no duplicate first)
// - each z_flush_addr = pixel_index*4 (Z-backing-relative, 32-bit Z), each index once
// - z_flush_data == the tile Z RAM contents at flush time (snooped via tile_z writes:
// CLEAR sets all 256 to TILE_CLEAR_Z, RENDER overwrites covered pixels) — Z is NOT
// truncated/endian-swapped
// - color flush count UNCHANGED (256, full tile) — the color path is untouched
// - the FSM actually entered TP_ZFLUSH (after the color FLUSH)
`timescale 1ns/1ps
module tb_gs_tile_zflush;
localparam int H_ACTIVE = 16, V_ACTIVE = 16;
localparam logic [2:0] TP_FLUSH = 3'd3, TP_ZFLUSH = 3'd6;
localparam logic [31:0] TILE_CLEAR_Z = 32'h0000_4000; // matches gs_stub
logic clk = 0; always #5 clk = ~clk;
logic rst_n, core_go;
logic [7:0] r,g,b; logic hsync,vsync,de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow, frame_toggle, dma_done_toggle;
logic z_flush_emit; logic [31:0] z_flush_addr, z_flush_data;
// Reload staging: this TB exercises Z-FLUSH, so make reload a re-clear (staging returns the
// clear values, always warm) — the tile starts as if cleared, so the Z-flush check is unchanged.
logic reload_start; logic [7:0] tile_reload_raddr;
wire tile_reload_ready = 1'b1;
wire [31:0] tile_reload_color = 32'hFF00_8000; // TILE_CLEAR_COLOR
wire [31:0] tile_reload_z = 32'h0000_4000; // TILE_CLEAR_Z
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(8*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_SPILL_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.z_flush_emit_o(z_flush_emit), .z_flush_addr_o(z_flush_addr), .z_flush_data_o(z_flush_data),
.reload_start_o(reload_start), .tile_reload_raddr_o(tile_reload_raddr),
.tile_reload_ready_i(tile_reload_ready), .tile_reload_color_i(tile_reload_color),
.tile_reload_z_i(tile_reload_z)
);
// ---- snoop the tile Z RAM contents (mirror), indexed by TILE index (waddr 0..255):
// CLEAR writes all 256, RENDER overwrites covered pixels.
logic [31:0] z_mirror [0:255];
// ---- capture the Z-flush stream keyed by SCREEN pixel index (addr>>2). The Z is flushed
// at the screen position (screen_index*4), mirroring the color flush, so we map tile index
// -> screen index = (tile_oy+y)*fbw*64 + (tile_ox+x) at compare time. Single tile @ origin.
logic [31:0] z_got [0:2047];
bit z_seen [0:2047];
int z_count, color_count;
logic [5:0] fbw_seen;
bit saw_zflush, zflush_after_flush;
logic [2:0] phase_d;
initial begin
for (int i=0;i<256;i++) z_mirror[i]=32'hX;
for (int i=0;i<2048;i++) begin z_got[i]=32'h0; z_seen[i]=1'b0; end
z_count=0; color_count=0; fbw_seen=6'd1; saw_zflush=0; zflush_after_flush=0; phase_d=3'd0;
end
always_ff @(posedge clk) begin
if (rst_n) begin
// tile Z RAM mirror (any phase that writes Z: CLEAR + RENDER).
if (dut.u_gs.tile_z_we) z_mirror[dut.u_gs.tile_z_waddr] <= dut.u_gs.tile_z_wdata;
// color flush emits (raster_pixel_emit) — must stay 256 (full tile), unchanged.
if (dut.u_gs.raster_pixel_emit) begin
color_count <= color_count + 1;
fbw_seen <= dut.u_gs.ras_fbw; // FB width (×64 px) for the screen-index map
end
// Z-flush stream capture, keyed by screen pixel index = addr>>2.
if (z_flush_emit) begin
int sidx; sidx = int'(z_flush_addr >> 2);
if (sidx >= 0 && sidx < 2048) begin
z_got[sidx] <= z_flush_data; z_seen[sidx] <= 1'b1;
end
z_count <= z_count + 1;
end
// phase tracking: did we enter TP_ZFLUSH, and did it follow TP_FLUSH?
phase_d <= dut.u_gs.tile_phase;
if (dut.u_gs.tile_phase == TP_ZFLUSH) begin
saw_zflush <= 1'b1;
if (phase_d == TP_FLUSH) zflush_after_flush <= 1'b1;
end
end
end
int errors;
task automatic chk(input bit c, input string m);
if (!c) begin errors++; $display("[zflush] FAIL: %s", m); end endtask
initial begin
errors=0; rst_n=0; core_go=0;
repeat(4) @(posedge clk); rst_n=1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active); // falls only after TP_ZFLUSH completes
repeat(10) @(posedge clk);
// ---- assertions ----
chk(saw_zflush, "FSM never entered TP_ZFLUSH");
chk(zflush_after_flush, "TP_ZFLUSH did not follow TP_FLUSH");
chk(z_count == 256, $sformatf("z_flush count=%0d exp 256 (off-by-one?)", z_count));
chk(color_count == 256, $sformatf("color flush count=%0d exp 256 (color path disturbed!)", color_count));
begin int miss=0, mism=0, stride; stride = int'(fbw_seen) * 64;
for (int i=0;i<256;i++) begin
int x, y, sidx; x = i & 8'h0F; y = (i >> 4) & 8'h0F;
sidx = y*stride + x; // single tile @ origin (ox=oy=0)
if (!z_seen[sidx]) miss++;
else if (z_got[sidx] !== z_mirror[i]) begin
mism++;
if (mism<=6) $display("[zflush] Z mismatch tile idx %0d (screen %0d): flushed %08x exp(tileZ) %08x",
i, sidx, z_got[sidx], z_mirror[i]);
end
end
chk(miss==0, $sformatf("%0d tile pixels never Z-flushed at their screen addr", miss));
chk(mism==0, $sformatf("%0d Z values != tile Z RAM", mism));
end
chk(!raster_overflow, "raster_overflow set");
$display("[zflush] z_count=%0d color_count=%0d saw_zflush=%0d after_flush=%0d errors=%0d",
z_count, color_count, saw_zflush, zflush_after_flush, errors);
if (errors==0) $display("[tb_gs_tile_zflush] PASS");
else $display("[tb_gs_tile_zflush] FAIL");
$finish;
end
initial begin #20000000; $display("[tb_gs_tile_zflush] TIMEOUT"); $finish; end
endmodule
sim/tb/top/tb_hdmi_i2c_wake_smoke.sv
+526
View File
@@ -0,0 +1,526 @@
// retroDE_ps2 — tb_hdmi_i2c_wake_smoke (Ch165 Medium + Ch166 NACK watchdog + Ch167 byte-sequence lock)
//
// Focused, accelerated bring-up TB for the Ch165 ADV7513 I²C
// wake-up FSM (`I2C_HDMI_Config` → `I2C_Controller`). The
// existing Ch149 board TB only smoke-tests the wrapper and
// can't observe the LUT walk because at the production I²C
// clock divider (50 MHz / 20 kHz = 2500) the full 38-entry
// walk takes ~125 ms simulated (controller-clock period
// ~100 µs × 33 phases per byte × 38 bytes) — far longer
// than the 5 ms board-TB runtime. This TB instantiates
// `I2C_HDMI_Config` directly with a tiny `CLK_Freq / I2C_Freq`
// ratio so the LUT walks in microseconds, then exercises:
// Phase 1 — `LUT_INDEX` advances 0 → LUT_SIZE−1 (38-entry walk).
// Phase 1 — `READY` (= `hdmi_init_done`) rises after the walk.
// Phase 1 — Ch167 byte-sequence lock: a bus-level decoder samples
// SDA on each SCL rising edge between START/STOP and
// assembles all 38 transactions as 24-bit
// {dev_addr, reg, data} tuples; in parallel a snoop on
// `mI2C_GO` rises captures the FSM-intent payload from
// `u_dut.mI2C_DATA[23:0]`. After the walk completes the
// test asserts the captured wire bytes match the
// FSM-intent bytes one-for-one and that every dev_addr
// is 8'h72 (ADV7513 write address).
// Phase 2 — `HDMI_TX_INT` low retriggers the FSM (`LUT_INDEX`
// back to 0; `READY` falls until the second walk).
// Bus capture is disabled here so the retrigger walk
// doesn't overflow the captured/expected logs.
// Phase 3 — Open-drain shape check: SDA is never `'x` (would
// indicate two drivers contending for strong-HIGH).
// Phase 1-3 — `ERROR` (Ch166 NACK watchdog) stays LOW on the
// healthy bus.
// Phase 4 — Force `u_dut.mI2C_ACK = 1` to simulate a slave that
// never ACKs. The FSM retries the same LUT entry; after
// NACK_LIMIT (overridden to 4) consecutive retries
// `ERROR` must latch HIGH. Releasing the force must
// NOT clear `ERROR` (sticky semantics).
//
// Bus model — Ch167 switched the legacy pulldown(sda) to
// pullup(sda) plus a minimal slave-ACK driver: after each START,
// count SCL rising edges; on the 8th, 17th, and 26th edge the
// slave drives SDA strong-LOW for one ACK clock so the master
// FSM sees ACK=0 and advances. Pullup is required because the
// master encodes a 1-bit by *releasing* SDA (1'bz), and a
// pulldown would mask every released bit as 0 — preventing
// byte-level decode.
//
// Slave model: the TB pulls SDA LOW unconditionally (weak
// pulldown). The master drives SDA either strong-LOW (sending
// 0 or releasing to high-Z while the chip ACKs); on
// release-cycles the pulldown wins and the master reads ACK=0
// → the FSM advances every byte. Data correctness on the bus
// is NOT modeled — this TB only verifies FSM progress + the
// open-drain release behavior, which is exactly the audit's
// scope (`Medium — verify the LUT walk + READY + SDA + INT
// retrigger`).
`timescale 1ns/1ps
module tb_hdmi_i2c_wake_smoke;
// 100 MHz TB clock. The wake-up FSM divides this internally,
// but the parameter overrides below collapse the divider to
// ~2 cycles per I²C controller-clock toggle.
logic clk;
initial clk = 1'b0;
always #5 clk = ~clk;
logic rst_n;
logic hdmi_tx_int;
// I²C bus modeling. The bus floats high through external
// pull-ups in real hardware. Ch167 byte-sequence-lock work
// requires the line to read each transmitted bit faithfully:
// master drives strong-LOW for 0 and releases (1'bz) for 1,
// so a pull-up is needed to bring 1's up to 1'b1 (pulldown
// would mask every released bit as 0). The minimal I²C slave
// model below drives SDA strong-LOW during the three ACK
// windows of every transaction so the master FSM sees ACK=0
// and advances to the next LUT entry.
wire scl;
wire sda;
pullup(sda);
// ----------------------------------------------------------
// Bus-edge detection (used by the slave-ACK driver and the
// byte-sequence decoder). Sampled on the TB master clock.
// ----------------------------------------------------------
reg scl_d, sda_d;
always_ff @(posedge clk) begin
scl_d <= scl;
sda_d <= sda;
end
wire scl_rise = scl && !scl_d;
wire sda_fall_during_scl_high = scl && !sda && sda_d;
wire sda_rise_during_scl_high = scl && sda && !sda_d;
// ----------------------------------------------------------
// Minimal I²C slave-ACK driver. The master's I2C_Controller
// FSM lives at u_dut.u0; phase encoding is a 6-bit register
// with PH_ACK0=11, PH_ACK1=20, PH_ACK2=29 (see
// rtl/platform/I2C_Controller.v parameters). Drive SDA
// strong-LOW for the entire ACK phase so the master sees
// ACK=0 regardless of where it samples within the phase.
// Outside ACK phases SDA is 1'bz so the master's data bits
// (released → 1'b1, driven → 1'b0) are visible to the
// byte decoder. This is far more robust than counting SCL
// edges (which races at ACK boundaries when input-clock
// resolution is only 2× the controller-clock period).
// ----------------------------------------------------------
wire slave_in_ack_phase =
(u_dut.u0.phase == 6'd11) || // PH_ACK0
(u_dut.u0.phase == 6'd20) || // PH_ACK1
(u_dut.u0.phase == 6'd29); // PH_ACK2
assign sda = slave_in_ack_phase ? 1'b0 : 1'bz;
// ----------------------------------------------------------
// Ch167 byte-sequence lock. Bus-level decoder: between
// START and STOP, sample SDA on each SCL rising edge and
// assemble three 8-bit data bytes (skipping the ACK windows
// at edges 8, 17, 26). On STOP, append the 24-bit
// {dev_addr, reg, data} payload to a captured[] log. A
// parallel snoop on `mI2C_GO` rising edges captures the
// FSM's intent (`u_dut.mI2C_DATA[23:0]`) into expected[].
// After the first LUT walk completes (Phase 1), the test
// asserts captured[i] === expected[i] for i = 0..LUT_SIZE-1.
// ----------------------------------------------------------
bit bus_capture_enable;
initial bus_capture_enable = 1'b1;
typedef enum logic [0:0] { DEC_IDLE, DEC_TXN } dec_state_t;
dec_state_t dec_state;
int dec_bit_count;
logic [23:0] dec_payload;
int captured_count;
logic [23:0] captured [0:63];
always_ff @(posedge clk) begin
if (!rst_n) begin
dec_state <= DEC_IDLE;
dec_bit_count <= 0;
dec_payload <= 24'h0;
captured_count <= 0;
end else if (bus_capture_enable) begin
case (dec_state)
DEC_IDLE: begin
if (sda_fall_during_scl_high) begin
dec_state <= DEC_TXN;
dec_bit_count <= 0;
dec_payload <= 24'h0;
end
end
DEC_TXN: begin
if (sda_rise_during_scl_high &&
!slave_in_ack_phase &&
dec_bit_count >= 27) begin
// STOP — record the captured payload.
if (captured_count < 64)
captured[captured_count] <= dec_payload;
captured_count <= captured_count + 1;
dec_state <= DEC_IDLE;
end else if (scl_rise && dec_bit_count < 27) begin
// Map SCL-rise position within transaction
// to a bit slot in the 24-bit payload
// (MSB-first per byte). Edges 8/17/26 are
// ACK windows - sample but discard.
case (dec_bit_count)
0: dec_payload[23] <= sda;
1: dec_payload[22] <= sda;
2: dec_payload[21] <= sda;
3: dec_payload[20] <= sda;
4: dec_payload[19] <= sda;
5: dec_payload[18] <= sda;
6: dec_payload[17] <= sda;
7: dec_payload[16] <= sda;
// 8 = ACK0
9: dec_payload[15] <= sda;
10: dec_payload[14] <= sda;
11: dec_payload[13] <= sda;
12: dec_payload[12] <= sda;
13: dec_payload[11] <= sda;
14: dec_payload[10] <= sda;
15: dec_payload[9] <= sda;
16: dec_payload[8] <= sda;
// 17 = ACK1
18: dec_payload[7] <= sda;
19: dec_payload[6] <= sda;
20: dec_payload[5] <= sda;
21: dec_payload[4] <= sda;
22: dec_payload[3] <= sda;
23: dec_payload[2] <= sda;
24: dec_payload[1] <= sda;
25: dec_payload[0] <= sda;
// 26 = ACK2
default: ;
endcase
dec_bit_count <= dec_bit_count + 1;
end
end
endcase
end
end
// FSM-intent snoop: capture u_dut.mI2C_DATA on each rising
// edge of u_dut.mI2C_GO. The FSM raises GO once per LUT
// entry's first attempt (and again on each retry, but
// expected_count is gated to LUT_SIZE so retries don't
// overflow).
reg mi2c_go_d;
int expected_count;
logic [23:0] expected_seq [0:63];
always_ff @(posedge clk) begin
if (!rst_n) begin
mi2c_go_d <= 1'b0;
expected_count <= 0;
end else begin
mi2c_go_d <= u_dut.mI2C_GO;
if (u_dut.mI2C_GO && !mi2c_go_d && bus_capture_enable) begin
if (expected_count < 64)
expected_seq[expected_count] <= u_dut.mI2C_DATA[23:0];
expected_count <= expected_count + 1;
end
end
end
// The DUT. Tiny CLK_Freq/I2C_Freq ratio (≈ 1) collapses the
// controller-clock divider so the LUT walks in microseconds
// instead of tens of milliseconds. NACK_LIMIT shrunk from
// production 16 → 4 so Phase 4 (forced-NACK error trigger)
// finishes in microseconds rather than tens of ms.
logic ready;
logic dut_error;
I2C_HDMI_Config #(
.CLK_Freq (2),
.I2C_Freq (1),
.LUT_SIZE (38),
.NACK_LIMIT (4)
) u_dut (
.iCLK (clk),
.iRST_N (rst_n),
.I2C_SCLK (scl),
.I2C_SDAT (sda),
.HDMI_TX_INT(hdmi_tx_int),
.READY (ready),
.ERROR (dut_error)
);
// ----------------------------------------------------------
// Phase 1: reset, watch the FSM walk LUT_INDEX 0 → 37.
// ----------------------------------------------------------
int errors;
int lut_index_max_seen;
int ready_rise_cycles;
bit saw_lut_full_walk;
bit saw_ready_rise;
bit saw_error_during_happy_path;
// Hoisted out of the Phase-2/Phase-3/Phase-4 initial block below so
// iverilog 12 (which rejects mid-block declarations after executable
// statements) accepts the file. Module-scope `bit`/`int` initialize
// to 0 / 1'b0.
bit saw_restart;
int lut_idx_after_int;
int sda_high_obs;
bit saw_error_rise;
initial begin
errors = 0;
lut_index_max_seen = 0;
ready_rise_cycles = 0;
saw_lut_full_walk = 1'b0;
saw_ready_rise = 1'b0;
rst_n = 1'b0;
hdmi_tx_int = 1'b1; // deasserted (active-low)
repeat (10) @(posedge clk);
rst_n = 1'b1;
end
// Track the highest LUT_INDEX ever observed, and whether the
// ERROR output ever rose during the "happy path" (Phases 1-3,
// before the explicit NACK-injection Phase 4 begins).
bit happy_path_active;
initial happy_path_active = 1'b1;
always_ff @(posedge clk) begin
if (rst_n) begin
if (int'(u_dut.LUT_INDEX) > lut_index_max_seen)
lut_index_max_seen <= int'(u_dut.LUT_INDEX);
if (u_dut.LUT_INDEX == u_dut.LUT_SIZE - 1)
saw_lut_full_walk <= 1'b1;
if (ready && !saw_ready_rise) begin
saw_ready_rise <= 1'b1;
ready_rise_cycles <= 0;
end else if (saw_ready_rise) begin
ready_rise_cycles <= ready_rise_cycles + 1;
end
if (happy_path_active && dut_error)
saw_error_during_happy_path <= 1'b1;
end
end
// ----------------------------------------------------------
// Slave-side ACK behavior is implicit in the SDA pulldown:
// when the master releases SDA at the 9th bit, the bus reads
// LOW, the controller's mI2C_ACK samples 0, and the wake-up
// FSM advances to LUT_INDEX+1. Sanity-check that the bus is
// actually toggling (master drives SCL) — if SCL never
// toggles, the FSM is stuck and we'd time out below.
int scl_edge_count;
initial scl_edge_count = 0;
always @(scl) if (rst_n) scl_edge_count = scl_edge_count + 1;
// ----------------------------------------------------------
// Phase 2: once READY, pull HDMI_TX_INT LOW briefly and
// assert the LUT walk restarts (LUT_INDEX returns to 0;
// READY falls).
// ----------------------------------------------------------
initial begin
// Wait for the first LUT walk to complete.
wait (rst_n);
fork
begin
wait (ready == 1'b1);
end
begin
#5_000_000; // 5 ms wall budget
$error("Phase 1: READY never asserted in 5 ms (LUT walk stuck or too slow)");
errors = errors + 1;
end
join_any
disable fork;
// Phase 1 asserts. LUT_INDEX walks 0..LUT_SIZE-1 inside the
// case() loop, then the post-step increments it to LUT_SIZE
// (38) on the cycle the FSM falls through to the READY-high
// branch — so the max value ever observed is LUT_SIZE, not
// LUT_SIZE-1. The full-walk evidence comes from the separate
// `saw_lut_full_walk` flag (LUT_INDEX == LUT_SIZE-1).
if (lut_index_max_seen != 38) begin
$error("Phase 1: LUT_INDEX max seen = %0d, expected 38 (LUT_SIZE)", lut_index_max_seen);
errors = errors + 1;
end
if (!saw_lut_full_walk) begin
$error("Phase 1: never observed LUT_INDEX == LUT_SIZE-1 (37)");
errors = errors + 1;
end
if (!ready) begin
$error("Phase 1: READY low after wait — fork race");
errors = errors + 1;
end
if (scl_edge_count < 100) begin
$error("Phase 1: only %0d SCL edges seen — bus is stuck", scl_edge_count);
errors = errors + 1;
end
// ------------------------------------------------------
// Ch167 byte-sequence lock. Compare every captured
// 24-bit transaction (assembled from the wire) against
// the FSM-intent snapshot (assembled at mI2C_GO rise).
// Both should be exactly LUT_SIZE entries long; mismatch
// means either the controller miswired the data path or
// the FSM tried to send something unexpected.
// ------------------------------------------------------
// Settle a few extra cycles so the last STOP gets recorded.
repeat (32) @(posedge clk);
if (captured_count != int'(u_dut.LUT_SIZE)) begin
$error("Ch167: captured %0d transactions on the wire, expected %0d",
captured_count, u_dut.LUT_SIZE);
errors = errors + 1;
end
if (expected_count != int'(u_dut.LUT_SIZE)) begin
$error("Ch167: snooped %0d FSM-intent payloads, expected %0d",
expected_count, u_dut.LUT_SIZE);
errors = errors + 1;
end
for (int i = 0; i < int'(u_dut.LUT_SIZE); i++) begin
if (captured[i] !== expected_seq[i]) begin
$error("Ch167: txn %0d mismatch: bus=24'h%06h fsm=24'h%06h",
i, captured[i], expected_seq[i]);
errors = errors + 1;
end
end
// First byte of every transaction must be 8'h72 = ADV7513
// write address (7-bit 0x39 << 1, R/W=0). Cross-check the
// captured stream directly so we lock the dev_addr too.
for (int i = 0; i < int'(u_dut.LUT_SIZE); i++) begin
if (captured[i][23:16] !== 8'h72) begin
$error("Ch167: txn %0d dev_addr=8'h%02h, expected 8'h72",
i, captured[i][23:16]);
errors = errors + 1;
end
end
// Disable bus capture for the rest of the test —
// Phase 2 retriggers the LUT (would overflow captured[])
// and Phase 4 forces NACKs (broken bus by design).
bus_capture_enable = 1'b0;
// Phase 2: HDMI_TX_INT retrigger. Pull INT low while
// READY is high; the FSM should reset LUT_INDEX to 0
// and re-walk.
@(posedge clk); hdmi_tx_int = 1'b0;
// Hold long enough for the FSM to sample it.
repeat (8) @(posedge clk);
hdmi_tx_int = 1'b1;
// Wait for LUT_INDEX to dip back below the max (proves
// the FSM restarted) and then for READY to come back up.
saw_restart = 1'b0;
fork
begin
wait (u_dut.LUT_INDEX == 0);
saw_restart = 1'b1;
end
begin
#5_000_000;
$error("Phase 2: LUT_INDEX never returned to 0 after HDMI_TX_INT pulse");
errors = errors + 1;
end
join_any
disable fork;
if (!saw_restart) begin
// (already errored above)
end else begin
// Wait for the second walk to complete.
fork
begin
wait (ready == 1'b1 && u_dut.LUT_INDEX >= u_dut.LUT_SIZE);
end
begin
#5_000_000;
$error("Phase 2: READY did not reassert after retrigger walk");
errors = errors + 1;
end
join_any
disable fork;
end
// Phase 3: open-drain shape check. With the Ch167 pullup
// + slave-ACK bus model, the line is HIGH at idle and
// LOW only when the master drives a 0 or when the slave
// drives the ACK. The relevant violation is that no two
// drivers ever simultaneously drive strong-HIGH (which
// would resolve to 'x' on a tri-state wire). Sample SDA
// repeatedly and assert it is never 'x'.
// (Reusing `sda_high_obs` as the violation counter.)
sda_high_obs = 0;
repeat (50) begin
@(posedge clk);
if (sda === 1'bx) sda_high_obs = sda_high_obs + 1;
end
if (sda_high_obs > 0) begin
$error("Phase 3: SDA was 'x' on %0d/50 sample cycles (driver conflict / open-drain violation)",
sda_high_obs);
errors = errors + 1;
end
// Happy-path ERROR check: across Phases 1-3 the bus was
// healthy (pulldown → ACK=0), so the NACK watchdog must
// never have fired.
if (saw_error_during_happy_path) begin
$error("Happy path: ERROR rose during normal walk (NACK watchdog false-positive)");
errors = errors + 1;
end
if (dut_error) begin
$error("Happy path: ERROR is HIGH at end of Phase 3 (expected LOW)");
errors = errors + 1;
end
// ----------------------------------------------------------
// Phase 4: forced-NACK error trigger. The healthy bus
// produced ACK=0 every byte (master sees the pulldown
// win the release window). Force `mI2C_ACK = 1'b1` to
// simulate a slave that doesn't ACK — every transaction
// bounces back to mSetup_ST=0 and retries the same LUT
// entry. After NACK_LIMIT consecutive retries (overridden
// to 4 above) the watchdog must latch ERROR.
//
// We also pulse HDMI_TX_INT so the FSM restarts the walk
// at LUT_INDEX=0 → predictable retry counter starting
// point.
happy_path_active = 1'b0;
@(posedge clk); hdmi_tx_int = 1'b0;
repeat (8) @(posedge clk);
hdmi_tx_int = 1'b1;
wait (u_dut.LUT_INDEX == 0);
force u_dut.mI2C_ACK = 1'b1;
saw_error_rise = 1'b0;
fork
begin
wait (dut_error == 1'b1);
saw_error_rise = 1'b1;
end
begin
#5_000_000;
$error("Phase 4: ERROR never asserted within 5 ms after forced NACK");
errors = errors + 1;
end
join_any
disable fork;
// ERROR is sticky. Releasing the force (slave starts ACKing
// again) must NOT clear it — only iRST_N would.
release u_dut.mI2C_ACK;
repeat (200) @(posedge clk);
if (!dut_error) begin
$error("Phase 4: ERROR was not sticky — went LOW after force released");
errors = errors + 1;
end
$display("[tb_hdmi_i2c_wake_smoke] lut_index_max=%0d saw_full_walk=%0b saw_ready_rise=%0b scl_edges=%0d saw_error_rise=%0b errors=%0d",
lut_index_max_seen, saw_lut_full_walk, saw_ready_rise,
scl_edge_count, saw_error_rise, errors);
if (errors == 0) $display("[tb_hdmi_i2c_wake_smoke] PASS");
else $display("[tb_hdmi_i2c_wake_smoke] FAIL");
$finish;
end
// Hard timeout — bound the whole test.
initial begin
#20_000_000;
$error("[tb_hdmi_i2c_wake_smoke] hard timeout");
$finish;
end
endmodule : tb_hdmi_i2c_wake_smoke
sim/tb/top/tb_top_psmct32_alpha_blend_demo.sv
+223
View File
@@ -0,0 +1,223 @@
// retroDE_ps2 — tb_top_psmct32_alpha_blend_demo (Brick 2a)
//
// TOP-LEVEL alpha-blend (transparency) demo TB for the BRAM BOARD
// VARIANT. Proves the synthesizable FLAT alpha-blended SPRITE path
// renders end-to-end through `top_psmct32_raster_demo_bram` — the
// variant the de25_nano board top instantiates — exactly as a board
// load would SHOW on HDMI.
//
// EE bootlet (bios_alpha.mem) + GIF payload (payload_alpha.mem):
// U1 PACKED -> opaque BG SPRITE (ABE=0) solid blue, full 16x8.
// U2 PACKED -> semi-transparent overlay SPRITE (PRIM.ABE=1,
// source-over ALPHA_1, RGBAQ.A=0x40, red) over x[0..7].
//
// The overlay pixel is a read-MODIFY-write against the framebuffer:
// the GS reads the BG pixel back through vram_bram_stub.read2 (the same
// spare port the texel fetch uses — mutually exclusive because a flat
// blend never textures) and blends source-over.
//
// Source-over Cv = ((Cs - Cd) * As) >> 7 + Cd, As=0x40 (=64):
// overlap (x in [0..7]) -> (0x7F, 0x00, 0x60)
// non-overlap (x in [8..15]) -> pure BG blue (0x00, 0x00, 0xC0)
//
// Verification is via the PCRTC scanout RGB (the same r/g/b/de a board
// wires to a video PHY). The overlap is asserted to be NEITHER the pure
// source (0xFF,0x00,0x00) NOR the pure dest (0x00,0x00,0xC0) — proving
// real blending happened, not a flat copy.
`timescale 1ns/1ps
module tb_top_psmct32_alpha_blend_demo;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.PSMCT32_SWIZZLE(1'b0)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// ----- Expected colors -----
// Background (opaque) blue, overlay (red, As=0x40), source-over blend.
localparam logic [7:0] BG_R = 8'h00, BG_G = 8'h00, BG_B = 8'hC0;
localparam logic [7:0] OV_R = 8'hFF, OV_G = 8'h00, OV_B = 8'h00;
// Blend = ((Cs - Cd) * 64) >> 7 + Cd, per channel:
// R: (255-0)*64>>7 + 0 = 127 = 0x7F
// G: (0-0) = 0 = 0x00
// B: (0-192)*64>>7 + 192 = 96 = 0x60
localparam logic [7:0] BL_R = 8'h7F, BL_G = 8'h00, BL_B = 8'h60;
// ----- Frame capture (delayed counters: BRAM read is registered) -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 8'd0;
cap_g[y][x] = 8'd0;
cap_b[y][x] = 8'd0;
cap_de[y][x] = 1'b0;
end
capture_armed = 1'b0;
end
logic [31:0] hcnt_d;
logic [31:0] vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin
hcnt_d <= 32'd0;
vcnt_d <= 32'd0;
end else begin
hcnt_d <= 32'(dut.u_pcrtc.hcnt);
vcnt_d <= 32'(dut.u_pcrtc.vcnt);
end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de
&& (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
int errors;
int blend_pixels_ok;
int bg_pixels_ok;
initial begin
errors = 0;
blend_pixels_ok = 0;
bg_pixels_ok = 0;
end
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk);
core_go = 1'b1;
@(negedge clk);
core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1)
wait (dut.xfer_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1)
wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// --- Overlap region (x in [0..7]): must equal the source-over blend
// of overlay-red over BG-blue, AND be neither pure src nor dest. ---
for (int y = 0; y < 8; y++) begin
for (int x = 0; x < 8; x++) begin
if (!cap_de[y][x]) begin
$error("blend (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== BL_R || cap_g[y][x] !== BL_G || cap_b[y][x] !== BL_B) begin
$error("[blend] (%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x)",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], BL_R, BL_G, BL_B);
errors = errors + 1;
end else begin
blend_pixels_ok = blend_pixels_ok + 1;
end
// Guard: blending actually happened (not a flat copy of
// either operand).
if (cap_r[y][x] === OV_R && cap_g[y][x] === OV_G && cap_b[y][x] === OV_B) begin
$error("[blend] (%0d,%0d) is PURE SOURCE — no blend happened", x, y);
errors = errors + 1;
end
if (cap_r[y][x] === BG_R && cap_g[y][x] === BG_G && cap_b[y][x] === BG_B) begin
$error("[blend] (%0d,%0d) is PURE DEST — overlay never drew", x, y);
errors = errors + 1;
end
end
end
// --- Non-overlap region (x in [8..15]): pure BG blue (overlay
// does not cover it). ---
for (int y = 0; y < 8; y++) begin
for (int x = 8; x < 16; x++) begin
if (!cap_de[y][x]) begin
$error("bg (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== BG_R || cap_g[y][x] !== BG_G || cap_b[y][x] !== BG_B) begin
$error("[bg] (%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x)",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], BG_R, BG_G, BG_B);
errors = errors + 1;
end else begin
bg_pixels_ok = bg_pixels_ok + 1;
end
end
end
// --- Status bundle. ---
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_alpha_blend_demo] blend_ok=%0d/64 bg_ok=%0d/64 raster_emits=%0d errors=%0d",
blend_pixels_ok, bg_pixels_ok,
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_alpha_blend_demo] PASS");
else
$display("[tb_top_psmct32_alpha_blend_demo] FAIL");
$finish;
end
initial begin
#20000000;
$error("[tb_top_psmct32_alpha_blend_demo] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_alpha_blend_demo
sim/tb/top/tb_top_psmct32_combined_demo.sv
+206
View File
@@ -0,0 +1,206 @@
// retroDE_ps2 — tb_top_psmct32_combined_demo (Ch302)
//
// COMBINED textured + alpha + depth probe TB. Proves the multi-beat per-pixel
// memory-op SCHEDULE (per the architect: assert the SEQUENCE of reads/writes,
// not just final pixels), plus the rendered occlusion/blend result.
//
// Fixture (bake.py combined): opaque GREEN Z-writing background (Cbg, Zbg=0x4000)
// then a TME+ABE+ZTE triangle whose interpolated Z runs 0x6000 (top, PASS) ->
// 0x2000 (bottom, FAIL), texture = translucent (A=0x40) red(left)/blue(right).
//
// MEMORY-OP TRACER: while comb_active, per held pixel (ras_cur_x/ras_cur_y) count
// z_rd_en, tex_rd_en, fb_rd_en, color-writes (emit to FB addr <0x400),
// z-writes (emit to Z addr >=0x1000).
// Asserts:
// PROOF A (depth FAIL): >=1 inside-but-hidden pixel with z_rd=1, tex_rd=0,
// fb_rd=0, color_wr=0, z_wr=0 (no texel read, no dest read, no writes).
// PROOF B (depth PASS): >=1 visible pixel with z_rd=1, tex_rd=1, fb_rd=1,
// color_wr=1, z_wr=1.
// PROOF C (outside triangle): z_rd=0 (FSM beat0 sees !inside, no reads/writes).
// PROOF D (render): PASS pixel == blend(texel, green) — texel RGB AND green
// dest both present in the result; FAIL/outside pixel == green (occluded).
`timescale 1ns/1ps
module tb_top_psmct32_combined_demo;
localparam int H_ACTIVE = 16, V_ACTIVE = 16;
localparam int ZBG = 'h4000;
localparam int ZBUF_BASE = 2*2048; // ZBP=2 -> 0x1000 (FB stride=256B/row -> FB spans 0..0xFFF)
localparam int TEX_BASE = 32*256; // 0x2000 (above FB+Z)
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// ---- reference: barycentric on the triangle v0(2,1) v1(13,1) v2(7,14) ----
function automatic real bdet(input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bdet=(by-cy)*(ax-cx)+(cx-bx)*(ay-cy); endfunction
function automatic real bwa(input real px,input real py,input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bwa=((by-cy)*(px-cx)+(cx-bx)*(py-cy))/bdet(ax,ay,bx,by,cx,cy); endfunction
function automatic real bwb(input real px,input real py,input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bwb=((cy-ay)*(px-cx)+(ax-cx)*(py-cy))/bdet(ax,ay,bx,by,cx,cy); endfunction
// ---- memory-op tracer (per held pixel) ----
int zr [0:V_ACTIVE-1][0:H_ACTIVE-1];
int txr [0:V_ACTIVE-1][0:H_ACTIVE-1];
int fbr [0:V_ACTIVE-1][0:H_ACTIVE-1];
int cwr [0:V_ACTIVE-1][0:H_ACTIVE-1]; // color writes
int zwr [0:V_ACTIVE-1][0:H_ACTIVE-1]; // z writes
initial for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
zr[y][x]=0; txr[y][x]=0; fbr[y][x]=0; cwr[y][x]=0; zwr[y][x]=0; end
always_ff @(posedge clk) begin
if (rst_n && dut.u_gs.comb_active) begin
int cx, cy;
// READS: issued while the walker is held at the pixel -> index by ras_cur_x/y.
cx = int'(dut.u_gs.ras_cur_x); cy = int'(dut.u_gs.ras_cur_y);
if (cx < H_ACTIVE && cy < V_ACTIVE) begin
if (dut.u_gs.z_rd_en) zr [cy][cx] <= zr [cy][cx] + 1;
if (dut.u_gs.tex_rd_en) txr[cy][cx] <= txr[cy][cx] + 1;
if (dut.u_gs.fb_rd_en) fbr[cy][cx] <= fbr[cy][cx] + 1;
end
// WRITES: the Z write (last beat) coincides with the walker advance,
// so attribute writes by DECODING the FB/Z address (robust to timing).
if (dut.u_gs.raster_pixel_emit) begin
int wa, wx, wy;
wa = int'(dut.u_gs.raster_pixel_fb_addr_q);
if (wa < ZBUF_BASE) begin
wx = (wa>>2) % 64; wy = (wa>>2) / 64;
if (wx<H_ACTIVE && wy<V_ACTIVE) cwr[wy][wx] <= cwr[wy][wx] + 1; // FB color
end else if (wa < TEX_BASE) begin
wx = ((wa-ZBUF_BASE)>>2) % 64; wy = ((wa-ZBUF_BASE)>>2) / 64;
if (wx<H_ACTIVE && wy<V_ACTIVE) zwr[wy][wx] <= zwr[wy][wx] + 1; // Z
end
end
end
end
// ---- scanout capture ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_pass, n_fail, n_out;
initial begin
errors=0; n_pass=0; n_fail=0; n_out=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
if (dut.u_gs.raster_active==1'b1) wait (dut.u_gs.raster_active==1'b0);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
real wa, wb, wc, fragz, uu, vv;
bit clearly_in, clearly_out, pix_pass, pix_fail;
logic [7:0] er, eg, eb;
wa = bwa(px,py, 2,1, 13,1, 7,14);
wb = bwb(px,py, 2,1, 13,1, 7,14);
wc = 1.0 - wa - wb;
clearly_in = (wa>0.06)&&(wb>0.06)&&(wc>0.06);
clearly_out = (wa<-0.06)||(wb<-0.06)||(wc<-0.06);
fragz = (wa+wb)*real'('h6000) + wc*real'('h2000);
pix_pass = clearly_in && (fragz >= (real'(ZBG) + 1024.0)); // clearly above Zbg
pix_fail = clearly_in && (fragz <= (real'(ZBG) - 1024.0)); // clearly below Zbg
// PROOF C — clearly OUTSIDE the triangle: FSM does NO reads/writes.
if (clearly_out) begin
n_out++;
if (zr[py][px]!=0 || txr[py][px]!=0 || fbr[py][px]!=0 || cwr[py][px]!=0 || zwr[py][px]!=0) begin
if (errors<12) $error("[comb] OUTSIDE (%0d,%0d) had ops z=%0d t=%0d f=%0d cw=%0d zw=%0d",
px,py, zr[py][px],txr[py][px],fbr[py][px],cwr[py][px],zwr[py][px]); errors++;
end
// background green
if (cap_de[py][px] && !(cap_r[py][px]==8'h00 && cap_g[py][px]==8'h80 && cap_b[py][px]==8'h00)) begin
if (errors<12) $error("[comb] OUTSIDE (%0d,%0d) not green: (%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px]); errors++;
end
end
// PROOF A — depth FAIL (hidden): exactly the Z read, nothing else.
if (pix_fail) begin
n_fail++;
if (!(zr[py][px]==1 && txr[py][px]==0 && fbr[py][px]==0 && cwr[py][px]==0 && zwr[py][px]==0)) begin
if (errors<12) $error("[comb] FAIL (%0d,%0d) wrong ops z=%0d t=%0d f=%0d cw=%0d zw=%0d (want 1,0,0,0,0)",
px,py, zr[py][px],txr[py][px],fbr[py][px],cwr[py][px],zwr[py][px]); errors++;
end
// occluded -> background green
if (cap_de[py][px] && !(cap_r[py][px]==8'h00 && cap_g[py][px]==8'h80 && cap_b[py][px]==8'h00)) begin
if (errors<12) $error("[comb] FAIL (%0d,%0d) not green: (%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px]); errors++;
end
end
// PROOF B + D — depth PASS (visible): full read+write schedule + blend.
if (pix_pass) begin
n_pass++;
if (!(zr[py][px]==1 && txr[py][px]==1 && fbr[py][px]==1 && cwr[py][px]==1 && zwr[py][px]==1)) begin
if (errors<12) $error("[comb] PASS (%0d,%0d) wrong ops z=%0d t=%0d f=%0d cw=%0d zw=%0d (want 1,1,1,1,1)",
px,py, zr[py][px],txr[py][px],fbr[py][px],cwr[py][px],zwr[py][px]); errors++;
end
// expected blend: texel (red u<4 / blue u>=4, A=0x40) over green
uu = wb*7.0 + wc*3.0; vv = wc*7.0;
if (uu < 4.0) begin er=8'd127; eg=8'd64; eb=8'd0; end // red over green
else begin er=8'd0; eg=8'd64; eb=8'd127; end // blue over green
if (cap_de[py][px] && !(cap_r[py][px]===er && cap_g[py][px]===eg && cap_b[py][px]===eb)) begin
if (errors<12) $error("[comb] PASS (%0d,%0d) u=%.1f got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",
px,py,uu, cap_r[py][px],cap_g[py][px],cap_b[py][px], er,eg,eb); errors++;
end
end
end
end
if (n_pass < 6) begin $error("[comb] too few PASS pixels (%0d) — geometry issue", n_pass); errors++; end
if (n_fail < 6) begin $error("[comb] too few FAIL pixels (%0d) — geometry issue", n_fail); errors++; end
if (n_out < 20) begin $error("[comb] too few OUTSIDE pixels (%0d)", n_out); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_combined_demo] PASS-pix=%0d FAIL-pix=%0d OUT-pix=%0d errors=%0d", n_pass, n_fail, n_out, errors);
if (errors==0) $display("[tb_top_psmct32_combined_demo] PASS");
else $display("[tb_top_psmct32_combined_demo] FAIL");
$finish;
end
initial begin #120000000; $error("[tb_top_psmct32_combined_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_combined_demo
sim/tb/top/tb_top_psmct32_feeder_accum_demo.sv
+135
View File
@@ -0,0 +1,135 @@
// retroDE_ps2 — tb_top_psmct32_feeder_accum_demo (Ch336)
//
// >FIFO_DEPTH FRAMEBUFFER ACCUMULATION. A 14-primitive scene (FIFO depth 8) renders in TWO batches
// that COMPOSE into one framebuffer instead of wiping each other:
// batch 0 (prims 0-7, tiles 0-7) = RED — clears + full-flushes
// batch 1 (prims 8-13, tiles 8-13) = BLUE — sparse-flushes onto the accumulated FB
// PROOF: at the end, the RED batch-0 tiles AND the BLUE batch-1 tiles are SIMULTANEOUSLY visible.
// If batches wiped each other (the pre-Ch336 behavior), tiles 0-7 would be green. v1 = color
// accumulation + per-batch Z (non-overlapping/tile-separated, so the per-batch-Z limit is honest).
`timescale 1ns/1ps
module tb_top_psmct32_feeder_accum_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam real MARG = 0.12;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(feeder_ready_tb), .feeder_records_o(), .feeder_waits_o()
);
logic feeder_go_tb;
logic feeder_ready_tb;
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
task automatic clear_cap;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
endtask
initial begin clear_cap(); capture_armed=1'b0; end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
function automatic int color_in_box(input int bx0, input int by0, input logic [7:0] er, eg, eb);
int n; begin n=0;
for (int y=by0;y<by0+16;y++) for (int x=bx0;x<bx0+16;x++)
if (cap_de[y][x] && cap_r[y][x]===er && cap_g[y][x]===eg && cap_b[y][x]===eb) n++;
color_in_box = n;
end
endfunction
int errors;
localparam logic [7:0] FF=8'hFF, ZZ=8'h00;
// Re-arm the frame capture and sample two whole frames into cap_*.
task automatic recapture;
repeat(200000) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); clear_cap(); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
endtask
initial begin
errors=0; feeder_go_tb=1'b0;
// BOARD-FAITHFUL boot: the bitstream-inits feeder_stg to LIST-A (cap4, all-textured boot
// splash) and renders it ONCE at boot, leaving its render state behind. The board then GOes
// the accum scene as the FIRST retrigger. The old auto-run loaded accum at boot (clean state)
// and so never reproduced the first-GO-after-boot color poisoning.
$readmemh(`FEEDER_LISTA_FILE, dut.g_feeder.feeder_stg);
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
wait (feeder_ready_tb==1'b1); // list-A rendered, control FSM back in C_READY
// ---- GO 1 : FIRST accum GO after boot (the board's failing path) ----
$readmemh(`FEEDER_ACCUM_FILE, dut.g_feeder.feeder_stg);
@(negedge clk); feeder_go_tb=1'b1; @(negedge clk); feeder_go_tb=1'b0;
recapture();
// batch 0 (tiles 0-7) RED must SURVIVE batch 1 — accumulation proof.
for (int t=0;t<8;t++)
if (color_in_box((t%4)*16,(t/4)*16, FF,ZZ,ZZ) < 15) begin
$error("[accum GO1] batch-0 tile %0d not RED (%0d px)", t, color_in_box((t%4)*16,(t/4)*16,FF,ZZ,ZZ)); errors++; end
// batch 1 (tiles 8-13) BLUE — the bit the board renders RED on the first GO.
for (int t=8;t<14;t++)
if (color_in_box((t%4)*16,(t/4)*16, ZZ,ZZ,FF) < 15) begin
$error("[accum GO1] batch-1 tile %0d not BLUE (%0d px) <-- board shows RED on first GO", t, color_in_box((t%4)*16,(t/4)*16,ZZ,ZZ,FF)); errors++; end
if (int'(dut.feeder_records) != 14) begin $error("[accum GO1] records=%0d (want 14)", int'(dut.feeder_records)); errors++; end
if (raster_overflow) begin $error("[accum GO1] raster_overflow set"); errors++; end
$display("[accum GO1] batch0 RED: t0=%0d t7=%0d | batch1 BLUE: t8=%0d t13=%0d | t8 as RED=%0d | records=%0d",
color_in_box(0,0,FF,ZZ,ZZ), color_in_box(48,16,FF,ZZ,ZZ),
color_in_box(0,32,ZZ,ZZ,FF), color_in_box(16,48,ZZ,ZZ,FF), color_in_box(0,32,FF,ZZ,ZZ), int'(dut.feeder_records));
// ---- GO 2 : second accum GO (board renders this correctly) ----
wait (feeder_ready_tb==1'b1);
@(negedge clk); feeder_go_tb=1'b1; @(negedge clk); feeder_go_tb=1'b0;
recapture();
for (int t=8;t<14;t++)
if (color_in_box((t%4)*16,(t/4)*16, ZZ,ZZ,FF) < 15) begin
$error("[accum GO2] batch-1 tile %0d not BLUE (%0d px)", t, color_in_box((t%4)*16,(t/4)*16,ZZ,ZZ,FF)); errors++; end
$display("[accum GO2] batch0 RED: t0=%0d t7=%0d | batch1 BLUE: t8=%0d t13=%0d | records=%0d",
color_in_box(0,0,FF,ZZ,ZZ), color_in_box(48,16,FF,ZZ,ZZ),
color_in_box(0,32,ZZ,ZZ,FF), color_in_box(16,48,ZZ,ZZ,FF), int'(dut.feeder_records));
$display("[tb_top_psmct32_feeder_accum_demo] errors=%0d", errors);
if (errors==0) $display("[tb_top_psmct32_feeder_accum_demo] PASS");
else $display("[tb_top_psmct32_feeder_accum_demo] FAIL");
$finish;
end
initial begin #1500000000; $error("[tb_top_psmct32_feeder_accum_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_accum_demo
sim/tb/top/tb_top_psmct32_feeder_bridge_demo.sv
+164
View File
@@ -0,0 +1,164 @@
// retroDE_ps2 — tb_top_psmct32_feeder_bridge_demo (Ch330 Brick 3)
//
// RUNTIME PRIMITIVE-LIST SWAP without an RBF rebuild. The feeder plays list A
// (4 combined-TAZ tris in tile t0), the renderer draws it. Then we overwrite the
// staging RAM with list B (4 tris in tile t15) — exactly what a bridge write would
// do at runtime — and pulse the retrigger. The image changes from "blue in t0" to
// "blue in t15", with NO RBF rebuild and NO reset.
//
// The single proof that matters here is Codex's "known-empty" gotcha: list B must
// NOT append onto list A. The retrigger control FSM (C_SETUP->C_RUN->C_DRAIN->C_READY)
// gates a new list on the previous grid having actually run AND drained the FIFO. So:
// image A : blue in t0 box, ZERO blue in t15 box
// image B : blue in t15 box, ZERO blue in t0 box <- t0 went back to GREEN = no append
// Plus: records_emitted == 4 for each list (the feeder re-ran B's full list), and the
// FSM made a clean C_READY -> C_RUN -> C_READY round-trip on the retrigger.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_bridge_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam real MARG = 0.12;
// control-FSM state encodings (mirror the bram-top localparams; not visible across the generate)
localparam logic [1:0] C_RUN = 2'd1, C_READY = 2'd3;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
// Ch330 Brick 4 — list B is loaded ENTIRELY through the staging-write PORT
// (feeder_stg_we_i/waddr/wdata), exactly what the bridge+CDC drive on the board.
.feeder_stg_we_i(stg_we_tb), .feeder_stg_waddr_i(stg_waddr_tb), .feeder_stg_wdata_i(stg_wdata_tb),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(feeder_ready_w), .feeder_records_o(feeder_records_w), .feeder_waits_o(feeder_waits_w)
);
logic feeder_go_tb, stg_we_tb;
logic [11:0] stg_waddr_tb;
logic [63:0] stg_wdata_tb;
logic feeder_ready_w;
logic [15:0] feeder_records_w;
logic [31:0] feeder_waits_w;
localparam int FEEDER_STG_WORDS = 256;
logic [63:0] bmem [0:FEEDER_STG_WORDS-1]; // list B image, streamed in through the port
// ---- scanout frame capture (one frame at a time; re-armed between lists) ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
task automatic clear_cap;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0;
end
endtask
initial begin clear_cap(); capture_armed=1'b0; end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
// count opaque-blue pixels inside a tile box [bx0,bx0+15] x [by0,by0+15]
function automatic int blue_in_box(input int bx0, input int by0);
int n; begin n=0;
for (int y=by0;y<by0+16;y++) for (int x=bx0;x<bx0+16;x++)
if (cap_de[y][x] && cap_b[y][x]===8'hFF && cap_r[y][x]===8'h00 && cap_g[y][x]===8'h00) n++;
blue_in_box = n;
end
endfunction
task automatic capture_frame; // arm for exactly one frame, then disarm
clear_cap();
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
endtask
int errors;
int blueA_t0, blueA_t15, blueB_t0, blueB_t15;
int recA, recB;
initial begin
errors=0;
// the retrigger + staging-write ports are the bram-top feeder PORTS (bridge-driven on board)
feeder_go_tb = 1'b0; stg_we_tb = 1'b0; stg_waddr_tb = 12'd0; stg_wdata_tb = 64'd0;
// ---- list A: loaded into staging at t0; auto-plays after the bootlet upload ----
$readmemh(`FEEDER_STG_A_FILE, dut.g_feeder.feeder_stg);
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// list A runs + drains -> control FSM lands in C_READY
wait (dut.g_feeder.cst == C_READY);
recA = int'(dut.feeder_records);
capture_frame();
blueA_t0 = blue_in_box(0,0); blueA_t15 = blue_in_box(48,48);
// list A's ready status must be visible on the feeder_ready_o PORT (bridge sees it)
if (!feeder_ready_w) begin $error("[demo] feeder_ready_o low in C_READY"); errors++; end
// ---- runtime swap: STREAM list B in through the staging-write PORT, then RETRIGGER ----
$readmemh(`FEEDER_STG_B_FILE, bmem);
for (int wi=0; wi<FEEDER_STG_WORDS; wi++) begin
@(negedge clk); stg_we_tb=1'b1; stg_waddr_tb=wi[11:0]; stg_wdata_tb=bmem[wi];
end
@(negedge clk); stg_we_tb=1'b0;
@(negedge clk); feeder_go_tb = 1'b1; @(negedge clk); feeder_go_tb = 1'b0;
wait (dut.g_feeder.cst == C_RUN); // FSM left READY -> RUN (B started)
wait (dut.g_feeder.cst == C_READY); // B ran + drained
recB = int'(feeder_records_w); // read the records counter via the PORT
capture_frame();
blueB_t0 = blue_in_box(0,0); blueB_t15 = blue_in_box(48,48);
// ---- proofs ----
// list A: blue in t0, nothing in t15
if (blueA_t0 < 20) begin $error("[demo] list A: too few blue px in t0 (%0d) — A not rendered", blueA_t0); errors++; end
if (blueA_t15 != 0) begin $error("[demo] list A: blue px in t15 (%0d) — should be empty", blueA_t15); errors++; end
// list B: blue in t15, t0 went BACK to green => no append
if (blueB_t15 < 20) begin $error("[demo] list B: too few blue px in t15 (%0d) — B not rendered after retrigger", blueB_t15); errors++; end
if (blueB_t0 != 0) begin $error("[demo] list B: blue px STILL in t0 (%0d) — list B APPENDED onto list A!", blueB_t0); errors++; end
// the image actually changed
if (blueA_t0 < 20 || blueB_t15 < 20) begin /* covered above */ end
// both lists fully emitted by the feeder
if (recA != 4) begin $error("[demo] list A records_emitted=%0d (want 4)", recA); errors++; end
if (recB != 4) begin $error("[demo] list B records_emitted=%0d (want 4)", recB); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_feeder_bridge_demo] A:{t0=%0d t15=%0d rec=%0d} B:{t0=%0d t15=%0d rec=%0d} errors=%0d",
blueA_t0, blueA_t15, recA, blueB_t0, blueB_t15, recB, errors);
if (errors==0) $display("[tb_top_psmct32_feeder_bridge_demo] PASS");
else $display("[tb_top_psmct32_feeder_bridge_demo] FAIL");
$finish;
end
initial begin #900000000; $error("[tb_top_psmct32_feeder_bridge_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_bridge_demo
sim/tb/top/tb_top_psmct32_feeder_colors_demo.sv
+142
View File
@@ -0,0 +1,142 @@
// retroDE_ps2 — tb_top_psmct32_feeder_colors_demo (Ch333)
//
// VISUAL PAYLOAD DIVERSITY: the runtime feeder now controls COLOR, not just geometry. A unity
// (0x80) texture + TEX0.TFX=MODULATE means the staging RGBAQ flows through the texel unchanged, so
// each primitive's color is host-controlled at runtime. Three scenes (all <= FIFO_DEPTH), switched
// with no rebuild/reset:
// COLOR_TRI : red / green / blue TRIANGLES tiles {0,5,10}
// COLOR_RECT : red / green / blue filled QUADS tiles {0,5,10}
// COLOR_MIX : red tri(0) + green rect(5) + blue tri(10) + yellow rect(15) (shape AND color vary)
//
// PROOF: each scene tile shows its EXACT staging RGBAQ color (not blue), empties stay green clean,
// records == prim count. The DECAL anchors (Ch330-332) stay blue — verified by their own TBs.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_colors_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam real MARG = 0.12;
localparam logic [1:0] C_RUN = 2'd1, C_READY = 2'd3;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle, feeder_go_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(), .feeder_records_o(), .feeder_waits_o()
);
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
task automatic clear_cap;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
endtask
initial begin clear_cap(); capture_armed=1'b0; end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
// count pixels in tile-box [bx0..+15]^2 that exactly match (er,eg,eb)
function automatic int color_in_box(input int bx0, input int by0, input logic [7:0] er, eg, eb);
int n; begin n=0;
for (int y=by0;y<by0+16;y++) for (int x=bx0;x<bx0+16;x++)
if (cap_de[y][x] && cap_r[y][x]===er && cap_g[y][x]===eg && cap_b[y][x]===eb) n++;
color_in_box = n;
end
endfunction
task automatic capture_frame;
clear_cap();
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
endtask
task automatic stage_and_run(input string memfile);
$readmemh(memfile, dut.g_feeder.feeder_stg);
@(negedge clk); feeder_go_tb=1'b1; @(negedge clk); feeder_go_tb=1'b0;
wait (dut.g_feeder.cst == C_RUN); wait (dut.g_feeder.cst == C_READY);
capture_frame();
endtask
int errors;
localparam logic [7:0] RR=8'hFF, GG=8'hFF, BB=8'hFF, ZZ=8'h00;
// assert tile t shows >=15 px of exactly (er,eg,eb)
task automatic want_color(input string label, input int t, input logic [7:0] er, eg, eb);
int nb; nb = color_in_box((t%4)*16, (t/4)*16, er, eg, eb);
if (nb < 15) begin $error("[%s] tile %0d wants color (%02x,%02x,%02x) but only %0d px", label, t, er,eg,eb, nb); errors++; end
endtask
task automatic want_green_clear(input string label, input int t); // empty tile = green clear (0x008000)
int nb; nb = color_in_box((t%4)*16, (t/4)*16, 8'h00, 8'h80, 8'h00);
if (nb < 200) begin $error("[%s] tile %0d not clean green-clear (%0d px)", label, t, nb); errors++; end
endtask
initial begin
errors=0; feeder_go_tb=1'b0;
$readmemh(`FEEDER_COLOR_TRI_FILE, dut.g_feeder.feeder_stg); // power-up scene = COLOR_TRI
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// COLOR_TRI: red(0) green(5) blue(10) triangles
wait (dut.g_feeder.cst == C_READY); capture_frame();
want_color("COLOR_TRI", 0, RR,ZZ,ZZ); want_color("COLOR_TRI", 5, ZZ,GG,ZZ); want_color("COLOR_TRI", 10, ZZ,ZZ,BB);
if (int'(dut.feeder_records)!=3) begin $error("COLOR_TRI records=%0d (want 3)", int'(dut.feeder_records)); errors++; end
$display("[COLOR_TRI] red0=%0d green5=%0d blue10=%0d records=%0d",
color_in_box(0,0,RR,ZZ,ZZ), color_in_box(16,16,ZZ,GG,ZZ), color_in_box(32,32,ZZ,ZZ,BB), int'(dut.feeder_records));
// COLOR_RECT: red/green/blue filled quads
stage_and_run(`FEEDER_COLOR_RECT_FILE);
want_color("COLOR_RECT", 0, RR,ZZ,ZZ); want_color("COLOR_RECT", 5, ZZ,GG,ZZ); want_color("COLOR_RECT", 10, ZZ,ZZ,BB);
if (int'(dut.feeder_records)!=6) begin $error("COLOR_RECT records=%0d (want 6)", int'(dut.feeder_records)); errors++; end
$display("[COLOR_RECT] red0=%0d green5=%0d blue10=%0d records=%0d",
color_in_box(0,0,RR,ZZ,ZZ), color_in_box(16,16,ZZ,GG,ZZ), color_in_box(32,32,ZZ,ZZ,BB), int'(dut.feeder_records));
// COLOR_MIX: red tri(0), green rect(5), blue tri(10), yellow rect(15) — shape AND color vary
stage_and_run(`FEEDER_COLOR_MIX_FILE);
want_color("COLOR_MIX", 0, RR,ZZ,ZZ); want_color("COLOR_MIX", 5, ZZ,GG,ZZ);
want_color("COLOR_MIX", 10, ZZ,ZZ,BB); want_color("COLOR_MIX", 15, RR,GG,ZZ); // yellow
if (int'(dut.feeder_records)!=6) begin $error("COLOR_MIX records=%0d (want 6)", int'(dut.feeder_records)); errors++; end
$display("[COLOR_MIX] red0=%0d green5=%0d blue10=%0d yellow15=%0d records=%0d",
color_in_box(0,0,RR,ZZ,ZZ), color_in_box(16,16,ZZ,GG,ZZ), color_in_box(32,32,ZZ,ZZ,BB), color_in_box(48,48,RR,GG,ZZ), int'(dut.feeder_records));
if (raster_overflow) begin $error("raster_overflow set"); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_feeder_colors_demo] errors=%0d", errors);
if (errors==0) $display("[tb_top_psmct32_feeder_colors_demo] PASS");
else $display("[tb_top_psmct32_feeder_colors_demo] FAIL");
$finish;
end
initial begin #1200000000; $error("[tb_top_psmct32_feeder_colors_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_colors_demo
sim/tb/top/tb_top_psmct32_feeder_cube_demo.sv
+180
View File
@@ -0,0 +1,180 @@
// retroDE_ps2 — tb_top_psmct32_feeder_cube_demo (Ch343)
//
// LOCAL smoke for the AUTHENTIC cube board fixtures (dump-derived; this TB is NOT in the committed
// regression — it needs the local cube .mem from `python3 tools/gs_make_cube_fixture.py`). It runs the
// FULL boot path that the feeder_cube de25 profile fits, so it exercises the cube-specific deltas that
// the Ch342 persp gate (which backdoored a 16x16 texture) did not:
// * the 64x64 cube texture upload via the QWC=1030 bootlet GIF DMA into a 32 KiB EE RAM, and
// * the 27 translated perspective triangles rendered through the feeder + S1 perspective path.
//
// Proofs:
// TEX — after boot, VRAM at the bound TBP (=64) matches the cube texels byte-for-byte (upload worked).
// SEQ — the feeder emits perspective ST (not UV) for all 27 tris: ST==81 (27*3), UV==0.
// DRAW — the captured frame is non-trivial textured content: enough DE pixels, multiple distinct colors.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_cube_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam int TEXW = 64, TEXH = 64;
localparam int TBP = 128; // relocated past the Z buffer (ZBP=2=word 4096); see tool
localparam int TEX_W0 = TBP*64; // VRAM word base = TBP*64 = 8192
localparam int NTRI = 6; // Ch343 — one isolated corner-view cube (3 faces x 2 tris), re-fit to fill the frame
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
logic feeder_go_tb, feeder_ready_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(64*1024), .RAM_SIZE_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
// matches GS_FEEDER_PERSP_DEMO / feeder_cube: ABE=0 S1 perspective path, tiling OFF.
.COMBINED_TAZ(1'b0), .TILE_LOCAL(1'b0), .TILE_COLS(1), .TILE_ROWS(1),
.TILE_MULTIPRIM(1'b0), .TILE_PRIM_COUNT(1), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b0), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256),
.PERSPECTIVE_CORRECT(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(feeder_ready_tb), .feeder_records_o(), .feeder_waits_o()
);
// ---- feeder register-sequence monitor (perspective => ST, not UV) ----
int n_st, n_uv; logic [7:0] seq_first [0:8]; int seq_n;
always_ff @(posedge clk) begin
if (!rst_n) begin n_st<=0; n_uv<=0; seq_n<=0; end
else if (dut.feeder_gif_reg_wr_en) begin
if (dut.feeder_gif_reg_num==8'h02) n_st<=n_st+1;
if (dut.feeder_gif_reg_num==8'h03) n_uv<=n_uv+1;
if ((dut.feeder_gif_reg_num==8'h01 || dut.feeder_gif_reg_num==8'h02 || dut.feeder_gif_reg_num==8'h05) && seq_n<9) begin
seq_first[seq_n]<=dut.feeder_gif_reg_num; seq_n<=seq_n+1;
end
end
end
// ---- diagnostic raster probes (split geometry vs Z/mask reject) ----
int dbg_inside, dbg_emit, dbg_ztst_pix; time dbg_last_emit;
always_ff @(posedge clk) begin
if (!rst_n) begin dbg_inside<=0; dbg_emit<=0; dbg_ztst_pix<=0; dbg_last_emit<=0; end
else begin
if (dut.u_gs.s2_valid_q && dut.u_gs.s2_inside_q) dbg_inside<=dbg_inside+1;
if (dut.u_gs.s2_ztest_pixel) dbg_ztst_pix<=dbg_ztst_pix+1;
if (dut.raster_pixel_emit) begin dbg_emit<=dbg_emit+1; dbg_last_emit<=$time; end
end
end
// ---- frame capture ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
logic [31:0] cube_tex_ref [0:TEXW*TEXH-1];
int errors, tex_mismatch, de_pixels, nonzero_pixels, distinct;
logic [23:0] seen_col [0:31];
initial begin
errors=0; tex_mismatch=0; de_pixels=0; nonzero_pixels=0; distinct=0; feeder_go_tb=1'b0;
$readmemh(`FEEDER_CUBE_FILE, dut.g_feeder.feeder_stg);
$readmemh(`FEEDER_CUBE_TEX_FILE, cube_tex_ref);
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
// run the REAL boot: bootlet DMAs the 64x64 texture upload payload into VRAM.
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
repeat(50) @(posedge clk);
// ---- TEX: the upload landed at TBP=64 byte-for-byte ----
for (int i=0; i<TEXW*TEXH; i++)
if (dut.u_vram.mem[TEX_W0 + i] !== cube_tex_ref[i]) begin
if (tex_mismatch<8) $error("[feeder_cube] tex word %0d: vram=%08x exp=%08x", i, dut.u_vram.mem[TEX_W0+i], cube_tex_ref[i]);
tex_mismatch++;
end
if (tex_mismatch!=0) begin $error("[feeder_cube] texture upload mismatched %0d/%0d words", tex_mismatch, TEXW*TEXH); errors++; end
// let the feeder render the 27 perspective triangles, then capture a frame.
wait (feeder_ready_tb==1'b1);
repeat(300000) @(posedge clk);
// probe the FB directly (words 0..4095) right before capture
begin int fbnz; fbnz=0;
for (int i=0;i<4096;i++) if (dut.u_vram.mem[i]!==32'd0 && dut.u_vram.mem[i]!==32'hFF000000) fbnz++;
$display("[feeder_cube] FB-probe @%0t: nonbg FB words=%0d ; last_emit@%0t emits=%0d", $time, fbnz, dbg_last_emit, dbg_emit);
end
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// ---- SEQ: perspective ST for all 27 tris, no UV ----
$display("[feeder_cube] ST=%0d UV=%0d first-seq=%02x %02x %02x", n_st, n_uv, seq_first[0], seq_first[1], seq_first[2]);
if (n_st != NTRI*3) begin $error("[feeder_cube] ST writes=%0d (want %0d = %0d tris x 3)", n_st, NTRI*3, NTRI); errors++; end
if (n_uv != 0) begin $error("[feeder_cube] UV writes=%0d (want 0 in perspective mode)", n_uv); errors++; end
if (!(seq_first[0]==8'h01 && seq_first[1]==8'h02 && seq_first[2]==8'h05))
begin $error("[feeder_cube] vertex seq not RGBAQ->ST->XYZ2 (got %02x %02x %02x)", seq_first[0],seq_first[1],seq_first[2]); errors++; end
// ---- DRAW: non-trivial textured content rendered ----
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) if (cap_de[y][x]) begin
logic [23:0] key; bit found;
key = {cap_b[y][x],cap_g[y][x],cap_r[y][x]};
de_pixels++;
if (key!=24'd0) nonzero_pixels++;
found = 1'b0;
for (int k=0;k<distinct;k++) if (seen_col[k]===key) found=1'b1;
if (!found && distinct<32) begin seen_col[distinct]=key; distinct++; end
end
// The authentic cube texture is verified 2-color (black 0xFF000000 / white 0xFFFFFFFF, 50/50). On
// screen the black texels alias the black background, so "distinct colors" caps at 2; the texture is
// proven SAMPLED by both values appearing: white texels are visible (nonzero) AND more pixels were
// emitted than are white (emits > white => black texels also drawn = the B/W pattern, not a flat fill).
// ---- dump the actual rendered frame as ASCII (ground truth = what the board shows) ----
$display("[feeder_cube] RENDERED FRAME ('#'=white texel, '.'=black/bg DE, ' '=blank):");
for (int y=0; y<V_ACTIVE; y++) begin
string row; row = "";
for (int x=0; x<H_ACTIVE; x++) begin
if (!cap_de[y][x]) row = {row, " "};
else if ({cap_b[y][x],cap_g[y][x],cap_r[y][x]}!=24'd0) row = {row, "#"};
else row = {row, "."};
end
$display(" %s", row);
end
$display("[feeder_cube] RASTER PROBE: inside_pixels=%0d ztest_pixels=%0d emits=%0d", dbg_inside, dbg_ztst_pix, dbg_emit);
$display("[feeder_cube] de_pixels=%0d white(nonzero)=%0d distinct_colors=%0d", de_pixels, nonzero_pixels, distinct);
if (de_pixels < 1000) begin $error("[feeder_cube] too few DE pixels (%0d) — scanout dead?", de_pixels); errors++; end
if (nonzero_pixels < 80) begin $error("[feeder_cube] too few white texels (%0d) — cube didn't draw", nonzero_pixels); errors++; end
if (nonzero_pixels > 2500) begin $error("[feeder_cube] white area too large (%0d) — flood, not a cube shape", nonzero_pixels); errors++; end
if (dbg_emit <= nonzero_pixels) begin $error("[feeder_cube] emits(%0d) <= white(%0d) — no black texels: texture pattern not sampled", dbg_emit, nonzero_pixels); errors++; end
if (raster_overflow) begin $error("[feeder_cube] raster_overflow set"); errors++; end
if (errors==0) begin $display("[tb_top_psmct32_feeder_cube_demo] PASS"); $finish; end
else $fatal(1, "[tb_top_psmct32_feeder_cube_demo] FAIL (%0d errors)", errors);
end
initial begin #2000000000; $error("[tb_top_psmct32_feeder_cube_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_cube_demo
sim/tb/top/tb_top_psmct32_feeder_equiv_demo.sv
+263
View File
@@ -0,0 +1,263 @@
// retroDE_ps2 — tb_top_psmct32_feeder_equiv_demo (Ch315)
//
// PRIMITIVE/BIN CAPACITY scaling. The 4x4 (64x64) grid with TILE_FIFO_DEPTH=8 and
// SEVEN prims (vs Ch312's 3). Six of them (P0..P5) fall ENTIRELY inside centre tile
// t5 (col1,row1 = x[16..31],y[16..31]); the seventh (P6) is a lone corner prim in
// t15. So:
// bin_n[t5] = 6 (P0..P5, in draw order) <- DEEPER than the old FIFO depth 4
// bin_n[t15] = 1 (P6)
// all other 14 tiles = 0 (empty)
// One shared OPAQUE-blue texture, so a covered pixel is blue and order doesn't change
// the colour — draw order is proven instead by the BIN ORDER read-back.
//
// PROOFS:
// CAPACITY : bin_occ_max_r == 6 (a bin held 6 prims, > the old depth-4 limit),
// and raster_overflow / count / bin_overflow are ALL 0 (depth-8 FIFO
// swallowed all 7 with room to spare).
// BIN COUNTS : bin_n[t]==# prims whose bbox overlaps tile t (t5=6,t15=1,rest 0).
// BIN ORDER : bin_prim[5][0..5] == {0,1,2,3,4,5} (draw order preserved at depth 6).
// IMAGE : whole 64x64 == reference (covered-by-any-prim -> blue, else green).
// GRID : 16 tiles cleared (256 each) + 16*256 flush; prim list == 7.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_equiv_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.12;
localparam int NPRIM = 4;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
// Ch330 Brick 4 feeder ports — unused here (staging via $readmemh, single list, no retrigger).
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(1'b0),
.feeder_ready_o(), .feeder_records_o(), .feeder_waits_o()
);
// the 7 prim vertex tables (must match bake.py CAP_PRIMS)
int vx [0:NPRIM-1][0:2];
int vy [0:NPRIM-1][0:2];
initial begin
// iverilog-12: no array-slice '{} assignment — set elements individually.
// P0..P5 are SIX IDENTICAL t0 triangles (match bake.py CAP_T0); P6 = corner t15.
for (int p=0;p<NPRIM;p++) begin
vx[p][0]=1; vx[p][1]=14; vx[p][2]=1; // 4 combined tris, tile t0
vy[p][0]=1; vy[p][1]=1; vy[p][2]=14;
end
end
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
// expected: prim p's bbox overlaps tile t? (bboxes derived from the verts)
function automatic bit binx(input int p, input int t);
int xl,xh,yl,yh,tx0,tx1,ty0,ty1;
begin
xl=vx[p][0]; xh=vx[p][0]; yl=vy[p][0]; yh=vy[p][0];
for (int k=1;k<3;k++) begin
if (vx[p][k]<xl) xl=vx[p][k]; if (vx[p][k]>xh) xh=vx[p][k];
if (vy[p][k]<yl) yl=vy[p][k]; if (vy[p][k]>yh) yh=vy[p][k];
end
tx0=(t%4)*16; tx1=tx0+15; ty0=(t/4)*16; ty1=ty0+15;
binx = !((xl>tx1)||(xh<tx0)||(yl>ty1)||(yh<ty0));
end
endfunction
int clear_cw [0:15];
int flush_emits; bit saw_prim_count_4;
initial begin for(int t=0;t<16;t++) clear_cw[t]=0; flush_emits=0; saw_prim_count_4=0; end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int t; t=int'(dut.u_gs.tile_row_r)*4 + int'(dut.u_gs.tile_col_r);
if (t>=0 && t<16) clear_cw[t] <= clear_cw[t] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==4)) saw_prim_count_4 <= 1'b1;
end
// Ch330 — load the feeder staging (the 4-tri list) into the bram-top's staging RAM.
initial $readmemh(`FEEDER_STG_IMAGE_FILE, dut.g_feeder.feeder_stg);
// Ch330 phase monitors (Codex acceptance): the bootlet's TRX/IMAGE upload must complete
// in phase 0 BEFORE the feeder takes the bus, and the feeder must not emit before handoff.
bit xfer_went_high, xfer_low_before_feeder, feeder_emit_before_handoff, handoff_seen;
logic feeder_owns_d;
always_ff @(posedge clk) if (rst_n) begin
feeder_owns_d <= dut.feeder_owns_bus;
if (dut.xfer_busy) xfer_went_high <= 1'b1;
if (!dut.feeder_owns_bus && dut.feeder_gif_reg_wr_en) feeder_emit_before_handoff <= 1'b1;
if (dut.feeder_owns_bus && !feeder_owns_d) begin // handoff 0->1
handoff_seen <= 1'b1;
if (xfer_went_high && !dut.xfer_busy) xfer_low_before_feeder <= 1'b1;
end
end
initial begin xfer_went_high=0; xfer_low_before_feeder=0; feeder_emit_before_handoff=0; handoff_seen=0; end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_blue, n_green;
int bnv [0:15];
int b5 [0:5]; // t5's six bin slots
int occ_max, ovf_count; logic ovf, bin_ovf;
initial begin
errors=0; n_match=0; n_check=0; n_blue=0; n_green=0;
for(int t=0;t<16;t++) bnv[t]=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
// Big settle: the 7-prim render (6 prims deep in tile t5, across 16 tiles)
// takes far longer than the 3-prim scenes, and raster_active can dip between
// phases — wait a generous fixed window so the WHOLE frame is flushed before
// sampling bins + arming the scanout capture (avoids a mid-render race).
repeat(120000) @(posedge clk);
bnv[0]=int'(dut.u_gs.bin_n[0]); bnv[1]=int'(dut.u_gs.bin_n[1]);
bnv[2]=int'(dut.u_gs.bin_n[2]); bnv[3]=int'(dut.u_gs.bin_n[3]);
bnv[4]=int'(dut.u_gs.bin_n[4]); bnv[5]=int'(dut.u_gs.bin_n[5]);
bnv[6]=int'(dut.u_gs.bin_n[6]); bnv[7]=int'(dut.u_gs.bin_n[7]);
bnv[8]=int'(dut.u_gs.bin_n[8]); bnv[9]=int'(dut.u_gs.bin_n[9]);
bnv[10]=int'(dut.u_gs.bin_n[10]); bnv[11]=int'(dut.u_gs.bin_n[11]);
bnv[12]=int'(dut.u_gs.bin_n[12]); bnv[13]=int'(dut.u_gs.bin_n[13]);
bnv[14]=int'(dut.u_gs.bin_n[14]); bnv[15]=int'(dut.u_gs.bin_n[15]);
b5[0]=int'(dut.u_gs.bin_prim[0][0]); b5[1]=int'(dut.u_gs.bin_prim[0][1]);
b5[2]=int'(dut.u_gs.bin_prim[0][2]); b5[3]=int'(dut.u_gs.bin_prim[0][3]);
b5[4]=int'(dut.u_gs.bin_prim[0][4]); b5[5]=int'(dut.u_gs.bin_prim[0][5]);
occ_max = int'(dut.u_gs.bin_occ_max_r);
ovf_count = int'(dut.u_gs.raster_overflow_count_r);
ovf = dut.u_gs.raster_overflow;
bin_ovf = dut.u_gs.bin_overflow_r;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// PROOF GRID
for (int t=0;t<16;t++)
if (clear_cw[t] != 256) begin $error("[cap] tile %0d cleared %0d (want 256)", t, clear_cw[t]); errors++; end
if (flush_emits != 16*256) begin $error("[cap] flush emitted %0d (want %0d)", flush_emits, 16*256); errors++; end
if (!saw_prim_count_4) begin $error("[feeder] prim_count_r never == 4 (feeder pushed 4 prims)"); errors++; end
// PROOF — the FEEDER drove 4 combined-TAZ prims into the grid.
if (occ_max != 4) begin $error("[feeder] bin_occ_max=%0d (want 4)", occ_max); errors++; end
if (ovf) begin $error("[feeder] raster_overflow set"); errors++; end
if (ovf_count != 0) begin $error("[feeder] overflow_count=%0d (want 0)", ovf_count); errors++; end
if (bin_ovf) begin $error("[feeder] bin_overflow set"); errors++; end
// PROOF PHASE HANDOFF (Codex acceptance):
if (!handoff_seen) begin $error("[feeder] feeder never took the bus (no phase handoff)"); errors++; end
if (!xfer_went_high) begin $error("[feeder] TRX/IMAGE upload never ran in phase 0 (xfer_busy never high)"); errors++; end
if (!xfer_low_before_feeder) begin $error("[feeder] texture upload not committed before feeder start (xfer_busy not low at handoff)"); errors++; end
if (feeder_emit_before_handoff) begin $error("[feeder] feeder emitted gif_reg_* BEFORE owning the bus"); errors++; end
// PROOF BIN COUNTS
for (int t=0;t<16;t++) begin
int exp_n; exp_n=0;
for (int p=0;p<NPRIM;p++) if (binx(p,t)) exp_n++;
if (bnv[t] !== exp_n) begin $error("[cap] tile %0d bin_n=%0d, want %0d", t, bnv[t], exp_n); errors++; end
end
// PROOF BIN ORDER — t0 holds the feeder's 4 prims in emit order.
for (int s=0;s<4;s++)
if (b5[s] !== s) begin $error("[feeder] tile0 slot %0d = prim %0d (want %0d)", s, b5[s], s); errors++; end
$display("[cap] bin_n[0..15]=%0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d t5={%0d%0d%0d%0d%0d%0d} occ_max=%0d ovf=%0b cnt=%0d",
bnv[0],bnv[1],bnv[2],bnv[3],bnv[4],bnv[5],bnv[6],bnv[7],bnv[8],bnv[9],bnv[10],bnv[11],bnv[12],bnv[13],bnv[14],bnv[15],
b5[0],b5[1],b5[2],b5[3],b5[4],b5[5],occ_max,ovf,ovf_count);
// PROOF IMAGE — covered by ANY prim -> opaque blue; else green clear.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
bit is_in, is_bnd; logic [7:0] er,eg,eb;
is_in=0; is_bnd=0;
for (int p=0;p<NPRIM;p++) begin
int c; c = tri_cls(real'(px),real'(py),
real'(vx[p][0]),real'(vy[p][0]),
real'(vx[p][1]),real'(vy[p][1]),
real'(vx[p][2]),real'(vy[p][2]));
if (c==1) is_in=1;
if (c==2) is_bnd=1;
end
if (is_bnd && !is_in) begin er=8'hxx;eg=8'hxx;eb=8'hxx; end // skip ambiguous edge
else if (is_in) begin er=8'h00; eg=8'h00; eb=8'hFF; end // blue
else begin er=8'h00; eg=8'h80; eb=8'h00; end // green clear
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
if (cap_r[py][px]===er&&cap_g[py][px]===eg&&cap_b[py][px]===eb) begin
n_match++;
if (eb==8'hFF) n_blue++; else n_green++;
end else begin
if (errors<14) $error("[cap] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb);
errors++;
end
end
end
end
if (n_check < 400) begin $error("[cap] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[cap] image match %0d/%0d", n_match, n_check); errors++; end
if (n_blue < 30) begin $error("[cap] too few blue pixels (%0d) — prims not rendered", n_blue); errors++; end
if (n_green < 200) begin $error("[cap] too few green pixels (%0d) — empty tiles not clear", n_green); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_feeder_equiv_demo] handoff=%0b xfer_hi=%0b xfer_lo_pre=%0b feeder_early=%0b occ_max=%0d match=%0d/%0d blue=%0d green=%0d errors=%0d",
handoff_seen, xfer_went_high, xfer_low_before_feeder, feeder_emit_before_handoff, occ_max, n_match, n_check, n_blue, n_green, errors);
if (errors==0) $display("[tb_top_psmct32_feeder_equiv_demo] PASS");
else $display("[tb_top_psmct32_feeder_equiv_demo] FAIL");
$finish;
end
initial begin #600000000; $error("[tb_top_psmct32_feeder_equiv_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_equiv_demo
sim/tb/top/tb_top_psmct32_feeder_gouraud_demo.sv
+144
View File
@@ -0,0 +1,144 @@
// retroDE_ps2 — tb_top_psmct32_feeder_gouraud_demo (Ch335)
//
// PER-VERTEX GOURAUD color. The combined-TAZ MODULATE path now multiplies the texel by the
// INTERPOLATED vertex color (aligned to the texel via comb_dx/comb_dy at CB_T), so distinct
// per-vertex RGBAQ produce a smooth gradient. Flat scenes (equal vertex colors) collapse to the
// constant (Ch333/334 anchors unchanged). Three runtime-switched scenes:
// GOURAUD_TRI : tile0 triangle, v0=red v1=green v2=blue -> RGB gradient
// GOURAUD_RECT : tile5 quad (2 tris), corners red/green/blue/white -> gradient quad
// GOURAUD_MIX : flat red triangle(0) + RGB gradient triangle(10)
//
// PROOF (a gradient, not flat): sampling each triangle near a vertex shows that vertex's channel
// dominating, AND the per-vertex samples differ. The flat tile in MIX is a single dominant color.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_gouraud_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam real MARG = 0.12;
localparam logic [1:0] C_RUN = 2'd1, C_READY = 2'd3;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle, feeder_go_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(), .feeder_records_o(), .feeder_waits_o()
);
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
task automatic clear_cap;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
endtask
initial begin clear_cap(); capture_armed=1'b0; end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
task automatic capture_frame;
clear_cap();
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
endtask
task automatic stage_and_run(input string memfile);
$readmemh(memfile, dut.g_feeder.feeder_stg);
@(negedge clk); feeder_go_tb=1'b1; @(negedge clk); feeder_go_tb=1'b0;
wait (dut.g_feeder.cst == C_RUN); wait (dut.g_feeder.cst == C_READY);
capture_frame();
endtask
int errors;
// assert pixel (x,y) is drawn and channel `ch` (0=r,1=g,2=b) strictly dominates the other two.
task automatic dom(input string lbl, input int x, input int y, input int ch);
logic [7:0] pr, pg, pb;
begin
pr=cap_r[y][x]; pg=cap_g[y][x]; pb=cap_b[y][x];
if (!cap_de[y][x]) begin $error("[%s] (%0d,%0d) not drawn", lbl,x,y); errors++; end
else begin
unique case (ch)
0: if (!(pr>pg && pr>pb)) begin $error("[%s] (%0d,%0d)=(%02x%02x%02x) not RED-dominant", lbl,x,y,pr,pg,pb); errors++; end
1: if (!(pg>pr && pg>pb)) begin $error("[%s] (%0d,%0d)=(%02x%02x%02x) not GREEN-dominant", lbl,x,y,pr,pg,pb); errors++; end
default: if (!(pb>pr && pb>pg)) begin $error("[%s] (%0d,%0d)=(%02x%02x%02x) not BLUE-dominant", lbl,x,y,pr,pg,pb); errors++; end
endcase
end
end
endtask
initial begin
errors=0; feeder_go_tb=1'b0;
$readmemh(`FEEDER_GOURAUD_TRI_FILE, dut.g_feeder.feeder_stg); // power-up = gouraud tri
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// GOURAUD_TRI: tile0 tri, v0=(1,1)red v1=(14,1)green v2=(1,14)blue -> gradient
wait (dut.g_feeder.cst == C_READY); capture_frame();
dom("G_TRI v0", 2, 2, 0); dom("G_TRI v1", 10, 2, 1); dom("G_TRI v2", 2, 10, 2);
if (int'(dut.feeder_records)!=1) begin $error("G_TRI records=%0d (want 1)", int'(dut.feeder_records)); errors++; end
$display("[G_TRI] v0(2,2)=%02x%02x%02x v1(10,2)=%02x%02x%02x v2(2,10)=%02x%02x%02x",
cap_r[2][2],cap_g[2][2],cap_b[2][2], cap_r[2][10],cap_g[2][10],cap_b[2][10], cap_r[10][2],cap_g[10][2],cap_b[10][2]);
// GOURAUD_RECT: tile5 quad, corners TL(17,17)red TR(30,17)green BL(17,30)blue BR(30,30)white
stage_and_run(`FEEDER_GOURAUD_RECT_FILE);
dom("G_RECT TL", 18, 18, 0); dom("G_RECT TR", 29, 18, 1); dom("G_RECT BL", 18, 29, 2);
// BR ~ white: all channels high
if (!(cap_r[29][29]>8'hA0 && cap_g[29][29]>8'hA0 && cap_b[29][29]>8'hA0)) begin
$error("G_RECT BR(29,29)=%02x%02x%02x not whiteish", cap_r[29][29],cap_g[29][29],cap_b[29][29]); errors++; end
if (int'(dut.feeder_records)!=2) begin $error("G_RECT records=%0d (want 2)", int'(dut.feeder_records)); errors++; end
$display("[G_RECT] TL=%02x%02x%02x TR=%02x%02x%02x BL=%02x%02x%02x BR=%02x%02x%02x",
cap_r[18][18],cap_g[18][18],cap_b[18][18], cap_r[18][29],cap_g[18][29],cap_b[18][29],
cap_r[29][18],cap_g[29][18],cap_b[29][18], cap_r[29][29],cap_g[29][29],cap_b[29][29]);
// GOURAUD_MIX: flat red tri(0) + gradient tri(10, ox=oy=32)
stage_and_run(`FEEDER_GOURAUD_MIX_FILE);
// tile0 flat red: all three sampled points red-dominant AND equal (no gradient)
dom("G_MIX flat", 3, 3, 0); dom("G_MIX flat", 10, 2, 0); dom("G_MIX flat", 2, 10, 0);
// tile10 gradient: vertex dominance (v0=(33,33)red v1=(46,33)green v2=(33,46)blue)
dom("G_MIX grad v0", 34, 34, 0); dom("G_MIX grad v1", 42, 34, 1); dom("G_MIX grad v2", 34, 42, 2);
if (int'(dut.feeder_records)!=2) begin $error("G_MIX records=%0d (want 2)", int'(dut.feeder_records)); errors++; end
$display("[G_MIX] flat0(3,3)=%02x%02x%02x grad10 v0(34,34)=%02x%02x%02x v1(42,34)=%02x%02x%02x v2(34,42)=%02x%02x%02x",
cap_r[3][3],cap_g[3][3],cap_b[3][3], cap_r[34][34],cap_g[34][34],cap_b[34][34],
cap_r[34][42],cap_g[34][42],cap_b[34][42], cap_r[42][34],cap_g[42][34],cap_b[42][34]);
if (raster_overflow) begin $error("raster_overflow set"); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_feeder_gouraud_demo] errors=%0d", errors);
if (errors==0) $display("[tb_top_psmct32_feeder_gouraud_demo] PASS");
else $display("[tb_top_psmct32_feeder_gouraud_demo] FAIL");
$finish;
end
initial begin #1200000000; $error("[tb_top_psmct32_feeder_gouraud_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_gouraud_demo
sim/tb/top/tb_top_psmct32_feeder_native_demo.sv
+129
View File
@@ -0,0 +1,129 @@
// retroDE_ps2 — tb_top_psmct32_feeder_native_demo (Ch334)
//
// HOST COMMAND COMPRESSION: a NATIVE rectangle record (3 staging words: color + 2 corners) that the
// FEEDER expands into two colored triangles. Same renderer, same gif_reg path — only the list format
// is richer. Acceptance: a native-rect scene matches the Ch333 explicit two-triangle COLOR_RECT
// scene by pixels, color, and records; a mixed scene combines a triangle with native rects.
//
// NATIVE_RECT : 3 native-rect records -> red/green/blue filled quads tiles {0,5,10} (records=6, ==COLOR_RECT)
// NATIVE_MIX : red triangle(0) + 3 native rects (green5/blue10/yellow15) (records=1+6=7)
//
// One native rect (3 words) replaces 18 explicit triangle words -> 6x host payload compression.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_native_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam real MARG = 0.12;
localparam logic [1:0] C_RUN = 2'd1, C_READY = 2'd3;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle, feeder_go_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(), .feeder_records_o(), .feeder_waits_o()
);
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
task automatic clear_cap;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
endtask
initial begin clear_cap(); capture_armed=1'b0; end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
function automatic int color_in_box(input int bx0, input int by0, input logic [7:0] er, eg, eb);
int n; begin n=0;
for (int y=by0;y<by0+16;y++) for (int x=bx0;x<bx0+16;x++)
if (cap_de[y][x] && cap_r[y][x]===er && cap_g[y][x]===eg && cap_b[y][x]===eb) n++;
color_in_box = n;
end
endfunction
task automatic capture_frame;
clear_cap();
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
endtask
task automatic stage_and_run(input string memfile);
$readmemh(memfile, dut.g_feeder.feeder_stg);
@(negedge clk); feeder_go_tb=1'b1; @(negedge clk); feeder_go_tb=1'b0;
wait (dut.g_feeder.cst == C_RUN); wait (dut.g_feeder.cst == C_READY);
capture_frame();
endtask
int errors;
localparam logic [7:0] FF=8'hFF, ZZ=8'h00;
task automatic want(input string lbl, input int t, input logic [7:0] er, eg, eb, input int lo, input int hi);
int nb; nb = color_in_box((t%4)*16, (t/4)*16, er, eg, eb);
if (nb < lo || nb > hi) begin $error("[%s] tile %0d color(%02x%02x%02x)=%0d px (want %0d..%0d)", lbl,t,er,eg,eb,nb,lo,hi); errors++; end
endtask
initial begin
errors=0; feeder_go_tb=1'b0;
$readmemh(`FEEDER_NATIVE_RECT_FILE, dut.g_feeder.feeder_stg); // power-up = native rect
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// NATIVE_RECT: red/green/blue FILLED quads (full 169px) — must MATCH Ch333 COLOR_RECT, records=6
wait (dut.g_feeder.cst == C_READY); capture_frame();
want("NATIVE_RECT", 0, FF,ZZ,ZZ, 130, 169); want("NATIVE_RECT", 5, ZZ,FF,ZZ, 130, 169); want("NATIVE_RECT", 10, ZZ,ZZ,FF, 130, 169);
if (int'(dut.feeder_records)!=6) begin $error("NATIVE_RECT records=%0d (want 6 = 3 rects x 2 tris)", int'(dut.feeder_records)); errors++; end
$display("[NATIVE_RECT] red0=%0d green5=%0d blue10=%0d records=%0d (matches COLOR_RECT)",
color_in_box(0,0,FF,ZZ,ZZ), color_in_box(16,16,ZZ,FF,ZZ), color_in_box(32,32,ZZ,ZZ,FF), int'(dut.feeder_records));
// NATIVE_MIX: red TRIANGLE(0, ~91px half-tile) + green/blue/yellow native RECTS(5/10/15, full), records=7
stage_and_run(`FEEDER_NATIVE_MIX_FILE);
want("NATIVE_MIX", 0, FF,ZZ,ZZ, 30, 120); // triangle = half-fill
want("NATIVE_MIX", 5, ZZ,FF,ZZ, 130, 169); // native rect = full
want("NATIVE_MIX", 10, ZZ,ZZ,FF, 130, 169);
want("NATIVE_MIX", 15, FF,FF,ZZ, 130, 169); // yellow native rect
if (int'(dut.feeder_records)!=7) begin $error("NATIVE_MIX records=%0d (want 7 = 1 tri + 3 rects*2)", int'(dut.feeder_records)); errors++; end
$display("[NATIVE_MIX] redTri0=%0d green5=%0d blue10=%0d yellow15=%0d records=%0d",
color_in_box(0,0,FF,ZZ,ZZ), color_in_box(16,16,ZZ,FF,ZZ), color_in_box(32,32,ZZ,ZZ,FF), color_in_box(48,48,FF,FF,ZZ), int'(dut.feeder_records));
if (raster_overflow) begin $error("raster_overflow set"); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_feeder_native_demo] errors=%0d", errors);
if (errors==0) $display("[tb_top_psmct32_feeder_native_demo] PASS");
else $display("[tb_top_psmct32_feeder_native_demo] FAIL");
$finish;
end
initial begin #1200000000; $error("[tb_top_psmct32_feeder_native_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_native_demo
sim/tb/top/tb_top_psmct32_feeder_persp_demo.sv
+198
View File
@@ -0,0 +1,198 @@
// retroDE_ps2 — tb_top_psmct32_feeder_persp_demo (Ch342)
//
// HARD GATE: perspective-correct ST/Q through the FEEDER on the actual tiled/multiprim feeder profile
// (FEEDER_ENABLE + TILE_LOCAL + TILE_MULTIPRIM + BIN_BUFFER + COMBINED_TAZ) with PERSPECTIVE_CORRECT=1.
// Drives feeder_persp.mem (word0[32]=1 perspective format, per-vertex RGBAQ/ST/XYZ2) through the
// staging RAM and backdoors the 16x16 checkerboard into VRAM at the bound TBP (=100). A receding quad
// (top FAR w=8, bottom NEAR w=1) so the checkerboard compresses toward the top under correct perspective.
//
// Proofs (mirroring the Ch301 tb_top_psmct32_perspective_demo, but through the FEEDER + tiled path):
// SEQ — the feeder emits RGBAQ -> ST -> XYZ2 per vertex (NOT RGBAQ -> UV -> XYZ2): ST(0x02) writes
// == 6 (2 tris x 3), UV(0x03) writes == 0.
// PROOF1— interior-of-cell pixels match a per-pixel barycentric PERSPECTIVE reference exactly.
// PROOF2— where perspective and affine references disagree, the capture matches PERSPECTIVE.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_persp_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam int TEXW = 16, TEXH = 16;
localparam int TBP = 100; // texture base (matches bake.py PERSP_FEEDER_TBP)
localparam int TEX_W0 = TBP*64; // VRAM word base = TBP*256/4
real W_FAR; real W_NEAR;
initial begin W_FAR = 8.0; W_NEAR = 1.0; end
// quad corners (screen) + uv + w — must match bake.py PERSP_QUAD.
localparam int QX0=16, QX1=48, QY0=12, QY1=52;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
logic feeder_go_tb, feeder_ready_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
// Ch342 — DEDICATED perspective profile: FEEDER + S1 perspective path, tiling OFF (the cube is
// ABE=0 -> non-combined -> S1 path where gs_persp_uv launches). COMBINED_TAZ perspective is a
// separate documented follow-on bug, NOT this gate.
.COMBINED_TAZ(1'b0), .TILE_LOCAL(1'b0), .TILE_COLS(1), .TILE_ROWS(1),
.TILE_MULTIPRIM(1'b0), .TILE_PRIM_COUNT(1), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b0), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256),
.PERSPECTIVE_CORRECT(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(feeder_ready_tb), .feeder_records_o(), .feeder_waits_o()
);
function automatic logic [23:0] exp_cell(input integer u, input integer v);
if ((((u >> 2) + (v >> 2)) & 1)) exp_cell = 24'hFFFFFF; // white
else exp_cell = 24'h902020; // {b,g,r} dark-blue
endfunction
function automatic real bdet(input real ax,ay,bx,by,cx,cy); bdet=(by-cy)*(ax-cx)+(cx-bx)*(ay-cy); endfunction
function automatic real bwa(input real px,py,ax,ay,bx,by,cx,cy);
bwa=((by-cy)*(px-cx)+(cx-bx)*(py-cy))/bdet(ax,ay,bx,by,cx,cy); endfunction
function automatic real bwb(input real px,py,ax,ay,bx,by,cx,cy);
bwb=((cy-ay)*(px-cx)+(ax-cx)*(py-cy))/bdet(ax,ay,bx,by,cx,cy); endfunction
function automatic real edge_dist(input real c); real m; m=c-(4.0*$floor(c/4.0)); edge_dist=(m<(4.0-m))?m:(4.0-m); endfunction
// ---- feeder register-sequence monitor (RGBAQ/ST/XYZ2, not UV) ----
int n_rgbaq, n_st, n_uv, n_xyz2; logic [7:0] seq_first [0:8]; int seq_n;
always_ff @(posedge clk) begin
if (!rst_n) begin n_rgbaq<=0; n_st<=0; n_uv<=0; n_xyz2<=0; seq_n<=0; end
else if (dut.feeder_gif_reg_wr_en) begin
unique case (dut.feeder_gif_reg_num)
8'h01: n_rgbaq<=n_rgbaq+1; 8'h02: n_st<=n_st+1;
8'h03: n_uv<=n_uv+1; 8'h05: n_xyz2<=n_xyz2+1;
default: ;
endcase
if ((dut.feeder_gif_reg_num==8'h01 || dut.feeder_gif_reg_num==8'h02 || dut.feeder_gif_reg_num==8'h05) && seq_n<9) begin
seq_first[seq_n]<=dut.feeder_gif_reg_num; seq_n<=seq_n+1;
end
end
end
// ---- frame capture ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
logic [31:0] tex_tmp [0:TEXW*TEXH-1];
int errors, interior_ok, interior_total, persp_ne_affine, persp_ne_affine_ok;
initial begin
errors=0; interior_ok=0; interior_total=0; persp_ne_affine=0; persp_ne_affine_ok=0; feeder_go_tb=1'b0;
$readmemh(`FEEDER_PERSP_FILE, dut.g_feeder.feeder_stg);
$readmemh(`FEEDER_PERSP_TEX_FILE, tex_tmp);
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
// backdoor the checkerboard into VRAM at TBP (linear, TBW=1 -> 64-word row stride).
for (int vv=0; vv<TEXH; vv++) for (int uu=0; uu<TEXW; uu++)
dut.u_vram.mem[TEX_W0 + vv*64 + uu] = tex_tmp[vv*TEXW + uu];
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// re-assert the texture after the boot xfer (in case setup touched nearby), then render settles.
for (int vv=0; vv<TEXH; vv++) for (int uu=0; uu<TEXW; uu++)
dut.u_vram.mem[TEX_W0 + vv*64 + uu] = tex_tmp[vv*TEXW + uu];
wait (feeder_ready_tb==1'b1);
repeat(200000) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// ---- SEQ: feeder emitted RGBAQ/ST/XYZ2, not UV ----
$display("[feeder_persp] reg counts: RGBAQ=%0d ST=%0d UV=%0d XYZ2=%0d ; first-seq=%02x %02x %02x %02x %02x %02x",
n_rgbaq, n_st, n_uv, n_xyz2, seq_first[0],seq_first[1],seq_first[2],seq_first[3],seq_first[4],seq_first[5]);
if (n_st != 6) begin $error("[feeder_persp] ST writes=%0d (want 6 = 2 tris x 3)", n_st); errors++; end
if (n_uv != 0) begin $error("[feeder_persp] UV writes=%0d (want 0 in perspective mode)", n_uv); errors++; end
if (!(seq_first[0]==8'h01 && seq_first[1]==8'h02 && seq_first[2]==8'h05))
begin $error("[feeder_persp] vertex seq not RGBAQ->ST->XYZ2 (got %02x %02x %02x)", seq_first[0],seq_first[1],seq_first[2]); errors++; end
// ---- PROOF1/PROOF2 over the quad region ----
for (int py=QY0; py<=QY1; py++) begin
for (int px=QX0; px<=QX1; px++) begin
real wa,wb,wc, su,sv,sq, pu,pv, au,av;
real uA,vA,wAv, uB,vB,wBv, uC,vC,wCv;
bit inA, outside; logic [23:0] pe, ae;
real lx, ly; // local quad coords (0..32 x, 0..40 y) for barycentric
lx = px - QX0; ly = py - QY0;
inA=1'b1; outside=1'b0;
// triangle A = TL(0,0),TR(32,0),BL(0,40) in local coords
wa=bwa(lx,ly, 0,0, 32,0, 0,40); wb=bwb(lx,ly, 0,0, 32,0, 0,40); wc=1.0-wa-wb;
if (wa<-0.001||wb<-0.001||wc<-0.001) begin
inA=1'b0;
// triangle B = TR(32,0),BL(0,40),BR(32,40)
wa=bwa(lx,ly, 32,0, 0,40, 32,40); wb=bwb(lx,ly, 32,0, 0,40, 32,40); wc=1.0-wa-wb;
if (wa<-0.001||wb<-0.001||wc<-0.001) outside=1'b1;
end
if (!outside) begin
if (inA) begin uA=0; vA=0; wAv=W_FAR; uB=16; vB=0; wBv=W_FAR; uC=0; vC=16; wCv=W_NEAR; end
else begin uA=16; vA=0; wAv=W_FAR; uB=0; vB=16; wBv=W_NEAR; uC=16; vC=16; wCv=W_NEAR; end
su=wa*(uA/wAv)+wb*(uB/wBv)+wc*(uC/wCv);
sv=wa*(vA/wAv)+wb*(vB/wBv)+wc*(vC/wCv);
sq=wa*(1.0/wAv)+wb*(1.0/wBv)+wc*(1.0/wCv);
pu=su/sq; pv=sv/sq;
au=wa*uA+wb*uB+wc*uC; av=wa*vA+wb*vB+wc*vC;
if (pu<0) pu=0; if (pu>TEXW-1) pu=TEXW-1; if (pv<0) pv=0; if (pv>TEXH-1) pv=TEXH-1;
if (au<0) au=0; if (au>TEXW-1) au=TEXW-1; if (av<0) av=0; if (av>TEXH-1) av=TEXH-1;
pe=exp_cell(int'(pu+0.5),int'(pv+0.5)); ae=exp_cell(int'(au+0.5),int'(av+0.5));
if (edge_dist(pu)>1.0 && edge_dist(pv)>1.0 && cap_de[py][px]) begin
interior_total++;
if ({cap_b[py][px],cap_g[py][px],cap_r[py][px]} === pe) interior_ok++;
else begin
if (errors<12) $error("[feeder_persp] (%0d,%0d) u=%.2f v=%.2f got(%02x%02x%02x) exp(%06x)",
px,py,pu,pv, cap_b[py][px],cap_g[py][px],cap_r[py][px], pe);
errors++;
end
end
if (pe!==ae && edge_dist(pu)>1.0 && edge_dist(pv)>1.0 && cap_de[py][px]) begin
persp_ne_affine++;
if ({cap_b[py][px],cap_g[py][px],cap_r[py][px]} === pe) persp_ne_affine_ok++;
end
end
end
end
if (interior_total < 50) begin $error("[feeder_persp] too few interior pixels (%0d)", interior_total); errors++; end
if (interior_ok != interior_total) begin $error("[feeder_persp] interior match %0d/%0d", interior_ok, interior_total); errors++; end
if (persp_ne_affine < 8) begin $error("[feeder_persp] only %0d persp!=affine pixels — warp too weak", persp_ne_affine); errors++; end
else if (persp_ne_affine_ok != persp_ne_affine) begin
$error("[feeder_persp] capture matches AFFINE not PERSPECTIVE at %0d/%0d", persp_ne_affine-persp_ne_affine_ok, persp_ne_affine); errors++; end
if (raster_overflow) begin $error("[feeder_persp] raster_overflow set"); errors++; end
$display("[feeder_persp] interior_ok=%0d/%0d persp!=affine=%0d (matched persp=%0d) errors=%0d",
interior_ok, interior_total, persp_ne_affine, persp_ne_affine_ok, errors);
if (errors==0) begin $display("[tb_top_psmct32_feeder_persp_demo] PASS"); $finish; end
else $fatal(1, "[tb_top_psmct32_feeder_persp_demo] FAIL (%0d errors)", errors); // nonzero exit
end
initial begin #1500000000; $error("[tb_top_psmct32_feeder_persp_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_persp_demo
sim/tb/top/tb_top_psmct32_feeder_runtime_demo.sv
+150
View File
@@ -0,0 +1,150 @@
// retroDE_ps2 — tb_top_psmct32_feeder_runtime_demo (Ch330 Brick 3)
//
// RUNTIME PRIMITIVE-LIST SWAP without an RBF rebuild. The feeder plays list A
// (4 combined-TAZ tris in tile t0), the renderer draws it. Then we overwrite the
// staging RAM with list B (4 tris in tile t15) — exactly what a bridge write would
// do at runtime — and pulse the retrigger. The image changes from "blue in t0" to
// "blue in t15", with NO RBF rebuild and NO reset.
//
// The single proof that matters here is Codex's "known-empty" gotcha: list B must
// NOT append onto list A. The retrigger control FSM (C_SETUP->C_RUN->C_DRAIN->C_READY)
// gates a new list on the previous grid having actually run AND drained the FIFO. So:
// image A : blue in t0 box, ZERO blue in t15 box
// image B : blue in t15 box, ZERO blue in t0 box <- t0 went back to GREEN = no append
// Plus: records_emitted == 4 for each list (the feeder re-ran B's full list), and the
// FSM made a clean C_READY -> C_RUN -> C_READY round-trip on the retrigger.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_runtime_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam real MARG = 0.12;
// control-FSM state encodings (mirror the bram-top localparams; not visible across the generate)
localparam logic [1:0] C_RUN = 2'd1, C_READY = 2'd3;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
// Ch330 Brick 4 feeder ports: staging written via $readmemh backdoor here,
// so the bridge staging-write port is idle; only feeder_go_i is exercised.
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(), .feeder_records_o(), .feeder_waits_o()
);
logic feeder_go_tb;
// ---- scanout frame capture (one frame at a time; re-armed between lists) ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
task automatic clear_cap;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0;
end
endtask
initial begin clear_cap(); capture_armed=1'b0; end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
// count opaque-blue pixels inside a tile box [bx0,bx0+15] x [by0,by0+15]
function automatic int blue_in_box(input int bx0, input int by0);
int n; begin n=0;
for (int y=by0;y<by0+16;y++) for (int x=bx0;x<bx0+16;x++)
if (cap_de[y][x] && cap_b[y][x]===8'hFF && cap_r[y][x]===8'h00 && cap_g[y][x]===8'h00) n++;
blue_in_box = n;
end
endfunction
task automatic capture_frame; // arm for exactly one frame, then disarm
clear_cap();
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
endtask
int errors;
int blueA_t0, blueA_t15, blueB_t0, blueB_t15;
int recA, recB;
initial begin
errors=0;
// the retrigger pulse is the bram-top feeder_go_i port (bridge owns it in Brick 4)
feeder_go_tb = 1'b0;
// ---- list A: loaded into staging at t0; auto-plays after the bootlet upload ----
$readmemh(`FEEDER_STG_A_FILE, dut.g_feeder.feeder_stg);
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// list A runs + drains -> control FSM lands in C_READY
wait (dut.g_feeder.cst == C_READY);
recA = int'(dut.feeder_records);
capture_frame();
blueA_t0 = blue_in_box(0,0); blueA_t15 = blue_in_box(48,48);
// ---- runtime swap: overwrite staging with list B (tile t15), then RETRIGGER ----
$readmemh(`FEEDER_STG_B_FILE, dut.g_feeder.feeder_stg);
@(negedge clk); feeder_go_tb = 1'b1; @(negedge clk); feeder_go_tb = 1'b0;
wait (dut.g_feeder.cst == C_RUN); // FSM left READY -> RUN (B started)
wait (dut.g_feeder.cst == C_READY); // B ran + drained
recB = int'(dut.feeder_records);
capture_frame();
blueB_t0 = blue_in_box(0,0); blueB_t15 = blue_in_box(48,48);
// ---- proofs ----
// list A: blue in t0, nothing in t15
if (blueA_t0 < 20) begin $error("[demo] list A: too few blue px in t0 (%0d) — A not rendered", blueA_t0); errors++; end
if (blueA_t15 != 0) begin $error("[demo] list A: blue px in t15 (%0d) — should be empty", blueA_t15); errors++; end
// list B: blue in t15, t0 went BACK to green => no append
if (blueB_t15 < 20) begin $error("[demo] list B: too few blue px in t15 (%0d) — B not rendered after retrigger", blueB_t15); errors++; end
if (blueB_t0 != 0) begin $error("[demo] list B: blue px STILL in t0 (%0d) — list B APPENDED onto list A!", blueB_t0); errors++; end
// the image actually changed
if (blueA_t0 < 20 || blueB_t15 < 20) begin /* covered above */ end
// both lists fully emitted by the feeder
if (recA != 4) begin $error("[demo] list A records_emitted=%0d (want 4)", recA); errors++; end
if (recB != 4) begin $error("[demo] list B records_emitted=%0d (want 4)", recB); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_feeder_runtime_demo] A:{t0=%0d t15=%0d rec=%0d} B:{t0=%0d t15=%0d rec=%0d} errors=%0d",
blueA_t0, blueA_t15, recA, blueB_t0, blueB_t15, recB, errors);
if (errors==0) $display("[tb_top_psmct32_feeder_runtime_demo] PASS");
else $display("[tb_top_psmct32_feeder_runtime_demo] FAIL");
$finish;
end
initial begin #900000000; $error("[tb_top_psmct32_feeder_runtime_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_runtime_demo
sim/tb/top/tb_top_psmct32_feeder_scene_retrigger_demo.sv
+179
View File
@@ -0,0 +1,179 @@
// retroDE_ps2 — tb_top_psmct32_feeder_scene_retrigger_demo (Ch337)
//
// CLEAN SCENE-LEVEL RETRIGGER for >FIFO_DEPTH (multi-batch) scenes. Ch336 proved a >8 scene composes
// into one framebuffer; Ch337 proves the host can retrigger a NEW >8 scene without racing the last
// batch's render/flush. The control FSM now gates its ready on gs_stub.raster_scene_busy (which stays
// high through the inter-batch raster_active dips) instead of raster_active alone.
//
// Sequence (each scene is 14 prims = 2 batches): boot renders scene A, then on EACH feeder_ready edge
// we retrigger the next scene IMMEDIATELY (minimal gap — a premature ready would let the new scene
// race the old one and corrupt the FB):
// A (tiles 0-13 RED) -> B (tiles 2-15 BLUE) -> A (tiles 0-13 RED)
// Each scene's first (full-flush) batch wipes the WHOLE framebuffer, so after each retrigger the FB
// must be EXACTLY that scene with ZERO residue from the other:
// after B: BLUE in tiles 2-15, and NO RED anywhere (scene A fully gone).
// after A: RED in tiles 0-13, and NO BLUE anywhere (scene B fully gone).
`timescale 1ns/1ps
module tb_top_psmct32_feeder_scene_retrigger_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
logic feeder_go_tb, feeder_ready_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(feeder_ready_tb), .feeder_records_o(), .feeder_waits_o()
);
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
task automatic clear_cap;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
endtask
initial begin clear_cap(); capture_armed=1'b0; end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
function automatic int color_in_box(input int bx0, input int by0, input logic [7:0] er, eg, eb);
int n; begin n=0;
for (int y=by0;y<by0+16;y++) for (int x=bx0;x<bx0+16;x++)
if (cap_de[y][x] && cap_r[y][x]===er && cap_g[y][x]===eg && cap_b[y][x]===eb) n++;
color_in_box = n;
end
endfunction
// Whole-frame pixel count of a color — the leftover detector.
function automatic int color_in_frame(input logic [7:0] er, eg, eb);
int n; begin n=0;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++)
if (cap_de[y][x] && cap_r[y][x]===er && cap_g[y][x]===eg && cap_b[y][x]===eb) n++;
color_in_frame = n;
end
endfunction
function automatic int tile_x(input int t); tile_x = (t%4)*16; endfunction
function automatic int tile_y(input int t); tile_y = (t/4)*16; endfunction
int errors;
localparam logic [7:0] FF=8'hFF, ZZ=8'h00;
// CONTRACT MONITOR (the real Ch337 acceptance): feeder_ready must NOT rise until the WHOLE scene
// has drained. Sampled from gs_stub's RAW drain state (not the derived scene_busy wire) so it is
// independent of the fix's own signal. With the pre-Ch337 gate (raster_active alone) ready rises
// in an inter-batch dip while the next batch's prims are still queued (fifo_count != 0) -> fires.
// The FB check alone can't catch this: a premature retrigger self-heals after the long settle +
// per-scene full-flush. This is what makes the TB bite.
int ready_violations;
logic ready_d;
always_ff @(posedge clk) begin
if (!rst_n) begin ready_d <= 1'b0; ready_violations <= 0; end
else begin
ready_d <= feeder_ready_tb;
if (feeder_ready_tb && !ready_d) begin // feeder_ready rising edge
if (dut.u_gs.fifo_count != 0 || dut.u_gs.raster_active ||
dut.u_gs.mp_flush_pending || (dut.u_gs.tile_phase_r != 3'd0)) begin
$error("[CONTRACT] feeder_ready rose mid-scene: fifo=%0d raster_active=%b mp_flush_pending=%b tile_phase=%0d",
dut.u_gs.fifo_count, dut.u_gs.raster_active, dut.u_gs.mp_flush_pending, dut.u_gs.tile_phase_r);
ready_violations <= ready_violations + 1;
end
end
end
end
task automatic recapture;
repeat(200000) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); clear_cap(); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
endtask
// Retrigger the staged scene the INSTANT ready asserts (minimal gap stresses the race).
task automatic go_now;
wait (feeder_ready_tb==1'b1);
@(negedge clk); feeder_go_tb=1'b1; @(negedge clk); feeder_go_tb=1'b0;
endtask
initial begin
errors=0; feeder_go_tb=1'b0;
// Boot scene = A (bitstream-init equivalent).
$readmemh(`FEEDER_SCENE_A_FILE, dut.g_feeder.feeder_stg);
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
wait (feeder_ready_tb==1'b1); // boot render of A complete
// ---- scene A (boot) : tiles 0-13 RED, NO blue, nothing in tiles 14-15 ----
recapture();
for (int t=0;t<14;t++)
if (color_in_box(tile_x(t),tile_y(t),FF,ZZ,ZZ) < 15) begin
$error("[A boot] tile %0d not RED (%0d px)", t, color_in_box(tile_x(t),tile_y(t),FF,ZZ,ZZ)); errors++; end
if (color_in_frame(ZZ,ZZ,FF) != 0) begin $error("[A boot] BLUE present (%0d px)", color_in_frame(ZZ,ZZ,FF)); errors++; end
$display("[retrig A boot] RED=%0d BLUE=%0d (t0=%0d t13=%0d)",
color_in_frame(FF,ZZ,ZZ), color_in_frame(ZZ,ZZ,FF), color_in_box(0,0,FF,ZZ,ZZ), color_in_box(tile_x(13),tile_y(13),FF,ZZ,ZZ));
// ---- retrigger scene B : tiles 2-15 BLUE, and scene A must be FULLY GONE (zero RED) ----
$readmemh(`FEEDER_SCENE_B_FILE, dut.g_feeder.feeder_stg);
go_now();
recapture();
for (int t=2;t<16;t++)
if (color_in_box(tile_x(t),tile_y(t),ZZ,ZZ,FF) < 15) begin
$error("[B] tile %0d not BLUE (%0d px)", t, color_in_box(tile_x(t),tile_y(t),ZZ,ZZ,FF)); errors++; end
if (color_in_frame(FF,ZZ,ZZ) != 0) begin $error("[B] RED leftover from scene A (%0d px) — premature ready / batch race!", color_in_frame(FF,ZZ,ZZ)); errors++; end
if (int'(dut.feeder_records) != 14) begin $error("[B] records=%0d (want 14)", int'(dut.feeder_records)); errors++; end
$display("[retrig B] BLUE=%0d RED-leftover=%0d records=%0d", color_in_frame(ZZ,ZZ,FF), color_in_frame(FF,ZZ,ZZ), int'(dut.feeder_records));
// ---- retrigger scene A again : tiles 0-13 RED, and scene B must be FULLY GONE (zero BLUE) ----
$readmemh(`FEEDER_SCENE_A_FILE, dut.g_feeder.feeder_stg);
go_now();
recapture();
for (int t=0;t<14;t++)
if (color_in_box(tile_x(t),tile_y(t),FF,ZZ,ZZ) < 15) begin
$error("[A2] tile %0d not RED (%0d px)", t, color_in_box(tile_x(t),tile_y(t),FF,ZZ,ZZ)); errors++; end
if (color_in_frame(ZZ,ZZ,FF) != 0) begin $error("[A2] BLUE leftover from scene B (%0d px) — premature ready / batch race!", color_in_frame(ZZ,ZZ,FF)); errors++; end
if (int'(dut.feeder_records) != 14) begin $error("[A2] records=%0d (want 14)", int'(dut.feeder_records)); errors++; end
if (raster_overflow) begin $error("[A2] raster_overflow set"); errors++; end
$display("[retrig A2] RED=%0d BLUE-leftover=%0d records=%0d", color_in_frame(FF,ZZ,ZZ), color_in_frame(ZZ,ZZ,FF), int'(dut.feeder_records));
if (ready_violations != 0) begin $error("[retrig] %0d premature-ready (mid-scene) violations", ready_violations); errors += ready_violations; end
$display("[retrig] ready-contract violations=%0d", ready_violations);
$display("[tb_top_psmct32_feeder_scene_retrigger_demo] errors=%0d", errors);
if (errors==0) $display("[tb_top_psmct32_feeder_scene_retrigger_demo] PASS");
else $display("[tb_top_psmct32_feeder_scene_retrigger_demo] FAIL");
$finish;
end
initial begin #2500000000; $error("[tb_top_psmct32_feeder_scene_retrigger_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_scene_retrigger_demo
sim/tb/top/tb_top_psmct32_feeder_scenes_demo.sv
+151
View File
@@ -0,0 +1,151 @@
// retroDE_ps2 — tb_top_psmct32_feeder_scenes_demo (Ch331)
//
// FEEDER EXPRESSIVENESS: variable-size, multi-tile command-list scenes via the end-of-list
// flush (MP_FLUSH_ONLY). Ch330 proved "runtime command ingestion exists" with a fixed 4-prim
// list. This proves it SCALES to scene-level control: lists of DIFFERENT sizes — 3 (< the old
// TILE_PRIM_COUNT threshold), 6 (> it), and 8 (== FIFO_DEPTH) — each rendered in ONE pass across
// arbitrary tiles, switched at runtime with no reset/rebuild.
//
// scene C1 : 3 prims in tiles {0,5,10} (proves a <TILE_PRIM_COUNT list renders)
// scene C2 : 6 prims in tiles {0,3,5,9,12,15} (proves a >TILE_PRIM_COUNT list renders in one pass)
// scene C3 : 8 prims in tiles {0,1,2,3,12,13,14,15} (proves a full FIFO_DEPTH list renders)
//
// PROOF per scene: every scene tile has blue pixels, every NON-scene tile is clean green, and
// records_emitted == the scene's prim count. The end-of-list flush fires the grid once per scene
// regardless of size; the old fixed threshold would have split C2/C3 across clearing passes.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_scenes_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam real MARG = 0.12;
localparam logic [1:0] C_RUN = 2'd1, C_READY = 2'd3;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
logic feeder_go_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(), .feeder_records_o(), .feeder_waits_o()
);
// ---- scanout frame capture (one frame, re-armed per scene) ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
task automatic clear_cap;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0;
end
endtask
initial begin clear_cap(); capture_armed=1'b0; end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
function automatic int blue_in_box(input int bx0, input int by0);
int n; begin n=0;
for (int y=by0;y<by0+16;y++) for (int x=bx0;x<bx0+16;x++)
if (cap_de[y][x] && cap_b[y][x]===8'hFF && cap_r[y][x]===8'h00 && cap_g[y][x]===8'h00) n++;
blue_in_box = n;
end
endfunction
task automatic capture_frame;
clear_cap();
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
endtask
int errors;
// verify the captured frame: scene tiles (mask bit set) have blue, all others are clean.
task automatic check_scene(input string label, input logic [15:0] mask, input int exp_records);
int nb, scene_n; scene_n = 0;
for (int t=0;t<16;t++) begin
nb = blue_in_box((t%4)*16, (t/4)*16);
if (mask[t]) begin
scene_n++;
if (nb < 15) begin $error("[%s] tile %0d in scene but only %0d blue px (not rendered)", label, t, nb); errors++; end
end else begin
if (nb != 0) begin $error("[%s] tile %0d NOT in scene but has %0d blue px (stray render)", label, t, nb); errors++; end
end
end
if (int'(dut.feeder_records) != exp_records)
begin $error("[%s] records=%0d (want %0d)", label, int'(dut.feeder_records), exp_records); errors++; end
$display("[%s] %0d scene tiles painted, all others clean, records=%0d", label, scene_n, int'(dut.feeder_records));
endtask
task automatic stage_and_run(input string memfile);
$readmemh(memfile, dut.g_feeder.feeder_stg);
@(negedge clk); feeder_go_tb = 1'b1; @(negedge clk); feeder_go_tb = 1'b0;
wait (dut.g_feeder.cst == C_RUN);
wait (dut.g_feeder.cst == C_READY);
capture_frame();
endtask
initial begin
errors=0; feeder_go_tb=1'b0;
// scene C1 is the power-up list (loaded into staging); it auto-runs after the bootlet upload.
$readmemh(`FEEDER_SCENE_C1_FILE, dut.g_feeder.feeder_stg);
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// C1 (3 prims, < TILE_PRIM_COUNT) — auto-run
wait (dut.g_feeder.cst == C_READY);
capture_frame();
check_scene("C1 (3 prims, tiles 0/5/10)", 16'h0421, 3);
// C2 (6 prims, > TILE_PRIM_COUNT) — runtime swap
stage_and_run(`FEEDER_SCENE_C2_FILE);
check_scene("C2 (6 prims, tiles 0/3/5/9/12/15)", 16'h9229, 6);
// C3 (8 prims, == FIFO_DEPTH) — runtime swap
stage_and_run(`FEEDER_SCENE_C3_FILE);
check_scene("C3 (8 prims, tiles 0-3/12-15)", 16'hF00F, 8);
if (raster_overflow) begin $error("raster_overflow set"); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_feeder_scenes_demo] errors=%0d", errors);
if (errors==0) $display("[tb_top_psmct32_feeder_scenes_demo] PASS");
else $display("[tb_top_psmct32_feeder_scenes_demo] FAIL");
$finish;
end
initial begin #1200000000; $error("[tb_top_psmct32_feeder_scenes_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_scenes_demo
sim/tb/top/tb_top_psmct32_feeder_shapes_demo.sv
+140
View File
@@ -0,0 +1,140 @@
// retroDE_ps2 — tb_top_psmct32_feeder_shapes_demo (Ch332)
//
// SHAPE VOCABULARY: the feeder is no longer triangle-only smoke. A RECTANGLE (filled quad) is
// expressed as two textured triangles sharing a diagonal — no new feeder record type, just two
// triangle records — proving the host can command quads on the existing Ch330/Ch331 path. Three
// runtime-switched scenes (all <= FIFO_DEPTH), no rebuild/reset:
// TRI : 3 half-tile triangles tiles {0,5,10}
// RECT : 3 filled quads (6 prims) tiles {0,5,10} — same tiles, visibly FULLER than TRI
// MIXED : triangles {0,15} + rects {5,10} — both shapes in one scene
//
// PROOF: empty tiles stay clean; a rectangle tile is filled MORE than a triangle tile (the quad's
// two triangles tile cleanly with no diagonal seam); records_emitted == prim count per scene.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_shapes_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam real MARG = 0.12;
localparam logic [1:0] C_RUN = 2'd1, C_READY = 2'd3;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle, feeder_go_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(), .feeder_records_o(), .feeder_waits_o()
);
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
task automatic clear_cap;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
endtask
initial begin clear_cap(); capture_armed=1'b0; end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
function automatic int blue_in_box(input int bx0, input int by0);
int n; begin n=0;
for (int y=by0;y<by0+16;y++) for (int x=bx0;x<bx0+16;x++)
if (cap_de[y][x] && cap_b[y][x]===8'hFF && cap_r[y][x]===8'h00 && cap_g[y][x]===8'h00) n++;
blue_in_box = n;
end
endfunction
task automatic capture_frame;
clear_cap();
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
endtask
task automatic stage_and_run(input string memfile);
$readmemh(memfile, dut.g_feeder.feeder_stg);
@(negedge clk); feeder_go_tb=1'b1; @(negedge clk); feeder_go_tb=1'b0;
wait (dut.g_feeder.cst == C_RUN); wait (dut.g_feeder.cst == C_READY);
capture_frame();
endtask
int errors;
// tri fill (half a 13x13 tile ~80px) vs rect fill (full 13x13 ~150-169px). Bands with a clear gap.
localparam int TRI_MIN = 30, TRI_MAX = 120, RECT_MIN = 130;
// kinds: 0=empty (must be clean), 1=triangle (TRI band), 2=rectangle (RECT band)
task automatic check_shapes(input string label, input logic [31:0] kinds2b, input int exp_records);
int nb, kind;
for (int t=0;t<16;t++) begin
nb = blue_in_box((t%4)*16, (t/4)*16);
kind = (kinds2b >> (2*t)) & 2'b11;
case (kind)
0: if (nb != 0) begin $error("[%s] tile %0d empty but %0d blue", label,t,nb); errors++; end
1: if (nb < TRI_MIN || nb > TRI_MAX) begin $error("[%s] tile %0d TRI but %0d blue (want %0d..%0d)", label,t,nb,TRI_MIN,TRI_MAX); errors++; end
2: if (nb < RECT_MIN) begin $error("[%s] tile %0d RECT but only %0d blue (want >=%0d) — quad not filled / seam?", label,t,nb,RECT_MIN); errors++; end
endcase
end
if (int'(dut.feeder_records) != exp_records) begin $error("[%s] records=%0d (want %0d)", label, int'(dut.feeder_records), exp_records); errors++; end
$display("[%s] t0=%0d t5=%0d t10=%0d t15=%0d records=%0d",
label, blue_in_box(0,0), blue_in_box(16,16), blue_in_box(32,32), blue_in_box(48,48), int'(dut.feeder_records));
endtask
initial begin
errors=0; feeder_go_tb=1'b0;
$readmemh(`FEEDER_SHAPE_TRI_FILE, dut.g_feeder.feeder_stg); // power-up scene = TRI
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// TRI: triangles in 0/5/10 (kinds: t0=1,t5=1,t10=1)
wait (dut.g_feeder.cst == C_READY); capture_frame();
check_shapes("TRI (tri 0/5/10)", (32'd1<<(2*0))|(32'd1<<(2*5))|(32'd1<<(2*10)), 3);
// RECT: filled quads in 0/5/10 (kinds: t0=2,t5=2,t10=2) — same tiles, fuller
stage_and_run(`FEEDER_SHAPE_RECT_FILE);
check_shapes("RECT (quad 0/5/10)", (32'd2<<(2*0))|(32'd2<<(2*5))|(32'd2<<(2*10)), 6);
// MIXED: tris in 0/15, rects in 5/10
stage_and_run(`FEEDER_SHAPE_MIXED_FILE);
check_shapes("MIXED (tri 0/15 rect 5/10)", (32'd1<<(2*0))|(32'd2<<(2*5))|(32'd2<<(2*10))|(32'd1<<(2*15)), 6);
if (raster_overflow) begin $error("raster_overflow set"); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_feeder_shapes_demo] errors=%0d", errors);
if (errors==0) $display("[tb_top_psmct32_feeder_shapes_demo] PASS");
else $display("[tb_top_psmct32_feeder_shapes_demo] FAIL");
$finish;
end
initial begin #1200000000; $error("[tb_top_psmct32_feeder_shapes_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_shapes_demo
sim/tb/top/tb_top_psmct32_feeder_sprite_demo.sv
+118
View File
@@ -0,0 +1,118 @@
// retroDE_ps2 — tb_top_psmct32_feeder_sprite_demo (Ch345a)
//
// RUNTIME FEEDER SPRITE path: textured + source-over alpha SPRITEs streamed through the gs_prim_list_feeder
// (sprite_mode = staging word0[33]) into the SPRITE_TEX_ALPHA hardware, on the bram board variant. Proves
// the capability: host sprite command -> staging -> feeder -> textured-alpha sprite hardware -> pixels.
// This is RUNTIME SPRITE INGESTION (the Ch344-proven subset), NOT authentic glyph ingestion (Ch345b).
//
// Setup bootlet (bios/payload_sprite_setup): upload an 8x8 alpha-checker texture + draw an opaque blue BG.
// Feeder staging (feeder_sprite.mem): 3 textured-alpha SPRITE records over the BG (PRIM SPRITE+TME+ABE,
// source-over, white tint = identity MODULATE, As = texel alpha).
//
// Verify (PCRTC scanout): each of the 3 sprite rects shows the alpha checker — gray (opaque texels) and
// blue (transparent texels reveal the BG); the border is the pure blue BG; both gray+blue appear.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_sprite_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
// the 3 SPRITE_FEEDER_SET rects from bake.py: (8,24)-(24,40), (26,24)-(42,40), (44,24)-(60,40)
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
logic feeder_go_tb, feeder_ready_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b0), .TILE_LOCAL(1'b0), .TILE_COLS(1), .TILE_ROWS(1),
.TILE_MULTIPRIM(1'b0), .TILE_PRIM_COUNT(1), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b0), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256),
.SPRITE_TEX_ALPHA(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(feeder_ready_tb), .feeder_records_o(), .feeder_waits_o()
);
localparam logic [7:0] BG_R=8'h00, BG_G=8'h00, BG_B=8'hC0; // blue BG
localparam logic [7:0] GR_R=8'hC0, GR_G=8'hC0, GR_B=8'hC0; // opaque-texel gray
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0; feeder_go_tb=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
function automatic bit in_any_sprite(input int x, input int y);
in_any_sprite = (x>=8 && x<24 && y>=24 && y<40)
|| (x>=26 && x<42 && y>=24 && y<40)
|| (x>=44 && x<60 && y>=24 && y<40);
endfunction
function automatic bit is_bg (input int x, input int y); is_bg =(cap_b[y][x]==BG_B)&&(cap_g[y][x]==BG_G)&&(cap_r[y][x]==BG_R); endfunction
function automatic bit is_gray(input int x, input int y); is_gray=(cap_b[y][x]==GR_B)&&(cap_g[y][x]==GR_G)&&(cap_r[y][x]==GR_R); endfunction
int errors, border_ok, spr_gray, spr_bg, spr_bad;
initial begin errors=0; border_ok=0; spr_gray=0; spr_bg=0; spr_bad=0; end
initial begin
rst_n=1'b0; core_go=1'b0;
$readmemh(`FEEDER_SPRITE_FILE, dut.g_feeder.feeder_stg);
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
wait (feeder_ready_tb==1'b1);
repeat(200000) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
if (!cap_de[y][x]) begin if (errors<8) $error("[fsprite] (%0d,%0d) DE never asserted", x, y); errors++; end
else if (in_any_sprite(x,y)) begin
if (is_gray(x,y)) spr_gray++;
else if (is_bg(x,y)) spr_bg++;
else begin spr_bad++; if (errors<12) $error("[fsprite] sprite (%0d,%0d)=(%02x,%02x,%02x) neither gray nor BG", x,y,cap_b[y][x],cap_g[y][x],cap_r[y][x]); errors++; end
end else begin
if (is_bg(x,y)) border_ok++;
else begin if (errors<12) $error("[fsprite] border (%0d,%0d)=(%02x,%02x,%02x) not BG", x,y,cap_b[y][x],cap_g[y][x],cap_r[y][x]); errors++; end
end
end
if (spr_gray < 96) begin $error("[fsprite] too few gray (opaque) sprite px (%0d) across 3 sprites", spr_gray); errors++; end
if (spr_bg < 96) begin $error("[fsprite] too few transparent sprite px (%0d) — texel alpha not honored", spr_bg); errors++; end
if (spr_bad != 0) begin $error("[fsprite] %0d sprite px neither gray nor BG", spr_bad); errors++; end
if (raster_overflow) begin $error("[fsprite] raster_overflow set"); errors++; end
$display("[tb_top_psmct32_feeder_sprite_demo] border_ok=%0d sprite gray=%0d bg=%0d bad=%0d emits=%0d errors=%0d",
border_ok, spr_gray, spr_bg, spr_bad, dut.u_gs.raster_pixel_emit_count, errors);
if (errors==0) begin $display("[tb_top_psmct32_feeder_sprite_demo] PASS"); $finish; end
else $fatal(1, "[tb_top_psmct32_feeder_sprite_demo] FAIL (%0d errors)", errors);
end
initial begin #1500000000; $error("[tb_top_psmct32_feeder_sprite_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_sprite_demo
sim/tb/top/tb_top_psmct32_feeder_zpersist_demo.sv
+158
View File
@@ -0,0 +1,158 @@
// retroDE_ps2 — tb_top_psmct32_feeder_zpersist_demo (Ch338)
//
// CROSS-BATCH Z ORDERING for >FIFO_DEPTH scenes. A NEAR (RED) and a FAR (BLUE) triangle occupy the
// SAME tile (tile 5) but are SPLIT across FIFO batches. ZBUF clear = 0x4000, TEST = GEQUAL (higher Z
// = nearer wins). With PERSISTENT cross-batch Z (TILE_Z_PERSIST, on with FEEDER_ENABLE) the NEAR
// triangle wins the overlap regardless of which batch it is in — the Ch338 acceptance:
// NEAR_FIRST (near RED in batch0, far BLUE in batch1): tile5 = RED (far is Z-rejected)
// FAR_FIRST (far BLUE in batch0, near RED in batch1): tile5 = RED (near wins on submit too)
// With per-batch Z (the Ch336 v1 limit) NEAR_FIRST would wrongly show BLUE (the later batch starts
// from a fresh Z and overwrites the nearer earlier prim). Identical final overlap pixel regardless of
// the batch boundary == correct GS depth semantics preserved across the FIFO split.
`timescale 1ns/1ps
module tb_top_psmct32_feeder_zpersist_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
logic feeder_go_tb, feeder_ready_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb),
.feeder_ready_o(feeder_ready_tb), .feeder_records_o(), .feeder_waits_o()
);
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
task automatic clear_cap;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
endtask
initial begin clear_cap(); capture_armed=1'b0; end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
function automatic int color_in_box(input int bx0, input int by0, input logic [7:0] er, eg, eb);
int n; begin n=0;
for (int y=by0;y<by0+16;y++) for (int x=bx0;x<bx0+16;x++)
if (cap_de[y][x] && cap_r[y][x]===er && cap_g[y][x]===eg && cap_b[y][x]===eb) n++;
color_in_box = n;
end
endfunction
function automatic int tx(input int t); tx = (t%4)*16; endfunction
function automatic int ty(input int t); ty = (t/4)*16; endfunction
// count of any DRAWN (de) pixel in a tile box — used for the gradient overlap (its colors vary).
function automatic int drawn_in_box(input int bx0, input int by0);
int n; begin n=0;
for (int y=by0;y<by0+16;y++) for (int x=bx0;x<bx0+16;x++) if (cap_de[y][x]) n++;
drawn_in_box = n;
end
endfunction
int errors;
localparam logic [7:0] FF=8'hFF, ZZ=8'h00;
task automatic recapture;
repeat(200000) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); clear_cap(); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
endtask
// The overlap tile (5) must show NEAR=RED with NO far BLUE bleed-through, in BOTH orderings.
task automatic check_overlap(input string label);
if (color_in_box(tx(5),ty(5),FF,ZZ,ZZ) < 15) begin
$error("[%s] overlap tile 5 not RED (near) — %0d red px (cross-batch Z lost)", label, color_in_box(tx(5),ty(5),FF,ZZ,ZZ)); errors++; end
if (color_in_box(tx(5),ty(5),ZZ,ZZ,FF) != 0) begin
$error("[%s] overlap tile 5 has %0d BLUE (far) px — later batch overwrote the nearer prim!", label, color_in_box(tx(5),ty(5),ZZ,ZZ,FF)); errors++; end
endtask
initial begin
errors=0; feeder_go_tb=1'b0;
$readmemh(`FEEDER_ZPN_FILE, dut.g_feeder.feeder_stg); // boot scene = NEAR_FIRST
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
wait (feeder_ready_tb==1'b1);
// ---- NEAR_FIRST : near RED (batch0) + far BLUE (batch1) overlap tile 5 ----
recapture();
check_overlap("NEAR_FIRST");
// sanity: batch0 filler tile 0 RED, batch1 filler tile 8 BLUE
if (color_in_box(tx(0),ty(0),FF,ZZ,ZZ) < 15) begin $error("[NEAR_FIRST] tile0 not RED"); errors++; end
if (color_in_box(tx(8),ty(8),ZZ,ZZ,FF) < 15) begin $error("[NEAR_FIRST] tile8 not BLUE"); errors++; end
if (int'(dut.feeder_records) != 14) begin $error("[NEAR_FIRST] records=%0d (want 14)", int'(dut.feeder_records)); errors++; end
$display("[zpersist NEAR_FIRST] tile5 RED=%0d BLUE=%0d | t0 RED=%0d t8 BLUE=%0d | records=%0d",
color_in_box(tx(5),ty(5),FF,ZZ,ZZ), color_in_box(tx(5),ty(5),ZZ,ZZ,FF),
color_in_box(tx(0),ty(0),FF,ZZ,ZZ), color_in_box(tx(8),ty(8),ZZ,ZZ,FF), int'(dut.feeder_records));
// ---- FAR_FIRST (retrigger) : far BLUE (batch0) + near RED (batch1) overlap tile 5 ----
wait (feeder_ready_tb==1'b1);
$readmemh(`FEEDER_ZPF_FILE, dut.g_feeder.feeder_stg);
@(negedge clk); feeder_go_tb=1'b1; @(negedge clk); feeder_go_tb=1'b0;
recapture();
check_overlap("FAR_FIRST");
// sanity: batch0 filler tile 0 BLUE, batch1 filler tile 8 RED (colors reversed vs NEAR_FIRST)
if (color_in_box(tx(0),ty(0),ZZ,ZZ,FF) < 15) begin $error("[FAR_FIRST] tile0 not BLUE"); errors++; end
if (color_in_box(tx(8),ty(8),FF,ZZ,ZZ) < 15) begin $error("[FAR_FIRST] tile8 not RED"); errors++; end
if (raster_overflow) begin $error("[FAR_FIRST] raster_overflow set"); errors++; end
$display("[zpersist FAR_FIRST] tile5 RED=%0d BLUE=%0d | t0 BLUE=%0d t8 RED=%0d | records=%0d",
color_in_box(tx(5),ty(5),FF,ZZ,ZZ), color_in_box(tx(5),ty(5),ZZ,ZZ,FF),
color_in_box(tx(0),ty(0),ZZ,ZZ,FF), color_in_box(tx(8),ty(8),FF,ZZ,ZZ), int'(dut.feeder_records));
// ---- GRADIENT (retrigger) : NEAR gouraud RGB (batch0) + FAR flat WHITE (batch1) overlap ----
// Mixed colored/gradient scene: the near GRADIENT must win the overlap, so tile 5 is drawn with
// interpolated colors and ZERO white (the far flat prim is Z-rejected across the batch split).
wait (feeder_ready_tb==1'b1);
$readmemh(`FEEDER_ZPG_FILE, dut.g_feeder.feeder_stg);
@(negedge clk); feeder_go_tb=1'b1; @(negedge clk); feeder_go_tb=1'b0;
recapture();
if (color_in_box(tx(5),ty(5),FF,FF,FF) != 0) begin
$error("[GRAD] overlap tile 5 has %0d WHITE (far) px — far overwrote the near gradient!", color_in_box(tx(5),ty(5),FF,FF,FF)); errors++; end
if (drawn_in_box(tx(5),ty(5)) < 60) begin
$error("[GRAD] overlap tile 5 only %0d drawn px — near gradient missing", drawn_in_box(tx(5),ty(5))); errors++; end
if (int'(dut.feeder_records) != 14) begin $error("[GRAD] records=%0d (want 14)", int'(dut.feeder_records)); errors++; end
$display("[zpersist GRAD] tile5 WHITE=%0d drawn=%0d (gradient near wins, no far white) | records=%0d",
color_in_box(tx(5),ty(5),FF,FF,FF), drawn_in_box(tx(5),ty(5)), int'(dut.feeder_records));
$display("[tb_top_psmct32_feeder_zpersist_demo] errors=%0d", errors);
if (errors==0) $display("[tb_top_psmct32_feeder_zpersist_demo] PASS");
else $display("[tb_top_psmct32_feeder_zpersist_demo] FAIL");
$finish;
end
initial begin #2500000000; $error("[tb_top_psmct32_feeder_zpersist_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_feeder_zpersist_demo
sim/tb/top/tb_top_psmct32_persp_floor_demo.sv
+190
View File
@@ -0,0 +1,190 @@
// retroDE_ps2 — tb_top_psmct32_persp_floor_demo (Ch301b)
//
// PERSPECTIVE-CORRECT FLOOR demo TB — the human-recognizable perspective demo,
// and (per the architect) the one that proves SEAM CONTINUITY, which the Ch301
// per-triangle TB could NOT (it was fed the same inconsistent vertex data as the
// RTL, so it only proved RTL==fixture-math, not that the two triangles form ONE
// coherent surface).
//
// The fixture (bake.py persp_floor) derives all four trapezoid corners from ONE
// pinhole projection of a flat floor, so s/w, t/w, 1/w are screen-AFFINE over
// the WHOLE quad. This TB therefore builds a SINGLE affine S/T/Q plane (from the
// Tri1 corners NL,NR,FR, extrapolated) and checks EVERY inside pixel of BOTH
// triangles against that one plane:
//
// PROOF 1 — FLOOR-PLANE MATCH: every interior-of-cell pixel (in Tri1 OR Tri2)
// matches persp_texel(u,v) where (u,v)=(S/Q,T/Q) from the single
// plane. A per-triangle divergence (the Ch301 shear bug) would make
// Tri2 pixels mismatch this one-plane reference → caught.
// PROOF 2 — SEAM CONTINUITY: Tri2's interior pixels are checked against the
// SAME plane fitted from Tri1's vertices; requiring Tri2 to match it
// is exactly the assertion that the two triangles agree across the
// shared NL-FR diagonal. Tracked + asserted separately.
// PROOF 3 — PERSPECTIVE != AFFINE: at interior pixels where the perspective
// and affine references give different cells, captured matches
// perspective (compression toward the far/top edge).
`timescale 1ns/1ps
module tb_top_psmct32_persp_floor_demo;
localparam int H_ACTIVE = 34;
localparam int V_ACTIVE = 19;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.VRAM_BYTES (8 * 1024),
.PSMCT32_SWIZZLE (1'b0),
.PERSPECTIVE_CORRECT(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
function automatic logic [23:0] exp_cell(input integer u, input integer v);
if ((((u >> 2) + (v >> 2)) & 1)) exp_cell = 24'hFFFFFF;
else exp_cell = 24'h902020; // {b,g,r}
endfunction
function automatic real bdet(input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bdet = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
endfunction
function automatic real bwa(input real px,input real py,input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bwa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / bdet(ax,ay,bx,by,cx,cy);
endfunction
function automatic real bwb(input real px,input real py,input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bwb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / bdet(ax,ay,bx,by,cx,cy);
endfunction
function automatic real edge_dist(input real c);
real m; m = c - (4.0 * $floor(c/4.0));
edge_dist = (m < (4.0-m)) ? m : (4.0-m);
endfunction
// ---- capture ----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b;
cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, t1_ok, t1_tot, t2_ok, t2_tot, pna, pna_ok;
initial begin
errors=0; t1_ok=0; t1_tot=0; t2_ok=0; t2_tot=0; pna=0; pna_ok=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
if (dut.u_gs.raster_active==1'b1) wait (dut.u_gs.raster_active==1'b0);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
real w1a,w1b,w1c, w2a,w2b,w2c;
real S,T,Q, pu,pv, au,av;
bit in1, in2;
logic [23:0] pe, ae;
// Tri1 = NL(0,18),NR(32,18),FR(20,0) ; Tri2 = NL(0,18),FR(20,0),FL(12,0)
w1a=bwa(px,py, 0,18, 32,18, 20,0); w1b=bwb(px,py, 0,18, 32,18, 20,0); w1c=1.0-w1a-w1b;
w2a=bwa(px,py, 0,18, 20,0, 12,0); w2b=bwb(px,py, 0,18, 20,0, 12,0); w2c=1.0-w2a-w2b;
in1 = (w1a>=-0.001)&&(w1b>=-0.001)&&(w1c>=-0.001);
in2 = (w2a>=-0.001)&&(w2b>=-0.001)&&(w2c>=-0.001);
if (in1 || in2) begin
// SINGLE plane from Tri1 corners (NL,NR,FR), extrapolated for
// Tri2 pixels — this is the floor-plane / seam-continuity ref.
// u/w,v/w,1/w: NL(0,0,1) NR(15,0,1) FR(3.75,3.75,0.25)
S = w1a*0.0 + w1b*15.0 + w1c*3.75;
T = w1a*0.0 + w1b*0.0 + w1c*3.75;
Q = w1a*1.0 + w1b*1.0 + w1c*0.25;
pu = S/Q; pv = T/Q;
// affine ref (interpolate integer u,v directly via Tri1)
au = w1a*0.0 + w1b*15.0 + w1c*15.0;
av = w1a*0.0 + w1b*0.0 + w1c*15.0;
if (pu<0) pu=0; if (pu>15) pu=15; if (pv<0) pv=0; if (pv>15) pv=15;
if (au<0) au=0; if (au>15) au=15; if (av<0) av=0; if (av>15) av=15;
pe = exp_cell(int'(pu+0.5), int'(pv+0.5));
ae = exp_cell(int'(au+0.5), int'(av+0.5));
if (edge_dist(pu)>1.0 && edge_dist(pv)>1.0 && cap_de[py][px]) begin
bit match;
match = ({cap_b[py][px],cap_g[py][px],cap_r[py][px]} === pe);
// PROOF 1 + 2 — attribute to whichever triangle owns it (Tri1 priority).
if (in1) begin t1_tot++; if (match) t1_ok++; end
else begin t2_tot++; if (match) t2_ok++; end
if (!match) begin
if (errors<12)
$error("[pfloor] (%0d,%0d) tri%0d u=%.2f v=%.2f got(%02x,%02x,%02x) exp(%06x)",
px,py, in1?1:2, pu,pv, cap_r[py][px],cap_g[py][px],cap_b[py][px], pe);
errors++;
end
// PROOF 3
if (pe!==ae) begin pna++; if (match) pna_ok++; end
end
end
end
end
// Tri2 (the FL-side sliver) is geometrically small, so fewer interior-of-
// cell samples than Tri1 — 8 is plenty to prove seam continuity (every
// one must still match the single Tri1-derived plane).
if (t1_tot < 20 || t2_tot < 8) begin
$error("[pfloor] too few interior pixels (tri1=%0d tri2=%0d) — geometry/capture issue", t1_tot, t2_tot); errors++;
end
// PROOF 1: Tri1 matches the plane.
if (t1_ok != t1_tot) begin $error("[pfloor] Tri1 plane match %0d/%0d", t1_ok, t1_tot); errors++; end
// PROOF 2 (SEAM): Tri2 must ALSO match the SAME (Tri1-derived) plane.
if (t2_ok != t2_tot) begin
$error("[pfloor] SEAM DISCONTINUITY: Tri2 matched the single floor-plane only %0d/%0d — the two triangles disagree across the shared diagonal", t2_ok, t2_tot);
errors++;
end
// PROOF 3
if (pna < 8) begin $error("[pfloor] only %0d persp!=affine pixels — warp too weak", pna); errors++; end
else if (pna_ok != pna) begin $error("[pfloor] captured matched AFFINE not PERSPECTIVE at %0d/%0d", pna-pna_ok, pna); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_persp_floor_demo] tri1=%0d/%0d tri2(seam)=%0d/%0d persp!=affine=%0d(ok=%0d) errors=%0d",
t1_ok,t1_tot, t2_ok,t2_tot, pna,pna_ok, errors);
if (errors==0) $display("[tb_top_psmct32_persp_floor_demo] PASS");
else $display("[tb_top_psmct32_persp_floor_demo] FAIL");
$finish;
end
initial begin #80000000; $error("[tb_top_psmct32_persp_floor_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_persp_floor_demo
sim/tb/top/tb_top_psmct32_perspective_demo.sv
+237
View File
@@ -0,0 +1,237 @@
// retroDE_ps2 — tb_top_psmct32_perspective_demo (Ch301)
//
// TOP-LEVEL PERSPECTIVE-CORRECT textured-triangle demo for the BRAM board
// variant. A receding "floor" quad (2 TME TRIANGLEs) textured with a 4x4-cell
// checkerboard. Texture coords supplied via ST (S=u/w, T=v/w) + RGBAQ.Q (=1/w);
// top edge FAR (w=8), bottom NEAR (w=1). With PERSPECTIVE_CORRECT=1 the
// rasterizer recovers per-pixel (u,v)=(S/Q,T/Q) through the pipelined reciprocal
// LUT + gs_persp_uv (NO per-pixel divider) — the checkerboard compresses toward
// the far (top) edge. PSMCT32_SWIZZLE=0 (linear texture).
//
// Verification (matches bake.py persp_* fixture):
// PROOF 1 — per-pixel vs a barycentric PERSPECTIVE reference (real math):
// interior-of-cell pixels (>1 texel from a 4px cell edge) must match
// the captured scanout exactly (the recip's sub-texel error can only
// flip a cell exactly at a boundary, which we skip).
// PROOF 2 — PERSPECTIVE != AFFINE: where perspective and affine references
// disagree, the captured frame must match PERSPECTIVE (not affine).
`timescale 1ns/1ps
module tb_top_psmct32_perspective_demo;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 24;
localparam int SCR_W = 16, SCR_H = 24, TEXW = 16, TEXH = 16;
real W_FAR; real W_NEAR;
initial begin W_FAR = 8.0; W_NEAR = 1.0; end
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.VRAM_BYTES (8 * 1024),
.PSMCT32_SWIZZLE (1'b0),
.PERSPECTIVE_CORRECT(1'b1)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// expected checkerboard texel (mirrors bake.py persp_texel): packed {b,g,r}.
function automatic logic [23:0] exp_cell(input integer u, input integer v);
if ((((u >> 2) + (v >> 2)) & 1)) exp_cell = 24'hFFFFFF; // white
else exp_cell = 24'h902020; // {b,g,r} dark-blue
endfunction
// single-return barycentric helpers (no output args — iverilog-12 friendly).
function automatic real bdet(input real ax, input real ay, input real bx,
input real by, input real cx, input real cy);
bdet = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
endfunction
function automatic real bwa(input real px, input real py, input real ax, input real ay,
input real bx, input real by, input real cx, input real cy);
bwa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / bdet(ax,ay,bx,by,cx,cy);
endfunction
function automatic real bwb(input real px, input real py, input real ax, input real ay,
input real bx, input real by, input real cx, input real cy);
bwb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / bdet(ax,ay,bx,by,cx,cy);
endfunction
// distance from c to the nearest 4px cell edge.
function automatic real edge_dist(input real c);
real m;
m = c - (4.0 * $floor(c/4.0));
edge_dist = (m < (4.0-m)) ? m : (4.0-m);
endfunction
// ---- frame capture ----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
capture_armed = 1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b;
cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, interior_ok, interior_total, persp_ne_affine, persp_ne_affine_ok;
initial begin
errors=0; interior_ok=0; interior_total=0; persp_ne_affine=0; persp_ne_affine_ok=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
if (dut.u_gs.raster_active==1'b1) wait (dut.u_gs.raster_active==1'b0);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// TEMP: dump the captured frame as ASCII (W=white B=blue .=other/none)
$display("=== captured frame (W=white B=blue) ===");
for (int dy=0; dy<SCR_H; dy++) begin
string row;
row = "";
for (int dx=0; dx<SCR_W; dx++) begin
if (!cap_de[dy][dx]) row = {row, "_"};
else if (cap_r[dy][dx]==8'hFF && cap_g[dy][dx]==8'hFF && cap_b[dy][dx]==8'hFF) row = {row, "W"};
else if (cap_b[dy][dx]==8'h90) row = {row, "B"};
else row = {row, "?"};
end
$display("y=%2d |%s|", dy, row);
end
for (int py=0; py<SCR_H; py++) begin
for (int px=0; px<SCR_W; px++) begin
real wa, wb, wc;
real su, sv, sq, pu, pv, au, av;
real uA,vA,wAv, uB,vB,wBv, uC,vC,wCv;
bit inA, outside;
logic [23:0] pe, ae;
// triangle A = TL(0,0),TR(15,0),BL(0,23)
inA = 1'b1; outside = 1'b0;
wa = bwa(px,py, 0,0, 15,0, 0,23);
wb = bwb(px,py, 0,0, 15,0, 0,23);
wc = 1.0 - wa - wb;
if (wa < -0.001 || wb < -0.001 || wc < -0.001) begin
inA = 1'b0;
// triangle B = TR(15,0),BR(15,23),BL(0,23)
wa = bwa(px,py, 15,0, 15,23, 0,23);
wb = bwb(px,py, 15,0, 15,23, 0,23);
wc = 1.0 - wa - wb;
if (wa < -0.001 || wb < -0.001 || wc < -0.001) outside = 1'b1; // outside quad
end
if (!outside) begin
// per-vertex (u,v,w) for the chosen triangle
if (inA) begin
uA=0; vA=0; wAv=W_FAR; uB=15; vB=0; wBv=W_FAR; uC=0; vC=15; wCv=W_NEAR;
end else begin
uA=15; vA=0; wAv=W_FAR; uB=15; vB=15; wBv=W_NEAR; uC=0; vC=15; wCv=W_NEAR;
end
// perspective: interp u/w,v/w,1/w then divide
su = wa*(uA/wAv) + wb*(uB/wBv) + wc*(uC/wCv);
sv = wa*(vA/wAv) + wb*(vB/wBv) + wc*(vC/wCv);
sq = wa*(1.0/wAv) + wb*(1.0/wBv) + wc*(1.0/wCv);
pu = su / sq; pv = sv / sq;
// affine: interp u,v directly
au = wa*uA + wb*uB + wc*uC;
av = wa*vA + wb*vB + wc*vC;
if (pu<0) pu=0; if (pu>TEXW-1) pu=TEXW-1;
if (pv<0) pv=0; if (pv>TEXH-1) pv=TEXH-1;
if (au<0) au=0; if (au>TEXW-1) au=TEXW-1;
if (av<0) av=0; if (av>TEXH-1) av=TEXH-1;
pe = exp_cell(int'(pu+0.5), int'(pv+0.5));
ae = exp_cell(int'(au+0.5), int'(av+0.5));
// PROOF 1 — interior-of-cell pixels match perspective exactly.
if (edge_dist(pu) > 1.0 && edge_dist(pv) > 1.0 && cap_de[py][px]) begin
interior_total++;
if ({cap_b[py][px],cap_g[py][px],cap_r[py][px]} === pe)
interior_ok++;
else begin
if (errors < 12)
$error("[persp] (%0d,%0d) u=%.2f v=%.2f got(%02x,%02x,%02x) exp(%06x)",
px,py,pu,pv, cap_r[py][px],cap_g[py][px],cap_b[py][px], pe);
errors++;
end
end
// PROOF 2 — where the perspective and affine references give
// DIFFERENT cells (and the perspective pixel is cell-interior,
// so its captured color is unambiguous), the captured frame
// must match PERSPECTIVE — proving it is not the affine path.
if (pe !== ae && edge_dist(pu)>1.0 && edge_dist(pv)>1.0 && cap_de[py][px]) begin
persp_ne_affine++;
if ({cap_b[py][px],cap_g[py][px],cap_r[py][px]} === pe)
persp_ne_affine_ok++;
end
end
end
end
if (interior_total < 50) begin
$error("[persp] too few interior pixels (%0d) — geometry/capture issue", interior_total); errors++;
end
if (interior_ok != interior_total) begin
$error("[persp] interior match %0d/%0d", interior_ok, interior_total); errors++;
end
if (persp_ne_affine < 8) begin
$error("[persp] only %0d persp!=affine pixels — warp too weak", persp_ne_affine); errors++;
end else if (persp_ne_affine_ok != persp_ne_affine) begin
$error("[persp] captured matches AFFINE not PERSPECTIVE at %0d/%0d divergent pixels",
persp_ne_affine - persp_ne_affine_ok, persp_ne_affine); errors++;
end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow set"); errors++; end
$display("[tb_top_psmct32_perspective_demo] interior_ok=%0d/%0d persp!=affine=%0d (matched persp=%0d) errors=%0d",
interior_ok, interior_total, persp_ne_affine, persp_ne_affine_ok, errors);
if (errors==0) $display("[tb_top_psmct32_perspective_demo] PASS");
else $display("[tb_top_psmct32_perspective_demo] FAIL");
$finish;
end
initial begin
#80000000;
$error("[tb_top_psmct32_perspective_demo] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_perspective_demo
sim/tb/top/tb_top_psmct32_raster_demo.sv
+212
View File
@@ -0,0 +1,212 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo (Ch146)
//
// Focused TB for the first hardware-targeted top wrapper. Drives the
// top with the static .mem fixtures generated by sim/data/
// top_psmct32_raster_demo/bake.py and verifies the same 16×8 PCRTC
// frame Ch123 produces. The point of this TB is NOT to re-verify
// every Ch123 invariant — that's already covered by
// tb_gs_demo_psmct32_swizzle_e2e — but to prove:
// (1) The top wrapper compiles standalone with no hierarchical
// refs into TB scopes.
// (2) `$readmemh` of the static fixtures produces identical
// behavior to the procedural Ch123 preload.
// (3) The status bundle (core_halt + dma_done_seen + frame_seen)
// fires in the expected order.
// (4) The active PCRTC region matches Ch123's per-quadrant
// grayscale exactly — so a board-level bring-up that wires
// r/g/b/hsync/vsync/de to a video PHY would display the same
// image the sim produces.
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
// BIOS / payload image paths are passed to the top wrapper via
// pre-defined macros (the Ch146 build rule sets
// TOP_PSMCT32_RASTER_DEMO_BIOS_IMAGE_FILE +
// TOP_PSMCT32_RASTER_DEMO_PAYLOAD_IMAGE_FILE via -D, then the
// wrapper expands them at the bios_rom_stub / ee_ram_stub
// instances).
top_psmct32_raster_demo #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen)
);
// ----------------------------------------------------------------
// Per-quadrant expected RGB (matches Ch123 / bake.py).
// ----------------------------------------------------------------
function automatic int quadrant_idx(input int x, input int y);
int qx, qy;
qx = (x < 8) ? 0 : 1;
qy = (y < 4) ? 0 : 1;
return qy * 2 + qx;
endfunction
function automatic logic [7:0] expected_r(input int q);
case (q)
0: return 8'h55;
1: return 8'h66;
2: return 8'h77;
default: return 8'h88;
endcase
endfunction
function automatic logic [7:0] expected_g(input int q);
case (q)
0: return 8'hAA;
1: return 8'hBB;
2: return 8'h33;
default: return 8'h44;
endcase
endfunction
function automatic logic [7:0] expected_b(input int q);
case (q)
0: return 8'hCC;
1: return 8'hDD;
2: return 8'h99;
default: return 8'h22;
endcase
endfunction
// ----------------------------------------------------------------
// Frame capture.
// ----------------------------------------------------------------
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 8'd0;
cap_g[y][x] = 8'd0;
cap_b[y][x] = 8'd0;
cap_de[y][x] = 1'b0;
end
capture_armed = 1'b0;
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de
&& (dut.u_pcrtc.vcnt < V_ACTIVE)
&& (dut.u_pcrtc.hcnt < H_ACTIVE)) begin
cap_r [dut.u_pcrtc.vcnt][dut.u_pcrtc.hcnt] <= r;
cap_g [dut.u_pcrtc.vcnt][dut.u_pcrtc.hcnt] <= g;
cap_b [dut.u_pcrtc.vcnt][dut.u_pcrtc.hcnt] <= b;
cap_de[dut.u_pcrtc.vcnt][dut.u_pcrtc.hcnt] <= 1'b1;
end
end
int errors;
initial errors = 0;
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
// Pulse core_go for one cycle. On hardware a board reset-
// release sequencer can do the same.
@(negedge clk);
core_go = 1'b1;
@(negedge clk);
core_go = 1'b0;
// Wait for the EE to halt (SYSCALL halt_o), then for DMAC
// DONE event to be sticky-latched.
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1)
wait (dut.xfer_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1)
wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// Phase 1 — scanout assertion. Per-pixel per-quadrant RGB.
for (int y = 0; y < V_ACTIVE; y++) begin
for (int x = 0; x < H_ACTIVE; x++) begin
int q;
logic [7:0] er, eg, eb;
q = quadrant_idx(x, y);
er = expected_r(q);
eg = expected_g(q);
eb = expected_b(q);
if (!cap_de[y][x]) begin
$error("(%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end
if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
$error("[scanout] (%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x) sprite=%0d",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb, q);
errors = errors + 1;
end
end
end
// Phase 2 — status bundle. core_halt, dma_done_seen, frame_seen
// all latched.
if (!core_halt) begin
$error("core_halt low at end of test");
errors = errors + 1;
end
if (!dma_done_seen) begin
$error("dma_done_seen never latched");
errors = errors + 1;
end
if (!frame_seen) begin
$error("frame_seen never latched");
errors = errors + 1;
end
$display("[tb_top_psmct32_raster_demo] core_halt=%0b dma_done_seen=%0b frame_seen=%0b raster_emits=%0d errors=%0d",
core_halt, dma_done_seen, frame_seen,
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_raster_demo] PASS");
else
$display("[tb_top_psmct32_raster_demo] FAIL");
$finish;
end
// Watchdog.
initial begin
#20000000;
$error("[tb_top_psmct32_raster_demo] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_raster_demo
sim/tb/top/tb_top_psmct32_raster_demo_bram.sv
+272
View File
@@ -0,0 +1,272 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo_bram (Ch155 origin /
// Ch158 frame-capture enabled)
//
// Integration TB for `top_psmct32_raster_demo_bram` — the same
// Ch146 dep tree, but with `vram_bram_stub` (Ch154) replacing
// `vram_stub` and (since Ch158) `gs_pcrtc_stub` instantiated with
// `VRAM_SYNC_READ=1` so its data-decode + sync-output stages line
// up with the BRAM's registered read. Drives the same Ch146 .mem
// fixtures (4 SPRITE PACKED PSMCT32 packets), waits for the EE
// bootlet to halt + DMAC done + raster drained, then runs two
// verification phases:
//
// Phase 1 (Ch155): per-pixel VRAM probe via hierarchical ref to
// `dut.u_vram.mem[byte_addr >> 2]` for each of the 16×8 pixels
// at canonical PSMCT32 swizzled word indices.
//
// Phase 2 (Ch158, NEW): wait for the next end-of-frame, capture
// one full PCRTC frame's worth of (de, r, g, b) into a 2D
// `cap_*[v][h]` array, then assert every active-region pixel
// matches the ABGR-decoded expected color for its quadrant.
// PCRTC's `VRAM_SYNC_READ=1` pipeline means r/g/b are no longer
// 1-column shifted — captured pixel @(x,y) holds the value at
// the swizzled mem location for that (x,y).
//
// Codex Ch155 framing: "vram_bram_stub integration TB for the
// Ch123 PSMCT32 path first, because CT32 already matches the
// contract." Ch158 closes the loop by capturing the scanout too.
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo_bram;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE),
.V_ACTIVE(V_ACTIVE)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen)
);
// Per-quadrant expected ABGR (matches Ch146 bake.py).
function automatic int quadrant_idx(input int x, input int y);
int qx, qy;
qx = (x < 8) ? 0 : 1;
qy = (y < 4) ? 0 : 1;
return qy * 2 + qx;
endfunction
function automatic logic [7:0] expected_r(input int q);
case (q)
0: return 8'h55; 1: return 8'h66; 2: return 8'h77; default: return 8'h88;
endcase
endfunction
function automatic logic [7:0] expected_g(input int q);
case (q)
0: return 8'hAA; 1: return 8'hBB; 2: return 8'h33; default: return 8'h44;
endcase
endfunction
function automatic logic [7:0] expected_b(input int q);
case (q)
0: return 8'hCC; 1: return 8'hDD; 2: return 8'h99; default: return 8'h22;
endcase
endfunction
// ABGR ordering: write_data[31:24]=A, [23:16]=B, [15:8]=G, [7:0]=R.
function automatic logic [31:0] expected_word(input int q);
return {8'hFF, expected_b(q), expected_g(q), expected_r(q)};
endfunction
// PSMCT32 swizzle reference — same shape as Ch123's TB.
function automatic int ref_block_idx_ct32(input int by, input int bx);
case ({by[1:0], bx[2:0]})
5'd0: return 0; 5'd1: return 1; 5'd2: return 4; 5'd3: return 5;
5'd4: return 16; 5'd5: return 17; 5'd6: return 20; 5'd7: return 21;
5'd8: return 2; 5'd9: return 3; 5'd10: return 6; 5'd11: return 7;
5'd12: return 18; 5'd13: return 19; 5'd14: return 22; 5'd15: return 23;
5'd16: return 8; 5'd17: return 9; 5'd18: return 12; 5'd19: return 13;
5'd20: return 24; 5'd21: return 25; 5'd22: return 28; 5'd23: return 29;
5'd24: return 10; 5'd25: return 11; 5'd26: return 14; 5'd27: return 15;
5'd28: return 26; 5'd29: return 27; 5'd30: return 30; default: return 31;
endcase
endfunction
function automatic int ref_addr_psmct32(
input int fbp_v, input int fbw_v, input int x_v, input int y_v);
int page_x, page_y, page_idx, page_base;
int by, bx, blk_idx, xb, yb;
page_x = x_v / 64;
page_y = y_v / 32;
page_idx = page_y * fbw_v + page_x;
page_base = fbp_v * 2048 + page_idx * 8192;
by = (y_v % 32) / 8;
bx = (x_v % 64) / 8;
blk_idx = ref_block_idx_ct32(by, bx);
xb = x_v % 8;
yb = y_v % 8;
return page_base + blk_idx * 256 + yb * 32 + xb * 4;
endfunction
int errors;
initial errors = 0;
// ------------------------------------------------------------
// Ch158 — frame capture. Latches r/g/b for every pixel in the
// PCRTC active region while `cap_armed` is high.
// ------------------------------------------------------------
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit cap_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r [y][x] = 8'd0;
cap_g [y][x] = 8'd0;
cap_b [y][x] = 8'd0;
cap_de[y][x] = 1'b0;
end
cap_armed = 1'b0;
end
// Ch158: PCRTC's `de` is the registered (decode-stage) view
// when VRAM_SYNC_READ=1, so when it pulses high the r/g/b on
// output corresponds to PCRTC's `hcnt`/`vcnt` at the PRIOR
// posedge (the pixel that was at the address stage one cycle
// ago). The TB therefore registers a 1-cycle-late copy of the
// address-stage counters and uses them as the cap[][] indices.
logic [31:0] hcnt_d;
logic [31:0] vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin
hcnt_d <= 32'd0;
vcnt_d <= 32'd0;
end else begin
hcnt_d <= 32'(dut.u_pcrtc.hcnt);
vcnt_d <= 32'(dut.u_pcrtc.vcnt);
end
end
always_ff @(posedge clk) begin
if (rst_n && cap_armed && de
&& (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk); core_go = 1'b1;
@(negedge clk); core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1) wait (dut.xfer_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1) wait (dut.u_gs.raster_active == 1'b0);
repeat (20) @(posedge clk);
// Per-pixel VRAM probe via hierarchical ref. vram_bram_stub
// is word-indexed (`mem [0:WORDS-1]`); convert byte_addr →
// word_idx by `>> 2`.
for (int y = 0; y < V_ACTIVE; y++) begin
for (int x = 0; x < H_ACTIVE; x++) begin
int q;
int byte_addr;
logic [31:0] expected;
logic [31:0] got;
q = quadrant_idx(x, y);
byte_addr = ref_addr_psmct32(0, 1, x, y);
expected = expected_word(q);
got = dut.u_vram.mem[byte_addr >> 2];
if (got !== expected) begin
$error("[vram] (%0d,%0d) word @byte 0x%04x got 0x%08x expected 0x%08x sprite=%0d",
x, y, byte_addr, got, expected, q);
errors = errors + 1;
end
end
end
// -----------------------------------------------------------
// Phase 2 (Ch158) — frame capture. Arm the capture latch on
// the next vsync rising edge so we record exactly one full
// frame of active-region pixels, then assert each captured
// pixel matches the expected ABGR for its quadrant after
// PCRTC's PSMCT32 → r/g/b decode (which drops alpha).
// -----------------------------------------------------------
@(negedge dut.vsync); // currently in vsync? wait for it to clear
@(posedge dut.vsync); // next vsync rising
cap_armed = 1'b1;
// Capture for one full frame plus a margin.
repeat ((H_ACTIVE + 4) * (V_ACTIVE + 4) + 50) @(posedge clk);
cap_armed = 1'b0;
for (int y = 0; y < V_ACTIVE; y++) begin
for (int x = 0; x < H_ACTIVE; x++) begin
int q;
logic [7:0] exp_r_q, exp_g_q, exp_b_q;
q = quadrant_idx(x, y);
exp_r_q = expected_r(q);
exp_g_q = expected_g(q);
exp_b_q = expected_b(q);
if (!cap_de[y][x]) begin
$error("[scanout] (%0d,%0d) not captured (cap_de=0)", x, y);
errors = errors + 1;
end else if ((cap_r[y][x] !== exp_r_q) ||
(cap_g[y][x] !== exp_g_q) ||
(cap_b[y][x] !== exp_b_q)) begin
$error("[scanout] (%0d,%0d) got rgb=(0x%02x,0x%02x,0x%02x) expected (0x%02x,0x%02x,0x%02x) sprite=%0d",
x, y,
cap_r[y][x], cap_g[y][x], cap_b[y][x],
exp_r_q, exp_g_q, exp_b_q, q);
errors = errors + 1;
end
end
end
// Status bundle: core_halt + dma_done_seen latched.
if (!core_halt) begin
$error("core_halt low at end of test");
errors = errors + 1;
end
if (!dma_done_seen) begin
$error("dma_done_seen never latched");
errors = errors + 1;
end
if (!frame_seen) begin
$error("frame_seen never latched (PCRTC end-of-frame not observed)");
errors = errors + 1;
end
$display("[tb_top_psmct32_raster_demo_bram] core_halt=%0b dma_done_seen=%0b frame_seen=%0b errors=%0d",
core_halt, dma_done_seen, frame_seen, errors);
if (errors == 0) $display("[tb_top_psmct32_raster_demo_bram] PASS");
else $display("[tb_top_psmct32_raster_demo_bram] FAIL");
$finish;
end
initial begin
#20000000;
$error("[tb_top_psmct32_raster_demo_bram] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_raster_demo_bram
sim/tb/top/tb_top_psmct32_raster_demo_bram_ch171.sv
+456
View File
@@ -0,0 +1,456 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo_bram_ch171
//
// Spot-check TB for the Ch251 320x240 animated demo (was Ch171 four-
// quadrant pre-Ch251 — the TB name is kept to avoid Makefile churn,
// but the assertions track the Ch251 SPRITE layout instead).
//
// Instantiates top_psmct32_raster_demo_bram with the board-wrapper
// overrides (H_ACTIVE=640 / V_ACTIVE=480, VRAM_BYTES=512 KiB) so the
// full 640x480 scanout is exercised, with the Ch251 fixtures painting
// the 320x240 demo content in the upper-left:
//
// - 8 vertical color bars (40 px wide each, full screen height)
// - 4 grey border strips (4 px thick)
// - 4 orange corner-alignment markers (8x8)
// - 1 cyan/red heartbeat at (152..167, 112..127) — NOT probed here
// because its color toggles between two values as the EE bootlet's
// loop iterates. Pixel-level heartbeat behavior is observed
// visually on hardware; this TB cares about the static portion.
//
// Probed coordinates (all outside the heartbeat box):
//
// Bar centers — bar index = x/40:
// ( 20, 80) bar 0 white
// ( 60, 80) bar 1 yellow
// (100, 80) bar 2 cyan
// (220, 80) bar 5 red
// (260, 80) bar 6 blue
// (300, 80) bar 7 black
// Border (mid-edge, non-corner):
// (160, 2) top grey
// (160, 237) bottom grey
// Corner markers:
// ( 4, 4) TL orange
// (315, 4) TR orange
// Outside DISPLAY1 (VRAM-side zero):
// (400, 100)
// (100, 300)
//
// VRAM contents are probed via hierarchical reference into dut.u_vram.mem;
// scanout pixels are captured into per-coord latches as r/g/b/de samples
// land on the wire.
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo_bram_ch171;
// Match the board-wrapper Ch169 + Ch171 overrides.
localparam int H_ACTIVE = 640;
localparam int V_ACTIVE = 480;
localparam int H_FRONT = 16;
localparam int H_SYNC_W = 96;
localparam int H_BACK = 48;
localparam int V_FRONT = 10;
localparam int V_SYNC_W = 2;
localparam int V_BACK = 33;
localparam int VRAM_BYTES = 512 * 1024;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
// Ch255 — heartbeat color override inputs (Sony ○ = A, × = B
// bits on INPUT_P1_RAW). Default 0 so the existing heartbeat /
// pixel-pattern assertions below see the EE-driven cyan.
logic joy_a_pressed;
logic joy_b_pressed;
initial begin
joy_a_pressed = 1'b0;
joy_b_pressed = 1'b0;
end
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.H_FRONT (H_FRONT),
.H_SYNC (H_SYNC_W),
.H_BACK (H_BACK),
.V_FRONT (V_FRONT),
.V_SYNC (V_SYNC_W),
.V_BACK (V_BACK),
.VRAM_BYTES (VRAM_BYTES),
// Ch252 — mirror the hardware build profile: 512 KiB VRAM
// with ENABLE_READ2=0. The PSMCT32-only demo never consults
// read2, so disabling it both keeps the integration test
// faithful to silicon and clears the Ch252 replication-
// tripwire ($fatal) inside `vram_bram_stub`. PSMT4 RMW
// coverage continues to live in the dedicated PSMT4 TBs at
// the default (small VRAM_BYTES, ENABLE_READ2=1).
.VRAM_ENABLE_READ2 (1'b0),
// Ch296 — mirror the hardware build's useg-shadow strip. This TB
// is the bram-top integration check that proves the board config
// (USEG_SHADOW_ENABLE=0) renders the PSMCT32 raster demo
// correctly with the ~33k-FF useg_shadow_mem array removed. The
// SPRITE-only bootlet issues no useg traffic, so the strip is a
// no-op for the rendered output.
.USEG_SHADOW_ENABLE (1'b0)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.joy_a_pressed_i(joy_a_pressed),
.joy_b_pressed_i(joy_b_pressed)
);
// ----------------------------------------------------------
// Expected pixel color (matches build_ch251_sprites() in bake.py).
// See module-header comment for the SPRITE layout summary.
// Outside (any x>=320 or y>=240): black.
// ----------------------------------------------------------
// ----------------------------------------------------------
// Ch251 expected ABGR pattern. Painting order is bottom-up
// (later SPRITEs win): 8 color bars (full screen) → 4 grey
// border strips (4 px thick, x∈[0,3]/[316,319] and y∈[0,3]/
// [236,239]) → 4 orange corner markers (8×8 squares at the
// four corners) → 1 cyan-initially heartbeat at (152..167,
// 112..127). Outside DISPLAY1 (x>=320 or y>=240) = black.
//
// The TB samples non-heartbeat coordinates so the result is
// independent of how many loop iterations the bootlet has
// executed when we probe VRAM.
// ----------------------------------------------------------
localparam int BORDER_W = 4;
localparam int CORNER_S = 8;
function automatic logic ch251_in_corner(input int x, input int y);
return ((x < CORNER_S && y < CORNER_S) ||
(x >= 320 - CORNER_S && y < CORNER_S) ||
(x < CORNER_S && y >= 240 - CORNER_S) ||
(x >= 320 - CORNER_S && y >= 240 - CORNER_S));
endfunction
function automatic logic ch251_in_border(input int x, input int y);
return (x < BORDER_W) || (x >= 320 - BORDER_W)
|| (y < BORDER_W) || (y >= 240 - BORDER_W);
endfunction
// 8 color bars (matches build_ch251_sprites() in bake.py).
function automatic logic [7:0] ch251_bar_r(input int bar);
case (bar)
0: return 8'hFF; 1: return 8'hFF; 2: return 8'h00; 3: return 8'h00;
4: return 8'hFF; 5: return 8'hFF; 6: return 8'h00; default: return 8'h00;
endcase
endfunction
function automatic logic [7:0] ch251_bar_g(input int bar);
case (bar)
0: return 8'hFF; 1: return 8'hFF; 2: return 8'hFF; 3: return 8'hFF;
4: return 8'h00; 5: return 8'h00; 6: return 8'h00; default: return 8'h00;
endcase
endfunction
function automatic logic [7:0] ch251_bar_b(input int bar);
case (bar)
0: return 8'hFF; 1: return 8'h00; 2: return 8'hFF; 3: return 8'h00;
4: return 8'hFF; 5: return 8'h00; 6: return 8'hFF; default: return 8'h00;
endcase
endfunction
function automatic logic [7:0] expected_r_at(input int x, input int y);
if (x >= 320 || y >= 240) return 8'h00; // outside DISPLAY1
if (ch251_in_corner(x, y)) return 8'hFF; // orange (R=FF)
if (ch251_in_border(x, y)) return 8'h80; // grey
return ch251_bar_r(x / 40);
endfunction
function automatic logic [7:0] expected_g_at(input int x, input int y);
if (x >= 320 || y >= 240) return 8'h00;
if (ch251_in_corner(x, y)) return 8'h80; // orange (G=80)
if (ch251_in_border(x, y)) return 8'h80; // grey
return ch251_bar_g(x / 40);
endfunction
function automatic logic [7:0] expected_b_at(input int x, input int y);
if (x >= 320 || y >= 240) return 8'h00;
if (ch251_in_corner(x, y)) return 8'h00; // orange (B=00)
if (ch251_in_border(x, y)) return 8'h80; // grey
return ch251_bar_b(x / 40);
endfunction
// ABGR word stored in VRAM: {A, B, G, R}. ABGR is what
// gs_stub raster channel writes; PCRTC then re-decodes
// back to r/g/b on scanout.
function automatic logic [31:0] expected_vram_at(input int x, input int y);
return {8'hFF, expected_b_at(x, y), expected_g_at(x, y), expected_r_at(x, y)};
endfunction
// ----------------------------------------------------------
// PSMCT32 swizzle reference (page/block walk per real PS2 GS
// semantics). Same shape as Ch155/Ch158 — refactored verbatim
// so this TB can probe VRAM by (x, y) at the Ch171 320x240
// pattern. fbp=0, fbw=1 from the Ch171 bake.
// ----------------------------------------------------------
function automatic int ref_block_idx_ct32(input int by, input int bx);
case ({by[1:0], bx[2:0]})
5'd0: return 0; 5'd1: return 1; 5'd2: return 4; 5'd3: return 5;
5'd4: return 16; 5'd5: return 17; 5'd6: return 20; 5'd7: return 21;
5'd8: return 2; 5'd9: return 3; 5'd10: return 6; 5'd11: return 7;
5'd12: return 18; 5'd13: return 19; 5'd14: return 22; 5'd15: return 23;
5'd16: return 8; 5'd17: return 9; 5'd18: return 12; 5'd19: return 13;
5'd20: return 24; 5'd21: return 25; 5'd22: return 28; 5'd23: return 29;
5'd24: return 10; 5'd25: return 11; 5'd26: return 14; 5'd27: return 15;
5'd28: return 26; 5'd29: return 27; 5'd30: return 30; default: return 31;
endcase
endfunction
function automatic int ref_addr_psmct32(input int x_v, input int y_v);
// fbp=0, fbw=5 — matches Ch171 bake.py DISPFB1 / FRAME_1 (320-wide
// framebuffer = 5 pages of 64 px). The Ch171 first-board-test bug
// was an FBW=1 mismatch here AND in bake.py; both ends agreed
// (so this TB happily passed) but the resulting page layout
// wrapped horizontally every 64 px on the monitor → visible
// staircase. With FBW=5, raster + scanout + this reference all
// agree on the spatial-correct 320-wide page grid.
int page_x, page_y, page_idx, page_base;
int by, bx, blk_idx, xb, yb;
page_x = x_v / 64;
page_y = y_v / 32;
page_idx = page_y * 5 + page_x; // fbw=5
page_base = page_idx * 8192;
by = (y_v % 32) / 8;
bx = (x_v % 64) / 8;
blk_idx = ref_block_idx_ct32(by, bx);
xb = x_v % 8;
yb = y_v % 8;
return page_base + blk_idx * 256 + yb * 32 + xb * 4;
endfunction
// ----------------------------------------------------------
// Scanout capture latches. Rather than a 640x480 array (≈300K
// entries — bloats sim memory), keep a small list of probe
// coordinates and latch r/g/b/de whenever the scanout
// (hcnt, vcnt) hits one of them.
// ----------------------------------------------------------
// VRAM probe (x, y) table — inside the 320x240 paint region.
// Initialized in `initial begin` below (iverilog 12 doesn't
// accept '{...} array literals on unpacked arrays).
//
// Ch171 board-iter-2 audit: previous probe set only sampled Q3
// center. When hardware showed Q3 missing (black instead of
// white), tightening this with Q3-corner probes was the first
// diagnostic — if sim PASSES every Q3 corner but hardware
// still drops it, the divergence is in BRAM/scanout/PCRTC
// hardware behavior (not the GS raster path).
localparam int N_PROBES = 10;
int probe_x [N_PROBES];
int probe_y [N_PROBES];
// Ch251 probe set — sample non-heartbeat coordinates so the
// assertions are stable regardless of bootlet loop iteration.
// Heartbeat sits at (152..167, 112..127); everything below
// avoids that box.
initial begin
// Bar centers (y=80 picked to dodge top border / corner markers)
probe_x[0] = 20; probe_y[0] = 80; // bar 0 white
probe_x[1] = 60; probe_y[1] = 80; // bar 1 yellow
probe_x[2] = 100; probe_y[2] = 80; // bar 2 cyan
probe_x[3] = 220; probe_y[3] = 80; // bar 5 red
probe_x[4] = 260; probe_y[4] = 80; // bar 6 blue
probe_x[5] = 300; probe_y[5] = 80; // bar 7 black
// Border samples (non-corner)
probe_x[6] = 160; probe_y[6] = 2; // top border, mid
probe_x[7] = 160; probe_y[7] = 237; // bottom border, mid
// Corner markers
probe_x[8] = 4; probe_y[8] = 4; // TL corner (orange)
probe_x[9] = 315; probe_y[9] = 4; // TR corner (orange)
// Outside-DISPLAY1 VRAM probes were dropped: PSMCT32 page
// swizzling at FBW=5 aliases x>=320 reads back into the
// active framebuffer (so VRAM at e.g. (400,100) reads the
// heartbeat byte, not the "unwritten zero" the naive
// address math would suggest). The active area is the
// demo content; outside-DISPLAY1 black is a PCRTC scanout
// property, tested implicitly by the scanout latches —
// the per-pixel scanout-side assertions of the Ch171
// original aren't in scope for Ch251's spot-check.
end
int errors;
initial errors = 0;
// Module-scope locals for the probe loop (hoisted out of the
// `for` body to dodge an iverilog 12 declaration-with-initializer
// mis-elaboration that silently zeroed loop-local ints).
int probe_loop_x;
int probe_loop_y;
int probe_loop_byte_addr;
logic [31:0] probe_loop_expected;
logic [31:0] probe_loop_got;
// Ch255 — snapshot of the EE-driven hb_rgbaq_reg taken just
// before the override sweep so XOR / passthrough assertions can
// reference a stable value.
logic [31:0] ch255_baseline;
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (10) @(posedge clk);
rst_n = 1'b1;
repeat (4) @(posedge clk);
@(negedge clk); core_go = 1'b1;
@(negedge clk); core_go = 1'b0;
// Ch251 — wait for the FIRST DMAC drain + raster idle. The
// animated bootlet loops forever, so we don't gate on
// core_halt anymore. Frame heartbeat checks (Ch251 motion
// proof) live in tb_de25_nano_psmct32_raster_demo_top; this
// TB is the pixel-pattern spot-check.
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1) wait (dut.xfer_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1) wait (dut.u_gs.raster_active == 1'b0);
repeat (40) @(posedge clk);
// -----------------------------------------------------
// VRAM probe spot-checks. ABGR-word-in-VRAM is what the
// raster sink stores. Sampling here proves the entire
// GS path is alive (DMAC → GIF → raster → VRAM) at the
// probe coordinates. The "rest of screen is black" check
// belongs on hardware (it's a PCRTC scanout-side
// property gated by DISPLAY1, not a VRAM-side property).
// -----------------------------------------------------
// Probe loop. Hoisted local int decls to module scope so
// iverilog 12 doesn't silently zero them per-iteration
// (declarations-with-initializers inside for-loop bodies
// mis-elaborate in this tool version; the silent-zero made
// the TB a false-positive for Q3 probes until caught).
for (int i = 0; i < N_PROBES; i++) begin
probe_loop_x = probe_x[i];
probe_loop_y = probe_y[i];
probe_loop_byte_addr = ref_addr_psmct32(probe_loop_x, probe_loop_y);
probe_loop_expected = expected_vram_at(probe_loop_x, probe_loop_y);
probe_loop_got = dut.u_vram.mem[probe_loop_byte_addr >> 2];
if (probe_loop_got !== probe_loop_expected) begin
$error("[vram] probe[%0d] @(%0d,%0d) got 0x%08x expected 0x%08x",
i, probe_loop_x, probe_loop_y,
probe_loop_got, probe_loop_expected);
errors = errors + 1;
end
end
// Status latches. Ch251: core_halt is EXPECTED LOW (bootlet
// loops forever). dma_done_seen + frame_seen prove the
// demo's GIF/raster pipeline is alive.
if (core_halt) begin $error("core_halt high at end (Ch251 bootlet must loop, not SYSCALL)"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
// ----------------------------------------------------------
// Ch251 — verify the initial DMAC kick painted the heartbeat
// RGBAQ qword with CYAN. The bootlet then animates this via
// XOR + SW between CYAN and RED in its main loop; with the
// production-grade delay (~1 Hz at 50 MHz hardware) catching
// a toggle in sim would need >30 s sim time, so we only
// sample the first-kick state here. The dynamic blink is
// a hardware-monitor proof, not a sim regression.
// ----------------------------------------------------------
if (dut.u_ram.mem[115][31:0] !== 32'hFFFFFF00) begin
$error("heartbeat RGBAQ qword[115][31:0] = 0x%08x at first-DMAC-done (expected 0xFFFFFF00 CYAN from bake.py)",
dut.u_ram.mem[115][31:0]);
errors = errors + 1;
end
// ----------------------------------------------------------
// Ch255 — exercise the wrapper-side heartbeat override mux.
// The mux feeds the splicer (which only fires when DMAC reads
// qword 115); to keep the test fast and deterministic we
// probe the combinational `hb_rgbaq_effective` wire directly
// for each of the four {joy_a, joy_b} input combinations.
// We also re-check `hb_rgbaq_reg` after each step to confirm
// the override does NOT corrupt the EE-driven background
// animation (the EE keeps owning hb_rgbaq_reg via SW writes).
// ----------------------------------------------------------
// Snapshot the current EE-driven value so the XOR check uses
// the actual reg state rather than the bake.py initial. The
// bootlet may have toggled it by now.
ch255_baseline = dut.hb_rgbaq_reg;
// {A=0, B=0} → mux passes hb_rgbaq_reg through.
joy_a_pressed = 1'b0;
joy_b_pressed = 1'b0;
@(negedge clk);
if (dut.hb_rgbaq_effective !== ch255_baseline) begin
$error("[Ch255 override] {A=0,B=0}: hb_rgbaq_effective=0x%08x expected baseline 0x%08x",
dut.hb_rgbaq_effective, ch255_baseline);
errors = errors + 1;
end
// {A=1, B=0} → force RED.
joy_a_pressed = 1'b1;
joy_b_pressed = 1'b0;
@(negedge clk);
if (dut.hb_rgbaq_effective !== 32'hFF00_00FF) begin
$error("[Ch255 override] {A=1,B=0}: hb_rgbaq_effective=0x%08x expected 0xFF0000FF (RED)",
dut.hb_rgbaq_effective);
errors = errors + 1;
end
if (dut.hb_rgbaq_reg !== ch255_baseline) begin
$error("[Ch255 override] {A=1,B=0}: hb_rgbaq_reg corrupted from 0x%08x to 0x%08x",
ch255_baseline, dut.hb_rgbaq_reg);
errors = errors + 1;
end
// {A=0, B=1} → force CYAN.
joy_a_pressed = 1'b0;
joy_b_pressed = 1'b1;
@(negedge clk);
if (dut.hb_rgbaq_effective !== 32'hFFFF_FF00) begin
$error("[Ch255 override] {A=0,B=1}: hb_rgbaq_effective=0x%08x expected 0xFFFFFF00 (CYAN)",
dut.hb_rgbaq_effective);
errors = errors + 1;
end
// {A=1, B=1} → invert (XOR with 0x00FFFFFF) of the live
// EE-driven value at THIS moment.
joy_a_pressed = 1'b1;
joy_b_pressed = 1'b1;
@(negedge clk);
if (dut.hb_rgbaq_effective !== (dut.hb_rgbaq_reg ^ 32'h00FF_FFFF)) begin
$error("[Ch255 override] {A=1,B=1}: hb_rgbaq_effective=0x%08x expected 0x%08x (XOR of hb_rgbaq_reg=0x%08x)",
dut.hb_rgbaq_effective,
dut.hb_rgbaq_reg ^ 32'h00FF_FFFF,
dut.hb_rgbaq_reg);
errors = errors + 1;
end
// Release — mux returns to passthrough.
joy_a_pressed = 1'b0;
joy_b_pressed = 1'b0;
@(negedge clk);
if (dut.hb_rgbaq_effective !== dut.hb_rgbaq_reg) begin
$error("[Ch255 override] release: hb_rgbaq_effective=0x%08x expected hb_rgbaq_reg=0x%08x",
dut.hb_rgbaq_effective, dut.hb_rgbaq_reg);
errors = errors + 1;
end
$display("[tb_top_psmct32_raster_demo_bram_ch171] errors=%0d", errors);
if (errors == 0) $display("[tb_top_psmct32_raster_demo_bram_ch171] PASS");
else $display("[tb_top_psmct32_raster_demo_bram_ch171] FAIL");
$finish;
end
// Watchdog — generous because we sit through a full 640×480 frame.
initial begin
#30_000_000;
$error("[tb_top_psmct32_raster_demo_bram_ch171] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_raster_demo_bram_ch171
sim/tb/top/tb_top_psmct32_raster_demo_bram_clut.sv
+231
View File
@@ -0,0 +1,231 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo_bram_clut (Ch296)
//
// TOP-LEVEL PSMT8 INDEXED-TEXTURE + CLUT demo for the BRAM BOARD VARIANT
// (the variant the de25_nano board top instantiates). Proves the
// PALETTIZED texture path renders end-to-end through
// top_psmct32_raster_demo_bram exactly as a board load would:
//
// GIF payload (payload_clut.mem) — NO new EE/BIOS scaffolding:
// U1 BITBLT -> uploads the CLUT (8 PSMCT32 palette entries) to VRAM
// U2 BITBLT -> uploads an 8x8 PSMT8 texture (an array of INDICES)
// U3 PRIM(SPRITE+TME) + TEX0(PSM=PSMT8, CLD=1 -> VRAM->CLUT load)
// + UV/XYZ2: a PSMT8-textured 8x8 sprite at (0,0)..(7,7)
// U5 PACKED -> a FLAT green control sprite at (8,0)..(15,7)
//
// On TEX0 commit, clut_loader_stub copies the CLUT from VRAM into
// clut_stub. During the raster scan the texel fetch reads an 8-bit
// INDEX from VRAM and gs_stub looks it up in clut_stub -> PSMCT32
// color (DECAL). A PASS here means the board would SHOW the indexed
// texture, with each index mapped through the palette.
//
// Expected (mirrors bake.py clut8_index + clut8_palette):
// index(x,y): framed 'X' -> 0=corner(0,0), 1=border, 3=both diagonals,
// 2=interior.
// palette: 0=black 1=RED 2=GREEN 3=BLUE. PCRTC PSMCT32 ->
// r=color[7:0] g=color[15:8] b=color[23:16].
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo_bram_clut;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
localparam int TEXW = 8;
localparam int TEXH = 8;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.PSMCT32_SWIZZLE(1'b0)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// ----- expected index + palette (mirrors bake.py) -----
function automatic int idx(input int x, input int y);
if (x == 0 && y == 0) return 0;
if (x == y || x == (TEXW - 1 - y)) return 3;
if (x == 0 || y == 0 || x == TEXW-1 || y == TEXH-1) return 1;
return 2;
endfunction
function automatic logic [7:0] pal_r(input int i);
case (i) 0: return 8'h00; 1: return 8'hFF; 2: return 8'h00; 3: return 8'h00; default: return 8'h7F; endcase
endfunction
function automatic logic [7:0] pal_g(input int i);
case (i) 0: return 8'h00; 1: return 8'h00; 2: return 8'hFF; 3: return 8'h00; default: return 8'h7F; endcase
endfunction
function automatic logic [7:0] pal_b(input int i);
case (i) 0: return 8'h00; 1: return 8'h00; 2: return 8'h00; 3: return 8'hFF; default: return 8'h7F; endcase
endfunction
localparam logic [7:0] FLAT_R = 8'h20;
localparam logic [7:0] FLAT_G = 8'hC0;
localparam logic [7:0] FLAT_B = 8'h40;
// ----- frame capture (VRAM_SYNC_READ=1 -> delayed counters) -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 0; cap_g[y][x] = 0; cap_b[y][x] = 0; cap_de[y][x] = 0;
end
capture_armed = 1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d <= 0; vcnt_d <= 0; end
else begin hcnt_d <= 32'(dut.u_pcrtc.hcnt); vcnt_d <= 32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
int errors;
int tex_pixels_ok;
int distinct_colors;
initial begin errors = 0; tex_pixels_ok = 0; distinct_colors = 0; end
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk); core_go = 1'b1;
@(negedge clk); core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1) wait (dut.xfer_busy == 1'b0);
if (dut.clut_ld_busy == 1'b1) wait (dut.clut_ld_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1) wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// --- PSMT8 indexed-textured region (x in [0..7]): each pixel is
// palette[index(x,y)]. ---
for (int y = 0; y < TEXH; y++) begin
for (int x = 0; x < TEXW; x++) begin
logic [7:0] er, eg, eb;
int i;
i = idx(x, y);
er = pal_r(i); eg = pal_g(i); eb = pal_b(i);
if (!cap_de[y][x]) begin
$error("indexed (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
$error("[indexed] (%0d,%0d) idx=%0d got (%02x,%02x,%02x) exp (%02x,%02x,%02x)",
x, y, i, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb);
errors = errors + 1;
end else begin
tex_pixels_ok = tex_pixels_ok + 1;
end
end
end
// --- the indexed region must use multiple distinct palette
// colors (proves the CLUT indirection produced real variety,
// not a flat fill). Count distinct R+G+B keys in row of x. ---
begin
logic [23:0] seen [0:7];
int n;
n = 0;
for (int y = 0; y < TEXH; y++)
for (int x = 0; x < TEXW; x++) begin
logic [23:0] key;
bit found;
key = {cap_b[y][x], cap_g[y][x], cap_r[y][x]};
found = 1'b0;
for (int k = 0; k < n; k++) if (seen[k] === key) found = 1'b1;
if (!found && n < 8) begin seen[n] = key; n = n + 1; end
end
distinct_colors = n;
if (distinct_colors < 3) begin
$error("indexed region shows only %0d distinct colors — CLUT indirection collapsed",
distinct_colors);
errors = errors + 1;
end
end
// --- flat control region (x in [8..15]) ---
for (int y = 0; y < TEXH; y++) begin
for (int x = 8; x < 16; x++) begin
if (!cap_de[y][x]) begin
$error("flat (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== FLAT_R || cap_g[y][x] !== FLAT_G || cap_b[y][x] !== FLAT_B) begin
$error("[flat] (%0d,%0d) got (%02x,%02x,%02x) exp (%02x,%02x,%02x)",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], FLAT_R, FLAT_G, FLAT_B);
errors = errors + 1;
end
end
end
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_raster_demo_bram_clut] idx_ok=%0d/64 distinct_colors=%0d raster_emits=%0d errors=%0d",
tex_pixels_ok, distinct_colors,
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_raster_demo_bram_clut] PASS");
else
$display("[tb_top_psmct32_raster_demo_bram_clut] FAIL");
$finish;
end
initial begin
#20000000;
$error("[tb_top_psmct32_raster_demo_bram_clut] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_raster_demo_bram_clut
sim/tb/top/tb_top_psmct32_raster_demo_bram_clut4.sv
+245
View File
@@ -0,0 +1,245 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo_bram_clut4 (Ch297)
//
// TOP-LEVEL PSMT4 INDEXED-TEXTURE + CLUT demo for the BRAM BOARD VARIANT
// (the variant the de25_nano board top instantiates). Proves the 4-bit
// PALETTIZED texture path — the MOST common PS2 texture format — renders
// end-to-end through top_psmct32_raster_demo_bram exactly as a board load
// would, built directly on the Ch296 PSMT8+CLUT rung (only NEW datapath
// bit: the nibble extract in gs_texture_unit).
//
// GIF payload (payload_clut4.mem) — NO new EE/BIOS scaffolding:
// U1 BITBLT -> uploads the 16-entry CLUT (PSMCT32 palette) to VRAM
// U2 BITBLT -> uploads an 8x8 PSMT4 texture (2 indices/byte)
// U3 PRIM(SPRITE+TME) + TEX0(PSM=PSMT4, CLD=1 -> VRAM->CLUT load)
// + UV/XYZ2: a PSMT4-textured 8x8 sprite at (0,0)..(7,7)
// U5 PACKED -> a FLAT green control sprite at (8,0)..(15,7)
//
// On TEX0 commit, clut_loader_stub copies the CLUT from VRAM into
// clut_stub. During the raster scan the texel fetch reads a 4-bit
// INDEX (the right NIBBLE of the fetched byte) from VRAM and gs_stub
// looks it up in clut_stub -> PSMCT32 color (DECAL). A PASS means the
// board would SHOW the indexed texture with all 16 palette entries.
//
// Expected (mirrors bake.py clut4_index + clut4_palette):
// index(x,y) = (x + 2*y) mod 16 (a diagonal ramp through ALL 16).
// palette: 16 boldly distinct PSMCT32 entries. PCRTC PSMCT32 ->
// r=color[7:0] g=color[15:8] b=color[23:16].
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo_bram_clut4;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
localparam int TEXW = 8;
localparam int TEXH = 8;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.PSMCT32_SWIZZLE(1'b0)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// ----- expected index + 16-entry palette (mirrors bake.py) -----
function automatic int idx(input int x, input int y);
return (x + 2*y) % 16;
endfunction
function automatic logic [7:0] pal_r(input int i);
case (i)
0: return 8'h00; 1: return 8'hFF; 2: return 8'h00; 3: return 8'h00;
4: return 8'hFF; 5: return 8'hFF; 6: return 8'h00; 7: return 8'hFF;
8: return 8'h80; 9: return 8'h00; 10: return 8'h00; 11: return 8'h80;
12: return 8'h80; 13: return 8'h00; 14: return 8'hC0; default: return 8'h40;
endcase
endfunction
function automatic logic [7:0] pal_g(input int i);
case (i)
0: return 8'h00; 1: return 8'h00; 2: return 8'hFF; 3: return 8'h00;
4: return 8'hFF; 5: return 8'h00; 6: return 8'hFF; 7: return 8'hFF;
8: return 8'h00; 9: return 8'h80; 10: return 8'h00; 11: return 8'h80;
12: return 8'h00; 13: return 8'h80; 14: return 8'h60; default: return 8'h40;
endcase
endfunction
function automatic logic [7:0] pal_b(input int i);
case (i)
0: return 8'h00; 1: return 8'h00; 2: return 8'h00; 3: return 8'hFF;
4: return 8'h00; 5: return 8'hFF; 6: return 8'hFF; 7: return 8'hFF;
8: return 8'h00; 9: return 8'h00; 10: return 8'h80; 11: return 8'h00;
12: return 8'h80; 13: return 8'h80; 14: return 8'h20; default: return 8'h40;
endcase
endfunction
localparam logic [7:0] FLAT_R = 8'h20;
localparam logic [7:0] FLAT_G = 8'hC0;
localparam logic [7:0] FLAT_B = 8'h40;
// ----- frame capture (VRAM_SYNC_READ=1 -> delayed counters) -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 0; cap_g[y][x] = 0; cap_b[y][x] = 0; cap_de[y][x] = 0;
end
capture_armed = 1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d <= 0; vcnt_d <= 0; end
else begin hcnt_d <= 32'(dut.u_pcrtc.hcnt); vcnt_d <= 32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
int errors;
int tex_pixels_ok;
int distinct_colors;
initial begin errors = 0; tex_pixels_ok = 0; distinct_colors = 0; end
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk); core_go = 1'b1;
@(negedge clk); core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1) wait (dut.xfer_busy == 1'b0);
if (dut.clut_ld_busy == 1'b1) wait (dut.clut_ld_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1) wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// --- PSMT4 indexed-textured region (x in [0..7]): each pixel is
// palette[index(x,y)] with index = (x+2y) mod 16. ---
for (int y = 0; y < TEXH; y++) begin
for (int x = 0; x < TEXW; x++) begin
logic [7:0] er, eg, eb;
int i;
i = idx(x, y);
er = pal_r(i); eg = pal_g(i); eb = pal_b(i);
if (!cap_de[y][x]) begin
$error("indexed (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
$error("[indexed] (%0d,%0d) idx=%0d got (%02x,%02x,%02x) exp (%02x,%02x,%02x)",
x, y, i, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb);
errors = errors + 1;
end else begin
tex_pixels_ok = tex_pixels_ok + 1;
end
end
end
// --- the indexed region must use MANY distinct palette colors
// (proves the 16-entry CLUT indirection + nibble select
// produced real variety, not a stuck nibble). The ramp over
// an 8x8 region with idx=(x+2y)%16 spans all 16 entries. ---
begin
logic [23:0] seen [0:15];
int n;
n = 0;
for (int y = 0; y < TEXH; y++)
for (int x = 0; x < TEXW; x++) begin
logic [23:0] key;
bit found;
key = {cap_b[y][x], cap_g[y][x], cap_r[y][x]};
found = 1'b0;
for (int k = 0; k < n; k++) if (seen[k] === key) found = 1'b1;
if (!found && n < 16) begin seen[n] = key; n = n + 1; end
end
distinct_colors = n;
if (distinct_colors < 8) begin
$error("indexed region shows only %0d distinct colors — nibble/CLUT collapsed",
distinct_colors);
errors = errors + 1;
end
end
// --- flat control region (x in [8..15]) ---
for (int y = 0; y < TEXH; y++) begin
for (int x = 8; x < 16; x++) begin
if (!cap_de[y][x]) begin
$error("flat (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== FLAT_R || cap_g[y][x] !== FLAT_G || cap_b[y][x] !== FLAT_B) begin
$error("[flat] (%0d,%0d) got (%02x,%02x,%02x) exp (%02x,%02x,%02x)",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], FLAT_R, FLAT_G, FLAT_B);
errors = errors + 1;
end
end
end
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_raster_demo_bram_clut4] idx_ok=%0d/64 distinct_colors=%0d raster_emits=%0d errors=%0d",
tex_pixels_ok, distinct_colors,
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_raster_demo_bram_clut4] PASS");
else
$display("[tb_top_psmct32_raster_demo_bram_clut4] FAIL");
$finish;
end
initial begin
#20000000;
$error("[tb_top_psmct32_raster_demo_bram_clut4] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_raster_demo_bram_clut4
sim/tb/top/tb_top_psmct32_raster_demo_bram_lpddrtex.sv
+247
View File
@@ -0,0 +1,247 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo_bram_lpddrtex (Ch322 Brick 2)
//
// END-TO-END proof of the PREFILLED LPDDR texture cache: the SAME textured
// triangle as tb_top_psmct32_raster_demo_bram_tritex, but with GS_LPDDR_TEX=1
// so the texel-fetch port is muxed to gs_texture_cache, warmed from a behavioral
// LPDDR (EMIF-ish) read model BEFORE raster.
//
// STRONG PROOF: after the EE bootlet uploads the texture to VRAM, the TB CORRUPTS
// the VRAM texture region. The cache was already warmed from the (good) LPDDR
// model, so if the rendered triangle still shows the correct quadrant texels, the
// texels provably came from LPDDR through the cache — not from BRAM. Acceptance:
// - tex_cache_ready high BEFORE raster, fill_done, fill_beats=64, rd_errs=0
// - every interior pixel == the expected tex_demo_texel (matches BRAM ref)
// - >1 distinct colour (texturing not collapsed)
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo_bram_lpddrtex;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
// cache geometry: tritex texture is 8x8 PSMCT32, TBW=1 (64-texel/256-B row
// stride) at TBP0=8 -> VRAM byte base 2048. Addressed range spans 8 rows *
// 256 B = 2048 B = 64 single-beat (32 B) reads.
localparam [29:0] LPDDR_TEX_BASE = 30'h0010_0000;
localparam int TEX_VRAM_BASE = 2048;
localparam int TEX_BYTES = 2048;
localparam int N_BEATS = 64;
localparam int TEX_WORDS = TEX_BYTES/4; // 512
logic clk; logic rst_n;
initial clk = 1'b0; always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
// bram-top <-> texture-cache tap
logic gs_tex_rd_en_o;
logic [31:0] gs_tex_rd_addr_o;
logic [31:0] tex_cache_data;
logic tex_cache_ready;
logic [31:0] tex_cache_hits, tex_bram_hits; // Ch322 texel-source counters
// texture-cache AXI read channel <-> behavioral LPDDR model
logic [29:0] araddr; logic [1:0] arburst; logic [6:0] arid;
logic [7:0] arlen; logic [2:0] arsize; logic arvalid, arready;
logic [255:0] rdata; logic [1:0] rresp; logic rlast, rvalid, rready;
logic fill_start, fill_done;
logic [31:0] fill_beats, fill_bytes, tex_rd_errs;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE), .PSMCT32_SWIZZLE(1'b0),
.GS_LPDDR_TEX(1'b1), .TEX_VRAM_BASE(TEX_VRAM_BASE), .TEX_CACHE_BYTES(TEX_BYTES)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen), .frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.gs_tex_rd_en_o(gs_tex_rd_en_o), .gs_tex_rd_addr_o(gs_tex_rd_addr_o),
.tex_cache_data_i(tex_cache_data), .tex_cache_ready_i(tex_cache_ready),
.tex_cache_hits_o(tex_cache_hits), .tex_bram_hits_o(tex_bram_hits)
);
gs_texture_cache #(
.LPDDR_TEX_BASE(LPDDR_TEX_BASE), .TEX_VRAM_BASE(TEX_VRAM_BASE),
.TEX_BYTES(TEX_BYTES), .N_BEATS(N_BEATS)
) u_cache (
.axi_clk(clk), .axi_rst_n(rst_n),
.fill_start(fill_start), .fill_done(fill_done),
.fill_beats(fill_beats), .fill_bytes(fill_bytes), .rd_errs(tex_rd_errs),
.araddr(araddr), .arburst(arburst), .arid(arid), .arlen(arlen),
.arsize(arsize), .arvalid(arvalid), .arready(arready),
.rdata(rdata), .rresp(rresp), .rlast(rlast), .rvalid(rvalid), .rready(rready),
.sample_clk(clk), .tex_rd_en(gs_tex_rd_en_o),
.tex_rd_addr(gs_tex_rd_addr_o), .tex_rd_data(tex_cache_data), .tex_ready(tex_cache_ready)
);
// tritex texel word (mirrors bake.py tex_demo_texel): ABGR, A=FF.
function automatic logic [31:0] texw(input int x, input int y);
logic [7:0] rr, gg, bb; logic lft, top;
lft = (x<4); top = (y<4);
if (top && lft) begin rr=8'hFF; gg=8'h00; bb=8'h00; end
else if (top && !lft) begin rr=8'h00; gg=8'hFF; bb=8'h00; end
else if (!top && lft) begin rr=8'h00; gg=8'h00; bb=8'hFF; end
else begin rr=8'hFF; gg=8'hFF; bb=8'h00; end
texw = {8'hFF, bb, gg, rr};
endfunction
// ---- behavioral LPDDR model: 512 words, sparse texel layout ----
// texel(u,v) lives at word (v*64+u) (= VRAM byte (base+(v*64+u)*4) >> 2).
logic [31:0] lpddr_mem [0:TEX_WORDS-1];
initial begin
for (int i=0; i<TEX_WORDS; i++) lpddr_mem[i] = 32'h0;
for (int v=0; v<8; v++)
for (int u=0; u<8; u++)
lpddr_mem[v*64 + u] = texw(u, v);
end
// single-beat (arlen=0) read model, a few cycles latency.
typedef enum logic [1:0] { S_IDLE, S_WAIT, S_DATA } sstate_t; sstate_t sst;
logic [3:0] dly; int beat_idx;
always_ff @(posedge clk) begin
if (!rst_n) begin
sst<=S_IDLE; arready<=0; rvalid<=0; rlast<=0; rresp<=2'b00; rdata<='0; dly<='0;
end else begin
arready<=0; rvalid<=0; rlast<=0;
case (sst)
S_IDLE: if (arvalid) begin
arready<=1; beat_idx<=(araddr-LPDDR_TEX_BASE)>>5; dly<=4'd3; sst<=S_WAIT;
end
S_WAIT: if (dly==0) sst<=S_DATA; else dly<=dly-1'b1;
S_DATA: if (rready) begin
for (int w=0; w<8; w++) rdata[w*32 +: 32] <= lpddr_mem[beat_idx*8 + w];
rresp<=2'b00; rvalid<=1; rlast<=1; sst<=S_IDLE;
end
endcase
end
end
// ----- reference: triangle interior + expected texel (UV==XY trick) -----
localparam int VX0=1, VY0=1, VX1=7, VY1=1, VX2=2, VY2=6;
int sx1, sy1, sx2, sy2;
function automatic int edge_f(input int px,py,ax,ay,bx,by);
return (px-ax)*(by-ay) - (py-ay)*(bx-ax); endfunction
function automatic bit tolr(input int ax,ay,bx,by);
int dx,dy; dx=bx-ax; dy=by-ay; return (dy>0)||((dy==0)&&(dx>0)); endfunction
task automatic setup_ref(); int sa;
sa=(VX1-VX0)*(VY2-VY0)-(VY1-VY0)*(VX2-VX0);
if (sa<0) begin sx1=VX2; sy1=VY2; sx2=VX1; sy2=VY1; end
else begin sx1=VX1; sy1=VY1; sx2=VX2; sy2=VY2; end endtask
function automatic bit ref_inside(input int px,py); int e0,e1,e2,b0,b1,b2;
e0=edge_f(px,py,VX0,VY0,sx1,sy1); e1=edge_f(px,py,sx1,sy1,sx2,sy2);
e2=edge_f(px,py,sx2,sy2,VX0,VY0);
b0=tolr(VX0,VY0,sx1,sy1)?0:1; b1=tolr(sx1,sy1,sx2,sy2)?0:1; b2=tolr(sx2,sy2,VX0,VY0)?0:1;
return ((e0+b0)<=0)&&((e1+b1)<=0)&&((e2+b2)<=0); endfunction
function automatic logic [7:0] tex_exp_r(input int x,y); return ((x<4)==(y<4))?8'hFF:8'h00; endfunction
function automatic logic [7:0] tex_exp_g(input int x,y); return (x>=4)?8'hFF:8'h00; endfunction
function automatic logic [7:0] tex_exp_b(input int x,y); return ((x<4)&&(y>=4))?8'hFF:8'h00; endfunction
// ----- frame capture (BRAM sync-read: index by delayed counters) -----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
logic [31:0] hcnt_d, vcnt_d;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
capture_armed=0;
end
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g;
cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, tex_pixels_ok, distinct_seen;
bit ready_before_raster;
initial begin
errors=0; tex_pixels_ok=0; distinct_seen=0; ready_before_raster=0;
setup_ref();
rst_n=0; core_go=0; fill_start=0;
repeat (4) @(posedge clk); rst_n=1; repeat (4) @(posedge clk);
// warm the cache FIRST, independent of the VRAM upload. fill_start is an EDGE/TOGGLE:
// flip it ONCE (and hold) to trigger a single fill — do NOT pulse 0->1->0, since the
// falling edge would trigger a second fill that races the ready check below.
@(posedge clk) fill_start<=1'b1;
begin int gd=0; while (!fill_done && gd<5000) begin @(posedge clk); gd++; end end
if (!fill_done) begin $error("cache fill_done never asserted"); errors++; end
if (fill_beats!==N_BEATS) begin $error("fill_beats=%0d exp %0d", fill_beats, N_BEATS); errors++; end
if (fill_bytes!==TEX_BYTES)begin $error("fill_bytes=%0d exp %0d", fill_bytes, TEX_BYTES); errors++; end
if (tex_rd_errs!==0) begin $error("tex_rd_errs=%0d exp 0", tex_rd_errs); errors++; end
// now start the EE bootlet (uploads texture to VRAM, then draws).
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen==1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// STRONG PROOF: corrupt the VRAM texture region now (upload done, before
// the raster reads texels). The cache holds the good texture from LPDDR;
// a correct render hereafter proves texels came from the cache, not BRAM.
ready_before_raster = tex_cache_ready; // must already be warm
if (!ready_before_raster) begin $error("cache not ready before raster"); errors++; end
for (int wi=0; wi<TEX_WORDS; wi++)
dut.u_vram.mem[(TEX_VRAM_BASE>>2) + wi] = 32'hDEAD_BEEF;
if (dut.u_gs.raster_active==1'b1) wait (dut.u_gs.raster_active==1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=0;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++)
if (ref_inside(x,y)) begin
logic [7:0] er,eg,eb; er=tex_exp_r(x,y); eg=tex_exp_g(x,y); eb=tex_exp_b(x,y);
if (!cap_de[y][x]) begin $error("(%0d,%0d) DE never asserted", x,y); errors++; end
else if (cap_r[y][x]!==er || cap_g[y][x]!==eg || cap_b[y][x]!==eb) begin
$error("[lpddrtex] (%0d,%0d) got (%02x,%02x,%02x) exp (%02x,%02x,%02x)",
x,y,cap_r[y][x],cap_g[y][x],cap_b[y][x],er,eg,eb); errors++;
end else tex_pixels_ok++;
end
begin logic [23:0] first; bit have; logic [23:0] px;
have=0; distinct_seen=1;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++)
if (ref_inside(x,y) && cap_de[y][x]) begin
px={cap_b[y][x],cap_g[y][x],cap_r[y][x]};
if (!have) begin first=px; have=1; end
else if (px!==first) distinct_seen=2;
end
end
// Ch322 — the texel-source counter must show the cache served the triangle's
// texels (and VRAM was corrupted, so BRAM fallback would have produced garbage).
if (tex_cache_hits == 32'd0) begin $error("tex_cache_hits=0 — cache served no texels"); errors++; end
$display("[lpddrtex] tex_cache_hits=%0d tex_bram_hits=%0d", tex_cache_hits, tex_bram_hits);
if (distinct_seen<2) begin $error("textured triangle uniform — texturing collapsed"); errors++; end
if (tex_pixels_ok<8) begin $error("too few interior textured px matched (%0d)", tex_pixels_ok); errors++; end
if (!core_halt) begin $error("core_halt low at end"); errors++; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors++; end
if (raster_overflow) begin $error("raster_overflow set"); errors++; end
$display("[lpddrtex] fill_done=%0d beats=%0d bytes=%0d rd_errs=%0d ready_pre_raster=%0d tex_ok=%0d distinct=%0d errors=%0d",
fill_done, fill_beats, fill_bytes, tex_rd_errs, ready_before_raster, tex_pixels_ok, distinct_seen, errors);
if (errors==0) $display("[tb_top_psmct32_raster_demo_bram_lpddrtex] PASS");
else $display("[tb_top_psmct32_raster_demo_bram_lpddrtex] FAIL");
$finish;
end
initial begin #20000000; $error("[tb_top_psmct32_raster_demo_bram_lpddrtex] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_raster_demo_bram_lpddrtex
sim/tb/top/tb_top_psmct32_raster_demo_bram_swz32.sv
+216
View File
@@ -0,0 +1,216 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo_bram_swz32 (Ch300)
//
// TOP-LEVEL SWIZZLED PSMCT32 (direct-color) texture demo for the BRAM BOARD
// variant — the CLOSURE rung of the swizzle layout family (after Ch298 swz4 +
// Ch299 swz8). PSMCT32 is DIRECT color (4 bytes/texel, NO CLUT), so the path is
// simpler than the indexed siblings. Proves the real-PS2 PSMCT32 page/block
// layout renders end-to-end through top_psmct32_raster_demo_bram with
// PSMCT32_SWIZZLE=1:
// - the texture UPLOAD (gif_image_xfer_stub) writes the 16x48 PSMCT32 texture
// into VRAM at SWIZZLED page/block addresses, and
// - the texture SAMPLER (gs_stub -> gs_texture_unit) reads it back through the
// SAME swizzle, so the two VRAM views are CONSISTENT.
// Because PSMCT32_SWIZZLE is a single per-format gate, the FRAMEBUFFER itself is
// ALSO swizzled here — proven coherent by the scanout, which de-swizzles back to
// raster order (this TB captures scanout pixels at raster (x,y), so a swizzled
// FB needs no change to the verify side).
//
// The sampled sprite is 16 wide x 40 TALL (a sub-window of a 22-wide texture —
// see the bake.py "heartbeat-splicer dodge" note for why the texture is wider
// than sampled) — crossing the 8-px PSMCT32 block ROW boundaries (y=8,16,24,32)
// AND — UNIQUELY for PSMCT32 vs the taller PSMT8 page — the 32-px PAGE-ROW
// boundary at v=32 (pixels v>=32 live in PAGE 1). Reading them swizzled recovers
// the intended coordinate-encoded gradient; reading the SAME bytes LINEARLY
// (PSMCT32_SWIZZLE=0) would scramble the bottom rows.
//
// Fixture: payload_swz32.mem / bios_swz32.mem (NO new EE/BIOS scaffolding —
// GIF payload only, reuses the one-shot textured-demo bootlet).
//
// Expected (mirrors bake.py swz32_texel):
// color(x,y): R = x<<4, G = y*5, B = (x+y)<<2 (A dropped by scanout).
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo_bram_swz32;
localparam int H_ACTIVE = 16; // sampled sprite width (texture is 22 wide; cols 16..21 unsampled)
localparam int V_ACTIVE = 40;
localparam int TEXW = 16; // sampled width (crosses block col at x=8)
localparam int TEXH = 40; // sampled height (crosses block rows 8,16,24,32 + PAGE row y=32)
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.VRAM_BYTES (32 * 1024), // swizzled FB (pages 0..1) + texture at 0x3000..
.PSMCT32_SWIZZLE(1'b1) // PSMCT32 FB + texture upload + sample SWIZZLED
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// ----- expected direct-color texel (mirrors bake.py swz32_texel) -----
function automatic logic [7:0] exp_r(input int x, input int y); return 8'((x << 4) & 8'hFF); endfunction
function automatic logic [7:0] exp_g(input int x, input int y); return 8'((y * 5) & 8'hFF); endfunction
function automatic logic [7:0] exp_b(input int x, input int y); return 8'(((x + y) << 2) & 8'hFF); endfunction
// ----- frame capture (VRAM_SYNC_READ=1 -> delayed counters) -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 0; cap_g[y][x] = 0; cap_b[y][x] = 0; cap_de[y][x] = 0;
end
capture_armed = 1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d <= 0; vcnt_d <= 0; end
else begin hcnt_d <= 32'(dut.u_pcrtc.hcnt); vcnt_d <= 32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
int errors;
int tex_pixels_ok;
int distinct_colors;
int cross_page_ok; // pixels in PAGE row 1 (y>=32) that matched
initial begin errors = 0; tex_pixels_ok = 0; distinct_colors = 0; cross_page_ok = 0; end
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk); core_go = 1'b1;
@(negedge clk); core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1) wait (dut.xfer_busy == 1'b0);
if (dut.clut_ld_busy == 1'b1) wait (dut.clut_ld_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1) wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// --- swizzled PSMCT32 direct-color region: each pixel is the
// coordinate-encoded texel color. The sprite covers the WHOLE 16x48
// window, crossing the 8-px block rows AND the 32-px page row at v=32. ---
for (int y = 0; y < TEXH; y++) begin
for (int x = 0; x < TEXW; x++) begin
logic [7:0] er, eg, eb;
er = exp_r(x, y); eg = exp_g(x, y); eb = exp_b(x, y);
if (!cap_de[y][x]) begin
$error("swz32 (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
$error("[swz32] (%0d,%0d) got (%02x,%02x,%02x) exp (%02x,%02x,%02x)",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb);
errors = errors + 1;
end else begin
tex_pixels_ok = tex_pixels_ok + 1;
if (y >= 32) cross_page_ok = cross_page_ok + 1; // proves PAGE 1 sampled OK
end
end
end
// --- the textured region must use MANY distinct colors (a stuck channel
// or wrong-block/page swizzle collapses the gradient). ---
begin
logic [23:0] seen [0:255];
int n;
n = 0;
for (int y = 0; y < TEXH; y++)
for (int x = 0; x < TEXW; x++) begin
logic [23:0] key;
bit found;
key = {cap_b[y][x], cap_g[y][x], cap_r[y][x]};
found = 1'b0;
for (int k = 0; k < n; k++) if (seen[k] === key) found = 1'b1;
if (!found && n < 256) begin seen[n] = key; n = n + 1; end
end
distinct_colors = n;
if (distinct_colors < 64) begin
$error("swz32 region shows only %0d distinct colors — channel/swizzle collapsed",
distinct_colors);
errors = errors + 1;
end
end
// The across-PAGE proof: PAGE row 1 (y in [32..39]) must have sampled
// correctly — that's exactly where the PSMCT32 swizzle diverges hardest
// from linear (a whole 8 KiB page hop).
if (cross_page_ok < 16*8) begin
$error("swz32 page-row 1 (y>=32) only %0d/%0d pixels correct — across-PAGE sampling failed",
cross_page_ok, 16*8);
errors = errors + 1;
end
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_raster_demo_bram_swz32] tex_ok=%0d/%0d cross_page_ok=%0d distinct_colors=%0d raster_emits=%0d errors=%0d",
tex_pixels_ok, TEXW*TEXH, cross_page_ok, distinct_colors,
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_raster_demo_bram_swz32] PASS");
else
$display("[tb_top_psmct32_raster_demo_bram_swz32] FAIL");
$finish;
end
initial begin
#60000000;
$error("[tb_top_psmct32_raster_demo_bram_swz32] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_raster_demo_bram_swz32
sim/tb/top/tb_top_psmct32_raster_demo_bram_swz4.sv
+233
View File
@@ -0,0 +1,233 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo_bram_swz4 (Ch298)
//
// TOP-LEVEL SWIZZLED PSMT4 INDEXED-TEXTURE + CLUT demo for the BRAM BOARD
// variant. Proves the real-PS2 PSMT4 BLOCK-layout texture path renders
// end-to-end through top_psmct32_raster_demo_bram with PSMT4_SWIZZLE=1:
// - the texture UPLOAD (gif_image_xfer_stub) writes the 64x32 PSMT4 index
// texture into VRAM at SWIZZLED block/column addresses, and
// - the texture SAMPLER (gs_stub -> gs_texture_unit) reads it back through
// the SAME swizzle, so the two VRAM views are CONSISTENT.
//
// The sampled sprite is 16 wide x 32 TALL — crossing the 16-px PSMT4 block
// ROW boundary (v=16) — so the bytes for v>=16 live in a DIFFERENT block than
// a linear layout would address. Reading them swizzled recovers the intended
// diagonal index ramp idx(x,y)=(x+2y)%16; reading the SAME bytes LINEARLY
// (PSMT4_SWIZZLE=0) would scramble across the block-row boundary.
//
// Fixture: payload_swz4.mem / bios_swz4.mem (NO new EE/BIOS scaffolding —
// GIF payload only, reuses the one-shot textured-demo bootlet).
//
// Expected (mirrors bake.py clut4_index + clut4_palette):
// index(x,y) = (x + 2*y) mod 16 ; 16 boldly distinct PSMCT32 palette entries.
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo_bram_swz4;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 32;
localparam int TEXW = 16; // sampled width (block column 0)
localparam int TEXH = 32; // sampled height (crosses block rows 0 & 1)
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.VRAM_BYTES (16 * 1024), // texture lives at 0x2400..0x27FF
.PSMCT32_SWIZZLE(1'b0), // FB stays LINEAR PSMCT32
.PSMT4_SWIZZLE (1'b1) // PSMT4 texture upload + sample SWIZZLED
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// ----- expected index + 16-entry palette (mirrors bake.py) -----
function automatic int idx(input int x, input int y);
return (x + 2*y) % 16;
endfunction
function automatic logic [7:0] pal_r(input int i);
case (i)
0: return 8'h00; 1: return 8'hFF; 2: return 8'h00; 3: return 8'h00;
4: return 8'hFF; 5: return 8'hFF; 6: return 8'h00; 7: return 8'hFF;
8: return 8'h80; 9: return 8'h00; 10: return 8'h00; 11: return 8'h80;
12: return 8'h80; 13: return 8'h00; 14: return 8'hC0; default: return 8'h40;
endcase
endfunction
function automatic logic [7:0] pal_g(input int i);
case (i)
0: return 8'h00; 1: return 8'h00; 2: return 8'hFF; 3: return 8'h00;
4: return 8'hFF; 5: return 8'h00; 6: return 8'hFF; 7: return 8'hFF;
8: return 8'h00; 9: return 8'h80; 10: return 8'h00; 11: return 8'h80;
12: return 8'h00; 13: return 8'h80; 14: return 8'h60; default: return 8'h40;
endcase
endfunction
function automatic logic [7:0] pal_b(input int i);
case (i)
0: return 8'h00; 1: return 8'h00; 2: return 8'h00; 3: return 8'hFF;
4: return 8'h00; 5: return 8'hFF; 6: return 8'hFF; 7: return 8'hFF;
8: return 8'h00; 9: return 8'h00; 10: return 8'h80; 11: return 8'h00;
12: return 8'h80; 13: return 8'h80; 14: return 8'h20; default: return 8'h40;
endcase
endfunction
// ----- frame capture (VRAM_SYNC_READ=1 -> delayed counters) -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 0; cap_g[y][x] = 0; cap_b[y][x] = 0; cap_de[y][x] = 0;
end
capture_armed = 1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d <= 0; vcnt_d <= 0; end
else begin hcnt_d <= 32'(dut.u_pcrtc.hcnt); vcnt_d <= 32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
int errors;
int tex_pixels_ok;
int distinct_colors;
int cross_row_ok; // pixels in block-row-1 (y>=16) that matched
initial begin errors = 0; tex_pixels_ok = 0; distinct_colors = 0; cross_row_ok = 0; end
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk); core_go = 1'b1;
@(negedge clk); core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1) wait (dut.xfer_busy == 1'b0);
if (dut.clut_ld_busy == 1'b1) wait (dut.clut_ld_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1) wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// --- swizzled PSMT4 indexed-textured region: each pixel is
// palette[index(x,y)] with index = (x+2y) mod 16. The sprite
// covers the WHOLE 16x32 window, crossing the v=16 block-row line. ---
for (int y = 0; y < TEXH; y++) begin
for (int x = 0; x < TEXW; x++) begin
logic [7:0] er, eg, eb;
int i;
i = idx(x, y);
er = pal_r(i); eg = pal_g(i); eb = pal_b(i);
if (!cap_de[y][x]) begin
$error("swz4 (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
$error("[swz4] (%0d,%0d) idx=%0d got (%02x,%02x,%02x) exp (%02x,%02x,%02x)",
x, y, i, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb);
errors = errors + 1;
end else begin
tex_pixels_ok = tex_pixels_ok + 1;
if (y >= 16) cross_row_ok = cross_row_ok + 1; // proves block-row-1 sampled OK
end
end
end
// --- the textured region must use MANY distinct palette colors
// (a stuck nibble or wrong-block swizzle collapses the ramp). ---
begin
logic [23:0] seen [0:15];
int n;
n = 0;
for (int y = 0; y < TEXH; y++)
for (int x = 0; x < TEXW; x++) begin
logic [23:0] key;
bit found;
key = {cap_b[y][x], cap_g[y][x], cap_r[y][x]};
found = 1'b0;
for (int k = 0; k < n; k++) if (seen[k] === key) found = 1'b1;
if (!found && n < 16) begin seen[n] = key; n = n + 1; end
end
distinct_colors = n;
if (distinct_colors < 12) begin
$error("swz4 region shows only %0d distinct colors — nibble/CLUT/swizzle collapsed",
distinct_colors);
errors = errors + 1;
end
end
// The across-block-row proof: block row 1 (y in [16..31]) must have
// sampled correctly — that's exactly where swizzle diverges from linear.
if (cross_row_ok < 16*16) begin
$error("swz4 block-row-1 (y>=16) only %0d/%0d pixels correct — across-block-boundary sampling failed",
cross_row_ok, 16*16);
errors = errors + 1;
end
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_raster_demo_bram_swz4] tex_ok=%0d/%0d cross_row_ok=%0d distinct_colors=%0d raster_emits=%0d errors=%0d",
tex_pixels_ok, TEXW*TEXH, cross_row_ok, distinct_colors,
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_raster_demo_bram_swz4] PASS");
else
$display("[tb_top_psmct32_raster_demo_bram_swz4] FAIL");
$finish;
end
initial begin
#40000000;
$error("[tb_top_psmct32_raster_demo_bram_swz4] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_raster_demo_bram_swz4
sim/tb/top/tb_top_psmct32_raster_demo_bram_swz8.sv
+235
View File
@@ -0,0 +1,235 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo_bram_swz8 (Ch299)
//
// TOP-LEVEL SWIZZLED PSMT8 INDEXED-TEXTURE + CLUT demo for the BRAM BOARD
// variant — the SIBLING of Ch298's swizzled-PSMT4 board demo, MINUS the nibble
// (PSMT8 is 1 byte/texel). Proves the real-PS2 PSMT8 BLOCK-layout texture path
// renders end-to-end through top_psmct32_raster_demo_bram with PSMT8_SWIZZLE=1:
// - the texture UPLOAD (gif_image_xfer_stub) writes the 64x48 PSMT8 index
// texture into VRAM at SWIZZLED block/column addresses, and
// - the texture SAMPLER (gs_stub -> gs_texture_unit) reads it back through
// the SAME swizzle, so the two VRAM views are CONSISTENT.
//
// The sampled sprite is 16 wide x 48 TALL — crossing the 16-px PSMT8 block ROW
// boundaries at v=16 AND v=32 — so the bytes for v>=16 live in DIFFERENT blocks
// than a linear layout would address. Reading them swizzled recovers the
// intended diagonal index ramp idx(x,y)=(x+2y)%16; reading the SAME bytes
// LINEARLY (PSMT8_SWIZZLE=0) would scramble across the block-row boundaries.
//
// Fixture: payload_swz8.mem / bios_swz8.mem (NO new EE/BIOS scaffolding —
// GIF payload only, reuses the one-shot textured-demo bootlet).
//
// Expected (mirrors bake.py swz8_index + clut4_palette):
// index(x,y) = (x + 2*y) mod 16 ; 16 boldly distinct PSMCT32 palette entries.
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo_bram_swz8;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 48;
localparam int TEXW = 16; // sampled width (block column 0)
localparam int TEXH = 48; // sampled height (crosses block rows 0,1,2)
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.VRAM_BYTES (32 * 1024), // texture lives at 0x3400..
.PSMCT32_SWIZZLE(1'b0), // FB stays LINEAR PSMCT32
.PSMT8_SWIZZLE (1'b1) // PSMT8 texture upload + sample SWIZZLED
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// ----- expected index + 16-entry palette (mirrors bake.py) -----
function automatic int idx(input int x, input int y);
return (x + 2*y) % 16;
endfunction
function automatic logic [7:0] pal_r(input int i);
case (i)
0: return 8'h00; 1: return 8'hFF; 2: return 8'h00; 3: return 8'h00;
4: return 8'hFF; 5: return 8'hFF; 6: return 8'h00; 7: return 8'hFF;
8: return 8'h80; 9: return 8'h00; 10: return 8'h00; 11: return 8'h80;
12: return 8'h80; 13: return 8'h00; 14: return 8'hC0; default: return 8'h40;
endcase
endfunction
function automatic logic [7:0] pal_g(input int i);
case (i)
0: return 8'h00; 1: return 8'h00; 2: return 8'hFF; 3: return 8'h00;
4: return 8'hFF; 5: return 8'h00; 6: return 8'hFF; 7: return 8'hFF;
8: return 8'h00; 9: return 8'h80; 10: return 8'h00; 11: return 8'h80;
12: return 8'h00; 13: return 8'h80; 14: return 8'h60; default: return 8'h40;
endcase
endfunction
function automatic logic [7:0] pal_b(input int i);
case (i)
0: return 8'h00; 1: return 8'h00; 2: return 8'h00; 3: return 8'hFF;
4: return 8'h00; 5: return 8'hFF; 6: return 8'hFF; 7: return 8'hFF;
8: return 8'h00; 9: return 8'h00; 10: return 8'h80; 11: return 8'h00;
12: return 8'h80; 13: return 8'h80; 14: return 8'h20; default: return 8'h40;
endcase
endfunction
// ----- frame capture (VRAM_SYNC_READ=1 -> delayed counters) -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 0; cap_g[y][x] = 0; cap_b[y][x] = 0; cap_de[y][x] = 0;
end
capture_armed = 1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d <= 0; vcnt_d <= 0; end
else begin hcnt_d <= 32'(dut.u_pcrtc.hcnt); vcnt_d <= 32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
int errors;
int tex_pixels_ok;
int distinct_colors;
int cross_row_ok; // pixels in block-row>=1 (y>=16) that matched
initial begin errors = 0; tex_pixels_ok = 0; distinct_colors = 0; cross_row_ok = 0; end
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk); core_go = 1'b1;
@(negedge clk); core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1) wait (dut.xfer_busy == 1'b0);
if (dut.clut_ld_busy == 1'b1) wait (dut.clut_ld_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1) wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// --- swizzled PSMT8 indexed-textured region: each pixel is
// palette[index(x,y)] with index = (x+2y) mod 16. The sprite
// covers the WHOLE 16x48 window, crossing the v=16 and v=32
// block-row lines. ---
for (int y = 0; y < TEXH; y++) begin
for (int x = 0; x < TEXW; x++) begin
logic [7:0] er, eg, eb;
int i;
i = idx(x, y);
er = pal_r(i); eg = pal_g(i); eb = pal_b(i);
if (!cap_de[y][x]) begin
$error("swz8 (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
$error("[swz8] (%0d,%0d) idx=%0d got (%02x,%02x,%02x) exp (%02x,%02x,%02x)",
x, y, i, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb);
errors = errors + 1;
end else begin
tex_pixels_ok = tex_pixels_ok + 1;
if (y >= 16) cross_row_ok = cross_row_ok + 1; // proves block-row>=1 sampled OK
end
end
end
// --- the textured region must use MANY distinct palette colors
// (a stuck byte or wrong-block swizzle collapses the ramp). ---
begin
logic [23:0] seen [0:15];
int n;
n = 0;
for (int y = 0; y < TEXH; y++)
for (int x = 0; x < TEXW; x++) begin
logic [23:0] key;
bit found;
key = {cap_b[y][x], cap_g[y][x], cap_r[y][x]};
found = 1'b0;
for (int k = 0; k < n; k++) if (seen[k] === key) found = 1'b1;
if (!found && n < 16) begin seen[n] = key; n = n + 1; end
end
distinct_colors = n;
if (distinct_colors < 12) begin
$error("swz8 region shows only %0d distinct colors — byte/CLUT/swizzle collapsed",
distinct_colors);
errors = errors + 1;
end
end
// The across-block-row proof: block rows >=1 (y in [16..47]) must have
// sampled correctly — that's exactly where swizzle diverges from linear.
if (cross_row_ok < 16*32) begin
$error("swz8 block-row>=1 (y>=16) only %0d/%0d pixels correct — across-block-boundary sampling failed",
cross_row_ok, 16*32);
errors = errors + 1;
end
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_raster_demo_bram_swz8] tex_ok=%0d/%0d cross_row_ok=%0d distinct_colors=%0d raster_emits=%0d errors=%0d",
tex_pixels_ok, TEXW*TEXH, cross_row_ok, distinct_colors,
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_raster_demo_bram_swz8] PASS");
else
$display("[tb_top_psmct32_raster_demo_bram_swz8] FAIL");
$finish;
end
initial begin
#60000000;
$error("[tb_top_psmct32_raster_demo_bram_swz8] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_raster_demo_bram_swz8
sim/tb/top/tb_top_psmct32_raster_demo_bram_textured.sv
+244
View File
@@ -0,0 +1,244 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo_bram_textured (Ch295)
//
// TOP-LEVEL textured-sprite demo TB for the BRAM BOARD VARIANT.
// Proves the synthesizable textured SPRITE path renders end-to-end
// through `top_psmct32_raster_demo_bram` — the variant the de25_nano
// board top instantiates — exactly as a board load would.
//
// This is the BRAM-backed companion to tb_top_psmct32_textured_demo
// (which drives the vram_stub variant top_psmct32_raster_demo). The
// difference that matters: vram_bram_stub's read2 (the texel-fetch
// port) is a 1-cycle REGISTERED sync read, NOT vram_stub's
// combinational read. The texel-fetch path therefore exercises
// gs_stub's TEX_RD_REGISTERED=1 timing model (texel address generated
// one pipeline stage early so the registered read lands in time). A
// PASS here means the BRAM board path samples the texture correctly
// despite the BRAM read latency — i.e. the board would SHOW the
// texture on HDMI.
//
// EE bootlet (bios_textured.mem) + GIF payload (payload_textured.mem):
// U1 BITBLT/TRX -> uploads an 8x8 PSMCT32 texture to VRAM (DBP=8)
// U2 IMAGE -> 16 qwords = the 64 texels
// U3/U4 PACKED -> PRIM(SPRITE+TME) + TEX0 + UV + XYZ2: textured
// 8x8 sprite at screen (0,0)..(7,7)
// U5 PACKED -> a FLAT green control sprite at (8,0)..(15,7)
//
// The top is built with PSMCT32_SWIZZLE=0 so the LINEAR gs_texel_addr
// fetch and the BITBLT upload share one VRAM layout (v1 scope).
//
// Verification is via the PCRTC scanout RGB (the same r/g/b/de a board
// wires to a video PHY):
// - Textured region x in [0..7]: scanout pixel == the uploaded texel.
// - Flat region x in [8..15]: scanout pixel == the flat green color.
// - The textured region must NOT be uniform (real sampled gradient).
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo_bram_textured;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
// PSMCT32_SWIZZLE=0 so texture-upload (BITBLT) and texel-fetch
// (gs_texel_addr, linear) share one VRAM layout. VRAM_ENABLE_READ2
// defaults to 1 (the texel-fetch needs read2 live).
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.PSMCT32_SWIZZLE(1'b0)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// ----- Expected texel/scanout for the textured region -----
// Bold 2x2-quadrant texture (mirrors bake.py tex_demo_texel):
// (x<4,y<4)=RED (x>=4,y<4)=GREEN (x<4,y>=4)=BLUE (x>=4,y>=4)=YELLOW
// PCRTC PSMCT32 -> r=texel[7:0], g=texel[15:8], b=texel[23:16].
function automatic logic [7:0] tex_exp_r(input int x, input int y); return ((x<4)==(y<4)) ? 8'hFF : 8'h00; endfunction
function automatic logic [7:0] tex_exp_g(input int x, input int y); return (x>=4) ? 8'hFF : 8'h00; endfunction
function automatic logic [7:0] tex_exp_b(input int x, input int y); return ((x<4)&&(y>=4)) ? 8'hFF : 8'h00; endfunction
// Flat control sprite color: rgbaq_data(0x20, 0xC0, 0x40).
localparam logic [7:0] FLAT_R = 8'h20;
localparam logic [7:0] FLAT_G = 8'hC0;
localparam logic [7:0] FLAT_B = 8'h40;
// ----- Frame capture -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 8'd0;
cap_g[y][x] = 8'd0;
cap_b[y][x] = 8'd0;
cap_de[y][x] = 1'b0;
end
capture_armed = 1'b0;
end
// VRAM_SYNC_READ=1: the PCRTC's r/g/b/de output at cycle T
// corresponds to the pixel whose address was driven at cycle T-1
// (the BRAM registers the read). So the captured pixel must be
// indexed by the DELAYED counters, matching tb_top_psmct32_raster
// _demo_bram's Ch158 capture. (The vram_stub textured TB uses the
// current counters because that PCRTC reads combinationally.)
logic [31:0] hcnt_d;
logic [31:0] vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin
hcnt_d <= 32'd0;
vcnt_d <= 32'd0;
end else begin
hcnt_d <= 32'(dut.u_pcrtc.hcnt);
vcnt_d <= 32'(dut.u_pcrtc.vcnt);
end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de
&& (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
int errors;
int tex_pixels_ok;
int distinct_tex_values;
logic [7:0] first_tex_g;
initial begin
errors = 0;
tex_pixels_ok = 0;
distinct_tex_values = 0;
end
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk);
core_go = 1'b1;
@(negedge clk);
core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1)
wait (dut.xfer_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1)
wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// --- Textured region (x in [0..7]) must match the uploaded texel. ---
for (int y = 0; y < 8; y++) begin
for (int x = 0; x < 8; x++) begin
logic [7:0] er, eg, eb;
er = tex_exp_r(x, y);
eg = tex_exp_g(x, y);
eb = tex_exp_b(x, y);
if (!cap_de[y][x]) begin
$error("textured (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
$error("[textured] (%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x)",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb);
errors = errors + 1;
end else begin
tex_pixels_ok = tex_pixels_ok + 1;
end
end
end
// --- The textured region must be a real gradient, not flat. ---
first_tex_g = cap_g[0][0];
for (int x = 1; x < 8; x++)
if (cap_g[0][x] !== first_tex_g)
distinct_tex_values = distinct_tex_values + 1;
if (distinct_tex_values == 0) begin
$error("textured region is uniform (G all = %02x) — texturing collapsed to flat",
first_tex_g);
errors = errors + 1;
end
// --- Flat control region (x in [8..15]) must be the flat color. ---
for (int y = 0; y < 8; y++) begin
for (int x = 8; x < 16; x++) begin
if (!cap_de[y][x]) begin
$error("flat (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== FLAT_R || cap_g[y][x] !== FLAT_G || cap_b[y][x] !== FLAT_B) begin
$error("[flat] (%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x)",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], FLAT_R, FLAT_G, FLAT_B);
errors = errors + 1;
end
end
end
// --- Status bundle. ---
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_raster_demo_bram_textured] tex_ok=%0d/64 gradient_distinct=%0d raster_emits=%0d errors=%0d",
tex_pixels_ok, distinct_tex_values,
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_raster_demo_bram_textured] PASS");
else
$display("[tb_top_psmct32_raster_demo_bram_textured] FAIL");
$finish;
end
initial begin
#20000000;
$error("[tb_top_psmct32_raster_demo_bram_textured] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_raster_demo_bram_textured
sim/tb/top/tb_top_psmct32_raster_demo_bram_tritex.sv
+248
View File
@@ -0,0 +1,248 @@
// retroDE_ps2 — tb_top_psmct32_raster_demo_bram_tritex
//
// TOP-LEVEL textured-TRIANGLE demo TB for the BRAM board variant
// (top_psmct32_raster_demo_bram — the variant the de25_nano board top
// instantiates). Proves the textured-triangle rung renders end-to-end
// through the BRAM VRAM, including vram_bram_stub.read2's 1-cycle
// registered texel-fetch latency (gs_stub TEX_RD_REGISTERED=1).
//
// EE bootlet (bios_tritex.mem) + GIF payload (payload_tritex.mem):
// U1 BITBLT/TRX -> uploads an 8x8 PSMCT32 texture (DBP=8)
// U2 IMAGE -> 16 qwords = the 64 texels
// U3 PACKED -> PRIM(TRI+TME) + TEX0 + 3 vertices (RGBAQ/UV/XYZ2):
// one non-axis-aligned textured triangle.
//
// UV == screen XY at each vertex, so the affine interpolated (u,v) ==
// (x,y) at every interior pixel; the sampled texel is exactly the
// uploaded tex_demo_texel(x,y). Verified through the PCRTC scanout RGB.
//
// Built with PSMCT32_SWIZZLE=0 so the LINEAR gs_texel_addr fetch and the
// BITBLT upload share one VRAM layout. ZTE=0, ABE=0 for this rung.
`timescale 1ns/1ps
module tb_top_psmct32_raster_demo_bram_tritex;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.PSMCT32_SWIZZLE(1'b0)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// ----- Reference: triangle interior + expected texel (UV==XY trick) -----
// Triangle from bake.py build_textured_triangle_demo_payload: (1,1),(7,1),(2,6).
localparam int VX0 = 1, VY0 = 1;
localparam int VX1 = 7, VY1 = 1;
localparam int VX2 = 2, VY2 = 6;
int sx1, sy1, sx2, sy2;
function automatic int edge_f(input int px, input int py,
input int ax, input int ay,
input int bx, input int by);
return (px - ax) * (by - ay) - (py - ay) * (bx - ax);
endfunction
function automatic bit tol(input int ax, input int ay, input int bx, input int by);
int dx, dy; dx = bx - ax; dy = by - ay;
return (dy > 0) || ((dy == 0) && (dx > 0));
endfunction
task automatic setup_ref();
int sa;
sa = (VX1 - VX0) * (VY2 - VY0) - (VY1 - VY0) * (VX2 - VX0);
if (sa < 0) begin sx1 = VX2; sy1 = VY2; sx2 = VX1; sy2 = VY1; end
else begin sx1 = VX1; sy1 = VY1; sx2 = VX2; sy2 = VY2; end
endtask
function automatic bit ref_inside(input int px, input int py);
int e0, e1, e2, b0, b1, b2;
e0 = edge_f(px, py, VX0, VY0, sx1, sy1);
e1 = edge_f(px, py, sx1, sy1, sx2, sy2);
e2 = edge_f(px, py, sx2, sy2, VX0, VY0);
b0 = tol(VX0, VY0, sx1, sy1) ? 0 : 1;
b1 = tol(sx1, sy1, sx2, sy2) ? 0 : 1;
b2 = tol(sx2, sy2, VX0, VY0) ? 0 : 1;
return ((e0 + b0) <= 0) && ((e1 + b1) <= 0) && ((e2 + b2) <= 0);
endfunction
// tex_demo_texel(x,y) quadrant pattern (mirrors bake.py):
// (x<4,y<4)=RED (x>=4,y<4)=GREEN (x<4,y>=4)=BLUE (x>=4,y>=4)=YELLOW
// PCRTC PSMCT32 -> r=texel[7:0], g=texel[15:8], b=texel[23:16].
function automatic logic [7:0] tex_exp_r(input int x, input int y); return ((x<4)==(y<4)) ? 8'hFF : 8'h00; endfunction
function automatic logic [7:0] tex_exp_g(input int x, input int y); return (x>=4) ? 8'hFF : 8'h00; endfunction
function automatic logic [7:0] tex_exp_b(input int x, input int y); return ((x<4)&&(y>=4)) ? 8'hFF : 8'h00; endfunction
// ----- Frame capture -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 8'd0; cap_g[y][x] = 8'd0; cap_b[y][x] = 8'd0;
cap_de[y][x] = 1'b0;
end
capture_armed = 1'b0;
end
// BRAM sync read: r/g/b at cycle T correspond to the pixel addressed
// at T-1, so index the captured pixel by the delayed counters.
logic [31:0] hcnt_d;
logic [31:0] vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin
hcnt_d <= 32'd0; vcnt_d <= 32'd0;
end else begin
hcnt_d <= 32'(dut.u_pcrtc.hcnt);
vcnt_d <= 32'(dut.u_pcrtc.vcnt);
end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de
&& (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
int errors;
int tex_pixels_ok;
int distinct_seen;
initial begin
errors = 0;
tex_pixels_ok = 0;
distinct_seen = 0;
setup_ref();
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk); core_go = 1'b1;
@(negedge clk); core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1)
wait (dut.xfer_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1)
wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// Every interior pixel must show the sampled texel for its (x,y).
for (int y = 0; y < V_ACTIVE; y++) begin
for (int x = 0; x < H_ACTIVE; x++) begin
if (ref_inside(x, y)) begin
logic [7:0] er, eg, eb;
er = tex_exp_r(x, y); eg = tex_exp_g(x, y); eb = tex_exp_b(x, y);
if (!cap_de[y][x]) begin
$error("tritex (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
$error("[tritex] (%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x)",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb);
errors = errors + 1;
end else begin
tex_pixels_ok = tex_pixels_ok + 1;
end
end
end
end
// The rendered triangle must show MORE THAN ONE distinct texel
// colour (real sampled gradient, not a collapsed flat fill).
// Count interior pixels whose colour differs from the first one.
begin
logic [23:0] first_seen;
bit have_first;
logic [23:0] this_px;
have_first = 1'b0;
distinct_seen = 1; // the first pixel itself
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++)
if (ref_inside(x, y) && cap_de[y][x]) begin
this_px = {cap_b[y][x], cap_g[y][x], cap_r[y][x]};
if (!have_first) begin
first_seen = this_px; have_first = 1'b1;
end else if (this_px !== first_seen) begin
distinct_seen = 2; // at least 2 distinct colours
end
end
end
if (distinct_seen < 2) begin
$error("textured triangle is uniform (distinct=%0d) — texturing collapsed",
distinct_seen);
errors = errors + 1;
end
if (tex_pixels_ok < 8) begin
$error("too few interior textured pixels matched (%0d)", tex_pixels_ok);
errors = errors + 1;
end
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_raster_demo_bram_tritex] tex_ok=%0d distinct=%0d raster_emits=%0d errors=%0d",
tex_pixels_ok, distinct_seen, dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_raster_demo_bram_tritex] PASS");
else
$display("[tb_top_psmct32_raster_demo_bram_tritex] FAIL");
$finish;
end
initial begin
#20000000;
$error("[tb_top_psmct32_raster_demo_bram_tritex] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_raster_demo_bram_tritex
sim/tb/top/tb_top_psmct32_sh3_clut_demo.sv
+132
View File
@@ -0,0 +1,132 @@
// retroDE_ps2 — tb_top_psmct32_sh3_clut_demo (Ch347 authentic board integration, pre-fit gate)
//
// Drives the AUTHENTIC Silent Hill 3 64x64-crop PSMT8 texture + real CLUT through the FULL board path
// (bram top: bootlet -> BITBLT-upload CLUT + PSMT8 texture -> TEX0(CLD=1) fires clut_loader_stub VRAM->CLUT
// load -> DECAL sprite -> PCRTC scanout) and pixel-diffs the SCANOUT RGB against the software reference.
//
// Label (Codex): "authentic 64x64 crop of SH3 PSMT8 indices + real SH3 CLUT rendered on silicon via chosen
// sprite geometry" — NOT full 128x128, NOT a faithful SH3 draw, NOT scene-accurate. DECAL/opaque RGB; the
// real CLUT alpha (~0x04) is preserved in the palette but not blended. Fixtures from gs_make_sh3_fixture.py
// (the crop from gs_extract_sh3_clut.py) — LOCAL/gitignored; NOT in the committable regression (skip-guard).
//
// PASS: every 64x64 scanout pixel RGB == sh3_ref64.mem RGB (= CLUT[crop_index]); >=20 distinct colors.
`timescale 1ns/1ps
module tb_top_psmct32_sh3_clut_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
logic clk, rst_n; initial clk=1'b0; always #5 clk=~clk;
logic core_go; logic [7:0] r,g,b; logic hsync,vsync,de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow, frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE), .PSMCT32_SWIZZLE(1'b0),
.RAM_SIZE_BYTES(8*1024), .VRAM_BYTES(32*1024), // 64x64 FB(16K)+tex@0x4000(4K)+CLUT(1K)
.HEARTBEAT_SPLICE_ENABLE(1'b0) // off: the Ch251/255 heartbeat splice patches EE-RAM qword 115's
// low 32 bits (animation), which collides with our texture payload
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen), .frame_seen(frame_seen),
.raster_overflow(raster_overflow), .frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// software reference (PSMCT32 ABGR = CLUT[crop_idx]); RGB is the authentic-art claim
logic [31:0] ref_mem [0:H_ACTIVE*V_ACTIVE-1];
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
cap_r[y][x]=0; cap_g[y][x]=0; cap_b[y][x]=0; cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
int errors, tex_pixels_ok, distinct_colors;
initial begin
errors=0; tex_pixels_ok=0; distinct_colors=0;
ref_mem[0]='x;
$readmemh("../../data/top_psmct32_raster_demo/sh3_ref64.mem", ref_mem);
if (ref_mem[0] === 32'bx) begin
$display("[tb_top_psmct32_sh3_clut_demo] SKIP — sh3_ref64.mem absent (run gs_extract_sh3_clut.py + gs_make_sh3_fixture.py with the local SH3 dump)");
$finish;
end
rst_n=1'b0; core_go=1'b0;
repeat (4) @(posedge clk); rst_n=1'b1; repeat (8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat (4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat (10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
if (dut.clut_ld_busy==1'b1) wait (dut.clut_ld_busy==1'b0);
if (dut.u_gs.raster_active==1'b1) wait (dut.u_gs.raster_active==1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// pixel-diff: scanout RGB == CLUT[crop_idx] RGB (= sh3_ref64.mem low 24 bits)
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
logic [7:0] er,eg,eb; logic [31:0] e;
e = ref_mem[y*H_ACTIVE+x]; er=e[7:0]; eg=e[15:8]; eb=e[23:16];
if (!cap_de[y][x]) begin
if (errors<12) $error("(%0d,%0d) DE never asserted", x, y); errors++;
end else if (cap_r[y][x]!==er || cap_g[y][x]!==eg || cap_b[y][x]!==eb) begin
if (errors<12) $error("(%0d,%0d) got (%02x,%02x,%02x) exp (%02x,%02x,%02x)",
x,y, cap_r[y][x],cap_g[y][x],cap_b[y][x], er,eg,eb);
errors++;
end else tex_pixels_ok++;
end
// variety: a collapsed CLUT would render flat. Count distinct colors (cap up to 32).
begin
logic [23:0] seen [0:31]; int n; n=0;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
logic [23:0] key; bit found; key={cap_b[y][x],cap_g[y][x],cap_r[y][x]}; found=1'b0;
for (int k=0;k<n;k++) if (seen[k]===key) found=1'b1;
if (!found && n<32) begin seen[n]=key; n++; end
end
distinct_colors=n;
if (distinct_colors<20) begin $error("only %0d distinct colors — CLUT indirection collapsed", distinct_colors); errors++; end
end
// DIAGNOSTIC: read the FB directly (bypass scanout) to isolate render vs scanout-capture.
begin
int fb_errors; fb_errors=0;
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin
logic [31:0] fbw; fbw = dut.u_vram.mem[y*H_ACTIVE+x];
if (fbw[23:0] !== ref_mem[y*H_ACTIVE+x][23:0]) fb_errors++;
end
$display("[tb_top_psmct32_sh3_clut_demo] FB-direct errors=%0d (0 => render OK)", fb_errors);
if (fb_errors != 0) errors += fb_errors;
end
if (!core_halt) begin $error("core_halt low at end"); errors++; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors++; end
if (raster_overflow)begin $error("raster_overflow set"); errors++; end
$display("[tb_top_psmct32_sh3_clut_demo] px_ok=%0d/%0d distinct_colors=%0d raster_emits=%0d errors=%0d",
tex_pixels_ok, H_ACTIVE*V_ACTIVE, distinct_colors, dut.u_gs.raster_pixel_emit_count, errors);
if (errors==0) $display("[tb_top_psmct32_sh3_clut_demo] PASS");
else $display("[tb_top_psmct32_sh3_clut_demo] FAIL");
$finish;
end
initial begin #40000000; $error("[tb_top_psmct32_sh3_clut_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_sh3_clut_demo
sim/tb/top/tb_top_psmct32_sh3_persp_demo.sv
+195
View File
@@ -0,0 +1,195 @@
// retroDE_ps2 — tb_top_psmct32_sh3_persp_demo (Ch348 authentic integration)
//
// Authentic SH3 PSMT8 texture + real CLUT rendered through the PROVEN perspective-triangle FEEDER path
// (Ch342 feeder_persp config + PERSPECTIVE_CORRECT=1) — composing Ch342 (perspective ST/Q) + Ch347 (SH3
// PSMT8->CLUT). The feeder staging (feeder_sh3_persp.mem) carries a perspective quad + TEX0(PSM=PSMT8,CLD=1);
// the feeder's TEX0 commit fires the clut_loader VRAM->CLUT load. The SH3 PSMT8 texture + CLUT are backdoored
// into VRAM (the upload path is proven by Ch347's board demo).
//
// Label (Codex): authentic SH3 PSMT8 texture + real CLUT through the perspective triangle path, chosen
// perspective geometry — NOT authentic SH3 draw geometry. DECAL/opaque.
//
// Proof: per-pixel barycentric PERSPECTIVE reference (u=S/Q -> SH3 idx -> CLUT). The SH3 texture is per-texel
// (no cells), so sub-texel aliasing at texel boundaries makes a small % differ (like the Ch343 cube 97.5%);
// PASS = high interior match-% + perspective!=affine (warp real) + every covered pixel is a real CLUT entry.
//
// Fixtures (LOCAL/gitignored): tools/gs_extract_sh3_clut.py + tools/gs_make_sh3_persp_fixture.py. NOT in the
// regression (reads dump-derived .mem); skip-guard if absent.
`timescale 1ns/1ps
module tb_top_psmct32_sh3_persp_demo;
localparam int H_ACTIVE=64, V_ACTIVE=64;
localparam int TBP=64, CBP=80; // matches gs_make_sh3_persp_fixture.py
localparam int TEX_W0=TBP*64, CLUT_W0=CBP*64;
real W_FAR, W_NEAR; initial begin W_FAR=8.0; W_NEAR=1.0; end
localparam int QX0=8, QX1=56, QY0=8, QY1=56; // perspective quad in the FB (matches the fixture)
localparam int TEXW=64, TEXH=64;
logic clk, rst_n; initial clk=1'b0; always #5 clk=~clk;
logic core_go; logic [7:0] r,g,b; logic hsync,vsync,de;
logic core_halt,dma_done_seen,frame_seen,raster_overflow,frame_toggle,dma_done_toggle;
logic feeder_go_tb, feeder_ready_tb;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b0), .TILE_LOCAL(1'b0), .TILE_COLS(1), .TILE_ROWS(1),
.TILE_MULTIPRIM(1'b0), .TILE_PRIM_COUNT(1), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b0), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(256),
.PERSPECTIVE_CORRECT(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen), .frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle), .joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb), .feeder_ready_o(feeder_ready_tb), .feeder_records_o(), .feeder_waits_o()
);
// SH3 fixtures
logic [31:0] tex_words [0:(TEXW*TEXH/4)-1]; // 1024 packed PSMT8 words (4 idx each)
logic [31:0] clut_mem [0:255];
function automatic logic [7:0] sh3_idx(input integer u, input integer v);
integer lin; logic [31:0] w;
lin = v*TEXW + u; w = tex_words[lin/4]; sh3_idx = w[(8*(lin%4)) +: 8];
endfunction
function automatic logic [23:0] exp_cell(input integer u, input integer v); // CLUT[idx] as {B,G,R}
exp_cell = clut_mem[sh3_idx(u,v)][23:0];
endfunction
function automatic real bdet(input real ax,ay,bx,by,cx,cy); bdet=(by-cy)*(ax-cx)+(cx-bx)*(ay-cy); endfunction
function automatic real bwa(input real px,py,ax,ay,bx,by,cx,cy);
bwa=((by-cy)*(px-cx)+(cx-bx)*(py-cy))/bdet(ax,ay,bx,by,cx,cy); endfunction
function automatic real bwb(input real px,py,ax,ay,bx,by,cx,cy);
bwb=((cy-ay)*(px-cx)+(ax-cx)*(py-cy))/bdet(ax,ay,bx,by,cx,cy); endfunction
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
int errors, match_ok, match_total, persp_ne_affine, persp_ne_affine_ok, clut_bad;
// bounded-mismatch report: histogram of min Chebyshev texel-distance at which the captured color matches
// a reference texel (0=exact,1,2,3,4=no-match-within-3); separately for INTERIOR (away from tri edges).
int hist[0:4], int_hist[0:4], int_total, n_drift; real sum_du, sum_dv;
initial begin
errors=0; match_ok=0; match_total=0; persp_ne_affine=0; persp_ne_affine_ok=0; clut_bad=0; feeder_go_tb=1'b0;
int_total=0; n_drift=0; sum_du=0.0; sum_dv=0.0;
for (int k=0;k<5;k++) begin hist[k]=0; int_hist[k]=0; end
tex_words[0]='x;
$readmemh(`FEEDER_SH3_PERSP_FILE, dut.g_feeder.feeder_stg);
$readmemh("../../data/top_psmct32_raster_demo/sh3_tex_idx64.mem", tex_words);
$readmemh("../../data/top_psmct32_raster_demo/sh3_clut.mem", clut_mem);
if (tex_words[0] === 32'bx) begin
$display("[tb_top_psmct32_sh3_persp_demo] SKIP — sh3_*.mem absent (run gs_extract_sh3_clut.py + gs_make_sh3_persp_fixture.py)");
$finish;
end
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
// backdoor the PSMT8 texture (packed 4 idx/word, linear) + the CLUT (256 PSMCT32, contiguous)
for (int w=0; w<TEXW*TEXH/4; w++) dut.u_vram.mem[TEX_W0 + w] = tex_words[w];
for (int i=0; i<256; i++) dut.u_vram.mem[CLUT_W0 + i] = clut_mem[i];
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// re-assert (the setup xfer may have touched VRAM); the feeder's TEX0 CLD=1 loads the CLUT
for (int w=0; w<TEXW*TEXH/4; w++) dut.u_vram.mem[TEX_W0 + w] = tex_words[w];
for (int i=0; i<256; i++) dut.u_vram.mem[CLUT_W0 + i] = clut_mem[i];
wait (feeder_ready_tb==1'b1);
repeat(200000) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
for (int py=QY0; py<=QY1; py++) for (int px=QX0; px<=QX1; px++) begin
real wa,wb,wc, su,sv,sq, pu,pv, au,av;
real uA,vA,wAv, uB,vB,wBv, uC,vC,wCv, lx,ly;
bit inA, outside; logic [23:0] pe, ae;
lx=px-QX0; ly=py-QY0; inA=1'b1; outside=1'b0;
// triangle A = TL(0,0),TR(48,0),BL(0,48) in local coords (quad is 48x48)
wa=bwa(lx,ly, 0,0, 48,0, 0,48); wb=bwb(lx,ly, 0,0, 48,0, 0,48); wc=1.0-wa-wb;
if (wa<-0.001||wb<-0.001||wc<-0.001) begin
inA=1'b0;
wa=bwa(lx,ly, 48,0, 0,48, 48,48); wb=bwb(lx,ly, 48,0, 0,48, 48,48); wc=1.0-wa-wb;
if (wa<-0.001||wb<-0.001||wc<-0.001) outside=1'b1;
end
if (!outside && cap_de[py][px]) begin
if (inA) begin uA=0; vA=0; wAv=W_FAR; uB=TEXW; vB=0; wBv=W_FAR; uC=0; vC=TEXH; wCv=W_NEAR; end
else begin uA=TEXW; vA=0; wAv=W_FAR; uB=0; vB=TEXH; wBv=W_NEAR; uC=TEXW; vC=TEXH; wCv=W_NEAR; end
su=wa*(uA/wAv)+wb*(uB/wBv)+wc*(uC/wCv);
sv=wa*(vA/wAv)+wb*(vB/wBv)+wc*(vC/wCv);
sq=wa*(1.0/wAv)+wb*(1.0/wBv)+wc*(1.0/wCv);
pu=su/sq; pv=sv/sq;
au=wa*uA+wb*uB+wc*uC; av=wa*vA+wb*vB+wc*vC;
if (pu<0) pu=0; if (pu>TEXW-1) pu=TEXW-1; if (pv<0) pv=0; if (pv>TEXH-1) pv=TEXH-1;
if (au<0) au=0; if (au>TEXW-1) au=TEXW-1; if (av<0) av=0; if (av>TEXH-1) av=TEXH-1;
pe=exp_cell(int'(pu),int'(pv)); ae=exp_cell(int'(au),int'(av)); // truncate (hardware floor)
match_total++;
// Min Chebyshev texel-distance D where the captured color matches a reference texel (search
// +/-3), with the signed delta at that min. Histogram D + accumulate the delta (drift check).
// The hardware's fixed-point gs_reciprocal picks a texel within ~+/-1 of the FLOAT reference
// at boundaries; this MACHINE-PROVES every residual is a bounded <=1-texel reciprocal delta
// (away from triangle edges) with no systematic drift — not a hand-waved %.
begin
int D, mdu, mdv; real minw;
D=99; mdu=0; mdv=0;
for (int rad=0; rad<=3; rad++)
for (int du=-rad; du<=rad; du++) for (int dv=-rad; dv<=rad; dv++) begin
int chev, tu, tv; chev=(du<0?-du:du); if ((dv<0?-dv:dv)>chev) chev=(dv<0?-dv:dv);
tu=int'(pu)+du; tv=int'(pv)+dv;
if (chev==rad && D==99 && tu>=0 && tu<TEXW && tv>=0 && tv<TEXH &&
{cap_b[py][px],cap_g[py][px],cap_r[py][px]} === exp_cell(tu,tv)) begin D=rad; mdu=du; mdv=dv; end
end
hist[(D<=3)?D:4]++;
if (D<=1) match_ok++;
if (D<=3) begin sum_du=sum_du+mdu; sum_dv=sum_dv+mdv; n_drift++; end
minw=wa; if (wb<minw) minw=wb; if (wc<minw) minw=wc; // bary min weight -> distance to nearest tri edge
if (minw > 0.04) begin int_total++; int_hist[(D<=3)?D:4]++; end // INTERIOR (away from edges/seam)
end
if (pe!==ae) persp_ne_affine++; // warp real: perspective texel differs from affine
begin bit f; logic [31:0] pc; f=1'b0; // every covered quad pixel must be a real CLUT entry
for (int i=0;i<256;i++) begin pc=clut_mem[i]; if (pc[23:0]==={cap_b[py][px],cap_g[py][px],cap_r[py][px]}) f=1'b1; end
if (!f) clut_bad++;
end
end
end
$display("[tb_top_psmct32_sh3_persp_demo] min-texel-dist hist ALL(%0d px): D0=%0d D1=%0d D2=%0d D3=%0d none=%0d",
match_total, hist[0],hist[1],hist[2],hist[3],hist[4]);
$display("[tb_top_psmct32_sh3_persp_demo] min-texel-dist hist INTERIOR(%0d px): D0=%0d D1=%0d D2=%0d D3=%0d none=%0d",
int_total, int_hist[0],int_hist[1],int_hist[2],int_hist[3],int_hist[4]);
$display("[tb_top_psmct32_sh3_persp_demo] <=1texel=%0d/%0d (%.1f%%) mean-delta=(%.3f,%.3f) persp!=affine=%0d clut_bad=%0d",
match_ok, match_total, 100.0*match_ok/match_total,
(n_drift>0)?sum_du/n_drift:0.0, (n_drift>0)?sum_dv/n_drift:0.0, persp_ne_affine, clut_bad);
// CRISP bounded acceptance (Codex): authentic palette ONLY (clut_bad=0) + every INTERIOR residual is
// <=1 texel (no >1-texel error away from tri edges) + no systematic drift + perspective real. Edge/seam
// pixels (partial coverage) are reported in ALL but not gated. This bounds the residual to fixed-point
// reciprocal sub-texel noise vs the float reference — NOT a hand-waved percentage.
if (match_total < 200) begin $error("too few quad pixels (%0d)", match_total); errors++; end
if (clut_bad != 0) begin $error("%0d covered pixels NOT a CLUT entry — wrong palette", clut_bad); errors++; end
if (int_hist[2]+int_hist[3]+int_hist[4] != 0) begin $error("%0d INTERIOR pixels >1 texel off — residual NOT bounded to +/-1", int_hist[2]+int_hist[3]+int_hist[4]); errors++; end
if (n_drift>0 && (sum_du/n_drift>0.3 || sum_du/n_drift<-0.3 || sum_dv/n_drift>0.3 || sum_dv/n_drift<-0.3))
begin $error("systematic drift (%.3f,%.3f) — not symmetric reciprocal noise", sum_du/n_drift, sum_dv/n_drift); errors++; end
if (persp_ne_affine < 8) begin $error("only %0d persp!=affine — warp too weak", persp_ne_affine); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
if (errors==0) begin $display("[tb_top_psmct32_sh3_persp_demo] PASS"); $finish; end
else $fatal(1, "[tb_top_psmct32_sh3_persp_demo] FAIL (%0d errors)", errors);
end
initial begin #1500000000; $error("[tb_top_psmct32_sh3_persp_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_sh3_persp_demo
sim/tb/top/tb_top_psmct32_sh3_real_draw_demo.sv
+238
View File
@@ -0,0 +1,238 @@
// retroDE_ps2 — tb_top_psmct32_sh3_real_draw_demo (Ch350 full-res LPDDR integration)
//
// The EXACT Ch349 SH3 draw (f1 idx89761 lamppost/bench) on the newly-closed paths, end-to-end:
// - reconstructed 512x512 PSMT8 texture lives in a behavioral LPDDR model, warmed into gs_texture_cache
// (GS_LPDDR_TEX=1) BEFORE raster — the texel-fetch is served from LPDDR, not BRAM;
// - the real CSM1 CLUT (16x16 CT32 grid bytes) is backdoored into BRAM; the feeder's TEX0 (CSM=0/CSM1,
// CLD=1) fires the Ch350 CSM1-grid clut_loader path (CLUT_CSM1_ENABLE=1);
// - the actual draw geometry (68 tris, perspective ST/Q) runs through the feeder S1 path.
// No crop / downscale / repack (Codex). Pixel-diff: read the linear PSMCT32 FB from BRAM and compare against
// the Ch349 host reference (per-pixel texel map) with the Ch348 bounded <=1-texel acceptance.
//
// Fixtures (LOCAL/gitignored): tools/gs_make_sh3_real_draw_fixture.py. NOT in the regression (dump-derived);
// skip-guard if absent. Run gs_extract_sh3_clut.py is NOT needed (this tool reconstructs from the dump).
`timescale 1ns/1ps
module tb_top_psmct32_sh3_real_draw_demo;
`include "sh3_real_params.vh"
logic clk; logic rst_n; initial clk=1'b0; always #5 clk=~clk;
logic core_go; logic [7:0] r,g,b; logic hsync,vsync,de;
logic core_halt,dma_done_seen,frame_seen,raster_overflow,frame_toggle,dma_done_toggle;
logic feeder_go_tb, feeder_ready_tb;
// bram-top <-> texture-cache tap (Ch322)
logic gs_tex_rd_en_o; logic [31:0] gs_tex_rd_addr_o;
logic [31:0] tex_cache_data; logic tex_cache_ready;
logic [31:0] tex_cache_hits, tex_bram_hits;
// cache AXI <-> behavioral LPDDR
logic [29:0] araddr; logic [1:0] arburst; logic [6:0] arid;
logic [7:0] arlen; logic [2:0] arsize; logic arvalid, arready;
logic [255:0] rdata; logic [1:0] rresp; logic rlast, rvalid, rready;
logic fill_start, fill_done; logic [31:0] fill_beats, fill_bytes, tex_rd_errs, fill_crc_w;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(FBPXW), .V_ACTIVE(FBH),
.VRAM_BYTES(VRAM_BYTES_P), .VRAM_ENABLE_READ2(1'b0), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b0), .TILE_LOCAL(1'b0), .TILE_COLS(1), .TILE_ROWS(1),
.TILE_MULTIPRIM(1'b0), .TILE_PRIM_COUNT(1), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b0), .HEARTBEAT_SPLICE_ENABLE(1'b0),
.FEEDER_ENABLE(1'b1), .FEEDER_STG_WORDS(STG_WORDS),
.PERSPECTIVE_CORRECT(1'b1), .PERSP_RECIP_IDX_BITS(11), // Ch351 — widened far-W reciprocal
.GRAD_SEQ_DIVIDER(1'b1), // Ch352 — match the board fit: sequential divider (must stay bit-exact)
.GRAD_DIV_CYCLES(4), // (ignored when GRAD_SEQ_DIVIDER=1)
.GS_LPDDR_TEX(1'b1), .TEX_VRAM_BASE(TEX_VRAM_BASE), .TEX_CACHE_BYTES(TEX_BYTES),
.CLUT_CSM1_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen), .frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle), .joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
.feeder_stg_we_i(1'b0), .feeder_stg_waddr_i(12'd0), .feeder_stg_wdata_i(64'd0),
.feeder_go_i(feeder_go_tb), .feeder_ready_o(feeder_ready_tb), .feeder_records_o(), .feeder_waits_o(),
.gs_tex_rd_en_o(gs_tex_rd_en_o), .gs_tex_rd_addr_o(gs_tex_rd_addr_o),
.tex_cache_data_i(tex_cache_data), .tex_cache_ready_i(tex_cache_ready),
.tex_cache_hits_o(tex_cache_hits), .tex_bram_hits_o(tex_bram_hits)
);
gs_texture_cache #(
.LPDDR_TEX_BASE(LPDDR_TEX_BASE), .TEX_VRAM_BASE(TEX_VRAM_BASE),
.TEX_BYTES(TEX_BYTES), .N_BEATS(N_BEATS)
) u_cache (
.axi_clk(clk), .axi_rst_n(rst_n),
.fill_start(fill_start), .fill_done(fill_done),
.fill_beats(fill_beats), .fill_bytes(fill_bytes), .rd_errs(tex_rd_errs), .fill_crc(fill_crc_w),
.araddr(araddr), .arburst(arburst), .arid(arid), .arlen(arlen),
.arsize(arsize), .arvalid(arvalid), .arready(arready),
.rdata(rdata), .rresp(rresp), .rlast(rlast), .rvalid(rvalid), .rready(rready),
.sample_clk(clk), .tex_rd_en(gs_tex_rd_en_o),
.tex_rd_addr(gs_tex_rd_addr_o), .tex_rd_data(tex_cache_data), .tex_ready(tex_cache_ready)
);
// ---- behavioral LPDDR model: 65536 words = the SWIZZLED PSMT8 texture bytes ----
logic [31:0] lpddr_mem [0:(TEX_BYTES/4)-1];
typedef enum logic [1:0] { S_IDLE, S_WAIT, S_DATA } sstate_t; sstate_t sst;
logic [3:0] dly; int beat_idx;
always_ff @(posedge clk) begin
if (!rst_n) begin sst<=S_IDLE; arready<=0; rvalid<=0; rlast<=0; rresp<=2'b00; rdata<='0; dly<='0; end
else begin
arready<=0; rvalid<=0; rlast<=0;
case (sst)
S_IDLE: if (arvalid) begin arready<=1; beat_idx<=(araddr-LPDDR_TEX_BASE)>>5; dly<=4'd2; sst<=S_WAIT; end
S_WAIT: if (dly==0) sst<=S_DATA; else dly<=dly-1'b1;
S_DATA: if (rready) begin
for (int w=0; w<8; w++) rdata[w*32 +: 32] <= lpddr_mem[beat_idx*8 + w];
rresp<=2'b00; rvalid<=1; rlast<=1; sst<=S_IDLE;
end
endcase
end
end
// ---- reference data: de-swizzled 512x512 indices (4/word), de-gridded palette, per-pixel texel map ----
logic [31:0] idx_words [0:(512*512/4)-1];
logic [31:0] pal [0:255];
logic [31:0] clut_grid [0:255]; // raw CT32-grid CLUT bytes -> backdoored into BRAM
logic [31:0] refmap [0:FBPXW*FBH-1];
function automatic logic [7:0] sh3_idx(input integer u, input integer v);
integer lin; logic [31:0] w; lin=v*TW+u; w=idx_words[lin/4]; sh3_idx=w[(8*(lin%4)) +: 8];
endfunction
function automatic logic [23:0] exp_cell(input integer u, input integer v);
exp_cell = pal[sh3_idx(u,v)][23:0]; endfunction
int errors, match_total, match_ok, clut_bad, int_total, n_drift; real sum_du, sum_dv;
int hist[0:4], int_hist[0:4], deep_hist[0:4], distinct_seen, deep_total, seam_bad;
initial begin
errors=0; match_total=0; match_ok=0; clut_bad=0; int_total=0; n_drift=0; sum_du=0.0; sum_dv=0.0;
distinct_seen=0; feeder_go_tb=1'b0;
deep_total=0; seam_bad=0; for (int k=0;k<5;k++) begin hist[k]=0; int_hist[k]=0; deep_hist[k]=0; end
idx_words[0]='x;
$readmemh(`FEEDER_SH3_REAL_FILE, dut.g_feeder.feeder_stg);
$readmemh("../../data/top_psmct32_raster_demo/sh3_real_tex_lpddr.mem", lpddr_mem);
$readmemh("../../data/top_psmct32_raster_demo/sh3_real_idx.mem", idx_words);
$readmemh("../../data/top_psmct32_raster_demo/sh3_real_pal.mem", pal);
$readmemh("../../data/top_psmct32_raster_demo/sh3_real_clut.mem", clut_grid);
$readmemh("../../data/top_psmct32_raster_demo/sh3_real_refmap.mem", refmap);
if (idx_words[0] === 32'bx) begin
$display("[tb_top_psmct32_sh3_real_draw_demo] SKIP — sh3_real_*.mem absent (run gs_make_sh3_real_draw_fixture.py)");
$finish;
end
rst_n=1'b0; core_go=1'b0; fill_start=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
// warm the LPDDR texture cache FIRST (edge-triggered fill_start; hold high — do not pulse).
@(posedge clk) fill_start<=1'b1;
begin int gd=0; while (!fill_done && gd<200000) begin @(posedge clk); gd++; end end
if (!fill_done) begin $error("cache fill_done never asserted"); errors++; end
if (fill_beats!==N_BEATS) begin $error("fill_beats=%0d exp %0d", fill_beats, N_BEATS); errors++; end
if (tex_rd_errs!==0) begin $error("tex_rd_errs=%0d exp 0", tex_rd_errs); errors++; end
// Ch352 — cache-fill CRC PROVES tex_mem integrity: sum32 of the words written into tex_mem must equal the
// texture file's sum32 (the same value the uploader prints / the board reg must report).
if (fill_crc_w!==32'hfbdeaa32) begin $error("cache fill_crc=%08x exp fbdeaa32 — tex_mem corrupt", fill_crc_w); errors++; end
else $display("[tb] cache fill_crc=%08x OK (tex_mem integrity proven)", fill_crc_w);
// Ch352 — NO CLUT backdoor: the BOOTLET (payload_sh3_real) uploads the CSM1 grid CLUT to CBP via a
// 256x1 BITBLT (the board path). This makes the SIM prove the board CLUT load end-to-end, not a backdoor.
// (clut_grid is still loaded only for the verify-vs-pal sanity, not written into VRAM.)
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
if (!tex_cache_ready) begin $error("tex cache not ready before raster"); errors++; end
wait (feeder_ready_tb==1'b1); // C_READY = the whole scene rendered + drained
repeat(50) @(posedge clk);
// DEBUG: dump the rendered FB (linear PSMCT32) for visual triage vs the host reference.
begin integer fd; fd=$fopen("../../data/top_psmct32_raster_demo/sh3_real_fb_out.mem","w");
for (int yy=0; yy<FBH; yy++) for (int xx=0; xx<FBPXW; xx++)
$fwrite(fd, "%08x\n", dut.u_vram.mem[yy*FBPXW+xx]);
$fclose(fd);
end
// ---- pixel-diff: read the linear PSMCT32 FB straight from BRAM ----
for (int py=0; py<FBH; py++) for (int px=0; px<FBPXW; px++) begin
logic [31:0] rm, fbw; logic [23:0] fb;
int tu, tv, interior, deepint;
rm = refmap[py*FBPXW+px];
if (rm[31]) begin // covered by the draw
interior = rm[30]; deepint = rm[29];
tu = (rm>>9)&9'h1FF; tv = rm&9'h1FF;
fbw = dut.u_vram.mem[py*FBPXW+px]; // FBP=0, linear PSMCT32
fb = fbw[23:0]; // {B,G,R}
match_total++;
// min Chebyshev texel-distance D at which fb matches a reference texel (search +/-3) + signed delta.
begin
int D, mdu, mdv;
D=99; mdu=0; mdv=0;
for (int rad=0; rad<=3; rad++)
for (int du=-rad; du<=rad; du++) for (int dv=-rad; dv<=rad; dv++) begin
int chev, ttu, ttv; chev=(du<0?-du:du); if ((dv<0?-dv:dv)>chev) chev=(dv<0?-dv:dv);
ttu=tu+du; ttv=tv+dv;
if (chev==rad && D==99 && ttu>=0 && ttu<TW && ttv>=0 && ttv<TH && fb===exp_cell(ttu,ttv))
begin D=rad; mdu=du; mdv=dv; end
end
hist[(D<=3)?D:4]++;
if (D<=1) match_ok++;
if (D<=3) begin sum_du=sum_du+mdu; sum_dv=sum_dv+mdv; n_drift++; end
if (interior) begin int_total++; int_hist[(D<=3)?D:4]++; end
if (deepint) begin deep_total++; deep_hist[(D<=3)?D:4]++; end
else if (interior && D>1) seam_bad++; // interior-but-near-a-seam, >1 texel
end
// every covered pixel must be a real CLUT (palette) entry.
begin bit f; f=1'b0;
for (int i=0;i<256;i++) if (pal[i][23:0]===fb) f=1'b1;
if (!f) clut_bad++;
end
end // close if (rm[31])
end
// render non-trivial: count distinct covered colors
begin logic [23:0] seen [0:63]; int ns; ns=0;
for (int py=0; py<FBH && ns<64; py++) for (int px=0; px<FBPXW && ns<64; px++)
if (refmap[py*FBPXW+px][31]) begin
logic [23:0] c; bit dup; c=dut.u_vram.mem[py*FBPXW+px][23:0]; dup=0;
for (int k=0;k<ns;k++) if (seen[k]===c) dup=1;
if (!dup) begin seen[ns]=c; ns++; end
end
distinct_seen=ns;
end
$display("[tb_top_psmct32_sh3_real_draw_demo] min-texel-dist hist ALL(%0d px): D0=%0d D1=%0d D2=%0d D3=%0d none=%0d",
match_total, hist[0],hist[1],hist[2],hist[3],hist[4]);
$display("[tb_top_psmct32_sh3_real_draw_demo] min-texel-dist hist INTERIOR(%0d px): D0=%0d D1=%0d D2=%0d D3=%0d none=%0d",
int_total, int_hist[0],int_hist[1],int_hist[2],int_hist[3],int_hist[4]);
$display("[tb_top_psmct32_sh3_real_draw_demo] min-texel-dist hist DEEP-INTERIOR(%0d px, seam-free): D0=%0d D1=%0d D2=%0d D3=%0d none=%0d",
deep_total, deep_hist[0],deep_hist[1],deep_hist[2],deep_hist[3],deep_hist[4]);
$display("[tb_top_psmct32_sh3_real_draw_demo] <=1texel ALL=%0d/%0d (%.1f%%) INT=%.1f%% DEEP=%.1f%% mean-delta=(%.3f,%.3f) clut_bad=%0d seam>1tex=%0d distinct=%0d cache_hits=%0d bram_hits=%0d",
match_ok, match_total, (match_total>0)?100.0*match_ok/match_total:0.0,
(int_total>0)?100.0*(int_hist[0]+int_hist[1])/int_total:0.0,
(deep_total>0)?100.0*(deep_hist[0]+deep_hist[1])/deep_total:0.0,
(n_drift>0)?sum_du/n_drift:0.0, (n_drift>0)?sum_dv/n_drift:0.0, clut_bad, seam_bad, distinct_seen,
tex_cache_hits, tex_bram_hits);
// Ch351 board-gate acceptance (Codex-approved): authentic palette ONLY (clut_bad=0), texels from LPDDR,
// NO systematic drift (|mean|<0.05), INTERIOR <=1 texel >=95%, and the seam-free DEEP interior is
// pixel-clean (D2+D3+none==0). Residuals worse than 1 texel live only in the clip/seam band (interior
// but near a triangle boundary, from the host-clip T-junctions) — reported as seam>1tex, not absorbed.
if (match_total < 4000) begin $error("too few covered pixels (%0d)", match_total); errors++; end
if (clut_bad != 0) begin $error("%0d covered pixels NOT a CLUT entry — wrong palette/CSM1", clut_bad); errors++; end
if (tex_cache_hits == 32'd0) begin $error("tex_cache_hits=0 — texels NOT served from LPDDR"); errors++; end
// DEEP (seam-free) zone must be tight: >=98% <=1 texel. The residual <2% is the irreducible dense-
// texture sub-texel-boundary effect (a correct sample at an exact texel edge picks an adjacent color in
// a 256-distinct texture) — NOT a perspective error (drift~0 proves the centers are right).
if (deep_total>0 && (100.0*(deep_hist[0]+deep_hist[1])/deep_total) < 98.0)
begin $error("DEEP-interior <=1 texel only %.1f%% (<98%%)", 100.0*(deep_hist[0]+deep_hist[1])/deep_total); errors++; end
if (int_total>0 && (100.0*(int_hist[0]+int_hist[1])/int_total) < 95.0)
begin $error("interior <=1 texel only %.1f%% (<95%%)", 100.0*(int_hist[0]+int_hist[1])/int_total); errors++; end
if (n_drift>0 && (sum_du/n_drift>0.05 || sum_du/n_drift<-0.05 || sum_dv/n_drift>0.05 || sum_dv/n_drift<-0.05))
begin $error("systematic drift (%.3f,%.3f) — |mean| must be <0.05", sum_du/n_drift, sum_dv/n_drift); errors++; end
if (distinct_seen < 8) begin $error("only %0d distinct colors — render collapsed", distinct_seen); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
if (errors==0) begin $display("[tb_top_psmct32_sh3_real_draw_demo] PASS"); $finish; end
else $fatal(1, "[tb_top_psmct32_sh3_real_draw_demo] FAIL (%0d errors)", errors);
end
initial begin #4000000000; $error("[tb_top_psmct32_sh3_real_draw_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_sh3_real_draw_demo
sim/tb/top/tb_top_psmct32_texalpha_demo.sv
+128
View File
@@ -0,0 +1,128 @@
// retroDE_ps2 — tb_top_psmct32_texalpha_demo (Ch344)
//
// TOP-LEVEL TEXTURED + source-over ALPHA SPRITE demo, end-to-end through the BRAM BOARD VARIANT
// (top_psmct32_raster_demo_bram) with SPRITE_TEX_ALPHA=1 — the integration the de25 board top fits,
// driving gs_stub through the REGISTERED read2 wrapper (the model the unit TB now matches).
//
// EE bootlet (bios_texalpha.mem) + GIF payload (payload_texalpha.mem):
// U1 -> upload an 8x8 checkerboard-ALPHA texture (opaque-white / fully-transparent).
// U2 -> opaque BG SPRITE (ABE=0), solid blue, full 64x64.
// U3 -> textured-alpha SPRITE (PRIM SPRITE+TME+ABE, source-over) over screen (16,16)-(48,48).
//
// Per pixel of the overlay: As = TEXEL alpha. Opaque texel (A=0x80) -> Cv = Cs (the gray texel,
// identity MODULATE by a white tint); transparent texel (A=0) -> Cv = Cd (the blue BG shows through).
//
// Verification (PCRTC scanout RGB — what a board wires to the video PHY):
// - the BORDER (outside the overlay rect) is the pure blue BG.
// - EVERY overlay pixel is EITHER gray (0xC0,0xC0,0xC0) OR blue BG — nothing else (binary alpha,
// no garbage), and BOTH appear in quantity (the checkerboard + per-texel alpha both rendered).
`timescale 1ns/1ps
module tb_top_psmct32_texalpha_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam int SX0 = 16, SY0 = 16, SX1 = 48, SY1 = 48; // overlay sprite rect
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.SPRITE_TEX_ALPHA(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// expected colors
localparam logic [7:0] BG_R=8'h00, BG_G=8'h00, BG_B=8'hC0; // blue BG
localparam logic [7:0] GR_R=8'hC0, GR_G=8'hC0, GR_B=8'hC0; // opaque-texel gray
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk)
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1; end
function automatic bit in_sprite(input int x, input int y);
in_sprite = (x>=SX0) && (x<SX1) && (y>=SY0) && (y<SY1);
endfunction
function automatic bit is_bg (input int x, input int y); is_bg = (cap_b[y][x]==BG_B)&&(cap_g[y][x]==BG_G)&&(cap_r[y][x]==BG_R); endfunction
function automatic bit is_gray(input int x, input int y); is_gray= (cap_b[y][x]==GR_B)&&(cap_g[y][x]==GR_G)&&(cap_r[y][x]==GR_R); endfunction
int errors, border_ok, spr_gray, spr_bg, spr_bad;
initial begin errors=0; border_ok=0; spr_gray=0; spr_bg=0; spr_bad=0; end
initial begin
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
if (dut.u_gs.raster_active==1'b1) wait (dut.u_gs.raster_active==1'b0);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
for (int y=0;y<V_ACTIVE;y++) begin
for (int x=0;x<H_ACTIVE;x++) begin
if (!cap_de[y][x]) begin
if (errors<8) $error("[texalpha] (%0d,%0d) DE never asserted", x, y); errors++;
end else if (in_sprite(x,y)) begin
if (is_gray(x,y)) spr_gray++;
else if (is_bg(x,y)) spr_bg++;
else begin
spr_bad++;
if (errors<12) $error("[texalpha] overlay (%0d,%0d)=(%02x,%02x,%02x) is neither gray nor BG",
x, y, cap_b[y][x], cap_g[y][x], cap_r[y][x]);
errors++;
end
end else begin
// border: pure BG
if (is_bg(x,y)) border_ok++;
else begin
if (errors<12) $error("[texalpha] border (%0d,%0d)=(%02x,%02x,%02x) not BG blue",
x, y, cap_b[y][x], cap_g[y][x], cap_r[y][x]);
errors++;
end
end
end
end
// The checkerboard + per-texel alpha must BOTH render (gray opaque checks AND BG-through checks).
if (spr_gray < 64) begin $error("[texalpha] too few opaque (gray) overlay px (%0d) — texel/blend dead", spr_gray); errors++; end
if (spr_bg < 64) begin $error("[texalpha] too few transparent overlay px (%0d) — texel ALPHA not honored", spr_bg); errors++; end
if (spr_bad != 0) begin $error("[texalpha] %0d overlay px were neither gray nor BG", spr_bad); errors++; end
if (raster_overflow) begin $error("[texalpha] raster_overflow set"); errors++; end
$display("[tb_top_psmct32_texalpha_demo] border_ok=%0d overlay gray=%0d bg=%0d bad=%0d emits=%0d errors=%0d",
border_ok, spr_gray, spr_bg, spr_bad, dut.u_gs.raster_pixel_emit_count, errors);
if (errors==0) begin $display("[tb_top_psmct32_texalpha_demo] PASS"); $finish; end
else $fatal(1, "[tb_top_psmct32_texalpha_demo] FAIL (%0d errors)", errors);
end
initial begin #30000000; $error("[tb_top_psmct32_texalpha_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_texalpha_demo
sim/tb/top/tb_top_psmct32_textured_demo.sv
+223
View File
@@ -0,0 +1,223 @@
// retroDE_ps2 — tb_top_psmct32_textured_demo (Brick 1)
//
// TOP-LEVEL textured-sprite demo TB. Proves the synthesizable textured
// SPRITE path renders end-to-end through the REAL hardware top
// (top_psmct32_raster_demo), exactly as a board load would:
//
// EE bootlet (bios_textured.mem) configures DISPFB1/DISPLAY1/PMODE
// and kicks DMAC ch2 to stream the GIF payload (payload_textured.mem):
// U1 BITBLT/TRX -> uploads an 8x8 PSMCT32 texture to VRAM (DBP=8)
// U2 IMAGE -> 16 qwords = the 64 texels
// U3/U4 PACKED -> PRIM(SPRITE+TME) + TEX0 + UV + XYZ2: a textured
// 8x8 sprite at screen (0,0)..(7,7)
// U5 PACKED -> a FLAT green control sprite at (8,0)..(15,7)
//
// The top is built with PSMCT32_SWIZZLE=0 so the LINEAR gs_texel_addr
// fetch and the BITBLT upload share one VRAM layout (v1 scope; the
// swizzle reconciliation is the gs_stub TODO, out of scope here).
//
// Verification is via the PCRTC scanout RGB (the same r/g/b/de a board
// wires to a video PHY) — so a PASS means the board would SHOW the
// texture:
// - Textured region x in [0..7]: scanout pixel == the uploaded texel
// for (x,y). Texel(x,y) ABGR = {A=FF, B=y, G=x, R=0x40}, and PCRTC
// PSMCT32 emits r=texel[7:0]=0x40, g=texel[15:8]=x, b=texel[23:16]=y.
// - Flat region x in [8..15]: scanout pixel == the flat green color
// (proves the TME=0 path still works alongside texturing).
// - The textured region must NOT be uniform (it's a real sampled
// gradient, not a flat fill) — guards against "texturing silently
// collapsed to flat."
`timescale 1ns/1ps
module tb_top_psmct32_textured_demo;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
// PSMCT32_SWIZZLE=0 so texture-upload (BITBLT) and texel-fetch
// (gs_texel_addr, linear) share one VRAM layout.
top_psmct32_raster_demo #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.PSMCT32_SWIZZLE(1'b0)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle)
);
// ----- Expected texel/scanout for the textured region -----
// Bold 2x2-quadrant texture (mirrors bake.py tex_demo_texel):
// (x<4,y<4)=RED (x>=4,y<4)=GREEN (x<4,y>=4)=BLUE (x>=4,y>=4)=YELLOW
// PCRTC PSMCT32 -> r=texel[7:0], g=texel[15:8], b=texel[23:16].
function automatic logic [7:0] tex_exp_r(input int x, input int y); return ((x<4)==(y<4)) ? 8'hFF : 8'h00; endfunction
function automatic logic [7:0] tex_exp_g(input int x, input int y); return (x>=4) ? 8'hFF : 8'h00; endfunction
function automatic logic [7:0] tex_exp_b(input int x, input int y); return ((x<4)&&(y>=4)) ? 8'hFF : 8'h00; endfunction
// Flat control sprite color: rgbaq_data(0x20, 0xC0, 0x40).
localparam logic [7:0] FLAT_R = 8'h20;
localparam logic [7:0] FLAT_G = 8'hC0;
localparam logic [7:0] FLAT_B = 8'h40;
// ----- Frame capture -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 8'd0;
cap_g[y][x] = 8'd0;
cap_b[y][x] = 8'd0;
cap_de[y][x] = 1'b0;
end
capture_armed = 1'b0;
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de
&& (dut.u_pcrtc.vcnt < V_ACTIVE)
&& (dut.u_pcrtc.hcnt < H_ACTIVE)) begin
cap_r [dut.u_pcrtc.vcnt][dut.u_pcrtc.hcnt] <= r;
cap_g [dut.u_pcrtc.vcnt][dut.u_pcrtc.hcnt] <= g;
cap_b [dut.u_pcrtc.vcnt][dut.u_pcrtc.hcnt] <= b;
cap_de[dut.u_pcrtc.vcnt][dut.u_pcrtc.hcnt] <= 1'b1;
end
end
int errors;
int tex_pixels_ok;
int distinct_tex_values;
logic [7:0] first_tex_g;
initial begin
errors = 0;
tex_pixels_ok = 0;
distinct_tex_values = 0;
end
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk);
core_go = 1'b1;
@(negedge clk);
core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1)
wait (dut.xfer_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1)
wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// --- Textured region (x in [0..7]) must match the uploaded texel. ---
for (int y = 0; y < 8; y++) begin
for (int x = 0; x < 8; x++) begin
logic [7:0] er, eg, eb;
er = tex_exp_r(x, y);
eg = tex_exp_g(x, y);
eb = tex_exp_b(x, y);
if (!cap_de[y][x]) begin
$error("textured (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
$error("[textured] (%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x)",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb);
errors = errors + 1;
end else begin
tex_pixels_ok = tex_pixels_ok + 1;
end
end
end
// --- The textured region must be a real gradient, not flat. ---
// (Guards against "texturing collapsed to a single texel / flat
// color".) Count how many distinct G values (= sampled u) appear
// across row 0.
first_tex_g = cap_g[0][0];
for (int x = 1; x < 8; x++)
if (cap_g[0][x] !== first_tex_g)
distinct_tex_values = distinct_tex_values + 1;
if (distinct_tex_values == 0) begin
$error("textured region is uniform (G all = %02x) — texturing collapsed to flat",
first_tex_g);
errors = errors + 1;
end
// --- Flat control region (x in [8..15]) must be the flat color. ---
for (int y = 0; y < 8; y++) begin
for (int x = 8; x < 16; x++) begin
if (!cap_de[y][x]) begin
$error("flat (%0d,%0d) DE never asserted", x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== FLAT_R || cap_g[y][x] !== FLAT_G || cap_b[y][x] !== FLAT_B) begin
$error("[flat] (%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x)",
x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], FLAT_R, FLAT_G, FLAT_B);
errors = errors + 1;
end
end
end
// --- Status bundle. ---
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_textured_demo] tex_ok=%0d/64 gradient_distinct=%0d raster_emits=%0d errors=%0d",
tex_pixels_ok, distinct_tex_values,
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_textured_demo] PASS");
else
$display("[tb_top_psmct32_textured_demo] FAIL");
$finish;
end
initial begin
#20000000;
$error("[tb_top_psmct32_textured_demo] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_textured_demo
sim/tb/top/tb_top_psmct32_tile2x2_demo.sv
+163
View File
@@ -0,0 +1,163 @@
// retroDE_ps2 — tb_top_psmct32_tile2x2_demo (Ch304)
//
// 2x2 MULTI-TILE renderer TB. ONE combined TME+ABE+ZTE triangle spanning the
// 32x32 region (a 2x2 grid of 16x16 tiles), crossing BOTH tile seams (x=16 and
// y=16). The renderer re-tests the triangle against each of the 4 tiles
// (CLEAR -> RENDER-clipped -> FLUSH per tile). Proves:
// PROOF GRID : all 4 tiles (col,row in {0,1}x{0,1}) clear independently
// (256 tile_color writes each) and flush (1024 FB emits total).
// PROOF SEAM : the WHOLE 32x32 scanout matches a SINGLE screen-space reference
// (one continuous barycentric function of screen x,y) — so the
// image is identical whether a pixel was rendered in tile (0,0)
// or its neighbour. Matching across x=15|16 and y=15|16 with NO
// discontinuity IS the seam proof. (Plus an explicit seam-pixel
// match count.)
// PROOF DEPTH/BLEND : top half blended (red->orange / blue->teal over green),
// bottom half occluded green — same per-pixel rule as Ch302/303.
`timescale 1ns/1ps
module tb_top_psmct32_tile2x2_demo;
localparam int H_ACTIVE = 32, V_ACTIVE = 32;
localparam int TP_CLEAR=1, TP_FLUSH=3;
localparam int ZBG = 'h4000;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(2), .TILE_ROWS(2)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// ---- single screen-space reference: triangle v0(3,3) v1(28,3) v2(16,29) ----
function automatic real bdet(input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bdet=(by-cy)*(ax-cx)+(cx-bx)*(ay-cy); endfunction
function automatic real bwa(input real px,input real py,input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bwa=((by-cy)*(px-cx)+(cx-bx)*(py-cy))/bdet(ax,ay,bx,by,cx,cy); endfunction
function automatic real bwb(input real px,input real py,input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bwb=((cy-ay)*(px-cx)+(ax-cx)*(py-cy))/bdet(ax,ay,bx,by,cx,cy); endfunction
// ---- grid tracers ----
int clear_cw_tile [0:1][0:1]; // tile_color writes per (row,col) during CLEAR
int flush_emits;
initial begin
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++) clear_cw_tile[rr][cc]=0;
flush_emits=0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int cc, rr; cc=int'(dut.u_gs.tile_col_r); rr=int'(dut.u_gs.tile_row_r);
if (cc<2 && rr<2) clear_cw_tile[rr][cc] <= clear_cw_tile[rr][cc] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1; // tile mode: only flush emits
end
// ---- scanout capture (32x32) ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_seam;
initial begin
errors=0; n_match=0; n_check=0; n_seam=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active); // grid render begins
@(negedge dut.u_gs.raster_active); // all 4 tiles done (clear+render+flush)
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// PROOF GRID — each of the 4 tiles cleared independently + total flushes.
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++)
if (clear_cw_tile[rr][cc] != 256) begin
$error("[t2x2] tile(col=%0d,row=%0d) cleared %0d color entries (want 256)", cc, rr, clear_cw_tile[rr][cc]); errors++;
end
if (flush_emits != 4*256) begin $error("[t2x2] flush emitted %0d (want %0d)", flush_emits, 4*256); errors++; end
// PROOF SEAM + DEPTH/BLEND — whole 32x32 vs ONE screen-space reference.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
real wa, wb, wc, fragz, uu;
bit clearly_in, clearly_out;
logic [7:0] er, eg, eb;
wa = bwa(px,py, 3,3, 28,3, 16,29);
wb = bwb(px,py, 3,3, 28,3, 16,29);
wc = 1.0 - wa - wb;
clearly_in = (wa>0.06)&&(wb>0.06)&&(wc>0.06);
clearly_out = (wa<-0.06)||(wb<-0.06)||(wc<-0.06);
fragz = (wa+wb)*real'('h6000) + wc*real'('h2000);
// expected color
if (clearly_out) begin er=8'h00; eg=8'h80; eb=8'h00; end // green clear
else if (clearly_in && (fragz <= real'(ZBG)-1024.0)) begin er=8'h00; eg=8'h80; eb=8'h00; end // occluded green
else if (clearly_in && (fragz >= real'(ZBG)+1024.0)) begin
uu = wb*7.0 + wc*3.0;
if (uu < 3.5) begin er=8'd127; eg=8'd64; eb=8'd0; end
else if (uu > 4.5) begin er=8'd0; eg=8'd64; eb=8'd127; end
else begin er=8'hxx; eg=8'hxx; eb=8'hxx; end // cell-boundary: skip
end else begin er=8'hxx; eg=8'hxx; eb=8'hxx; end // edge/Z-boundary: skip
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
if (cap_r[py][px]===er && cap_g[py][px]===eg && cap_b[py][px]===eb) begin
n_match++;
if (px==15||px==16||py==15||py==16) n_seam++; // seam-region pixels that matched
end else begin
if (errors<12) $error("[t2x2] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb);
errors++;
end
end
end
end
if (n_check < 200) begin $error("[t2x2] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[t2x2] image match %0d/%0d (seam/tiling error)", n_match, n_check); errors++; end
if (n_seam < 20) begin $error("[t2x2] too few SEAM-region matches (%0d) — seam not exercised", n_seam); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile2x2_demo] clears(per-tile)=[%0d %0d %0d %0d] flush=%0d match=%0d/%0d seam_matches=%0d errors=%0d",
clear_cw_tile[0][0],clear_cw_tile[0][1],clear_cw_tile[1][0],clear_cw_tile[1][1], flush_emits, n_match, n_check, n_seam, errors);
if (errors==0) $display("[tb_top_psmct32_tile2x2_demo] PASS");
else $display("[tb_top_psmct32_tile2x2_demo] FAIL");
$finish;
end
initial begin #250000000; $error("[tb_top_psmct32_tile2x2_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile2x2_demo
sim/tb/top/tb_top_psmct32_tile_alpha_demo.sv
+180
View File
@@ -0,0 +1,180 @@
// retroDE_ps2 — tb_top_psmct32_tile_alpha_demo (Ch309)
//
// GS ALPHA mode expansion. The Ch305 3-primitive scene over a 2x2 tile grid, but
// P1 uses the ADDITIVE blend mode (Cv=((Cs-0)*FIX>>7)+Cd with FIX=0x80 => Cs+Cd
// clamped) instead of source-over, so two visibly-different blend equations coexist:
// P0 blue bg : source-over (A=Cs,B=Cd,C=As,D=Cd, As=0x80 -> opaque blue).
// P1 red : ADDITIVE over the blue bg -> MAGENTA (255,0,255) (brighten/glow).
// P2 white : source-over translucent (A=0x40) -> light-blue over blue.
//
// PROOFS:
// ADDITIVE : the P1 region is MAGENTA (Cs+Cd clamped), not red -> additive + FIX work.
// SOURCE-OVER preserved : P2 light-blue (127,127,255) over blue -> source-over unchanged.
// DEPTH : P2 occluded by P1 (Z 0x5800 < 0x6000) -> magenta shows, not blended.
// IMAGE : whole 32x32 matches the per-mode software reference.
// GRID : 4 tiles cleared (256 each) + 1024 flush; prim list = 3.
`timescale 1ns/1ps
module tb_top_psmct32_tile_alpha_demo;
localparam int H_ACTIVE = 32, V_ACTIVE = 32;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.08;
localparam int Z0 = 'h5000, Z1 = 'h6000, Z2 = 'h5800, ZCLR = 'h4000;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(2), .TILE_ROWS(2),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3), .ALPHA_MODES_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
// source-over channel: clamp(((cs-cd)*as>>>7)+cd)
function automatic logic [7:0] sovr(input int cs, input int cd, input int aa);
int t; begin t=((cs-cd)*aa)>>>7; t=t+cd; if(t<0)t=0; if(t>255)t=255; sovr=t[7:0]; end
endfunction
// additive channel (FIX=0x80): clamp(((cs-0)*128>>>7)+cd) = clamp(cs+cd)
function automatic logic [7:0] addc(input int cs, input int cd);
int t; begin t=((cs-0)*'h80)>>>7; t=t+cd; if(t<0)t=0; if(t>255)t=255; addc=t[7:0]; end
endfunction
int clear_cw_tile [0:1][0:1];
int flush_emits;
bit saw_prim_count_3;
initial begin
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++) clear_cw_tile[rr][cc]=0;
flush_emits=0; saw_prim_count_3=1'b0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int cc, rr; cc=int'(dut.u_gs.tile_col_r); rr=int'(dut.u_gs.tile_row_r);
if (cc<2 && rr<2) clear_cw_tile[rr][cc] <= clear_cw_tile[rr][cc] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==3)) saw_prim_count_3 <= 1'b1;
end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_seam, n_magenta, n_lblue;
initial begin
errors=0; n_match=0; n_check=0; n_seam=0; n_magenta=0; n_lblue=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++)
if (clear_cw_tile[rr][cc] != 256) begin
$error("[tal] tile(col=%0d,row=%0d) cleared %0d (want 256)", cc, rr, clear_cw_tile[rr][cc]); errors++;
end
if (flush_emits != 4*256) begin $error("[tal] flush emitted %0d (want %0d)", flush_emits, 4*256); errors++; end
if (!saw_prim_count_3) begin $error("[tal] prim_count_r never == 3"); errors++; end
// reference: P0 source-over (blue) -> P1 ADDITIVE (red) -> P2 source-over (white)
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int c0, c1, c2, zz; logic [7:0] cr, cg, cb, er, eg, eb;
c0 = tri_cls(real'(px),real'(py), 1, 1, 30, 1, 15,30);
c1 = tri_cls(real'(px),real'(py), 8, 3, 22, 3, 15,20);
c2 = tri_cls(real'(px),real'(py), 7, 9, 23, 9, 15,28);
if (c0==2 || c1==2 || c2==2) begin er=8'hxx; eg=8'hxx; eb=8'hxx; end
else begin
cr=0; cg=128; cb=0; zz=ZCLR;
if (c0==1 && Z0>=zz) begin cr=sovr(0,cr,'h80); cg=sovr(0,cg,'h80); cb=sovr(255,cb,'h80); zz=Z0; end // blue src-over
if (c1==1 && Z1>=zz) begin cr=addc(255,cr); cg=addc(0,cg); cb=addc(0,cb); zz=Z1; end // red ADDITIVE
if (c2==1 && Z2>=zz) begin cr=sovr(255,cr,'h40); cg=sovr(255,cg,'h40); cb=sovr(255,cb,'h40); zz=Z2; end // white src-over
er=cr; eg=cg; eb=cb;
end
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
if (er==8'hFF && eg==8'h00 && eb==8'hFF) n_magenta++; // additive red over blue
if (er==8'h7F && eg==8'h7F && eb==8'hFF) n_lblue++; // source-over white over blue
if (cap_r[py][px]===er && cap_g[py][px]===eg && cap_b[py][px]===eb) begin
n_match++;
if (px==15||px==16||py==15||py==16) n_seam++;
end else begin
if (errors<14) $error("[tal] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x) [c0%0d c1%0d c2%0d]",
px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb,c0,c1,c2);
errors++;
end
end
end
end
if (n_check < 200) begin $error("[tal] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[tal] image match %0d/%0d (alpha-mode error)", n_match, n_check); errors++; end
if (n_magenta < 10) begin $error("[tal] ADDITIVE (magenta) region thin (%0d) — additive not proven", n_magenta); errors++; end
if (n_lblue < 10) begin $error("[tal] source-over (light-blue) thin (%0d) — src-over regressed?", n_lblue); errors++; end
if (n_seam < 15) begin $error("[tal] too few SEAM matches (%0d)", n_seam); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_alpha_demo] clears=[%0d %0d %0d %0d] flush=%0d prim3=%0b match=%0d/%0d seam=%0d | magenta=%0d lblue=%0d errors=%0d",
clear_cw_tile[0][0],clear_cw_tile[0][1],clear_cw_tile[1][0],clear_cw_tile[1][1],
flush_emits, saw_prim_count_3, n_match, n_check, n_seam, n_magenta, n_lblue, errors);
if (errors==0) $display("[tb_top_psmct32_tile_alpha_demo] PASS");
else $display("[tb_top_psmct32_tile_alpha_demo] FAIL");
$finish;
end
initial begin #300000000; $error("[tb_top_psmct32_tile_alpha_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_alpha_demo
sim/tb/top/tb_top_psmct32_tile_bilinear_demo.sv
+178
View File
@@ -0,0 +1,178 @@
// retroDE_ps2 — tb_top_psmct32_tile_bilinear_demo (Ch310 Phase 2)
//
// BILINEAR filtering integrated into the combined tiled renderer. Two triangles
// sample the SAME magnified 4x4 blue/white CHECKER (UV 0..4 over a ~12px-wide tri
// -> ~3 px/texel, so the affine interp produces fractional U/V), with different
// TEX1.MMAG:
// LEFT tri (x2..14, TEX1.MMAG=0, NEAREST): blocky checker — every pixel is one
// of the 2 texel colors, NO midtones.
// RIGHT tri (x18..30, TEX1.MMAG=1, LINEAR): smoothed — midtone (light-blue)
// pixels appear at texel boundaries.
// Checker colors blue (0,0,255) / white (255,255,255), b==255 in both; bilinear
// blends give r=g in (0,255), b=255 (a midtone). Green clear has b==0.
//
// The EXACT 4-tap math is proven separately by tb_gs_texture_bilinear; this board
// TB proves the DISTINCTION on silicon + that the combined FSM correctly stalls for
// the multi-beat sample (color writes happen — the bilinear tri renders fully).
//
// PROOFS:
// NEAREST blocky : LEFT tri has ZERO midtone pixels (only pure blue/white).
// BILINEAR smooth: RIGHT tri has >=N midtone pixels (4-tap blends at boundaries).
// RENDERED : both tris paint a healthy number of checker pixels (the
// ~9-cyc stall did not drop the bilinear prim).
// GRID : 4 tiles cleared (256 each) + 1024 flush; prim list = 2.
`timescale 1ns/1ps
module tb_top_psmct32_tile_bilinear_demo;
localparam int H_ACTIVE = 32, V_ACTIVE = 32;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.10;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(2), .TILE_ROWS(2),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(2), .BILINEAR_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
int clear_cw_tile [0:1][0:1];
int flush_emits;
bit saw_prim_count_2;
initial begin
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++) clear_cw_tile[rr][cc]=0;
flush_emits=0; saw_prim_count_2=1'b0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int cc, rr; cc=int'(dut.u_gs.tile_col_r); rr=int'(dut.u_gs.tile_row_r);
if (cc<2 && rr<2) clear_cw_tile[rr][cc] <= clear_cw_tile[rr][cc] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==2)) saw_prim_count_2 <= 1'b1;
end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors;
int n_near_tex, n_near_mid, n_bil_tex, n_bil_mid;
// a checker pixel = b high (>=200). midtone = checker AND r strictly between
// the two pure values (not 0, not 255).
function automatic bit is_checker(input logic [7:0] rr, input logic [7:0] gg, input logic [7:0] bb);
is_checker = (bb >= 8'd200);
endfunction
function automatic bit is_midtone(input logic [7:0] rr, input logic [7:0] gg, input logic [7:0] bb);
is_midtone = (bb >= 8'd200) && (rr > 8'd16) && (rr < 8'd239);
endfunction
initial begin
errors=0; n_near_tex=0; n_near_mid=0; n_bil_tex=0; n_bil_mid=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++)
if (clear_cw_tile[rr][cc] != 256) begin
$error("[bil] tile(col=%0d,row=%0d) cleared %0d (want 256)", cc, rr, clear_cw_tile[rr][cc]); errors++;
end
if (flush_emits != 4*256) begin $error("[bil] flush emitted %0d (want %0d)", flush_emits, 4*256); errors++; end
if (!saw_prim_count_2) begin $error("[bil] prim_count_r never == 2"); errors++; end
// classify each pixel: LEFT (nearest) tri vs RIGHT (bilinear) tri.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int cl, cr2;
logic [7:0] rr, gg, bb;
if (cap_de[py][px]) begin
rr=cap_r[py][px]; gg=cap_g[py][px]; bb=cap_b[py][px];
cl = tri_cls(real'(px),real'(py), 2, 4, 14, 4, 2,26); // LEFT nearest
cr2 = tri_cls(real'(px),real'(py), 18, 4, 30, 4, 18,26); // RIGHT bilinear
if (cl==1) begin // clearly inside LEFT
if (is_checker(rr,gg,bb)) n_near_tex++;
if (is_midtone(rr,gg,bb)) n_near_mid++;
end
if (cr2==1) begin // clearly inside RIGHT
if (is_checker(rr,gg,bb)) n_bil_tex++;
if (is_midtone(rr,gg,bb)) n_bil_mid++;
end
end
end
end
// PROOFS
if (n_near_tex < 30) begin $error("[bil] LEFT(nearest) too few checker pixels (%0d) — not rendered", n_near_tex); errors++; end
if (n_bil_tex < 30) begin $error("[bil] RIGHT(bilinear) too few checker pixels (%0d) — ~9cyc stall dropped the prim?", n_bil_tex); errors++; end
if (n_near_mid != 0) begin $error("[bil] NEAREST produced %0d midtone pixels — should be blocky (0)", n_near_mid); errors++; end
if (n_bil_mid < 10) begin $error("[bil] BILINEAR produced only %0d midtones — not smoothing", n_bil_mid); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_bilinear_demo] clears=[%0d %0d %0d %0d] flush=%0d prim2=%0b | nearTex=%0d nearMid=%0d bilTex=%0d bilMid=%0d errors=%0d",
clear_cw_tile[0][0],clear_cw_tile[0][1],clear_cw_tile[1][0],clear_cw_tile[1][1],
flush_emits, saw_prim_count_2, n_near_tex, n_near_mid, n_bil_tex, n_bil_mid, errors);
if (errors==0) $display("[tb_top_psmct32_tile_bilinear_demo] PASS");
else $display("[tb_top_psmct32_tile_bilinear_demo] FAIL");
$finish;
end
initial begin #400000000; $error("[tb_top_psmct32_tile_bilinear_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_bilinear_demo
sim/tb/top/tb_top_psmct32_tile_bin4x4_demo.sv
+209
View File
@@ -0,0 +1,209 @@
// retroDE_ps2 — tb_top_psmct32_tile_bin4x4_demo (Ch312)
//
// Scale the tiled renderer to a 4x4 grid (16 tiles, 16x16 each = 64x64), reusing
// the Ch311 bin-buffer mechanism. Three prims stress the larger grid:
// P0 blue (Z5000): top-left, bbox tiles t0,1,4,5 (4 tiles)
// P1 red (Z6000): mid, crosses x=16/32/48 & y=16/32 seams, bbox t5,6,7,9,10,11 (6)
// P2 white(Z5800): bottom-right corner tile t15 ONLY (1 tile)
// EMPTY tiles t2,3,8,12,13,14 -> no prim -> stay clear.
// Prim idx P0=0,P1=1,P2=2. Tile t=row*4+col; bounds (col*16,row*16)+15.
//
// PROOFS:
// BIN COUNTS : bin_n[t] for ALL 16 tiles == # prims whose bbox overlaps tile t
// (so each prim is in every overlapping bin, none else; empty=0).
// BIN ORDER : the one multi-prim tile (t5) lists {P0,P1} in draw order.
// EMPTY CLEAR : empty-tile pixels are clear green.
// IMAGE : whole 64x64 matches the screen-space re-test reference (depth+blend),
// with seam continuity across multiple x (16/32/48) & y (16/32) seams.
// GRID : 16 tiles cleared (256 each) + 16*256 flush; prim list = 3.
`timescale 1ns/1ps
module tb_top_psmct32_tile_bin4x4_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.10;
localparam int Z0 = 'h5000, Z1 = 'h6000, Z2 = 'h5800, ZCLR = 'h4000;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3), .BIN_BUFFER_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
function automatic logic [7:0] sovr(input int cs, input int cd, input int aa);
int t; begin t=((cs-cd)*aa)>>>7; t=t+cd; if(t<0)t=0; if(t>255)t=255; sovr=t[7:0]; end
endfunction
// expected: prim p's bbox overlaps tile t? (bboxes match bake.py Ch312 verts)
function automatic bit binx(input int p, input int t);
int xl,xh,yl,yh,tx0,tx1,ty0,ty1;
begin
case (p)
0: begin xl=2; xh=30; yl=2; yh=30; end // P0
1: begin xl=20; xh=50; yl=18; yh=40; end // P1
default: begin xl=52; xh=60; yl=52; yh=60; end // P2
endcase
tx0=(t%4)*16; tx1=tx0+15; ty0=(t/4)*16; ty1=ty0+15;
binx = !((xl>tx1)||(xh<tx0)||(yl>ty1)||(yh<ty0));
end
endfunction
int clear_cw [0:15];
int flush_emits; bit saw_prim_count_3;
initial begin for(int t=0;t<16;t++) clear_cw[t]=0; flush_emits=0; saw_prim_count_3=0; end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int t; t=int'(dut.u_gs.tile_row_r)*4 + int'(dut.u_gs.tile_col_r);
if (t>=0 && t<16) clear_cw[t] <= clear_cw[t] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==3)) saw_prim_count_3 <= 1'b1;
end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_seam, n_empty_chk;
int bnv [0:15]; // bin_n read-back (constant indices)
int b5_0, b5_1; // t5 bin slots (the only multi-prim tile)
initial begin
errors=0; n_match=0; n_check=0; n_seam=0; n_empty_chk=0;
for(int t=0;t<16;t++) bnv[t]=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
// grab all 16 bin_n + t5's two slots (constant indices; stable post-binning)
bnv[0]=int'(dut.u_gs.bin_n[0]); bnv[1]=int'(dut.u_gs.bin_n[1]);
bnv[2]=int'(dut.u_gs.bin_n[2]); bnv[3]=int'(dut.u_gs.bin_n[3]);
bnv[4]=int'(dut.u_gs.bin_n[4]); bnv[5]=int'(dut.u_gs.bin_n[5]);
bnv[6]=int'(dut.u_gs.bin_n[6]); bnv[7]=int'(dut.u_gs.bin_n[7]);
bnv[8]=int'(dut.u_gs.bin_n[8]); bnv[9]=int'(dut.u_gs.bin_n[9]);
bnv[10]=int'(dut.u_gs.bin_n[10]); bnv[11]=int'(dut.u_gs.bin_n[11]);
bnv[12]=int'(dut.u_gs.bin_n[12]); bnv[13]=int'(dut.u_gs.bin_n[13]);
bnv[14]=int'(dut.u_gs.bin_n[14]); bnv[15]=int'(dut.u_gs.bin_n[15]);
b5_0=int'(dut.u_gs.bin_prim[5][0]); b5_1=int'(dut.u_gs.bin_prim[5][1]);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// PROOF GRID
for (int t=0;t<16;t++)
if (clear_cw[t] != 256) begin $error("[b4] tile %0d cleared %0d (want 256)", t, clear_cw[t]); errors++; end
if (flush_emits != 16*256) begin $error("[b4] flush emitted %0d (want %0d)", flush_emits, 16*256); errors++; end
if (!saw_prim_count_3) begin $error("[b4] prim_count_r never == 3"); errors++; end
// PROOF BIN COUNTS — every tile's bin_n == # overlapping prims (incl. empty=0).
for (int t=0;t<16;t++) begin
int exp_n; exp_n=0;
for (int p=0;p<3;p++) if (binx(p,t)) exp_n++;
if (bnv[t] !== exp_n) begin $error("[b4] tile %0d bin_n=%0d, want %0d", t, bnv[t], exp_n); errors++; end
end
// PROOF BIN ORDER — t5 has both P0(0) and P1(1), in draw order.
if (b5_0 !== 0 || b5_1 !== 1) begin $error("[b4] tile5 bin = {%0d,%0d}, want {0,1}", b5_0, b5_1); errors++; end
$display("[b4] bin_n[0..15]=%0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d t5={%0d,%0d}",
bnv[0],bnv[1],bnv[2],bnv[3],bnv[4],bnv[5],bnv[6],bnv[7],bnv[8],bnv[9],bnv[10],bnv[11],bnv[12],bnv[13],bnv[14],bnv[15],b5_0,b5_1);
// PROOF IMAGE — re-test reference: P0 blue (src-over), P1 red (src-over),
// P2 white (src-over translucent A=0x40 over green clear), depth GEQUAL.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int c0,c1,c2,cr,cg,cb,zz; logic [7:0] er,eg,eb; bit scene_here, in_empty;
c0 = tri_cls(real'(px),real'(py), 2, 2, 30, 2, 2,30);
c1 = tri_cls(real'(px),real'(py), 20,18, 50,18, 35,40);
c2 = tri_cls(real'(px),real'(py), 52,52, 60,52, 52,60);
if (c0==2||c1==2||c2==2) begin er=8'hxx;eg=8'hxx;eb=8'hxx; end
else begin
scene_here = (c0==1)||(c1==1)||(c2==1);
cr=0;cg=128;cb=0;zz=ZCLR;
if (c0==1 && Z0>=zz) begin cr=sovr(0,cr,'h80); cg=sovr(0,cg,'h80); cb=sovr(255,cb,'h80); zz=Z0; end
if (c1==1 && Z1>=zz) begin cr=sovr(255,cr,'h80); cg=sovr(0,cg,'h80); cb=sovr(0,cb,'h80); zz=Z1; end
if (c2==1 && Z2>=zz) begin cr=sovr(255,cr,'h40); cg=sovr(255,cg,'h40); cb=sovr(255,cb,'h40); zz=Z2; end
er=cr[7:0]; eg=cg[7:0]; eb=cb[7:0];
// empty-tile sanity: a clearly-out-of-all pixel in an empty tile is green
if (!scene_here) in_empty=1;
end
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
if (in_empty && er==8'h00&&eg==8'h80&&eb==8'h00) n_empty_chk++;
if (cap_r[py][px]===er&&cap_g[py][px]===eg&&cap_b[py][px]===eb) begin
n_match++;
if (px==15||px==16||px==31||px==32||px==47||px==48||py==15||py==16||py==31||py==32) n_seam++;
end else begin
if (errors<14) $error("[b4] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb);
errors++;
end
end
end
end
if (n_check < 400) begin $error("[b4] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[b4] image match %0d/%0d (4x4 routing error)", n_match, n_check); errors++; end
if (n_empty_chk < 100) begin $error("[b4] too few empty-tile-clear pixels (%0d)", n_empty_chk); errors++; end
if (n_seam < 40) begin $error("[b4] too few SEAM matches (%0d) — 4x4 seams not exercised", n_seam); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_bin4x4_demo] tiles_cleared(all256)=%0b flush=%0d prim3=%0b match=%0d/%0d seam=%0d empty=%0d errors=%0d",
(flush_emits==16*256), flush_emits, saw_prim_count_3, n_match, n_check, n_seam, n_empty_chk, errors);
if (errors==0) $display("[tb_top_psmct32_tile_bin4x4_demo] PASS");
else $display("[tb_top_psmct32_tile_bin4x4_demo] FAIL");
$finish;
end
initial begin #600000000; $error("[tb_top_psmct32_tile_bin4x4_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_bin4x4_demo
sim/tb/top/tb_top_psmct32_tile_bin_demo.sv
+217
View File
@@ -0,0 +1,217 @@
// retroDE_ps2 — tb_top_psmct32_tile_bin_demo (Ch311)
//
// Per-tile BIN BUFFER. Three primitives with distinct tile coverage over the 2x2
// grid; a binning pass precomputes per-tile primitive-index lists, and each tile
// renders only its bin (vs the Ch305 re-test-every-prim-per-tile path).
// P0 blue bg (Z=0x5000): bbox all 4 tiles -> in every bin.
// P1 red (Z=0x6000): bbox tiles (0,0)+(1,0) only (2 bins).
// P2 white (Z=0x5800): bbox tile (1,1) only (1 bin).
// Prim indices P0=0,P1=1,P2=2. Tile index t=row*2+col: t0=(0,0) t1=(1,0) t2=(0,1) t3=(1,1).
// Expected bins: t0={0,1} t1={0,1} t2={0} t3={0,2}.
//
// PROOFS:
// BIN CONTENTS : bin_n/bin_prim match exactly — each prim appears in EVERY
// overlapping tile bin, in NO non-overlapping bin, draw order kept.
// IMAGE : the whole 32x32 scanout matches a single screen-space re-test
// reference (P0,P1,P2 replayed with depth + blend) — so routing
// through bins produces the SAME image; seams clean.
// GRID : 4 tiles cleared (256 each) + 1024 flush; prim list = 3.
`timescale 1ns/1ps
module tb_top_psmct32_tile_bin_demo;
localparam int H_ACTIVE = 32, V_ACTIVE = 32;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.08;
localparam int Z0 = 'h5000, Z1 = 'h6000, Z2 = 'h5800, ZCLR = 'h4000;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(2), .TILE_ROWS(2),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3), .BIN_BUFFER_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
function automatic logic [7:0] sovr(input int cs, input int cd, input int aa);
int t; begin t=((cs-cd)*aa)>>>7; t=t+cd; if(t<0)t=0; if(t>255)t=255; sovr=t[7:0]; end
endfunction
int clear_cw_tile [0:1][0:1];
int flush_emits;
bit saw_prim_count_3;
initial begin
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++) clear_cw_tile[rr][cc]=0;
flush_emits=0; saw_prim_count_3=1'b0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int cc, rr; cc=int'(dut.u_gs.tile_col_r); rr=int'(dut.u_gs.tile_row_r);
if (cc<2 && rr<2) clear_cw_tile[rr][cc] <= clear_cw_tile[rr][cc] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==3)) saw_prim_count_3 <= 1'b1;
end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_seam, n_red, n_lgreen;
// bins are stable from end-of-TP_BIN through the whole grid render and after
// (not cleared until the next grid start). Read them with CONSTANT indices
// post-render (iverilog cross-module array binds need constant, not loop-var).
int bn [0:3]; int bp [0:3][0:3];
initial begin for(int t=0;t<4;t++) begin bn[t]=0; for(int s=0;s<4;s++) bp[t][s]=0; end end
// expected bin (prim idx) helper: returns 1 if prim p should be in tile t's bin
// (bbox-overlap), via the same bbox-vs-tile test the hw bins on.
function automatic bit binx(input int p, input int t);
int xl,xh,yl,yh, tcx0,tcx1,tcy0,tcy1;
begin
// prim bboxes (must match bake.py Ch311 verts)
case (p)
0: begin xl=1; xh=30; yl=1; yh=30; end // P0
1: begin xl=8; xh=24; yl=2; yh=12; end // P1
default: begin xl=20; xh=28; yl=20; yh=28; end // P2
endcase
tcx0=(t%2)*16; tcx1=tcx0+15; tcy0=(t/2)*16; tcy1=tcy0+15;
binx = !((xl>tcx1)||(xh<tcx0)||(yl>tcy1)||(yh<tcy0));
end
endfunction
initial begin
errors=0; n_match=0; n_check=0; n_seam=0; n_red=0; n_lgreen=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
// grab bins (constant indices; stable after binning through end-of-grid)
bn[0]=int'(dut.u_gs.bin_n[0]); bn[1]=int'(dut.u_gs.bin_n[1]); bn[2]=int'(dut.u_gs.bin_n[2]); bn[3]=int'(dut.u_gs.bin_n[3]);
bp[0][0]=int'(dut.u_gs.bin_prim[0][0]); bp[0][1]=int'(dut.u_gs.bin_prim[0][1]);
bp[1][0]=int'(dut.u_gs.bin_prim[1][0]); bp[1][1]=int'(dut.u_gs.bin_prim[1][1]);
bp[2][0]=int'(dut.u_gs.bin_prim[2][0]); bp[2][1]=int'(dut.u_gs.bin_prim[2][1]);
bp[3][0]=int'(dut.u_gs.bin_prim[3][0]); bp[3][1]=int'(dut.u_gs.bin_prim[3][1]);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++)
if (clear_cw_tile[rr][cc] != 256) begin
$error("[bn] tile(col=%0d,row=%0d) cleared %0d (want 256)", cc, rr, clear_cw_tile[rr][cc]); errors++;
end
if (flush_emits != 4*256) begin $error("[bn] flush emitted %0d (want %0d)", flush_emits, 4*256); errors++; end
if (!saw_prim_count_3) begin $error("[bn] prim_count_r never == 3"); errors++; end
// PROOF BIN CONTENTS — every overlapping prim in the bin (draw order), none else.
for (int t=0;t<4;t++) begin
int exp_n, sidx;
exp_n=0;
for (int p=0;p<3;p++) if (binx(p,t)) begin
if (bp[t][exp_n] !== p) begin
$error("[bn] tile %0d bin slot %0d = prim %0d, want %0d (order/contents)", t, exp_n, bp[t][exp_n], p); errors++;
end
exp_n++;
end
if (bn[t] !== exp_n) begin $error("[bn] tile %0d bin_n=%0d, want %0d", t, bn[t], exp_n); errors++; end
end
$display("[bn] bins: t0(n=%0d:%0d,%0d) t1(n=%0d:%0d,%0d) t2(n=%0d:%0d) t3(n=%0d:%0d,%0d)",
bn[0],bp[0][0],bp[0][1], bn[1],bp[1][0],bp[1][1], bn[2],bp[2][0], bn[3],bp[3][0],bp[3][1]);
// PROOF IMAGE — re-test reference: P0 blue (src-over opaque), P1 red (opaque),
// P2 white (src-over translucent A=0x40), depth GEQUAL write-on-pass.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int c0,c1,c2,cr,cg,cb,zz; logic [7:0] er,eg,eb;
c0 = tri_cls(real'(px),real'(py), 1, 1, 30, 1, 15,30);
c1 = tri_cls(real'(px),real'(py), 8, 2, 24, 2, 16,12);
c2 = tri_cls(real'(px),real'(py), 20,20, 28,20, 20,28);
if (c0==2||c1==2||c2==2) begin er=8'hxx;eg=8'hxx;eb=8'hxx; end
else begin
cr=0;cg=128;cb=0;zz=ZCLR;
if (c0==1 && Z0>=zz) begin cr=sovr(0,cr,'h80); cg=sovr(0,cg,'h80); cb=sovr(255,cb,'h80); zz=Z0; end
if (c1==1 && Z1>=zz) begin cr=sovr(255,cr,'h80); cg=sovr(0,cg,'h80); cb=sovr(0,cb,'h80); zz=Z1; end
if (c2==1 && Z2>=zz) begin cr=sovr(255,cr,'h40); cg=sovr(255,cg,'h40); cb=sovr(255,cb,'h40); zz=Z2; end
er=cr[7:0]; eg=cg[7:0]; eb=cb[7:0];
end
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
if (er==8'hFF&&eg==8'h00&&eb==8'h00) n_red++;
if (er==8'h7F&&eg==8'hBF&&eb==8'h7F) n_lgreen++; // P2 white over GREEN clear
if (cap_r[py][px]===er&&cap_g[py][px]===eg&&cap_b[py][px]===eb) begin
n_match++; if (px==15||px==16||py==15||py==16) n_seam++;
end else begin
if (errors<14) $error("[bn] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb);
errors++;
end
end
end
end
if (n_check < 150) begin $error("[bn] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[bn] image match %0d/%0d (bin routing error)", n_match, n_check); errors++; end
if (n_red < 8) begin $error("[bn] RED region thin (%0d) — P1 not binned/rendered", n_red); errors++; end
if (n_lgreen < 4) begin $error("[bn] LIGHT-GREEN thin (%0d) — P2 (1-tile prim) not binned/rendered", n_lgreen); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_bin_demo] clears=[%0d %0d %0d %0d] flush=%0d prim3=%0b match=%0d/%0d seam=%0d | red=%0d lgreen=%0d errors=%0d",
clear_cw_tile[0][0],clear_cw_tile[0][1],clear_cw_tile[1][0],clear_cw_tile[1][1],
flush_emits, saw_prim_count_3, n_match, n_check, n_seam, n_red, n_lgreen, errors);
if (errors==0) $display("[tb_top_psmct32_tile_bin_demo] PASS");
else $display("[tb_top_psmct32_tile_bin_demo] FAIL");
$finish;
end
initial begin #300000000; $error("[tb_top_psmct32_tile_bin_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_bin_demo
sim/tb/top/tb_top_psmct32_tile_cap64_demo.sv
+235
View File
@@ -0,0 +1,235 @@
// retroDE_ps2 — tb_top_psmct32_tile_cap64_demo (Ch315)
//
// PRIMITIVE/BIN CAPACITY scaling. The 4x4 (64x64) grid with TILE_FIFO_DEPTH=8 and
// SEVEN prims (vs Ch312's 3). Six of them (P0..P5) fall ENTIRELY inside centre tile
// t5 (col1,row1 = x[16..31],y[16..31]); the seventh (P6) is a lone corner prim in
// t15. So:
// bin_n[t5] = 6 (P0..P5, in draw order) <- DEEPER than the old FIFO depth 4
// bin_n[t15] = 1 (P6)
// all other 14 tiles = 0 (empty)
// One shared OPAQUE-blue texture, so a covered pixel is blue and order doesn't change
// the colour — draw order is proven instead by the BIN ORDER read-back.
//
// PROOFS:
// CAPACITY : bin_occ_max_r == 6 (a bin held 6 prims, > the old depth-4 limit),
// and raster_overflow / count / bin_overflow are ALL 0 (depth-8 FIFO
// swallowed all 7 with room to spare).
// BIN COUNTS : bin_n[t]==# prims whose bbox overlaps tile t (t5=6,t15=1,rest 0).
// BIN ORDER : bin_prim[5][0..5] == {0,1,2,3,4,5} (draw order preserved at depth 6).
// IMAGE : whole 64x64 == reference (covered-by-any-prim -> blue, else green).
// GRID : 16 tiles cleared (256 each) + 16*256 flush; prim list == 7.
`timescale 1ns/1ps
module tb_top_psmct32_tile_cap64_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.12;
localparam int NPRIM = 18;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(18), .TILE_FIFO_DEPTH(64),
.BIN_BUFFER_ENABLE(1'b1), .HEARTBEAT_SPLICE_ENABLE(1'b0) // Ch329 — no heartbeat; payload crosses qword 115
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// the 7 prim vertex tables (must match bake.py CAP_PRIMS)
int vx [0:NPRIM-1][0:2];
int vy [0:NPRIM-1][0:2];
initial begin
// iverilog-12: no array-slice '{} assignment — set elements individually.
// P0..P5 are SIX IDENTICAL t0 triangles (match bake.py CAP_T0); P6 = corner t15.
for (int p=0;p<NPRIM;p++) begin
vx[p][0]=1; vx[p][1]=14; vx[p][2]=1; // all 18 identical, tile t0
vy[p][0]=1; vy[p][1]=1; vy[p][2]=14;
end
end
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
// expected: prim p's bbox overlaps tile t? (bboxes derived from the verts)
function automatic bit binx(input int p, input int t);
int xl,xh,yl,yh,tx0,tx1,ty0,ty1;
begin
xl=vx[p][0]; xh=vx[p][0]; yl=vy[p][0]; yh=vy[p][0];
for (int k=1;k<3;k++) begin
if (vx[p][k]<xl) xl=vx[p][k]; if (vx[p][k]>xh) xh=vx[p][k];
if (vy[p][k]<yl) yl=vy[p][k]; if (vy[p][k]>yh) yh=vy[p][k];
end
tx0=(t%4)*16; tx1=tx0+15; ty0=(t/4)*16; ty1=ty0+15;
binx = !((xl>tx1)||(xh<tx0)||(yl>ty1)||(yh<ty0));
end
endfunction
int clear_cw [0:15];
int flush_emits; bit saw_prim_count_18;
initial begin for(int t=0;t<16;t++) clear_cw[t]=0; flush_emits=0; saw_prim_count_18=0; end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int t; t=int'(dut.u_gs.tile_row_r)*4 + int'(dut.u_gs.tile_col_r);
if (t>=0 && t<16) clear_cw[t] <= clear_cw[t] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==18)) saw_prim_count_18 <= 1'b1;
end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_blue, n_green;
int bnv [0:15];
int b5 [0:5]; // t5's six bin slots
int occ_max, ovf_count; logic ovf, bin_ovf;
initial begin
errors=0; n_match=0; n_check=0; n_blue=0; n_green=0;
for(int t=0;t<16;t++) bnv[t]=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
// Big settle: the 7-prim render (6 prims deep in tile t5, across 16 tiles)
// takes far longer than the 3-prim scenes, and raster_active can dip between
// phases — wait a generous fixed window so the WHOLE frame is flushed before
// sampling bins + arming the scanout capture (avoids a mid-render race).
repeat(120000) @(posedge clk);
bnv[0]=int'(dut.u_gs.bin_n[0]); bnv[1]=int'(dut.u_gs.bin_n[1]);
bnv[2]=int'(dut.u_gs.bin_n[2]); bnv[3]=int'(dut.u_gs.bin_n[3]);
bnv[4]=int'(dut.u_gs.bin_n[4]); bnv[5]=int'(dut.u_gs.bin_n[5]);
bnv[6]=int'(dut.u_gs.bin_n[6]); bnv[7]=int'(dut.u_gs.bin_n[7]);
bnv[8]=int'(dut.u_gs.bin_n[8]); bnv[9]=int'(dut.u_gs.bin_n[9]);
bnv[10]=int'(dut.u_gs.bin_n[10]); bnv[11]=int'(dut.u_gs.bin_n[11]);
bnv[12]=int'(dut.u_gs.bin_n[12]); bnv[13]=int'(dut.u_gs.bin_n[13]);
bnv[14]=int'(dut.u_gs.bin_n[14]); bnv[15]=int'(dut.u_gs.bin_n[15]);
b5[0]=int'(dut.u_gs.bin_prim[0][0]); b5[1]=int'(dut.u_gs.bin_prim[0][1]);
b5[2]=int'(dut.u_gs.bin_prim[0][2]); b5[3]=int'(dut.u_gs.bin_prim[0][3]);
b5[4]=int'(dut.u_gs.bin_prim[0][4]); b5[5]=int'(dut.u_gs.bin_prim[0][5]);
occ_max = int'(dut.u_gs.bin_occ_max_r);
ovf_count = int'(dut.u_gs.raster_overflow_count_r);
ovf = dut.u_gs.raster_overflow;
bin_ovf = dut.u_gs.bin_overflow_r;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// PROOF GRID
for (int t=0;t<16;t++)
if (clear_cw[t] != 256) begin $error("[cap] tile %0d cleared %0d (want 256)", t, clear_cw[t]); errors++; end
if (flush_emits != 16*256) begin $error("[cap] flush emitted %0d (want %0d)", flush_emits, 16*256); errors++; end
if (!saw_prim_count_18) begin $error("[cap64] prim_count_r never == 18"); errors++; end
// PROOF CAPACITY — a bin held 6 (> old depth 4), no overflow at depth 8.
if (occ_max != 18) begin $error("[cap64] bin_occ_max=%0d (want 18 > 16)", occ_max); errors++; end
if (occ_max <= 16) begin $error("[cap64] bin_occ_max=%0d NOT > 16 — capacity not proven", occ_max); errors++; end
if (ovf) begin $error("[cap] raster_overflow set at depth 8 (should not drop)"); errors++; end
if (ovf_count != 0) begin $error("[cap] overflow_count=%0d at depth 8 (want 0)", ovf_count); errors++; end
if (bin_ovf) begin $error("[cap] bin_overflow set at depth 8 (should not)"); errors++; end
// PROOF BIN COUNTS
for (int t=0;t<16;t++) begin
int exp_n; exp_n=0;
for (int p=0;p<NPRIM;p++) if (binx(p,t)) exp_n++;
if (bnv[t] !== exp_n) begin $error("[cap] tile %0d bin_n=%0d, want %0d", t, bnv[t], exp_n); errors++; end
end
// PROOF BIN ORDER — t0 holds P0..P5 in draw order.
for (int s=0;s<6;s++)
if (b5[s] !== s) begin $error("[cap] tile0 slot %0d = prim %0d (want %0d)", s, b5[s], s); errors++; end
$display("[cap] bin_n[0..15]=%0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d t5={%0d%0d%0d%0d%0d%0d} occ_max=%0d ovf=%0b cnt=%0d",
bnv[0],bnv[1],bnv[2],bnv[3],bnv[4],bnv[5],bnv[6],bnv[7],bnv[8],bnv[9],bnv[10],bnv[11],bnv[12],bnv[13],bnv[14],bnv[15],
b5[0],b5[1],b5[2],b5[3],b5[4],b5[5],occ_max,ovf,ovf_count);
// PROOF IMAGE — covered by ANY prim -> opaque blue; else green clear.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
bit is_in, is_bnd; logic [7:0] er,eg,eb;
is_in=0; is_bnd=0;
for (int p=0;p<NPRIM;p++) begin
int c; c = tri_cls(real'(px),real'(py),
real'(vx[p][0]),real'(vy[p][0]),
real'(vx[p][1]),real'(vy[p][1]),
real'(vx[p][2]),real'(vy[p][2]));
if (c==1) is_in=1;
if (c==2) is_bnd=1;
end
if (is_bnd && !is_in) begin er=8'hxx;eg=8'hxx;eb=8'hxx; end // skip ambiguous edge
else if (is_in) begin er=8'h00; eg=8'h00; eb=8'hFF; end // blue
else begin er=8'h00; eg=8'h80; eb=8'h00; end // green clear
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
if (cap_r[py][px]===er&&cap_g[py][px]===eg&&cap_b[py][px]===eb) begin
n_match++;
if (eb==8'hFF) n_blue++; else n_green++;
end else begin
if (errors<14) $error("[cap] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb);
errors++;
end
end
end
end
if (n_check < 400) begin $error("[cap] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[cap] image match %0d/%0d", n_match, n_check); errors++; end
if (n_blue < 30) begin $error("[cap] too few blue pixels (%0d) — prims not rendered", n_blue); errors++; end
if (n_green < 200) begin $error("[cap] too few green pixels (%0d) — empty tiles not clear", n_green); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_tile_cap64_demo] flush=%0d prim7=%0b occ_max=%0d ovf=%0b ovf_cnt=%0d bin_ovf=%0b match=%0d/%0d blue=%0d green=%0d errors=%0d",
flush_emits, saw_prim_count_18, occ_max, ovf, ovf_count, bin_ovf, n_match, n_check, n_blue, n_green, errors);
if (errors==0) $display("[tb_top_psmct32_tile_cap64_demo] PASS");
else $display("[tb_top_psmct32_tile_cap64_demo] FAIL");
$finish;
end
initial begin #600000000; $error("[tb_top_psmct32_tile_cap64_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_cap64_demo
sim/tb/top/tb_top_psmct32_tile_cap_demo.sv
+235
View File
@@ -0,0 +1,235 @@
// retroDE_ps2 — tb_top_psmct32_tile_cap_demo (Ch315)
//
// PRIMITIVE/BIN CAPACITY scaling. The 4x4 (64x64) grid with TILE_FIFO_DEPTH=8 and
// SEVEN prims (vs Ch312's 3). Six of them (P0..P5) fall ENTIRELY inside centre tile
// t5 (col1,row1 = x[16..31],y[16..31]); the seventh (P6) is a lone corner prim in
// t15. So:
// bin_n[t5] = 6 (P0..P5, in draw order) <- DEEPER than the old FIFO depth 4
// bin_n[t15] = 1 (P6)
// all other 14 tiles = 0 (empty)
// One shared OPAQUE-blue texture, so a covered pixel is blue and order doesn't change
// the colour — draw order is proven instead by the BIN ORDER read-back.
//
// PROOFS:
// CAPACITY : bin_occ_max_r == 6 (a bin held 6 prims, > the old depth-4 limit),
// and raster_overflow / count / bin_overflow are ALL 0 (depth-8 FIFO
// swallowed all 7 with room to spare).
// BIN COUNTS : bin_n[t]==# prims whose bbox overlaps tile t (t5=6,t15=1,rest 0).
// BIN ORDER : bin_prim[5][0..5] == {0,1,2,3,4,5} (draw order preserved at depth 6).
// IMAGE : whole 64x64 == reference (covered-by-any-prim -> blue, else green).
// GRID : 16 tiles cleared (256 each) + 16*256 flush; prim list == 7.
`timescale 1ns/1ps
module tb_top_psmct32_tile_cap_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.12;
localparam int NPRIM = 7;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(7), .TILE_FIFO_DEPTH(8),
.BIN_BUFFER_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// the 7 prim vertex tables (must match bake.py CAP_PRIMS)
int vx [0:NPRIM-1][0:2];
int vy [0:NPRIM-1][0:2];
initial begin
// iverilog-12: no array-slice '{} assignment — set elements individually.
// P0..P5 are SIX IDENTICAL t0 triangles (match bake.py CAP_T0); P6 = corner t15.
for (int p=0;p<6;p++) begin
vx[p][0]=1; vx[p][1]=14; vx[p][2]=1;
vy[p][0]=1; vy[p][1]=1; vy[p][2]=14;
end
vx[6][0]=50; vx[6][1]=62; vx[6][2]=50; vy[6][0]=50; vy[6][1]=50; vy[6][2]=62;
end
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
// expected: prim p's bbox overlaps tile t? (bboxes derived from the verts)
function automatic bit binx(input int p, input int t);
int xl,xh,yl,yh,tx0,tx1,ty0,ty1;
begin
xl=vx[p][0]; xh=vx[p][0]; yl=vy[p][0]; yh=vy[p][0];
for (int k=1;k<3;k++) begin
if (vx[p][k]<xl) xl=vx[p][k]; if (vx[p][k]>xh) xh=vx[p][k];
if (vy[p][k]<yl) yl=vy[p][k]; if (vy[p][k]>yh) yh=vy[p][k];
end
tx0=(t%4)*16; tx1=tx0+15; ty0=(t/4)*16; ty1=ty0+15;
binx = !((xl>tx1)||(xh<tx0)||(yl>ty1)||(yh<ty0));
end
endfunction
int clear_cw [0:15];
int flush_emits; bit saw_prim_count_7;
initial begin for(int t=0;t<16;t++) clear_cw[t]=0; flush_emits=0; saw_prim_count_7=0; end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int t; t=int'(dut.u_gs.tile_row_r)*4 + int'(dut.u_gs.tile_col_r);
if (t>=0 && t<16) clear_cw[t] <= clear_cw[t] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==7)) saw_prim_count_7 <= 1'b1;
end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_blue, n_green;
int bnv [0:15];
int b5 [0:5]; // t5's six bin slots
int occ_max, ovf_count; logic ovf, bin_ovf;
initial begin
errors=0; n_match=0; n_check=0; n_blue=0; n_green=0;
for(int t=0;t<16;t++) bnv[t]=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
// Big settle: the 7-prim render (6 prims deep in tile t5, across 16 tiles)
// takes far longer than the 3-prim scenes, and raster_active can dip between
// phases — wait a generous fixed window so the WHOLE frame is flushed before
// sampling bins + arming the scanout capture (avoids a mid-render race).
repeat(120000) @(posedge clk);
bnv[0]=int'(dut.u_gs.bin_n[0]); bnv[1]=int'(dut.u_gs.bin_n[1]);
bnv[2]=int'(dut.u_gs.bin_n[2]); bnv[3]=int'(dut.u_gs.bin_n[3]);
bnv[4]=int'(dut.u_gs.bin_n[4]); bnv[5]=int'(dut.u_gs.bin_n[5]);
bnv[6]=int'(dut.u_gs.bin_n[6]); bnv[7]=int'(dut.u_gs.bin_n[7]);
bnv[8]=int'(dut.u_gs.bin_n[8]); bnv[9]=int'(dut.u_gs.bin_n[9]);
bnv[10]=int'(dut.u_gs.bin_n[10]); bnv[11]=int'(dut.u_gs.bin_n[11]);
bnv[12]=int'(dut.u_gs.bin_n[12]); bnv[13]=int'(dut.u_gs.bin_n[13]);
bnv[14]=int'(dut.u_gs.bin_n[14]); bnv[15]=int'(dut.u_gs.bin_n[15]);
b5[0]=int'(dut.u_gs.bin_prim[0][0]); b5[1]=int'(dut.u_gs.bin_prim[0][1]);
b5[2]=int'(dut.u_gs.bin_prim[0][2]); b5[3]=int'(dut.u_gs.bin_prim[0][3]);
b5[4]=int'(dut.u_gs.bin_prim[0][4]); b5[5]=int'(dut.u_gs.bin_prim[0][5]);
occ_max = int'(dut.u_gs.bin_occ_max_r);
ovf_count = int'(dut.u_gs.raster_overflow_count_r);
ovf = dut.u_gs.raster_overflow;
bin_ovf = dut.u_gs.bin_overflow_r;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// PROOF GRID
for (int t=0;t<16;t++)
if (clear_cw[t] != 256) begin $error("[cap] tile %0d cleared %0d (want 256)", t, clear_cw[t]); errors++; end
if (flush_emits != 16*256) begin $error("[cap] flush emitted %0d (want %0d)", flush_emits, 16*256); errors++; end
if (!saw_prim_count_7) begin $error("[cap] prim_count_r never == 7"); errors++; end
// PROOF CAPACITY — a bin held 6 (> old depth 4), no overflow at depth 8.
if (occ_max != 6) begin $error("[cap] bin_occ_max=%0d (want 6 — capacity not exercised)", occ_max); errors++; end
if (ovf) begin $error("[cap] raster_overflow set at depth 8 (should not drop)"); errors++; end
if (ovf_count != 0) begin $error("[cap] overflow_count=%0d at depth 8 (want 0)", ovf_count); errors++; end
if (bin_ovf) begin $error("[cap] bin_overflow set at depth 8 (should not)"); errors++; end
// PROOF BIN COUNTS
for (int t=0;t<16;t++) begin
int exp_n; exp_n=0;
for (int p=0;p<NPRIM;p++) if (binx(p,t)) exp_n++;
if (bnv[t] !== exp_n) begin $error("[cap] tile %0d bin_n=%0d, want %0d", t, bnv[t], exp_n); errors++; end
end
// PROOF BIN ORDER — t0 holds P0..P5 in draw order.
for (int s=0;s<6;s++)
if (b5[s] !== s) begin $error("[cap] tile0 slot %0d = prim %0d (want %0d)", s, b5[s], s); errors++; end
$display("[cap] bin_n[0..15]=%0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d t5={%0d%0d%0d%0d%0d%0d} occ_max=%0d ovf=%0b cnt=%0d",
bnv[0],bnv[1],bnv[2],bnv[3],bnv[4],bnv[5],bnv[6],bnv[7],bnv[8],bnv[9],bnv[10],bnv[11],bnv[12],bnv[13],bnv[14],bnv[15],
b5[0],b5[1],b5[2],b5[3],b5[4],b5[5],occ_max,ovf,ovf_count);
// PROOF IMAGE — covered by ANY prim -> opaque blue; else green clear.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
bit is_in, is_bnd; logic [7:0] er,eg,eb;
is_in=0; is_bnd=0;
for (int p=0;p<NPRIM;p++) begin
int c; c = tri_cls(real'(px),real'(py),
real'(vx[p][0]),real'(vy[p][0]),
real'(vx[p][1]),real'(vy[p][1]),
real'(vx[p][2]),real'(vy[p][2]));
if (c==1) is_in=1;
if (c==2) is_bnd=1;
end
if (is_bnd && !is_in) begin er=8'hxx;eg=8'hxx;eb=8'hxx; end // skip ambiguous edge
else if (is_in) begin er=8'h00; eg=8'h00; eb=8'hFF; end // blue
else begin er=8'h00; eg=8'h80; eb=8'h00; end // green clear
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
if (cap_r[py][px]===er&&cap_g[py][px]===eg&&cap_b[py][px]===eb) begin
n_match++;
if (eb==8'hFF) n_blue++; else n_green++;
end else begin
if (errors<14) $error("[cap] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb);
errors++;
end
end
end
end
if (n_check < 400) begin $error("[cap] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[cap] image match %0d/%0d", n_match, n_check); errors++; end
if (n_blue < 30) begin $error("[cap] too few blue pixels (%0d) — prims not rendered", n_blue); errors++; end
if (n_green < 200) begin $error("[cap] too few green pixels (%0d) — empty tiles not clear", n_green); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_tile_cap_demo] flush=%0d prim7=%0b occ_max=%0d ovf=%0b ovf_cnt=%0d bin_ovf=%0b match=%0d/%0d blue=%0d green=%0d errors=%0d",
flush_emits, saw_prim_count_7, occ_max, ovf, ovf_count, bin_ovf, n_match, n_check, n_blue, n_green, errors);
if (errors==0) $display("[tb_top_psmct32_tile_cap_demo] PASS");
else $display("[tb_top_psmct32_tile_cap_demo] FAIL");
$finish;
end
initial begin #600000000; $error("[tb_top_psmct32_tile_cap_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_cap_demo
sim/tb/top/tb_top_psmct32_tile_cap_overflow_demo.sv
+101
View File
@@ -0,0 +1,101 @@
// retroDE_ps2 — tb_top_psmct32_tile_cap_overflow_demo (Ch315)
//
// CAPACITY-CEILING / GRACEFUL-CLAMP proof. The SAME 6-deep-in-t0 capacity payload
// (payload_tile_cap), but a DEPTH-4 FIFO (TILE_FIFO_DEPTH=4, the OLD size) with
// TILE_PRIM_COUNT=4. The scene wants 6 prims in tile t0, but a depth-4 FIFO can only
// batch 4: bin_occ_max_r CLAMPS at 4 (the capacity ceiling — vs occ_max=6 at depth 8
// in tb_top_psmct32_tile_cap_demo), and the clamped 4-prim batch still renders ALL 16
// tiles and the core halts (graceful degradation, no hang/crash).
//
// This is the realistic capacity limit for the BATCHED tile path: the render triggers
// at TILE_PRIM_COUNT and DRAINS the FIFO, so excess prims are clamped (not push-dropped)
// — raster_overflow (the streaming-path push-while-full FLAG, counted by the new
// raster_overflow_count_r) does not fire here. The pair {this, cap_demo} shows the
// resource/behaviour difference between depth 4 and depth 8 directly.
//
// PROOFS:
// CEILING : bin_occ_max_r == 4 (depth-4 FIFO clamped the 6-prim t0 cluster to 4).
// GRACEFUL : all 16 tiles cleared (256 each) + 16*256 flush — the clamped batch
// rendered fully; core_halt asserted (no hang).
// DIAG : the overflow counters are wired + readable (raster_overflow_count_r,
// bin_overflow_r reported).
`timescale 1ns/1ps
module tb_top_psmct32_tile_cap_overflow_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam int TP_CLEAR = 1;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(4), .TILE_FIFO_DEPTH(4),
.BIN_BUFFER_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
int clear_cw [0:15];
int flush_emits;
initial begin for(int t=0;t<16;t++) clear_cw[t]=0; flush_emits=0; end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int t; t=int'(dut.u_gs.tile_row_r)*4 + int'(dut.u_gs.tile_col_r);
if (t>=0 && t<16) clear_cw[t] <= clear_cw[t] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
end
int errors, occ_max, ovf_count; logic ovf;
initial begin
errors=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// Fixed settle (no raster_active edge wait): under overflow the dropped-prim
// pushes + degraded render can perturb raster_active timing, so just wait a
// generous window for the surviving 4-prim batch to clear+render+flush all 16
// tiles, then sample the (stable) overflow flags + clear/flush counters.
repeat(120000) @(posedge clk);
occ_max = int'(dut.u_gs.bin_occ_max_r);
ovf_count = int'(dut.u_gs.raster_overflow_count_r);
ovf = dut.u_gs.raster_overflow;
// CEILING — depth-4 FIFO clamps the 6-prim t0 cluster to exactly 4.
if (occ_max != 4) begin $error("[ovf] bin_occ_max=%0d (want 4 — depth-4 ceiling)", occ_max); errors++; end
// GRACEFUL — the clamped 4-prim batch still renders all 16 tiles, no hang.
for (int t=0;t<16;t++)
if (clear_cw[t] != 256) begin $error("[ovf] tile %0d cleared %0d (want 256 — render did not complete)", t, clear_cw[t]); errors++; end
if (flush_emits != 16*256) begin $error("[ovf] flush emitted %0d (want %0d)", flush_emits, 16*256); errors++; end
if (!core_halt) begin $error("[ovf] core_halt low (hang)"); errors++; end
$display("[tb_top_psmct32_tile_cap_overflow_demo] ovf=%0b ovf_count=%0d occ_max=%0d flush=%0d errors=%0d",
ovf, ovf_count, occ_max, flush_emits, errors);
if (errors==0) $display("[tb_top_psmct32_tile_cap_overflow_demo] PASS");
else $display("[tb_top_psmct32_tile_cap_overflow_demo] FAIL");
$finish;
end
initial begin #600000000; $error("[tb_top_psmct32_tile_cap_overflow_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_cap_overflow_demo
sim/tb/top/tb_top_psmct32_tile_demo.sv
+203
View File
@@ -0,0 +1,203 @@
// retroDE_ps2 — tb_top_psmct32_tile_demo (Ch303)
//
// TILE-LOCAL combined renderer TB — first tiled-VRAM rung. The Ch302 combined
// TME+ABE+ZTE triangle is rendered into an ON-CHIP 16x16 color+Z tile
// (CLEAR -> RENDER -> FLUSH); texture still from VRAM. Proves the tile memory
// schedule (per the architect), not just final pixels:
//
// PROOF CLEAR : TP_CLEAR writes all 256 color + 256 Z tile entries.
// PROOF HIDDEN : a depth-FAIL pixel in TP_RENDER does NOT read texture and
// does NOT write tile color or tile Z.
// PROOF VISIBLE: a depth-PASS pixel reads texture and WRITES tile color + tile Z.
// PROOF FLUSH : TP_FLUSH emits 256 framebuffer writes (the tile -> VRAM copy).
// PROOF RENDER : final scanout == Ch302 result (cleared green; triangle top
// blended red->orange/blue->teal over green; bottom occluded green),
// which requires correct tile RAM registered-read latency end-to-end.
//
// tile_phase: 0=OFF 1=CLEAR 2=RENDER 3=FLUSH.
`timescale 1ns/1ps
module tb_top_psmct32_tile_demo;
localparam int H_ACTIVE = 16, V_ACTIVE = 16;
localparam int TP_CLEAR=1, TP_RENDER=2, TP_FLUSH=3;
localparam int ZBG = 'h4000;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(8*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// ---- reference (same triangle/texture as Ch302) ----
function automatic real bdet(input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bdet=(by-cy)*(ax-cx)+(cx-bx)*(ay-cy); endfunction
function automatic real bwa(input real px,input real py,input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bwa=((by-cy)*(px-cx)+(cx-bx)*(py-cy))/bdet(ax,ay,bx,by,cx,cy); endfunction
function automatic real bwb(input real px,input real py,input real ax,input real ay,input real bx,input real by,input real cx,input real cy);
bwb=((cy-ay)*(px-cx)+(ax-cx)*(py-cy))/bdet(ax,ay,bx,by,cx,cy); endfunction
// ---- per-pixel render-phase tracers ----
int txr [0:V_ACTIVE-1][0:H_ACTIVE-1]; // texture reads (VRAM)
int tcw [0:V_ACTIVE-1][0:H_ACTIVE-1]; // tile_color writes
int tzw [0:V_ACTIVE-1][0:H_ACTIVE-1]; // tile_z writes
int clear_cw, clear_zw, flush_emits;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin txr[y][x]=0; tcw[y][x]=0; tzw[y][x]=0; end
clear_cw=0; clear_zw=0; flush_emits=0;
end
always_ff @(posedge clk) begin
if (rst_n) begin
// CLEAR phase: count tile color/Z initializations.
if (dut.u_gs.tile_phase == TP_CLEAR) begin
if (dut.u_gs.tile_color_we) clear_cw <= clear_cw + 1;
if (dut.u_gs.tile_z_we) clear_zw <= clear_zw + 1;
end
// RENDER phase: per-pixel tile ops. Writes attributed by decoding the
// tile-RAM write address (robust to the walker advancing on the write
// cycle); texture reads by the held walker position.
if (dut.u_gs.tile_phase == TP_RENDER) begin
int tx, ty, cx, cy, zx, zy;
cx = int'(dut.u_gs.ras_cur_x[3:0]); cy = int'(dut.u_gs.ras_cur_y[3:0]);
if (dut.u_gs.tex_rd_en) txr[cy][cx] <= txr[cy][cx] + 1;
if (dut.u_gs.tile_color_we) begin
tx = int'(dut.u_gs.tile_color_waddr[3:0]); ty = int'(dut.u_gs.tile_color_waddr[7:4]);
tcw[ty][tx] <= tcw[ty][tx] + 1;
end
if (dut.u_gs.tile_z_we) begin
zx = int'(dut.u_gs.tile_z_waddr[3:0]); zy = int'(dut.u_gs.tile_z_waddr[7:4]);
tzw[zy][zx] <= tzw[zy][zx] + 1;
end
end
// FLUSH emits: in tile mode the ONLY raster_pixel_emit pulses are the
// tile->FB flush writes (render writes go to tile RAM; clear emits
// nothing). Count them unconditionally — the very last emit (idx 255)
// fires on the cycle tile_phase transitions FLUSH->OFF, so a
// phase==FLUSH gate would undercount by one.
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
end
end
// ---- scanout capture ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_pass, n_fail, n_out;
initial begin
errors=0; n_pass=0; n_fail=0; n_out=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// Bracket the tile render: wait for it to BEGIN then COMPLETE
// (CLEAR->RENDER->FLUSH). If FLUSH/R_DRAIN never fires, raster_active
// never falls and this hangs to the timeout, exposing the bug.
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// PROOF CLEAR + FLUSH (whole-tile counts)
if (clear_cw != 256) begin $error("[tile] CLEAR wrote %0d color entries (want 256)", clear_cw); errors++; end
if (clear_zw != 256) begin $error("[tile] CLEAR wrote %0d Z entries (want 256)", clear_zw); errors++; end
if (flush_emits != 256) begin $error("[tile] FLUSH emitted %0d FB pixels (want 256)", flush_emits); errors++; end
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
real wa, wb, wc, fragz, uu;
bit clearly_in, clearly_out, pix_pass, pix_fail;
logic [7:0] er, eg, eb;
wa = bwa(px,py, 2,1, 13,1, 7,14);
wb = bwb(px,py, 2,1, 13,1, 7,14);
wc = 1.0 - wa - wb;
clearly_in = (wa>0.06)&&(wb>0.06)&&(wc>0.06);
clearly_out = (wa<-0.06)||(wb<-0.06)||(wc<-0.06);
fragz = (wa+wb)*real'('h6000) + wc*real'('h2000);
pix_pass = clearly_in && (fragz >= (real'(ZBG)+1024.0));
pix_fail = clearly_in && (fragz <= (real'(ZBG)-1024.0));
if (clearly_out) begin
n_out++;
// outside the triangle: cleared green shows through.
if (cap_de[py][px] && !(cap_r[py][px]==8'h00 && cap_g[py][px]==8'h80 && cap_b[py][px]==8'h00)) begin
if (errors<10) $error("[tile] OUT (%0d,%0d) not green (%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px]); errors++;
end
end
// PROOF HIDDEN — depth fail: no texture read, no tile color/Z write.
if (pix_fail) begin
n_fail++;
if (!(txr[py][px]==0 && tcw[py][px]==0 && tzw[py][px]==0)) begin
if (errors<10) $error("[tile] HIDDEN (%0d,%0d) did ops tex=%0d cw=%0d zw=%0d (want 0,0,0)",px,py,txr[py][px],tcw[py][px],tzw[py][px]); errors++;
end
if (cap_de[py][px] && !(cap_r[py][px]==8'h00 && cap_g[py][px]==8'h80 && cap_b[py][px]==8'h00)) begin
if (errors<10) $error("[tile] HIDDEN (%0d,%0d) not green",px,py); errors++;
end
end
// PROOF VISIBLE — depth pass: tex read + tile color/Z write; blended color.
if (pix_pass) begin
n_pass++;
if (!(txr[py][px]>=1 && tcw[py][px]>=1 && tzw[py][px]>=1)) begin
if (errors<10) $error("[tile] VISIBLE (%0d,%0d) ops tex=%0d cw=%0d zw=%0d (want >=1 each)",px,py,txr[py][px],tcw[py][px],tzw[py][px]); errors++;
end
uu = wb*7.0 + wc*3.0;
if (uu < 4.0) begin er=8'd127; eg=8'd64; eb=8'd0; end // red over green
else begin er=8'd0; eg=8'd64; eb=8'd127; end // blue over green
if (cap_de[py][px] && !(cap_r[py][px]===er && cap_g[py][px]===eg && cap_b[py][px]===eb)) begin
if (errors<10) $error("[tile] VISIBLE (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb); errors++;
end
end
end
end
if (n_pass<6) begin $error("[tile] too few PASS pixels (%0d)", n_pass); errors++; end
if (n_fail<6) begin $error("[tile] too few FAIL pixels (%0d)", n_fail); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_demo] clear_cw=%0d clear_zw=%0d flush=%0d PASS-pix=%0d FAIL-pix=%0d OUT-pix=%0d errors=%0d",
clear_cw, clear_zw, flush_emits, n_pass, n_fail, n_out, errors);
if (errors==0) $display("[tb_top_psmct32_tile_demo] PASS");
else $display("[tb_top_psmct32_tile_demo] FAIL");
$finish;
end
initial begin #150000000; $error("[tb_top_psmct32_tile_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_demo
sim/tb/top/tb_top_psmct32_tile_late_demo.sv
+162
View File
@@ -0,0 +1,162 @@
// retroDE_ps2 — tb_top_psmct32_tile_late_demo (Ch316)
//
// LEADING-EMPTY-TILE traversal fix. ONE primitive, ONLY in the LAST tile t15
// ([48..63]^2) of a 4x4 (64x64) grid; tiles t0..t14 are EMPTY and PRECEDE the first
// (and only) non-empty tile. Before Ch316 the leading empty tiles flushed BLACK
// (the flush row-stride used ras_fbw, which was its reset value 0 until a primitive
// loaded → all rows collapsed onto row 0). Ch316 loads the batch FRAME params
// (ras_fbw/fbp/psm) at grid-render start so EVERY tile's flush address is valid.
//
// PROOFS:
// LEADING EMPTIES : every empty early tile (t0..t14) flushes the GREEN clear
// colour, NOT black (this is the regressed behaviour).
// LATE RENDER : t15 contains the blue triangle (the renderer reached the last
// tile — no premature done/idle) over its own green clear.
// IMAGE : whole 64x64 == reference (inside t15 triangle -> blue, else green).
// NO BLACK : ZERO rendered pixels are black (the bug's signature).
// GRID : 16 tiles cleared (256 each) + 16*256 flush; bin_n[15]==1.
`timescale 1ns/1ps
module tb_top_psmct32_tile_late_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.12;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(1), .BIN_BUFFER_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// the single prim — t15 triangle (matches bake.py build_tile_late_demo_payload)
localparam int LX0=50, LY0=50, LX1=62, LY1=50, LX2=50, LY2=62;
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
int clear_cw [0:15];
int flush_emits;
initial begin for(int t=0;t<16;t++) clear_cw[t]=0; flush_emits=0; end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int t; t=int'(dut.u_gs.tile_row_r)*4 + int'(dut.u_gs.tile_col_r);
if (t>=0 && t<16) clear_cw[t] <= clear_cw[t] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_blue, n_green, n_black, bn15;
initial begin
errors=0; n_match=0; n_check=0; n_blue=0; n_green=0; n_black=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
repeat(120000) @(posedge clk); // full-render settle
bn15 = int'(dut.u_gs.bin_n[15]);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// GRID — render reached every tile (no premature done): all cleared + flushed.
for (int t=0;t<16;t++)
if (clear_cw[t] != 256) begin $error("[late] tile %0d cleared %0d (want 256 — premature done?)", t, clear_cw[t]); errors++; end
if (flush_emits != 16*256) begin $error("[late] flush emitted %0d (want %0d)", flush_emits, 16*256); errors++; end
if (bn15 != 1) begin $error("[late] bin_n[15]=%0d (want 1)", bn15); errors++; end
// IMAGE — inside t15 triangle -> blue, else green; NO black anywhere.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int c; logic [7:0] er,eg,eb;
if (cap_de[py][px]) begin
// black-pixel detector (the regressed signature) — count regardless of expectation
if (cap_r[py][px]<8'h20 && cap_g[py][px]<8'h20 && cap_b[py][px]<8'h20) n_black++;
c = tri_cls(real'(px),real'(py), real'(LX0),real'(LY0),
real'(LX1),real'(LY1), real'(LX2),real'(LY2));
if (c==2) begin er=8'hxx;eg=8'hxx;eb=8'hxx; end // edge — skip
else if (c==1) begin er=8'h00; eg=8'h00; eb=8'hFF; end // blue
else begin er=8'h00; eg=8'h80; eb=8'h00; end // green clear
if (er!==8'hxx) begin
n_check++;
if (cap_r[py][px]===er&&cap_g[py][px]===eg&&cap_b[py][px]===eb) begin
n_match++;
if (eb==8'hFF) n_blue++; else n_green++;
end else begin
if (errors<14) $error("[late] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb);
errors++;
end
end
end
end
end
if (n_check < 1000) begin $error("[late] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[late] image match %0d/%0d", n_match, n_check); errors++; end
if (n_black != 0) begin $error("[late] %0d BLACK pixels — leading-empty-tile bug present", n_black); errors++; end
if (n_blue < 20) begin $error("[late] too few blue pixels (%0d) — t15 prim not rendered (premature done?)", n_blue); errors++; end
if (n_green < 2000) begin $error("[late] too few green pixels (%0d) — empty tiles not cleared", n_green); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_tile_late_demo] clears_all256=%0b flush=%0d bin15=%0d match=%0d/%0d blue=%0d green=%0d black=%0d errors=%0d",
(clear_cw[0]==256), flush_emits, bn15, n_match, n_check, n_blue, n_green, n_black, errors);
if (errors==0) $display("[tb_top_psmct32_tile_late_demo] PASS");
else $display("[tb_top_psmct32_tile_late_demo] FAIL");
$finish;
end
initial begin #600000000; $error("[tb_top_psmct32_tile_late_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_late_demo
sim/tb/top/tb_top_psmct32_tile_lpddr128_demo.sv
+129
View File
@@ -0,0 +1,129 @@
// ============================================================================
// tb_top_psmct32_tile_lpddr128_demo — Ch321
//
// Structural verification that the 128x128 PSMCT16 framebuffer renders: an 8x8
// grid of 16x16 tiles (64 tiles), every tile cleared (256 px) and flushed in
// PSMCT16, no raster overflow, 3 primitives, and the scanned-out frame is filled
// (not black). The exact pixel content is validated on the board (the scene is
// the 64x64 psmct16fb demo scaled 2x). Fixture: bios/payload_tile_lpddr128.
// ============================================================================
`timescale 1ns/1ps
module tb_top_psmct32_tile_lpddr128_demo;
localparam int H_ACTIVE = 128, V_ACTIVE = 128;
localparam int NTILES = 64; // 8x8
logic clk = 1'b0, rst_n;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(64*1024), .LPDDR_FB_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(8), .TILE_ROWS(8),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3), .BIN_BUFFER_ENABLE(1'b1),
.TILE_COLOR_PSMCT16(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// ---- flush-stream counters ----
int clear_cw [0:NTILES-1];
int flush_emits, flush_psmct16, flush_psmct32, flush_be_bad;
bit saw_prim_count_3;
initial begin
for (int t=0;t<NTILES;t++) clear_cw[t]=0;
flush_emits=0; flush_psmct16=0; flush_psmct32=0; flush_be_bad=0; saw_prim_count_3=0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==2'd1 /*TP_CLEAR*/ && dut.u_gs.tile_color_we) begin
int t; t = int'(dut.u_gs.tile_row_r)*8 + int'(dut.u_gs.tile_col_r);
if (t>=0 && t<NTILES) clear_cw[t] <= clear_cw[t] + 1;
end
if (dut.u_gs.raster_pixel_emit) begin
flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_pixel_psm_q == 6'h02) flush_psmct16 <= flush_psmct16 + 1;
if (dut.u_gs.raster_pixel_psm_q == 6'h00) flush_psmct32 <= flush_psmct32 + 1;
if (dut.u_gs.raster_pixel_be_q != 4'b0011) flush_be_bad <= flush_be_bad + 1;
end
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==3)) saw_prim_count_3 <= 1'b1;
end
// ---- coarse content capture (one scanned-out frame) ----
int n_de, n_nonblack, n_distinct_from_bg;
logic [23:0] bg_seen; // first non-black pixel = the clear/bg color
bit bg_set;
bit capture_armed;
logic [31:0] hcnt_d, vcnt_d;
initial begin n_de=0; n_nonblack=0; n_distinct_from_bg=0; bg_set=0; bg_seen=0; capture_armed=0; end
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
n_de <= n_de + 1;
if ({r,g,b} != 24'd0) begin
n_nonblack <= n_nonblack + 1;
if (!bg_set) begin bg_seen <= {r,g,b}; bg_set <= 1'b1; end
else if ({r,g,b} != bg_seen) n_distinct_from_bg <= n_distinct_from_bg + 1;
end
end
end
int errors;
initial begin
errors=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
// capture exactly one scanned-out frame
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// ---- structural proof: every tile cleared + flushed, all PSMCT16 ----
for (int t=0;t<NTILES;t++)
if (clear_cw[t] != 256) begin $error("[lp128] tile %0d cleared %0d (want 256)", t, clear_cw[t]); errors++; end
if (flush_emits != NTILES*256) begin $error("[lp128] flush emitted %0d (want %0d)", flush_emits, NTILES*256); errors++; end
if (flush_psmct16 != flush_emits) begin $error("[lp128] PSMCT16 flushes %0d != emits %0d", flush_psmct16, flush_emits); errors++; end
if (flush_psmct32 != 0) begin $error("[lp128] %0d PSMCT32 flushes leaked", flush_psmct32); errors++; end
if (flush_be_bad != 0) begin $error("[lp128] %0d flushes with be!=0011", flush_be_bad); errors++; end
if (!saw_prim_count_3) begin $error("[lp128] prim_count_r never == 3"); errors++; end
if (raster_overflow) begin $error("[lp128] raster_overflow asserted at 8x8/3-prim"); errors++; end
if (!frame_seen) begin $error("[lp128] frame_seen never asserted"); errors++; end
// ---- coarse content: frame is filled (not black) + has the triangles ----
if (n_de < 16000) begin $error("[lp128] only %0d active px captured (want ~16384)", n_de); errors++; end
if (n_nonblack < 15000) begin $error("[lp128] only %0d non-black px (frame not filled)", n_nonblack); errors++; end
if (n_distinct_from_bg < 100) begin $error("[lp128] only %0d px differ from bg (triangles missing)", n_distinct_from_bg); errors++; end
$display("[lp128] tiles=64 flush_emits=%0d psmct16=%0d ovf=%0d | de=%0d nonblack=%0d tri=%0d errors=%0d",
flush_emits, flush_psmct16, raster_overflow, n_de, n_nonblack, n_distinct_from_bg, errors);
if (errors==0) $display("[tb_top_psmct32_tile_lpddr128_demo] PASS");
else $display("[tb_top_psmct32_tile_lpddr128_demo] FAIL");
$finish;
end
initial begin
#50_000_000;
$display("[tb_top_psmct32_tile_lpddr128_demo] TIMEOUT");
$display("[tb_top_psmct32_tile_lpddr128_demo] FAIL");
$finish;
end
endmodule
sim/tb/top/tb_top_psmct32_tile_lpddrfb_demo.sv
+121
View File
@@ -0,0 +1,121 @@
// retroDE_ps2 — tb_top_psmct32_tile_lpddrfb_demo (Ch317)
//
// LPDDR-backed framebuffer, TILE-FLUSH ONLY. Runs the Ch313 full-PSMCT16-FB scene
// (4x4 grid, 64x64, payload_tile_psmct16fb) with LPDDR_FB_ENABLE=1, so the PSMCT16
// tile FLUSH is ALSO committed to the gs_lpddr_fb_writer model (linear address,
// per-row bursts, 4 KiB cap). Tile color/Z + texture stay on-chip.
//
// PROOF (write/readback): the LPDDR framebuffer must hold EXACTLY what the on-chip
// BRAM framebuffer holds — every one of the 64*64 pixels read back from the LPDDR
// model (pix16 = {fbmem[a+1],fbmem[a]}, a=(y*64+x)*2) equals the BRAM FB's pix16 at
// the same screen pixel. (The BRAM FB itself was proven against the rendered scene
// in Ch313 via scanout, so LPDDR==BRAM closes the loop.) Plus the scene is real
// (clear-green + the three prim colours), and the bandwidth/over-underflow counters
// are sane: 4096 px -> 8192 bytes, one 32-byte burst per tile-row (256), no overflow.
`timescale 1ns/1ps
module tb_top_psmct32_tile_lpddrfb_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
logic clk, rst_n; initial clk=0; always #5 clk=~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3), .BIN_BUFFER_ENABLE(1'b1),
.TILE_COLOR_PSMCT16(1'b1),
.LPDDR_FB_ENABLE(1'b1), .LPDDR_FB_BYTES(8192)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// BRAM FB pix16 for screen (x,y): word = (y*64+x)>>1, halfword per bit0.
function automatic logic [15:0] bram_pix16(input int x, input int y);
int idx; logic [31:0] w;
begin
idx = y*64 + x;
w = dut.u_vram.mem[idx >> 1];
bram_pix16 = idx[0] ? w[31:16] : w[15:0];
end
endfunction
// LPDDR FB pix16 for screen (x,y): byte addr = (y*64+x)*2.
function automatic logic [15:0] lpddr_pix16(input int x, input int y);
int a; begin a = (y*64 + x)*2; lpddr_pix16 = {dut.g_lpddr_fb.u_lpddr_fb.fbmem[a+1], dut.g_lpddr_fb.u_lpddr_fb.fbmem[a]}; end
endfunction
int errors, n_eq, n_clear, n_nonclear;
logic [15:0] clear16;
int x,y;
int bytes_w, bursts, busy, ovf, unf, occ;
initial begin
errors=0; n_eq=0; n_clear=0; n_nonclear=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
repeat(120000) @(posedge clk); // full-render + LPDDR-drain settle
bytes_w = int'(dut.lpfb_bytes_written);
bursts = int'(dut.lpfb_burst_count);
busy = int'(dut.lpfb_busy_cycles);
ovf = int'(dut.lpfb_overflow_count);
unf = int'(dut.lpfb_underflow_count);
occ = int'(dut.lpfb_occ);
// the clear colour as a PSMCT16 word, read straight from the BRAM FB at a
// pixel that no prim covers (top-right corner of the 64x64 frame).
clear16 = bram_pix16(60, 4);
// PROOF — LPDDR FB == BRAM FB for every pixel; tally clear vs non-clear.
for (y=0; y<64; y++) begin
for (x=0; x<64; x++) begin
logic [15:0] lp, br;
lp = lpddr_pix16(x,y); br = bram_pix16(x,y);
if (lp === br) n_eq++;
else begin
if (errors<12) $error("[lpfb] (%0d,%0d) LPDDR=%04x != BRAM=%04x", x,y,lp,br);
errors++;
end
if (br === clear16) n_clear++; else n_nonclear++;
end
end
if (n_eq != 4096) begin $error("[lpfb] LPDDR==BRAM only %0d/4096", n_eq); errors++; end
if (n_nonclear < 50) begin $error("[lpfb] only %0d non-clear px — scene didn't render to LPDDR", n_nonclear); errors++; end
if (n_clear < 1000) begin $error("[lpfb] only %0d clear px — FB looks wrong", n_clear); errors++; end
// counters
if (bytes_w != 8192) begin $error("[lpfb] bytes_written=%0d (want 8192 = 4096 px x 2)", bytes_w); errors++; end
if (ovf != 0) begin $error("[lpfb] fifo_overflow=%0d (want 0)", ovf); errors++; end
if (unf != 0) begin $error("[lpfb] fifo_underflow=%0d (want 0)", unf); errors++; end
if (bursts < 1) begin $error("[lpfb] bursts=%0d (want >0)", bursts); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
// effective GB/s for this small path (1 cycle = 10 ns => 100 MHz model clock)
$display("[lpfb] bytes=%0d bursts=%0d (%.1f B/burst) busy=%0d occ_max=%0d ovf=%0d unf=%0d eff=%.2f GB/s @100MHz",
bytes_w, bursts, (bursts>0)?(real'(bytes_w)/real'(bursts)):0.0, busy, occ, ovf, unf,
(busy>0) ? (real'(bytes_w) / (real'(busy)*10.0)) : 0.0);
$display("[tb_top_psmct32_tile_lpddrfb_demo] LPDDR==BRAM=%0d/4096 clear=%0d nonclear=%0d clear16=%04x errors=%0d",
n_eq, n_clear, n_nonclear, clear16, errors);
if (errors==0) $display("[tb_top_psmct32_tile_lpddrfb_demo] PASS");
else $display("[tb_top_psmct32_tile_lpddrfb_demo] FAIL");
$finish;
end
initial begin #600000000; $error("[tb_top_psmct32_tile_lpddrfb_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_lpddrfb_demo
sim/tb/top/tb_top_psmct32_tile_multiprim_demo.sv
+223
View File
@@ -0,0 +1,223 @@
// retroDE_ps2 — tb_top_psmct32_tile_multiprim_demo (Ch305)
//
// MULTI-PRIMITIVE tiled-scene TB. A fixed LIST of 3 combined TME+ABE+ZTE
// primitives is re-rendered PER TILE, IN ORDER, over a 2x2 grid of 16x16
// on-chip tiles (32x32 region). All three triangles cross BOTH seams (x=16,
// y=16). Draw order: P0 opaque BLUE bg (flat Z=0x5000) -> P1 opaque RED
// (flat Z=0x6000, in front) -> P2 translucent WHITE (flat Z=0x5800, blends).
//
// PROOFS:
// GRID : all 4 tiles clear independently (256 color writes each) and the
// grid flushes 4*256=1024 FB writes (one flush per tile, AFTER all
// 3 primitives composited into that tile).
// LIST : prim_count_r latched to 3 (the renderer processes a 3-primitive
// list per tile, not a single primitive).
// ORDER+DEPTH+ALPHA : the whole 32x32 scanout matches a SINGLE screen-space
// software reference that replays P0,P1,P2 in order with an integer
// Z-buffer (GEQUAL, write-on-pass) + source-over blend. Distinct
// regions exercised (counted): pure BLUE (opaque bg), RED (P1 over
// P0 = depth order), LIGHT-BLUE (P2 blended over blue = alpha + proves
// P0 rendered), and OCCLUSION (P0&P1&P2 -> P2 FAILS vs red's Z so RED
// shows through, NOT pink = depth occludes the blend). Seam-region
// matches counted separately (continuity across x=15|16, y=15|16).
`timescale 1ns/1ps
module tb_top_psmct32_tile_multiprim_demo;
localparam int H_ACTIVE = 32, V_ACTIVE = 32;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.08;
// primitive flat-Z + texel colors (must match bake.py Ch305 fixture)
localparam int Z0 = 'h5000, Z1 = 'h6000, Z2 = 'h5800, ZCLR = 'h4000;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(2), .TILE_ROWS(2),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// ---- triangle classify: 1=clearly-IN, 0=clearly-OUT, 2=EDGE(skip) ----
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
// ---- one-channel source-over blend, mirrors gs_alpha_blend EXACTLY:
// Cv = clamp( ((Cs-Cd)*As >>> 7) + Cd ). As=0x80 -> Cv=Cs (opaque). ----
function automatic logic [7:0] blendch(input int cs, input int cd, input int aa);
int t;
begin
t = ((cs - cd) * aa) >>> 7;
t = t + cd;
if (t < 0) t = 0;
if (t > 255) t = 255;
blendch = t[7:0];
end
endfunction
// ---- grid tracers ----
int clear_cw_tile [0:1][0:1]; // tile_color writes per (row,col) during CLEAR
int flush_emits;
bit saw_prim_count_3;
initial begin
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++) clear_cw_tile[rr][cc]=0;
flush_emits=0; saw_prim_count_3=1'b0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int cc, rr; cc=int'(dut.u_gs.tile_col_r); rr=int'(dut.u_gs.tile_row_r);
if (cc<2 && rr<2) clear_cw_tile[rr][cc] <= clear_cw_tile[rr][cc] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1; // tile mode: only flush emits
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==3)) saw_prim_count_3 <= 1'b1;
end
// ---- scanout capture (32x32) ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_seam;
int n_blue, n_red, n_lblue, n_occ, n_green;
initial begin
errors=0; n_match=0; n_check=0; n_seam=0;
n_blue=0; n_red=0; n_lblue=0; n_occ=0; n_green=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active); // grid render begins
@(negedge dut.u_gs.raster_active); // all tiles done (clear+3prims+flush)
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// PROOF GRID — each tile cleared independently + total flushes.
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++)
if (clear_cw_tile[rr][cc] != 256) begin
$error("[tmp] tile(col=%0d,row=%0d) cleared %0d (want 256)", cc, rr, clear_cw_tile[rr][cc]); errors++;
end
if (flush_emits != 4*256) begin $error("[tmp] flush emitted %0d (want %0d)", flush_emits, 4*256); errors++; end
// PROOF LIST — the batch was a 3-primitive list.
if (!saw_prim_count_3) begin $error("[tmp] prim_count_r never observed == 3 (list not formed)"); errors++; end
// PROOF ORDER+DEPTH+ALPHA — whole 32x32 vs the 3-primitive SW replay.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int c0, c1, c2, cr, cg, cb, zz;
logic [7:0] er, eg, eb;
real fpx, fpy;
fpx = real'(px); fpy = real'(py);
c0 = tri_cls(fpx,fpy, 1, 1, 30, 1, 15,30); // P0 blue
c1 = tri_cls(fpx,fpy, 8, 3, 22, 3, 15,20); // P1 red
c2 = tri_cls(fpx,fpy, 7, 9, 23, 9, 15,28); // P2 white
if (c0==2 || c1==2 || c2==2) begin er=8'hxx; eg=8'hxx; eb=8'hxx; end
else begin
cr=0; cg=128; cb=0; zz=ZCLR; // clear green
if (c0==1 && Z0>=zz) begin // P0 opaque blue
cr=blendch(0,cr,'h80); cg=blendch(0,cg,'h80); cb=blendch(255,cb,'h80); zz=Z0;
end
if (c1==1 && Z1>=zz) begin // P1 opaque red (in front)
cr=blendch(255,cr,'h80); cg=blendch(0,cg,'h80); cb=blendch(0,cb,'h80); zz=Z1;
end
if (c2==1 && Z2>=zz) begin // P2 translucent white (may FAIL vs red)
cr=blendch(255,cr,'h40); cg=blendch(255,cg,'h40); cb=blendch(255,cb,'h40); zz=Z2;
end
er=cr[7:0]; eg=cg[7:0]; eb=cb[7:0];
end
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
// region tally (for proof-coverage reporting)
if (er==8'h00 && eg==8'h00 && eb==8'hFF) n_blue++;
else if (er==8'hFF && eg==8'h00 && eb==8'h00) n_red++;
else if (er==8'h7F && eg==8'h7F && eb==8'hFF) n_lblue++;
else if (er==8'h00 && eg==8'h80 && eb==8'h00) n_green++;
if (cap_r[py][px]===er && cap_g[py][px]===eg && cap_b[py][px]===eb) begin
n_match++;
if (px==15||px==16||py==15||py==16) n_seam++;
end else begin
if (errors<14) $error("[tmp] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x) [c0%0d c1%0d c2%0d]",
px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb,c0,c1,c2);
errors++;
end
end
end
end
// occlusion count: pixels clearly-in ALL three -> must be RED (P2 occluded)
for (int py=0; py<V_ACTIVE; py++) for (int px=0; px<H_ACTIVE; px++) begin
real fpx2, fpy2;
fpx2 = real'(px); fpy2 = real'(py);
if (tri_cls(fpx2,fpy2, 1,1,30,1,15,30)==1 && tri_cls(fpx2,fpy2, 8,3,22,3,15,20)==1
&& tri_cls(fpx2,fpy2, 7,9,23,9,15,28)==1) n_occ++;
end
if (n_check < 200) begin $error("[tmp] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[tmp] image match %0d/%0d (composite/depth/alpha error)", n_match, n_check); errors++; end
if (n_seam < 20) begin $error("[tmp] too few SEAM matches (%0d)", n_seam); errors++; end
if (n_blue < 10) begin $error("[tmp] BLUE region thin (%0d) — opaque bg not proven", n_blue); errors++; end
if (n_red < 10) begin $error("[tmp] RED region thin (%0d) — depth order not proven", n_red); errors++; end
if (n_lblue < 10) begin $error("[tmp] LIGHT-BLUE region thin (%0d) — alpha-over-bg not proven", n_lblue); errors++; end
if (n_occ < 8) begin $error("[tmp] OCCLUSION region thin (%0d) — depth occlusion not proven", n_occ); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_multiprim_demo] clears=[%0d %0d %0d %0d] flush=%0d prim3=%0b match=%0d/%0d seam=%0d | blue=%0d red=%0d lblue=%0d occ=%0d green=%0d errors=%0d",
clear_cw_tile[0][0],clear_cw_tile[0][1],clear_cw_tile[1][0],clear_cw_tile[1][1],
flush_emits, saw_prim_count_3, n_match, n_check, n_seam,
n_blue, n_red, n_lblue, n_occ, n_green, errors);
if (errors==0) $display("[tb_top_psmct32_tile_multiprim_demo] PASS");
else $display("[tb_top_psmct32_tile_multiprim_demo] FAIL");
$finish;
end
initial begin #300000000; $error("[tb_top_psmct32_tile_multiprim_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_multiprim_demo
sim/tb/top/tb_top_psmct32_tile_palbilinear_demo.sv
+183
View File
@@ -0,0 +1,183 @@
// retroDE_ps2 — tb_top_psmct32_tile_palbilinear_demo (Ch314)
//
// BILINEAR filtering for a PALETTIZED (PSMT8 indexed) texture in the combined
// tiled renderer. Two triangles sample the SAME magnified 4x4 PSMT8 INDEX checker
// (idx 0/1) with a CLUT (0=blue, 1=white), at different TEX1.MMAG:
// LEFT tri (x2..14, MMAG=0, NEAREST): blocky checker — every pixel is one of
// the 2 CLUT colors, NO midtones.
// RIGHT tri (x18..30, MMAG=1, LINEAR): smoothed — midtone (light-blue) pixels
// at texel boundaries.
//
// This is the ON-BOARD CLUT-BEFORE-INTERP proof: each bilinear tap fetches an
// INDEX, CLUTs it to a color, then the 4 COLORS are interpolated. If the hardware
// instead interpolated INDICES and CLUT'd once, the RIGHT triangle would be just
// as blocky as the LEFT (an interpolated index rounds to one palette entry → a
// pure color). So midtones on the RIGHT but NONE on the LEFT proves colors — not
// indices — are interpolated. The exact 4-tap CLUT math is proven at the unit
// level by tb_gs_texture_bilinear (CASE7..CASE12).
//
// Checker colors blue (0,0,255) / white (255,255,255): b==255 in both, so a
// bilinear blend gives r=g in (0,255), b high (a midtone); green clear has b==0.
//
// PROOFS:
// NEAREST blocky : LEFT tri has ZERO midtone pixels (pure CLUT colors only).
// BILINEAR smooth: RIGHT tri has >=N midtone pixels (CLUT-then-blend at borders).
// RENDERED : both tris paint a healthy number of checker pixels (the
// ~9-cyc indexed stall + CLUT did not drop the bilinear prim).
// GRID : 4 tiles cleared (256 each) + 1024 flush; prim list = 2.
`timescale 1ns/1ps
module tb_top_psmct32_tile_palbilinear_demo;
localparam int H_ACTIVE = 32, V_ACTIVE = 32;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.10;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(2), .TILE_ROWS(2),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(2),
.BILINEAR_ENABLE(1'b1), .PALETTE_BILINEAR(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
int clear_cw_tile [0:1][0:1];
int flush_emits;
bit saw_prim_count_2;
initial begin
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++) clear_cw_tile[rr][cc]=0;
flush_emits=0; saw_prim_count_2=1'b0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int cc, rr; cc=int'(dut.u_gs.tile_col_r); rr=int'(dut.u_gs.tile_row_r);
if (cc<2 && rr<2) clear_cw_tile[rr][cc] <= clear_cw_tile[rr][cc] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==2)) saw_prim_count_2 <= 1'b1;
end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors;
int n_near_tex, n_near_mid, n_bil_tex, n_bil_mid;
// a checker pixel = b high (>=200). midtone = checker AND r strictly between
// the two pure CLUT values (not pure blue r=0, not pure white r=255).
function automatic bit is_checker(input logic [7:0] rr, input logic [7:0] gg, input logic [7:0] bb);
is_checker = (bb >= 8'd200);
endfunction
function automatic bit is_midtone(input logic [7:0] rr, input logic [7:0] gg, input logic [7:0] bb);
is_midtone = (bb >= 8'd200) && (rr > 8'd16) && (rr < 8'd239);
endfunction
initial begin
errors=0; n_near_tex=0; n_near_mid=0; n_bil_tex=0; n_bil_mid=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++)
if (clear_cw_tile[rr][cc] != 256) begin
$error("[pb] tile(col=%0d,row=%0d) cleared %0d (want 256)", cc, rr, clear_cw_tile[rr][cc]); errors++;
end
if (flush_emits != 4*256) begin $error("[pb] flush emitted %0d (want %0d)", flush_emits, 4*256); errors++; end
if (!saw_prim_count_2) begin $error("[pb] prim_count_r never == 2"); errors++; end
// classify each pixel: LEFT (nearest) tri vs RIGHT (bilinear) tri.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int cl, cr2;
logic [7:0] rr, gg, bb;
if (cap_de[py][px]) begin
rr=cap_r[py][px]; gg=cap_g[py][px]; bb=cap_b[py][px];
cl = tri_cls(real'(px),real'(py), 2, 4, 14, 4, 2,26); // LEFT nearest
cr2 = tri_cls(real'(px),real'(py), 18, 4, 30, 4, 18,26); // RIGHT bilinear
if (cl==1) begin // clearly inside LEFT
if (is_checker(rr,gg,bb)) n_near_tex++;
if (is_midtone(rr,gg,bb)) n_near_mid++;
end
if (cr2==1) begin // clearly inside RIGHT
if (is_checker(rr,gg,bb)) n_bil_tex++;
if (is_midtone(rr,gg,bb)) n_bil_mid++;
end
end
end
end
// PROOFS
if (n_near_tex < 30) begin $error("[pb] LEFT(nearest) too few checker pixels (%0d) — not rendered (CLUT not loaded?)", n_near_tex); errors++; end
if (n_bil_tex < 30) begin $error("[pb] RIGHT(bilinear) too few checker pixels (%0d) — indexed ~9cyc stall dropped the prim?", n_bil_tex); errors++; end
if (n_near_mid != 0) begin $error("[pb] NEAREST produced %0d midtone pixels — indexed nearest must be blocky (0)", n_near_mid); errors++; end
if (n_bil_mid < 10) begin $error("[pb] BILINEAR produced only %0d midtones — CLUT-before-interp not smoothing (indices interpolated?)", n_bil_mid); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_palbilinear_demo] clears=[%0d %0d %0d %0d] flush=%0d prim2=%0b | nearTex=%0d nearMid=%0d bilTex=%0d bilMid=%0d errors=%0d",
clear_cw_tile[0][0],clear_cw_tile[0][1],clear_cw_tile[1][0],clear_cw_tile[1][1],
flush_emits, saw_prim_count_2, n_near_tex, n_near_mid, n_bil_tex, n_bil_mid, errors);
if (errors==0) $display("[tb_top_psmct32_tile_palbilinear_demo] PASS");
else $display("[tb_top_psmct32_tile_palbilinear_demo] FAIL");
$finish;
end
initial begin #400000000; $error("[tb_top_psmct32_tile_palbilinear_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_palbilinear_demo
sim/tb/top/tb_top_psmct32_tile_psmct16_demo.sv
+199
View File
@@ -0,0 +1,199 @@
// retroDE_ps2 — tb_top_psmct32_tile_psmct16_demo (Ch308)
//
// PSMCT16 tile color buffer. The Ch305 3-primitive scene (opaque blue bg / opaque
// red / translucent white, over a 2x2 grid of 16x16 tiles) but with the on-chip
// tile color RAM AND the framebuffer in PSMCT16 (RGB5A1, 16-bit). Each primitive's
// blended color is QUANTIZED to 5-bit when stored, so later primitives blend over
// the quantized dest; scanout unpacks RGB5A1 -> ABGR. The software reference
// replays the 3 prims with the SAME per-step 5-bit quantization (q(c)=(c&0xF8)|(c>>5)),
// so the comparison is EXACT against the quantized result (not a tolerance).
//
// PROOFS:
// PSMCT16 : the whole 32x32 scanout matches the quantized 3-prim reference,
// proving pack-on-write, unpack-for-blend, PSMCT16 flush, and PSMCT16
// scanout all round-trip correctly through the 16-bit tile + FB.
// DEPTH/ALPHA preserved : red occludes white (solid red, not pink); white blends
// over blue (light-blue, 5-bit quantized 0x7B not 0x7F).
// GRID : 4 tiles cleared (256 each) + 1024 flush; prim list = 3.
`timescale 1ns/1ps
module tb_top_psmct32_tile_psmct16_demo;
localparam int H_ACTIVE = 32, V_ACTIVE = 32;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.08;
localparam int Z0 = 'h5000, Z1 = 'h6000, Z2 = 'h5800, ZCLR = 'h4000;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(2), .TILE_ROWS(2),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3), .TILE_COLOR_PSMCT16(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
function automatic logic [7:0] blendch(input int cs, input int cd, input int aa);
int t;
begin
t = ((cs - cd) * aa) >>> 7;
t = t + cd;
if (t < 0) t = 0;
if (t > 255) t = 255;
blendch = t[7:0];
end
endfunction
// PSMCT16 5-bit quantization: keep top 5 bits, bit-replicate top 3 into low.
function automatic logic [7:0] q5(input logic [7:0] c);
q5 = (c & 8'hF8) | (c >> 5);
endfunction
// ---- grid tracers ----
int clear_cw_tile [0:1][0:1];
int flush_emits;
bit saw_prim_count_3;
initial begin
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++) clear_cw_tile[rr][cc]=0;
flush_emits=0; saw_prim_count_3=1'b0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int cc, rr; cc=int'(dut.u_gs.tile_col_r); rr=int'(dut.u_gs.tile_row_r);
if (cc<2 && rr<2) clear_cw_tile[rr][cc] <= clear_cw_tile[rr][cc] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==3)) saw_prim_count_3 <= 1'b1;
end
// ---- scanout capture (32x32) ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_seam, n_lblue, n_green16;
initial begin
errors=0; n_match=0; n_check=0; n_seam=0; n_lblue=0; n_green16=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++)
if (clear_cw_tile[rr][cc] != 256) begin
$error("[t16] tile(col=%0d,row=%0d) cleared %0d (want 256)", cc, rr, clear_cw_tile[rr][cc]); errors++;
end
if (flush_emits != 4*256) begin $error("[t16] flush emitted %0d (want %0d)", flush_emits, 4*256); errors++; end
if (!saw_prim_count_3) begin $error("[t16] prim_count_r never == 3"); errors++; end
// PSMCT16 reference: replay P0,P1,P2 with per-step 5-bit quantization.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int c0, c1, c2; logic [7:0] cr, cg, cb; int zz;
logic [7:0] er, eg, eb;
c0 = tri_cls(real'(px),real'(py), 1, 1, 30, 1, 15,30);
c1 = tri_cls(real'(px),real'(py), 8, 3, 22, 3, 15,20);
c2 = tri_cls(real'(px),real'(py), 7, 9, 23, 9, 15,28);
if (c0==2 || c1==2 || c2==2) begin er=8'hxx; eg=8'hxx; eb=8'hxx; end
else begin
// clear green, quantized (the CLEAR write is packed to PSMCT16)
cr=q5(8'h00); cg=q5(8'h80); cb=q5(8'h00); zz=ZCLR;
if (c0==1 && Z0>=zz) begin
cr=q5(blendch(0,cr,'h80)); cg=q5(blendch(0,cg,'h80)); cb=q5(blendch(255,cb,'h80)); zz=Z0;
end
if (c1==1 && Z1>=zz) begin
cr=q5(blendch(255,cr,'h80)); cg=q5(blendch(0,cg,'h80)); cb=q5(blendch(0,cb,'h80)); zz=Z1;
end
if (c2==1 && Z2>=zz) begin
cr=q5(blendch(255,cr,'h40)); cg=q5(blendch(255,cg,'h40)); cb=q5(blendch(255,cb,'h40)); zz=Z2;
end
er=cr; eg=cg; eb=cb;
end
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
if (eg==8'h84 && er==8'h00 && eb==8'h00) n_green16++; // quantized clear green
if (er==8'h7B && eg==8'h7B && eb==8'hFF) n_lblue++; // quantized white-over-blue
if (cap_r[py][px]===er && cap_g[py][px]===eg && cap_b[py][px]===eb) begin
n_match++;
if (px==15||px==16||py==15||py==16) n_seam++;
end else begin
if (errors<14) $error("[t16] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x) [c0%0d c1%0d c2%0d]",
px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb,c0,c1,c2);
errors++;
end
end
end
end
if (n_check < 200) begin $error("[t16] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[t16] image match %0d/%0d (PSMCT16 round-trip error)", n_match, n_check); errors++; end
if (n_green16 < 100) begin $error("[t16] quantized green region thin (%0d)", n_green16); errors++; end
if (n_lblue < 8) begin $error("[t16] quantized light-blue thin (%0d) — alpha/quant not proven", n_lblue); errors++; end
if (n_seam < 15) begin $error("[t16] too few SEAM matches (%0d)", n_seam); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_psmct16_demo] clears=[%0d %0d %0d %0d] flush=%0d prim3=%0b match=%0d/%0d seam=%0d | green16=%0d lblue16=%0d errors=%0d",
clear_cw_tile[0][0],clear_cw_tile[0][1],clear_cw_tile[1][0],clear_cw_tile[1][1],
flush_emits, saw_prim_count_3, n_match, n_check, n_seam, n_green16, n_lblue, errors);
if (errors==0) $display("[tb_top_psmct32_tile_psmct16_demo] PASS");
else $display("[tb_top_psmct32_tile_psmct16_demo] FAIL");
$finish;
end
initial begin #300000000; $error("[tb_top_psmct32_tile_psmct16_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_psmct16_demo
sim/tb/top/tb_top_psmct32_tile_psmct16fb_demo.sv
+254
View File
@@ -0,0 +1,254 @@
// retroDE_ps2 — tb_top_psmct32_tile_psmct16fb_demo (Ch313)
//
// FULL PSMCT16 FRAMEBUFFER MODE. The same Ch312 4x4 (64x64) bin-buffer scene, but
// the WHOLE framebuffer is PSMCT16: FRAME_1.PSM=PSMCT16, so the relaxed
// close_combined gate must accept a PSMCT16 dest (it does, because
// TILE_COLOR_PSMCT16=1). The on-chip tile RAM is 16-bit, dest-color reads for
// blending unpack RGB5A1, the flush writes 16-bit halfword lanes (be=4'b0011,
// psm=0x02), and DISPFB1.PSM=PSMCT16 scans it out. The textures stay PSMCT32 DECAL.
// A 64x64 PSMCT16 FB is 8 KiB (HALF the 16 KiB PSMCT32 FB) -> 16 KiB VRAM (vs Ch312's
// 32 KiB). Same three prims:
// P0 blue (Z5000): top-left, bbox t0,1,4,5 (4 tiles)
// P1 red (Z6000): mid, crosses seams, bbox t5,6,7,9,10,11 (6 tiles)
// P2 white(Z5800): bottom-right corner, t15 ONLY (1 tile)
// EMPTY t2,3,8,12,13,14 -> stay clear (quantized green).
//
// PROOFS:
// BIN COUNTS : bin_n[t] for ALL 16 tiles == # prims whose bbox overlaps tile t
// (binning is format-independent; identical to Ch312).
// BIN ORDER : t5 (the one multi-prim tile) lists {P0,P1} in draw order.
// PSMCT16 FLUSH: every flush emit carries psm=0x02 + be=4'b0011 (16-bit lanes);
// NO PSMCT32 (psm=0x00) flush ever occurs -> the whole FB is 16-bit.
// IMAGE : whole 64x64 matches the screen-space re-test reference replayed
// with PER-STEP 5-bit quantization q5(c)=(c&0xF8)|(c>>5) — EXACT, not
// a tolerance — proving pack-on-write, unpack-for-blend, and PSMCT16
// scanout round-trip, with seam continuity across x=16/32/48 & y=16/32.
// QUANTIZED : MANY matched pixels differ from the un-quantized PSMCT32 value
// (e.g. clear green 0x80->0x84), and the capture matches the QUANTIZED
// one — direct evidence the framebuffer really is RGB5A1, not PSMCT32.
`timescale 1ns/1ps
module tb_top_psmct32_tile_psmct16fb_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam real MARG = 0.10;
localparam int Z0 = 'h5000, Z1 = 'h6000, Z2 = 'h5800, ZCLR = 'h4000;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3), .BIN_BUFFER_ENABLE(1'b1),
.TILE_COLOR_PSMCT16(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
function automatic logic [7:0] sovr(input int cs, input int cd, input int aa);
int t; begin t=((cs-cd)*aa)>>>7; t=t+cd; if(t<0)t=0; if(t>255)t=255; sovr=t[7:0]; end
endfunction
// PSMCT16 5-bit quantization: keep top 5 bits, replicate top 3 into the low 3
// (== the pack-to-RGB5A1 then unpack-on-scanout round trip). Idempotent.
function automatic logic [7:0] q5(input logic [7:0] c);
q5 = (c & 8'hF8) | (c >> 5);
endfunction
// prim p's bbox overlaps tile t? (bboxes match bake.py Ch313 verts == Ch312)
function automatic bit binx(input int p, input int t);
int xl,xh,yl,yh,tx0,tx1,ty0,ty1;
begin
case (p)
0: begin xl=2; xh=30; yl=2; yh=30; end // P0
1: begin xl=20; xh=50; yl=18; yh=40; end // P1
default: begin xl=52; xh=60; yl=52; yh=60; end // P2
endcase
tx0=(t%4)*16; tx1=tx0+15; ty0=(t/4)*16; ty1=ty0+15;
binx = !((xl>tx1)||(xh<tx0)||(yl>ty1)||(yh<ty0));
end
endfunction
int clear_cw [0:15];
int flush_emits; bit saw_prim_count_3;
int flush_psmct16, flush_psmct32, flush_be_bad; // PSMCT16-flush proof counters
initial begin
for(int t=0;t<16;t++) clear_cw[t]=0;
flush_emits=0; saw_prim_count_3=0; flush_psmct16=0; flush_psmct32=0; flush_be_bad=0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==2'd1 /*TP_CLEAR*/ && dut.u_gs.tile_color_we) begin
int t; t=int'(dut.u_gs.tile_row_r)*4 + int'(dut.u_gs.tile_col_r);
if (t>=0 && t<16) clear_cw[t] <= clear_cw[t] + 1;
end
if (dut.u_gs.raster_pixel_emit) begin
flush_emits <= flush_emits + 1;
// The flush emit register carries the FB write format. PSMCT16 mode must
// emit psm=0x02 + be=4'b0011 on EVERY flush; psm=0x00 must never appear.
if (dut.u_gs.raster_pixel_psm_q == 6'h02) flush_psmct16 <= flush_psmct16 + 1;
if (dut.u_gs.raster_pixel_psm_q == 6'h00) flush_psmct32 <= flush_psmct32 + 1;
if (dut.u_gs.raster_pixel_be_q != 4'b0011) flush_be_bad <= flush_be_bad + 1;
end
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==3)) saw_prim_count_3 <= 1'b1;
end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_seam, n_empty_chk, n_quant;
int bnv [0:15];
int b5_0, b5_1;
initial begin
errors=0; n_match=0; n_check=0; n_seam=0; n_empty_chk=0; n_quant=0;
for(int t=0;t<16;t++) bnv[t]=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
bnv[0]=int'(dut.u_gs.bin_n[0]); bnv[1]=int'(dut.u_gs.bin_n[1]);
bnv[2]=int'(dut.u_gs.bin_n[2]); bnv[3]=int'(dut.u_gs.bin_n[3]);
bnv[4]=int'(dut.u_gs.bin_n[4]); bnv[5]=int'(dut.u_gs.bin_n[5]);
bnv[6]=int'(dut.u_gs.bin_n[6]); bnv[7]=int'(dut.u_gs.bin_n[7]);
bnv[8]=int'(dut.u_gs.bin_n[8]); bnv[9]=int'(dut.u_gs.bin_n[9]);
bnv[10]=int'(dut.u_gs.bin_n[10]); bnv[11]=int'(dut.u_gs.bin_n[11]);
bnv[12]=int'(dut.u_gs.bin_n[12]); bnv[13]=int'(dut.u_gs.bin_n[13]);
bnv[14]=int'(dut.u_gs.bin_n[14]); bnv[15]=int'(dut.u_gs.bin_n[15]);
b5_0=int'(dut.u_gs.bin_prim[5][0]); b5_1=int'(dut.u_gs.bin_prim[5][1]);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// PROOF GRID
for (int t=0;t<16;t++)
if (clear_cw[t] != 256) begin $error("[f16] tile %0d cleared %0d (want 256)", t, clear_cw[t]); errors++; end
if (flush_emits != 16*256) begin $error("[f16] flush emitted %0d (want %0d)", flush_emits, 16*256); errors++; end
if (!saw_prim_count_3) begin $error("[f16] prim_count_r never == 3"); errors++; end
// PROOF PSMCT16 FLUSH — every flush emit is a 16-bit halfword write, NONE PSMCT32.
if (flush_psmct16 != flush_emits) begin $error("[f16] PSMCT16 flushes %0d != emits %0d", flush_psmct16, flush_emits); errors++; end
if (flush_psmct32 != 0) begin $error("[f16] %0d PSMCT32 flushes leaked (FB not fully 16-bit)", flush_psmct32); errors++; end
if (flush_be_bad != 0) begin $error("[f16] %0d flushes with be!=4'b0011", flush_be_bad); errors++; end
// PROOF BIN COUNTS
for (int t=0;t<16;t++) begin
int exp_n; exp_n=0;
for (int p=0;p<3;p++) if (binx(p,t)) exp_n++;
if (bnv[t] !== exp_n) begin $error("[f16] tile %0d bin_n=%0d, want %0d", t, bnv[t], exp_n); errors++; end
end
if (b5_0 !== 0 || b5_1 !== 1) begin $error("[f16] tile5 bin = {%0d,%0d}, want {0,1}", b5_0, b5_1); errors++; end
$display("[f16] bin_n[0..15]=%0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d %0d%0d%0d%0d t5={%0d,%0d}",
bnv[0],bnv[1],bnv[2],bnv[3],bnv[4],bnv[5],bnv[6],bnv[7],bnv[8],bnv[9],bnv[10],bnv[11],bnv[12],bnv[13],bnv[14],bnv[15],b5_0,b5_1);
// PROOF IMAGE — re-test reference with PER-STEP RGB5A1 quantization. Each blend
// step writes the quantized dest back to the 16-bit tile RAM, so the next
// blend reads the quantized value; q5 after every step models that exactly.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int c0,c1,c2,cr,cg,cb,zz; int rr,rg,rb; logic [7:0] er,eg,eb; bit scene_here, in_empty;
c0 = tri_cls(real'(px),real'(py), 2, 2, 30, 2, 2,30);
c1 = tri_cls(real'(px),real'(py), 20,18, 50,18, 35,40);
c2 = tri_cls(real'(px),real'(py), 52,52, 60,52, 52,60);
if (c0==2||c1==2||c2==2) begin er=8'hxx;eg=8'hxx;eb=8'hxx; end
else begin
scene_here = (c0==1)||(c1==1)||(c2==1);
in_empty = !scene_here;
// unquantized PSMCT32 reference (rr/rg/rb) tracked in parallel to
// witness where 16-bit quantization actually changes the result.
cr=q5(8'h00); cg=q5(8'h80); cb=q5(8'h00); zz=ZCLR; // quantized clear green
rr=8'h00; rg=8'h80; rb=8'h00;
if (c0==1 && Z0>=zz) begin
cr=q5(sovr(0,cr,'h80)); cg=q5(sovr(0,cg,'h80)); cb=q5(sovr(255,cb,'h80)); zz=Z0;
rr=sovr(0,rr,'h80); rg=sovr(0,rg,'h80); rb=sovr(255,rb,'h80);
end
if (c1==1 && Z1>=zz) begin
cr=q5(sovr(255,cr,'h80)); cg=q5(sovr(0,cg,'h80)); cb=q5(sovr(0,cb,'h80)); zz=Z1;
rr=sovr(255,rr,'h80); rg=sovr(0,rg,'h80); rb=sovr(0,rb,'h80);
end
if (c2==1 && Z2>=zz) begin
cr=q5(sovr(255,cr,'h40)); cg=q5(sovr(255,cg,'h40)); cb=q5(sovr(255,cb,'h40)); zz=Z2;
rr=sovr(255,rr,'h40); rg=sovr(255,rg,'h40); rb=sovr(255,rb,'h40);
end
er=cr[7:0]; eg=cg[7:0]; eb=cb[7:0];
end
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
if (in_empty && er==8'h00&&eg==8'h84&&eb==8'h00) n_empty_chk++;
if (cap_r[py][px]===er&&cap_g[py][px]===eg&&cap_b[py][px]===eb) begin
n_match++;
// quantization witness: this matched pixel would have been
// DIFFERENT in a PSMCT32 FB (proves the FB is genuinely 16-bit).
if (er!==rr[7:0] || eg!==rg[7:0] || eb!==rb[7:0]) n_quant++;
if (px==15||px==16||px==31||px==32||px==47||px==48||py==15||py==16||py==31||py==32) n_seam++;
end else begin
if (errors<14) $error("[f16] (%0d,%0d) got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",px,py,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb);
errors++;
end
end
end
end
if (n_check < 400) begin $error("[f16] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[f16] image match %0d/%0d (PSMCT16-FB round-trip error)", n_match, n_check); errors++; end
if (n_empty_chk < 100) begin $error("[f16] too few empty-tile quantized-green pixels (%0d)", n_empty_chk); errors++; end
if (n_quant < 100) begin $error("[f16] too few quantized-witness pixels (%0d) — FB may not be 16-bit", n_quant); errors++; end
if (n_seam < 40) begin $error("[f16] too few SEAM matches (%0d)", n_seam); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_psmct16fb_demo] flush=%0d psm16=%0d psm32=%0d be_bad=%0d prim3=%0b match=%0d/%0d seam=%0d empty=%0d quant=%0d errors=%0d",
flush_emits, flush_psmct16, flush_psmct32, flush_be_bad, saw_prim_count_3, n_match, n_check, n_seam, n_empty_chk, n_quant, errors);
if (errors==0) $display("[tb_top_psmct32_tile_psmct16fb_demo] PASS");
else $display("[tb_top_psmct32_tile_psmct16fb_demo] FAIL");
$finish;
end
initial begin #600000000; $error("[tb_top_psmct32_tile_psmct16fb_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_psmct16fb_demo
sim/tb/top/tb_top_psmct32_tile_scissor_demo.sv
+221
View File
@@ -0,0 +1,221 @@
// retroDE_ps2 — tb_top_psmct32_tile_scissor_demo (Ch306)
//
// GS SCISSOR clipping in the tiled renderer. The Ch305 3-primitive scene
// (opaque blue bg / opaque red / translucent white, over a 2x2 grid of 16x16
// tiles) PLUS a SCISSOR_1 rectangle [6..25]x[4..20] (inclusive) that crosses
// BOTH tile seams (x=16, y=16). Effective raster bounds = primitive bbox ∩ tile
// bbox ∩ scissor rect, baked into the walker (no per-pixel test). Pixels outside
// the scissor must stay the CLEAR color (no color/Z write).
//
// PROOFS:
// CLIP : pixels that would be inside a primitive but are OUTSIDE the
// scissor are GREEN (clear) — the scene is clipped, not drawn.
// INSIDE : pixels inside the scissor match the UNCLIPPED 3-prim reference
// (blue / red / light-blue / occlusion regions all present).
// EDGE : the scissor boundary is exact (integer rect; pixels at x=SX0/SX1
// and y=SY0/SY1 correct, and the pixel one step outside is green).
// SEAMS : the clip is correct across x=15|16 and y=15|16.
// GRID : 4 tiles cleared (256 each) + 1024 flush emits; prim list = 3.
`timescale 1ns/1ps
module tb_top_psmct32_tile_scissor_demo;
localparam int H_ACTIVE = 32, V_ACTIVE = 32;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.08;
localparam int Z0 = 'h5000, Z1 = 'h6000, Z2 = 'h5800, ZCLR = 'h4000;
// SCISSOR_1 rect (inclusive) — MUST match bake.py Ch306 (TSC_S*).
localparam int SX0 = 9, SX1 = 22, SY0 = 6, SY1 = 20;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(2), .TILE_ROWS(2),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(3), .SCISSOR_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
function automatic logic [7:0] blendch(input int cs, input int cd, input int aa);
int t;
begin
t = ((cs - cd) * aa) >>> 7;
t = t + cd;
if (t < 0) t = 0;
if (t > 255) t = 255;
blendch = t[7:0];
end
endfunction
// ---- grid tracers ----
int clear_cw_tile [0:1][0:1];
int flush_emits;
bit saw_prim_count_3;
initial begin
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++) clear_cw_tile[rr][cc]=0;
flush_emits=0; saw_prim_count_3=1'b0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int cc, rr; cc=int'(dut.u_gs.tile_col_r); rr=int'(dut.u_gs.tile_row_r);
if (cc<2 && rr<2) clear_cw_tile[rr][cc] <= clear_cw_tile[rr][cc] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==3)) saw_prim_count_3 <= 1'b1;
end
// ---- scanout capture (32x32) ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_seam;
int n_clipped, n_inside_scene, n_edge_pairs;
initial begin
errors=0; n_match=0; n_check=0; n_seam=0;
n_clipped=0; n_inside_scene=0; n_edge_pairs=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// PROOF GRID
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++)
if (clear_cw_tile[rr][cc] != 256) begin
$error("[tsc] tile(col=%0d,row=%0d) cleared %0d (want 256)", cc, rr, clear_cw_tile[rr][cc]); errors++;
end
if (flush_emits != 4*256) begin $error("[tsc] flush emitted %0d (want %0d)", flush_emits, 4*256); errors++; end
if (!saw_prim_count_3) begin $error("[tsc] prim_count_r never == 3"); errors++; end
// PROOF CLIP + INSIDE + EDGE + SEAMS — whole 32x32 vs the SCISSORED reference.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int c0, c1, c2, cr, cg, cb, zz;
bit insc, scene_here;
logic [7:0] er, eg, eb;
real fpx, fpy;
fpx = real'(px); fpy = real'(py);
c0 = tri_cls(fpx,fpy, 1, 1, 30, 1, 15,30); // P0 blue
c1 = tri_cls(fpx,fpy, 8, 3, 22, 3, 15,20); // P1 red
c2 = tri_cls(fpx,fpy, 7, 9, 23, 9, 15,28); // P2 white
insc = (px>=SX0)&&(px<=SX1)&&(py>=SY0)&&(py<=SY1); // scissor is EXACT (integer)
if (c0==2 || c1==2 || c2==2) begin er=8'hxx; eg=8'hxx; eb=8'hxx; end
else begin
scene_here = (c0==1) || (c1==1) || (c2==1);
cr=0; cg=128; cb=0; zz=ZCLR; // clear green
if (insc) begin // ONLY composite inside scissor
if (c0==1 && Z0>=zz) begin cr=blendch(0,cr,'h80); cg=blendch(0,cg,'h80); cb=blendch(255,cb,'h80); zz=Z0; end
if (c1==1 && Z1>=zz) begin cr=blendch(255,cr,'h80); cg=blendch(0,cg,'h80); cb=blendch(0,cb,'h80); zz=Z1; end
if (c2==1 && Z2>=zz) begin cr=blendch(255,cr,'h40); cg=blendch(255,cg,'h40); cb=blendch(255,cb,'h40); zz=Z2; end
end
er=cr[7:0]; eg=cg[7:0]; eb=cb[7:0];
end
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
if (!insc && scene_here) n_clipped++; // would-be-scene pixel, clipped -> green
if (insc && scene_here) n_inside_scene++; // scene pixel kept
if (cap_r[py][px]===er && cap_g[py][px]===eg && cap_b[py][px]===eb) begin
n_match++;
if (px==15||px==16||py==15||py==16) n_seam++;
end else begin
if (errors<14) $error("[tsc] (%0d,%0d) insc=%0b got(%02x,%02x,%02x) exp(%02x,%02x,%02x) [c0%0d c1%0d c2%0d]",
px,py,insc,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb,c0,c1,c2);
errors++;
end
end
end
end
// PROOF EDGE — explicit: just-inside vs just-outside each scissor border,
// at a row/col through the scene, must differ correctly (drawn vs green).
// (Sampled where the scene is clearly present so the transition is visible.)
for (int py=SY0+1; py<=SY1-1; py++) begin
// left border: x=SX0-1 outside (green), x=SX0 inside
if (cap_de[py][SX0-1] && cap_de[py][SX0]) begin
bit out_green, scn;
scn = (tri_cls(real'(SX0),real'(py), 1,1,30,1,15,30)==1) ||
(tri_cls(real'(SX0),real'(py), 8,3,22,3,15,20)==1) ||
(tri_cls(real'(SX0),real'(py), 7,9,23,9,15,28)==1);
out_green = (cap_r[py][SX0-1]===8'h00 && cap_g[py][SX0-1]===8'h80 && cap_b[py][SX0-1]===8'h00);
if (scn) begin
n_edge_pairs++;
if (!out_green) begin $error("[tsc] left scissor edge: (%0d,%0d) outside not green", SX0-1, py); errors++; end
end
end
end
if (n_check < 200) begin $error("[tsc] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[tsc] image match %0d/%0d (scissor/clip error)", n_match, n_check); errors++; end
if (n_clipped < 20) begin $error("[tsc] too few CLIPPED pixels (%0d) — scissor not exercised", n_clipped); errors++; end
if (n_inside_scene < 20) begin $error("[tsc] too few INSIDE-scene pixels (%0d)", n_inside_scene); errors++; end
if (n_edge_pairs < 5) begin $error("[tsc] too few scissor-edge samples (%0d)", n_edge_pairs); errors++; end
if (n_seam < 15) begin $error("[tsc] too few SEAM matches (%0d)", n_seam); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_scissor_demo] clears=[%0d %0d %0d %0d] flush=%0d prim3=%0b match=%0d/%0d seam=%0d | clipped=%0d inside=%0d edgePairs=%0d errors=%0d",
clear_cw_tile[0][0],clear_cw_tile[0][1],clear_cw_tile[1][0],clear_cw_tile[1][1],
flush_emits, saw_prim_count_3, n_match, n_check, n_seam,
n_clipped, n_inside_scene, n_edge_pairs, errors);
if (errors==0) $display("[tb_top_psmct32_tile_scissor_demo] PASS");
else $display("[tb_top_psmct32_tile_scissor_demo] FAIL");
$finish;
end
initial begin #300000000; $error("[tb_top_psmct32_tile_scissor_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_scissor_demo
sim/tb/top/tb_top_psmct32_tile_sprite18_demo.sv
+198
View File
@@ -0,0 +1,198 @@
// retroDE_ps2 — tb_top_psmct32_tile_sprite18_demo (Ch315)
//
// PRIMITIVE/BIN CAPACITY scaling. The 4x4 (64x64) grid with TILE_FIFO_DEPTH=8 and
// SEVEN prims (vs Ch312's 3). Six of them (P0..P5) fall ENTIRELY inside centre tile
// t5 (col1,row1 = x[16..31],y[16..31]); the seventh (P6) is a lone corner prim in
// t15. So:
// bin_n[t5] = 6 (P0..P5, in draw order) <- DEEPER than the old FIFO depth 4
// bin_n[t15] = 1 (P6)
// all other 14 tiles = 0 (empty)
// One shared OPAQUE-blue texture, so a covered pixel is blue and order doesn't change
// the colour — draw order is proven instead by the BIN ORDER read-back.
//
// PROOFS:
// CAPACITY : bin_occ_max_r == 6 (a bin held 6 prims, > the old depth-4 limit),
// and raster_overflow / count / bin_overflow are ALL 0 (depth-8 FIFO
// swallowed all 7 with room to spare).
// BIN COUNTS : bin_n[t]==# prims whose bbox overlaps tile t (t5=6,t15=1,rest 0).
// BIN ORDER : bin_prim[5][0..5] == {0,1,2,3,4,5} (draw order preserved at depth 6).
// IMAGE : whole 64x64 == reference (covered-by-any-prim -> blue, else green).
// GRID : 16 tiles cleared (256 each) + 16*256 flush; prim list == 7.
`timescale 1ns/1ps
module tb_top_psmct32_tile_sprite18_demo;
localparam int H_ACTIVE = 64, V_ACTIVE = 64;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.12;
localparam int NPRIM = 18;
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(32*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(4), .TILE_ROWS(4),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(18), .TILE_FIFO_DEPTH(64),
.BIN_BUFFER_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// the 7 prim vertex tables (must match bake.py CAP_PRIMS)
int vx [0:NPRIM-1][0:2];
int vy [0:NPRIM-1][0:2];
initial begin
// iverilog-12: no array-slice '{} assignment — set elements individually.
// P0..P5 are SIX IDENTICAL t0 triangles (match bake.py CAP_T0); P6 = corner t15.
for (int p=0;p<NPRIM;p++) begin
vx[p][0]=1; vx[p][1]=14; vx[p][2]=1; // all 18 identical, tile t0
vy[p][0]=1; vy[p][1]=1; vy[p][2]=14;
end
end
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
// expected: prim p's bbox overlaps tile t? (bboxes derived from the verts)
function automatic bit binx(input int p, input int t);
int xl,xh,yl,yh,tx0,tx1,ty0,ty1;
begin
xl=vx[p][0]; xh=vx[p][0]; yl=vy[p][0]; yh=vy[p][0];
for (int k=1;k<3;k++) begin
if (vx[p][k]<xl) xl=vx[p][k]; if (vx[p][k]>xh) xh=vx[p][k];
if (vy[p][k]<yl) yl=vy[p][k]; if (vy[p][k]>yh) yh=vy[p][k];
end
tx0=(t%4)*16; tx1=tx0+15; ty0=(t/4)*16; ty1=ty0+15;
binx = !((xl>tx1)||(xh<tx0)||(yl>ty1)||(yh<ty0));
end
endfunction
int clear_cw [0:15];
int flush_emits; bit saw_prim_count_18;
initial begin for(int t=0;t<16;t++) clear_cw[t]=0; flush_emits=0; saw_prim_count_18=0; end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int t; t=int'(dut.u_gs.tile_row_r)*4 + int'(dut.u_gs.tile_col_r);
if (t>=0 && t<16) clear_cw[t] <= clear_cw[t] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==18)) saw_prim_count_18 <= 1'b1;
end
// Ch328 — state trace (Codex): pinpoint where the >16/tile render walk sticks.
int trace_cnt, trace_lines; logic [3:0] ph_d;
initial begin trace_cnt = 0; trace_lines = 0; ph_d = 4'hF; end
always_ff @(posedge clk) if (rst_n && dut.u_gs.raster_active) begin
trace_cnt <= trace_cnt + 1;
if (int'(dut.u_gs.tile_phase_r) != int'(ph_d) && trace_lines < 80) begin // log every phase change
trace_lines <= trace_lines + 1;
$display("[trace t=%0d] phase %0d->%0d cur_t=%0d bin_n=%0d bin_slot=%0d combPE=%0b drain=%0b allgrad=%0b gpend=%0b",
trace_cnt, int'(ph_d), int'(dut.u_gs.tile_phase_r), int'(dut.u_gs.cur_t),
int'(dut.u_gs.bin_n[dut.u_gs.cur_t]), int'(dut.u_gs.bin_slot_r),
dut.u_gs.comb_pipe_empty, dut.u_gs.ras_drain_done, dut.u_gs.all_grad_done, dut.u_gs.grad_pending_any);
end
ph_d <= dut.u_gs.tile_phase_r;
end
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_blue, n_green;
int bnv [0:15];
int b5 [0:5]; // t5's six bin slots
int occ_max, ovf_count, tile_refused; logic ovf, bin_ovf;
initial begin
errors=0; n_match=0; n_check=0; n_blue=0; n_green=0;
for(int t=0;t<16;t++) bnv[t]=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
// Ch329 — do NOT wait @(posedge raster_active): the all-refused grid completes fast (~8.5k cyc)
// and does NOT loop, so raster_active may have already pulsed low by here (would hang). The
// settle below covers the grid (which runs after dma_done); then sample the refusal counters.
repeat(40000) @(posedge clk);
bnv[0]=int'(dut.u_gs.bin_n[0]); bnv[1]=int'(dut.u_gs.bin_n[1]);
bnv[2]=int'(dut.u_gs.bin_n[2]); bnv[3]=int'(dut.u_gs.bin_n[3]);
bnv[4]=int'(dut.u_gs.bin_n[4]); bnv[5]=int'(dut.u_gs.bin_n[5]);
bnv[6]=int'(dut.u_gs.bin_n[6]); bnv[7]=int'(dut.u_gs.bin_n[7]);
bnv[8]=int'(dut.u_gs.bin_n[8]); bnv[9]=int'(dut.u_gs.bin_n[9]);
bnv[10]=int'(dut.u_gs.bin_n[10]); bnv[11]=int'(dut.u_gs.bin_n[11]);
bnv[12]=int'(dut.u_gs.bin_n[12]); bnv[13]=int'(dut.u_gs.bin_n[13]);
bnv[14]=int'(dut.u_gs.bin_n[14]); bnv[15]=int'(dut.u_gs.bin_n[15]);
b5[0]=int'(dut.u_gs.bin_prim[0][0]); b5[1]=int'(dut.u_gs.bin_prim[0][1]);
b5[2]=int'(dut.u_gs.bin_prim[0][2]); b5[3]=int'(dut.u_gs.bin_prim[0][3]);
b5[4]=int'(dut.u_gs.bin_prim[0][4]); b5[5]=int'(dut.u_gs.bin_prim[0][5]);
occ_max = int'(dut.u_gs.bin_occ_max_r);
tile_refused = int'(dut.u_gs.tile_refused_count);
ovf_count = int'(dut.u_gs.raster_overflow_count_r);
ovf = dut.u_gs.raster_overflow;
bin_ovf = dut.u_gs.bin_overflow_r;
// ===== Ch329 Bug 1 — NON-COMBINED (sprite) REFUSAL =====
// All 18 sprites are non-combined → the multiprim grid must REFUSE them (no tile-local path):
// refused counter == 18, NOTHING binned (occ_max==0, every bin_n==0), and CRUCIALLY the grid
// still COMPLETES (each tile cleared 256 + the full 16*256 flush) — i.e. NO stall, unlike the
// pre-Ch329 freeze. Output is the clear colour everywhere (nothing rendered).
if (tile_refused != 18) begin $error("[sprite18] tile_refused_count=%0d (want 18 — all sprites refused)", tile_refused); errors++; end
if (occ_max != 0) begin $error("[sprite18] occ_max=%0d (want 0 — nothing should bin)", occ_max); errors++; end
for (int t=0;t<16;t++) if (bnv[t]!==0) begin $error("[sprite18] bin_n[%0d]=%0d (want 0)", t, bnv[t]); errors++; end
for (int t=0;t<16;t++) if (clear_cw[t]!=256) begin $error("[sprite18] tile %0d cleared %0d (want 256 — grid stalled?)", t, clear_cw[t]); errors++; end
if (flush_emits != 16*256) begin $error("[sprite18] flush=%0d (want %0d — grid did not complete)", flush_emits, 16*256); errors++; end
if (ovf) begin $error("[sprite18] raster_overflow set"); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
$display("[tb_top_psmct32_tile_sprite18_demo] refused=%0d occ_max=%0d flush=%0d ovf=%0b errors=%0d",
tile_refused, occ_max, flush_emits, ovf, errors);
if (errors==0) $display("[tb_top_psmct32_tile_sprite18_demo] PASS");
else $display("[tb_top_psmct32_tile_sprite18_demo] FAIL");
$finish;
end
initial begin #600000000; $error("[tb_top_psmct32_tile_sprite18_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_sprite18_demo
sim/tb/top/tb_top_psmct32_tile_wrap_demo.sv
+214
View File
@@ -0,0 +1,214 @@
// retroDE_ps2 — tb_top_psmct32_tile_wrap_demo (Ch307)
//
// GS texture WRAP MODES (REPEAT + CLAMP) in the tiled renderer. Two textured
// combined prims sample the SAME striped 4x4 texture (columns u=0,1 WHITE,
// u=2,3 BLUE; opaque A=0x80) with UV running u:0->8 (2x the texture width):
// REPEAT prim (top band, CLAMP_1 WMS=WMT=0): white stripe REPEATS at u=0 and
// u=4 -> TWO white stripes (texture tiles).
// CLAMP prim (bottom band, WMS=WMT=1): white at u=0..1 only; u>=2 sticks to
// the blue edge -> ONE white stripe.
// Both cross the x=16 tile seam. Distinguishing region u in [4,6): REPEAT=WHITE,
// CLAMP=BLUE. Opaque texels (As=0x80 -> Cv=Cs), so expected color == texel RGB.
//
// PROOFS:
// REPEAT-TILES : >=N pixels in the u-in-[4,6) band of the REPEAT prim are WHITE.
// CLAMP-STICKS : the SAME band of the CLAMP prim is BLUE (0 white there).
// FIRST-STRIPE : both prims show the u-in-[0,2) white stripe (texture sampled).
// IMAGE : whole 32x32 matches the wrap/clamp software reference.
// GRID : 4 tiles cleared (256 each) + 1024 flush; prim list = 2.
`timescale 1ns/1ps
module tb_top_psmct32_tile_wrap_demo;
localparam int H_ACTIVE = 32, V_ACTIVE = 32;
localparam int TP_CLEAR = 1;
localparam real MARG = 0.10; // triangle-edge barycentric margin
localparam real UFRAC = 0.30; // skip pixels whose interp-u is near a texel boundary
localparam int TWIDTH = 4; // 2^TW
logic clk, rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt, dma_done_seen, frame_seen, raster_overflow;
logic frame_toggle, dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
.VRAM_BYTES(16*1024), .PSMCT32_SWIZZLE(1'b0),
.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_COLS(2), .TILE_ROWS(2),
.TILE_MULTIPRIM(1'b1), .TILE_PRIM_COUNT(2), .TEX_WRAP_ENABLE(1'b1)
) dut (
.clk(clk), .rst_n(rst_n), .core_go(core_go),
.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt), .dma_done_seen(dma_done_seen),
.frame_seen(frame_seen), .raster_overflow(raster_overflow),
.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0)
);
// barycentric weights wb (of vertex b) for a triangle — used for the affine u.
function automatic int tri_cls(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d, wa, wb, wc;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
wa = ((by-cy)*(px-cx) + (cx-bx)*(py-cy)) / d;
wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
wc = 1.0 - wa - wb;
if (wa>MARG && wb>MARG && wc>MARG) tri_cls = 1;
else if (wa<-MARG || wb<-MARG || wc<-MARG) tri_cls = 0;
else tri_cls = 2;
end
endfunction
function automatic real tri_wb(input real px, input real py,
input real ax, input real ay,
input real bx, input real by,
input real cx, input real cy);
real d;
begin
d = (by-cy)*(ax-cx) + (cx-bx)*(ay-cy);
tri_wb = ((cy-ay)*(px-cx) + (ax-cx)*(py-cy)) / d;
end
endfunction
// ---- grid tracers ----
int clear_cw_tile [0:1][0:1];
int flush_emits;
bit saw_prim_count_2;
initial begin
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++) clear_cw_tile[rr][cc]=0;
flush_emits=0; saw_prim_count_2=1'b0;
end
always_ff @(posedge clk) if (rst_n) begin
if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_color_we) begin
int cc, rr; cc=int'(dut.u_gs.tile_col_r); rr=int'(dut.u_gs.tile_row_r);
if (cc<2 && rr<2) clear_cw_tile[rr][cc] <= clear_cw_tile[rr][cc] + 1;
end
if (dut.u_gs.raster_pixel_emit) flush_emits <= flush_emits + 1;
if (dut.u_gs.raster_active && (int'(dut.u_gs.prim_count_r)==2)) saw_prim_count_2 <= 1'b1;
end
// ---- scanout capture (32x32) ----
logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y=0;y<V_ACTIVE;y++) for (int x=0;x<H_ACTIVE;x++) begin cap_r[y][x]=0;cap_g[y][x]=0;cap_b[y][x]=0;cap_de[y][x]=0; end
capture_armed=1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; cap_de[vcnt_d][hcnt_d]<=1'b1;
end
end
int errors, n_match, n_check, n_seam;
int n_rep2_white, n_clamp2_blue, n_first_white;
initial begin
errors=0; n_match=0; n_check=0; n_seam=0;
n_rep2_white=0; n_clamp2_blue=0; n_first_white=0;
rst_n=1'b0; core_go=1'b0;
repeat(4) @(posedge clk); rst_n=1'b1; repeat(8) @(posedge clk);
@(negedge clk); core_go=1'b1; @(negedge clk); core_go=1'b0;
wait (core_halt==1'b1); repeat(4) @(posedge clk);
wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
@(posedge dut.u_gs.raster_active);
@(negedge dut.u_gs.raster_active);
repeat(10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b1;
@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed=1'b0;
// PROOF GRID
for (int rr=0;rr<2;rr++) for (int cc=0;cc<2;cc++)
if (clear_cw_tile[rr][cc] != 256) begin
$error("[twr] tile(col=%0d,row=%0d) cleared %0d (want 256)", cc, rr, clear_cw_tile[rr][cc]); errors++;
end
if (flush_emits != 4*256) begin $error("[twr] flush emitted %0d (want %0d)", flush_emits, 4*256); errors++; end
if (!saw_prim_count_2) begin $error("[twr] prim_count_r never == 2"); errors++; end
// PROOF IMAGE — whole 32x32 vs the wrap/clamp reference.
for (int py=0; py<V_ACTIVE; py++) begin
for (int px=0; px<H_ACTIVE; px++) begin
int crep, cclmp, tu, te, mode;
real uf, fr;
logic [7:0] er, eg, eb;
bit skip_u;
crep = tri_cls(real'(px),real'(py), 2,4, 29,4, 2,15); // REPEAT tri (top)
cclmp = tri_cls(real'(px),real'(py), 2,17,29,17,2,28); // CLAMP tri (bottom)
er=8'hxx; eg=8'hxx; eb=8'hxx; mode=-1; uf=0.0;
if (crep==2 || cclmp==2) begin
// near a triangle edge -> skip
end else if (crep==1) begin
mode=0; uf = 8.0 * tri_wb(real'(px),real'(py), 2,4, 29,4, 2,15);
end else if (cclmp==1) begin
mode=1; uf = 8.0 * tri_wb(real'(px),real'(py), 2,17,29,17,2,28);
end else begin
er=8'h00; eg=8'h80; eb=8'h00; // outside both -> clear green
end
if (mode>=0) begin
fr = uf - $floor(uf);
skip_u = (fr < UFRAC) || (fr > 1.0-UFRAC); // near texel boundary -> ambiguous
if (!skip_u) begin
tu = int'($floor(uf));
te = (mode==0) ? (tu & (TWIDTH-1)) : ((tu < TWIDTH) ? tu : TWIDTH-1);
// striped texture: columns 0,1 white; 2,3 blue (opaque -> texel RGB)
if (te <= 1) begin er=8'hFF; eg=8'hFF; eb=8'hFF; end
else begin er=8'h00; eg=8'h00; eb=8'hFF; end
end
end
if (er!==8'hxx && cap_de[py][px]) begin
n_check++;
// distinguishing tallies (u in [4,6))
if (mode>=0 && uf>=4.0 && uf<6.0 && !( (uf-$floor(uf))<UFRAC || (uf-$floor(uf))>1.0-UFRAC )) begin
if (mode==0 && er==8'hFF) n_rep2_white++;
if (mode==1 && eb==8'hFF && er==8'h00) n_clamp2_blue++;
end
if (mode>=0 && uf>=0.0 && uf<2.0 && er==8'hFF) n_first_white++;
if (cap_r[py][px]===er && cap_g[py][px]===eg && cap_b[py][px]===eb) begin
n_match++;
if (px==15||px==16) n_seam++;
end else begin
if (errors<14) $error("[twr] (%0d,%0d) mode=%0d uf=%0.2f got(%02x,%02x,%02x) exp(%02x,%02x,%02x)",
px,py,mode,uf,cap_r[py][px],cap_g[py][px],cap_b[py][px],er,eg,eb);
errors++;
end
end
end
end
if (n_check < 150) begin $error("[twr] too few checkable pixels (%0d)", n_check); errors++; end
if (n_match != n_check) begin $error("[twr] image match %0d/%0d (wrap/clamp error)", n_match, n_check); errors++; end
if (n_first_white < 8) begin $error("[twr] first white stripe thin (%0d) — texture not sampled", n_first_white); errors++; end
if (n_rep2_white < 4) begin $error("[twr] REPEAT 2nd stripe thin (%0d) — repeat not proven", n_rep2_white); errors++; end
if (n_clamp2_blue < 4) begin $error("[twr] CLAMP region not blue enough (%0d) — clamp not proven", n_clamp2_blue); errors++; end
if (n_seam < 8) begin $error("[twr] too few SEAM matches (%0d)", n_seam); errors++; end
if (!core_halt) begin $error("core_halt low"); errors++; end
if (raster_overflow) begin $error("raster_overflow"); errors++; end
$display("[tb_top_psmct32_tile_wrap_demo] clears=[%0d %0d %0d %0d] flush=%0d prim2=%0b match=%0d/%0d seam=%0d | firstW=%0d rep2W=%0d clamp2B=%0d errors=%0d",
clear_cw_tile[0][0],clear_cw_tile[0][1],clear_cw_tile[1][0],clear_cw_tile[1][1],
flush_emits, saw_prim_count_2, n_match, n_check, n_seam,
n_first_white, n_rep2_white, n_clamp2_blue, errors);
if (errors==0) $display("[tb_top_psmct32_tile_wrap_demo] PASS");
else $display("[tb_top_psmct32_tile_wrap_demo] FAIL");
$finish;
end
initial begin #300000000; $error("[tb_top_psmct32_tile_wrap_demo] TIMEOUT"); $finish; end
endmodule : tb_top_psmct32_tile_wrap_demo
sim/tb/top/tb_top_psmct32_triangle_demo.sv
+257
View File
@@ -0,0 +1,257 @@
// retroDE_ps2 — tb_top_psmct32_triangle_demo (Brick 3)
//
// TOP-LEVEL non-axis-aligned GOURAUD TRIANGLE demo TB for the BRAM BOARD
// VARIANT. Proves the first real triangle renders end-to-end through
// `top_psmct32_raster_demo_bram` exactly as a board load would SHOW on
// HDMI — with interpolated COLOR (Gouraud) and interpolated DEPTH (Z).
//
// EE bootlet (bios_triangle.mem) + GIF payload (payload_triangle.mem):
// U1 PACKED -> TRI A: Gouraud, v0=(1,1) RED, v1=(14,1) GREEN,
// v2=(7,7) BLUE, FLAT-NEAR Z=0x300, GEQUAL Z-test,
// ZBUF ZBP=2 PSMZ32 (cleared -> passes, stamps Z=0x300).
// U2 PACKED -> TRI B: grey (0x80) at FLAT-FAR Z=0x100, v0=(2,5)
// v1=(13,5) v2=(7,2). Drawn second; GEQUAL.
//
// Expected on screen:
// * TRI A is a real non-axis-aligned (downward) Gouraud triangle: its
// interior shows a visible R/G/B gradient (corners tend toward the
// vertex colors).
// * In the band where TRI B overlaps TRI A, TRI A WINS (its Z=0x300 >
// TRI B's interpolated Z=0x100 under GEQUAL), so those pixels are
// TRI A's Gouraud color, NOT grey — proving the per-pixel
// interpolated depth gated the second triangle's write.
// * TRI B only paints grey where TRI A did NOT cover (stored Z=0 there).
//
// Checks:
// (1) coverage: a representative set of TRI A interior pixels are
// drawn (non-zero color, DE asserted), and a clearly-outside
// pixel is background (black).
// (2) gradient: the color VARIES across TRI A (not flat) and the
// near-vertex regions lean toward the corresponding vertex color.
// (3) depth gating: a pixel inside the TRI A/TRI B overlap is NOT grey
// (TRI A won) — proving interpolated-Z depth test gated TRI B.
`timescale 1ns/1ps
module tb_top_psmct32_triangle_demo;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.PSMCT32_SWIZZLE(1'b0)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// ----- Frame capture (delayed counters: BRAM read is registered) -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 8'd0; cap_g[y][x] = 8'd0;
cap_b[y][x] = 8'd0; cap_de[y][x] = 1'b0;
end
capture_armed = 1'b0;
end
logic [31:0] hcnt_d, vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin
hcnt_d <= 32'd0; vcnt_d <= 32'd0;
end else begin
hcnt_d <= 32'(dut.u_pcrtc.hcnt);
vcnt_d <= 32'(dut.u_pcrtc.vcnt);
end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de
&& (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
int errors;
initial errors = 0;
function automatic bit is_grey(input int x, input int y);
return (cap_r[y][x] == 8'h80) && (cap_g[y][x] == 8'h80) && (cap_b[y][x] == 8'h80);
endfunction
function automatic bit nonzero(input int x, input int y);
return (cap_r[y][x] != 0) || (cap_g[y][x] != 0) || (cap_b[y][x] != 0);
endfunction
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk); core_go = 1'b1;
@(negedge clk); core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1) wait (dut.xfer_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1) wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
// ---- (1) Coverage: representative TRI A interior pixels drawn ----
// TRI A spans v0=(1,1) v1=(14,1) v2=(7,7); centre column near the
// top is solidly interior. Check a few deep-interior pixels.
begin
int interior_drawn;
interior_drawn = 0;
for (int yy = 2; yy <= 5; yy++)
for (int xx = 5; xx <= 9; xx++)
if (cap_de[yy][xx] && nonzero(xx, yy))
interior_drawn = interior_drawn + 1;
if (interior_drawn < 12) begin
$error("TRI A interior coverage too sparse: %0d/20 deep-interior pixels drawn",
interior_drawn);
errors = errors + 1;
end
$display("[tri_demo] TRI A deep-interior drawn = %0d/20", interior_drawn);
end
// Clearly-OUTSIDE pixel (top corners outside the downward tri).
if (nonzero(0, 7)) begin
// (0,7): far bottom-left, outside TRI A and outside TRI B.
$error("outside pixel (0,7) is colored (%02x,%02x,%02x), expected background",
cap_r[7][0], cap_g[7][0], cap_b[7][0]);
errors = errors + 1;
end
// ---- (2) Gradient present: color VARIES across TRI A ----
// Top-left interior (near RED v0) should have more R than B;
// top-right interior (near GREEN v1) more G than R; lower-centre
// (near BLUE v2) more B than R. We sample interior pixels.
begin
// near v0 (1,1) RED: pixel (3,2)
if (cap_de[2][3] && !(cap_r[2][3] > cap_b[2][3])) begin
$error("gradient: near-RED (3,2) R=%0d not > B=%0d", cap_r[2][3], cap_b[2][3]);
errors = errors + 1;
end
// near v1 (14,1) GREEN: pixel (12,2)
if (cap_de[2][12] && !(cap_g[2][12] > cap_r[2][12])) begin
$error("gradient: near-GREEN (12,2) G=%0d not > R=%0d", cap_g[2][12], cap_r[2][12]);
errors = errors + 1;
end
// near v2 (7,7) BLUE: pixel (7,6)
if (cap_de[6][7] && !(cap_b[6][7] > cap_r[6][7])) begin
$error("gradient: near-BLUE (7,6) B=%0d not > R=%0d", cap_b[6][7], cap_r[6][7]);
errors = errors + 1;
end
$display("[tri_demo] gradient samples: nearR(3,2)=(%0d,%0d,%0d) nearG(12,2)=(%0d,%0d,%0d) nearB(7,6)=(%0d,%0d,%0d)",
cap_r[2][3],cap_g[2][3],cap_b[2][3],
cap_r[2][12],cap_g[2][12],cap_b[2][12],
cap_r[6][7],cap_g[6][7],cap_b[6][7]);
end
// ---- (3) Depth gating: TRI A/TRI B overlap shows TRI A (not grey) ----
// The TRI B band is around y=2..5 mid-x; pixel (7,4) is inside both
// TRI A and TRI B. TRI A (Z=0x300) was stamped first; TRI B
// (Z=0x100) must FAIL GEQUAL there -> pixel is TRI A's Gouraud
// color, NOT grey 0x80.
begin
bit any_overlap_checked;
any_overlap_checked = 1'b0;
for (int yy = 3; yy <= 4; yy++) begin
for (int xx = 6; xx <= 8; xx++) begin
if (cap_de[yy][xx] && nonzero(xx, yy)) begin
any_overlap_checked = 1'b1;
if (is_grey(xx, yy)) begin
$error("depth gating FAIL: overlap (%0d,%0d) is GREY (TRI B won) — interp-Z not gated!",
xx, yy);
errors = errors + 1;
end
end
end
end
if (!any_overlap_checked) begin
$error("depth gating: no overlap pixel observed to test");
errors = errors + 1;
end
// And TRI B SHOULD have painted grey somewhere it was unoccluded
// (e.g. its lower band where TRI A didn't reach). Confirm grey
// appears at least once so we know TRI B actually drew.
begin
int grey_count;
grey_count = 0;
for (int yy = 0; yy < V_ACTIVE; yy++)
for (int xx = 0; xx < H_ACTIVE; xx++)
if (cap_de[yy][xx] && is_grey(xx, yy)) grey_count = grey_count + 1;
if (grey_count == 0) begin
$error("TRI B never painted grey anywhere — second triangle did not render");
errors = errors + 1;
end
$display("[tri_demo] grey (TRI B unoccluded) pixel count = %0d", grey_count);
end
end
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_triangle_demo] raster_emits=%0d errors=%0d",
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0) $display("[tb_top_psmct32_triangle_demo] PASS");
else $display("[tb_top_psmct32_triangle_demo] FAIL");
$finish;
end
initial begin
#20000000;
$error("[tb_top_psmct32_triangle_demo] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_triangle_demo
sim/tb/top/tb_top_psmct32_zbuffer_demo.sv
+216
View File
@@ -0,0 +1,216 @@
// retroDE_ps2 — tb_top_psmct32_zbuffer_demo (Brick 2b)
//
// TOP-LEVEL Z-buffer (depth test) demo TB for the BRAM BOARD VARIANT.
// Proves the synthesizable FLAT Z-tested PSMCT32 SPRITE path renders
// end-to-end through `top_psmct32_raster_demo_bram` exactly as a board
// load would SHOW on HDMI.
//
// EE bootlet (bios_zbuffer.mem) + GIF payload (payload_zbuffer.mem):
// U1 PACKED -> NEAR red SPRITE, Z=0x200, x[0..11] y[0..7],
// TEST_1.ZTE=1 ZTST=GEQUAL, ZBUF_1 ZBP=1 PSMZ32 ZMSK=0.
// U2 PACKED -> FAR blue SPRITE, Z=0x100, x[4..15] y[0..7] (drawn
// second; GIF context PRIM/FRAME/TEST/ZBUF persist).
//
// The Z buffer (ZBP=1 -> byte base 0x800) starts cleared (VRAM power-on
// zero). NEAR draws first (Z 0x200 >= 0 everywhere it covers, passes),
// stamping Z=0x200 at x[0..11]. FAR draws second; with GEQUAL its
// Z=0x100 is BEHIND the near Z(0x200) in the overlap x[4..11], so it
// FAILS and does NOT overwrite — near wins regardless of draw order.
//
// near-only x[0..3] -> RED (0xFF,0x00,0x00)
// overlap x[4..11] -> RED (near wins; NOT blue last-drawn)
// far-only x[12..15] -> BLUE (0x00,0x00,0xFF; stored Z=0 there)
//
// The overlap guard asserts the overlap is RED, NOT BLUE — proving the
// depth test actually gated the FAR write rather than last-write-wins.
`timescale 1ns/1ps
module tb_top_psmct32_zbuffer_demo;
localparam int H_ACTIVE = 16;
localparam int V_ACTIVE = 8;
logic clk;
logic rst_n;
initial clk = 1'b0;
always #5 clk = ~clk;
logic core_go;
logic [7:0] r, g, b;
logic hsync, vsync, de;
logic core_halt;
logic dma_done_seen;
logic frame_seen;
logic raster_overflow;
logic frame_toggle;
logic dma_done_toggle;
top_psmct32_raster_demo_bram #(
.H_ACTIVE (H_ACTIVE),
.V_ACTIVE (V_ACTIVE),
.PSMCT32_SWIZZLE(1'b0)
) dut (
.clk(clk), .rst_n(rst_n),
.core_go(core_go),
.r(r), .g(g), .b(b),
.hsync(hsync), .vsync(vsync), .de(de),
.core_halt(core_halt),
.dma_done_seen(dma_done_seen),
.frame_seen(frame_seen),
.raster_overflow(raster_overflow),
.frame_toggle(frame_toggle),
.dma_done_toggle(dma_done_toggle),
.joy_a_pressed_i(1'b0),
.joy_b_pressed_i(1'b0)
);
// ----- Expected colors -----
localparam logic [7:0] NEAR_R = 8'hFF, NEAR_G = 8'h00, NEAR_B = 8'h00; // red
localparam logic [7:0] FAR_R = 8'h00, FAR_G = 8'h00, FAR_B = 8'hFF; // blue
// ----- Frame capture (delayed counters: BRAM read is registered) -----
logic [7:0] cap_r [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_g [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic [7:0] cap_b [0:V_ACTIVE-1][0:H_ACTIVE-1];
logic cap_de[0:V_ACTIVE-1][0:H_ACTIVE-1];
bit capture_armed;
initial begin
for (int y = 0; y < V_ACTIVE; y++)
for (int x = 0; x < H_ACTIVE; x++) begin
cap_r[y][x] = 8'd0;
cap_g[y][x] = 8'd0;
cap_b[y][x] = 8'd0;
cap_de[y][x] = 1'b0;
end
capture_armed = 1'b0;
end
logic [31:0] hcnt_d;
logic [31:0] vcnt_d;
always_ff @(posedge clk) begin
if (!rst_n) begin
hcnt_d <= 32'd0;
vcnt_d <= 32'd0;
end else begin
hcnt_d <= 32'(dut.u_pcrtc.hcnt);
vcnt_d <= 32'(dut.u_pcrtc.vcnt);
end
end
always_ff @(posedge clk) begin
if (rst_n && capture_armed && de
&& (vcnt_d < V_ACTIVE) && (hcnt_d < H_ACTIVE)) begin
cap_r [vcnt_d][hcnt_d] <= r;
cap_g [vcnt_d][hcnt_d] <= g;
cap_b [vcnt_d][hcnt_d] <= b;
cap_de[vcnt_d][hcnt_d] <= 1'b1;
end
end
int errors;
int near_ok;
int overlap_ok;
int far_ok;
initial begin
errors = 0; near_ok = 0; overlap_ok = 0; far_ok = 0;
end
// Returns 1 (via `ok` output) when the pixel matched; iverilog-12
// doesn't support task reference ports, so the caller increments
// the per-region counter from `ok`.
task automatic chk(input int x, input int y,
input logic [7:0] er, input logic [7:0] eg, input logic [7:0] eb,
input string label, output bit ok);
ok = 1'b0;
if (!cap_de[y][x]) begin
$error("%s (%0d,%0d) DE never asserted", label, x, y);
errors = errors + 1;
end else if (cap_r[y][x] !== er || cap_g[y][x] !== eg || cap_b[y][x] !== eb) begin
$error("[%s] (%0d,%0d) got (%02x,%02x,%02x) expected (%02x,%02x,%02x)",
label, x, y, cap_r[y][x], cap_g[y][x], cap_b[y][x], er, eg, eb);
errors = errors + 1;
end else begin
ok = 1'b1;
end
endtask
initial begin
rst_n = 1'b0;
core_go = 1'b0;
repeat (4) @(posedge clk);
rst_n = 1'b1;
repeat (8) @(posedge clk);
@(negedge clk);
core_go = 1'b1;
@(negedge clk);
core_go = 1'b0;
wait (core_halt == 1'b1);
repeat (4) @(posedge clk);
wait (dma_done_seen == 1'b1);
repeat (10) @(posedge clk);
if (dut.xfer_busy == 1'b1)
wait (dut.xfer_busy == 1'b0);
if (dut.u_gs.raster_active == 1'b1)
wait (dut.u_gs.raster_active == 1'b0);
repeat (10) @(posedge clk);
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b1;
@(posedge dut.u_pcrtc.end_of_frame);
@(posedge clk);
capture_armed = 1'b0;
begin
bit ok;
for (int y = 0; y < 8; y++) begin
// near-only x[0..3] -> RED
for (int x = 0; x < 4; x++) begin
chk(x, y, NEAR_R, NEAR_G, NEAR_B, "near", ok);
if (ok) near_ok = near_ok + 1;
end
// overlap x[4..11] -> RED (near wins, NOT far/last-drawn)
for (int x = 4; x < 12; x++) begin
chk(x, y, NEAR_R, NEAR_G, NEAR_B, "overlap", ok);
if (ok) overlap_ok = overlap_ok + 1;
// Guard: overlap must NOT be the FAR (last-drawn) color.
if (cap_r[y][x] === FAR_R && cap_g[y][x] === FAR_G && cap_b[y][x] === FAR_B) begin
$error("[overlap] (%0d,%0d) is FAR (last-drawn) — depth NOT gated!", x, y);
errors = errors + 1;
end
end
// far-only x[12..15] -> BLUE
for (int x = 12; x < 16; x++) begin
chk(x, y, FAR_R, FAR_G, FAR_B, "far", ok);
if (ok) far_ok = far_ok + 1;
end
end
end
if (!core_halt) begin $error("core_halt low at end"); errors = errors + 1; end
if (!dma_done_seen) begin $error("dma_done_seen never latched"); errors = errors + 1; end
if (!frame_seen) begin $error("frame_seen never latched"); errors = errors + 1; end
if (raster_overflow) begin $error("raster_overflow set"); errors = errors + 1; end
$display("[tb_top_psmct32_zbuffer_demo] near_ok=%0d/32 overlap_ok=%0d/64 far_ok=%0d/32 raster_emits=%0d errors=%0d",
near_ok, overlap_ok, far_ok,
dut.u_gs.raster_pixel_emit_count, errors);
if (errors == 0)
$display("[tb_top_psmct32_zbuffer_demo] PASS");
else
$display("[tb_top_psmct32_zbuffer_demo] FAIL");
$finish;
end
initial begin
#20000000;
$error("[tb_top_psmct32_zbuffer_demo] TIMEOUT");
$finish;
end
endmodule : tb_top_psmct32_zbuffer_demo