thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
527 lines
22 KiB
Systemverilog
527 lines
22 KiB
Systemverilog
// retroDE_ps2 — tb_hdmi_i2c_wake_smoke (Ch165 Medium + Ch166 NACK watchdog + Ch167 byte-sequence lock)
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//
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// Focused, accelerated bring-up TB for the Ch165 ADV7513 I²C
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// wake-up FSM (`I2C_HDMI_Config` → `I2C_Controller`). The
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// existing Ch149 board TB only smoke-tests the wrapper and
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// can't observe the LUT walk because at the production I²C
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// clock divider (50 MHz / 20 kHz = 2500) the full 38-entry
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// walk takes ~125 ms simulated (controller-clock period
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// ~100 µs × 33 phases per byte × 38 bytes) — far longer
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// than the 5 ms board-TB runtime. This TB instantiates
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// `I2C_HDMI_Config` directly with a tiny `CLK_Freq / I2C_Freq`
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// ratio so the LUT walks in microseconds, then exercises:
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// Phase 1 — `LUT_INDEX` advances 0 → LUT_SIZE−1 (38-entry walk).
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// Phase 1 — `READY` (= `hdmi_init_done`) rises after the walk.
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// Phase 1 — Ch167 byte-sequence lock: a bus-level decoder samples
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// SDA on each SCL rising edge between START/STOP and
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// assembles all 38 transactions as 24-bit
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// {dev_addr, reg, data} tuples; in parallel a snoop on
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// `mI2C_GO` rises captures the FSM-intent payload from
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// `u_dut.mI2C_DATA[23:0]`. After the walk completes the
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// test asserts the captured wire bytes match the
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// FSM-intent bytes one-for-one and that every dev_addr
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// is 8'h72 (ADV7513 write address).
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// Phase 2 — `HDMI_TX_INT` low retriggers the FSM (`LUT_INDEX`
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// back to 0; `READY` falls until the second walk).
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// Bus capture is disabled here so the retrigger walk
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// doesn't overflow the captured/expected logs.
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// Phase 3 — Open-drain shape check: SDA is never `'x` (would
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// indicate two drivers contending for strong-HIGH).
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// Phase 1-3 — `ERROR` (Ch166 NACK watchdog) stays LOW on the
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// healthy bus.
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// Phase 4 — Force `u_dut.mI2C_ACK = 1` to simulate a slave that
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// never ACKs. The FSM retries the same LUT entry; after
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// NACK_LIMIT (overridden to 4) consecutive retries
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// `ERROR` must latch HIGH. Releasing the force must
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// NOT clear `ERROR` (sticky semantics).
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//
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// Bus model — Ch167 switched the legacy pulldown(sda) to
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// pullup(sda) plus a minimal slave-ACK driver: after each START,
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// count SCL rising edges; on the 8th, 17th, and 26th edge the
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// slave drives SDA strong-LOW for one ACK clock so the master
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// FSM sees ACK=0 and advances. Pullup is required because the
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// master encodes a 1-bit by *releasing* SDA (1'bz), and a
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// pulldown would mask every released bit as 0 — preventing
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// byte-level decode.
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//
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// Slave model: the TB pulls SDA LOW unconditionally (weak
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// pulldown). The master drives SDA either strong-LOW (sending
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// 0 or releasing to high-Z while the chip ACKs); on
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// release-cycles the pulldown wins and the master reads ACK=0
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// → the FSM advances every byte. Data correctness on the bus
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// is NOT modeled — this TB only verifies FSM progress + the
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// open-drain release behavior, which is exactly the audit's
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// scope (`Medium — verify the LUT walk + READY + SDA + INT
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// retrigger`).
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`timescale 1ns/1ps
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module tb_hdmi_i2c_wake_smoke;
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// 100 MHz TB clock. The wake-up FSM divides this internally,
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// but the parameter overrides below collapse the divider to
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// ~2 cycles per I²C controller-clock toggle.
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logic clk;
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initial clk = 1'b0;
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always #5 clk = ~clk;
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logic rst_n;
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logic hdmi_tx_int;
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// I²C bus modeling. The bus floats high through external
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// pull-ups in real hardware. Ch167 byte-sequence-lock work
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// requires the line to read each transmitted bit faithfully:
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// master drives strong-LOW for 0 and releases (1'bz) for 1,
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// so a pull-up is needed to bring 1's up to 1'b1 (pulldown
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// would mask every released bit as 0). The minimal I²C slave
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// model below drives SDA strong-LOW during the three ACK
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// windows of every transaction so the master FSM sees ACK=0
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// and advances to the next LUT entry.
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wire scl;
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wire sda;
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pullup(sda);
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// ----------------------------------------------------------
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// Bus-edge detection (used by the slave-ACK driver and the
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// byte-sequence decoder). Sampled on the TB master clock.
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// ----------------------------------------------------------
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reg scl_d, sda_d;
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always_ff @(posedge clk) begin
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scl_d <= scl;
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sda_d <= sda;
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end
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wire scl_rise = scl && !scl_d;
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wire sda_fall_during_scl_high = scl && !sda && sda_d;
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wire sda_rise_during_scl_high = scl && sda && !sda_d;
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// ----------------------------------------------------------
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// Minimal I²C slave-ACK driver. The master's I2C_Controller
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// FSM lives at u_dut.u0; phase encoding is a 6-bit register
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// with PH_ACK0=11, PH_ACK1=20, PH_ACK2=29 (see
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// rtl/platform/I2C_Controller.v parameters). Drive SDA
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// strong-LOW for the entire ACK phase so the master sees
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// ACK=0 regardless of where it samples within the phase.
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// Outside ACK phases SDA is 1'bz so the master's data bits
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// (released → 1'b1, driven → 1'b0) are visible to the
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// byte decoder. This is far more robust than counting SCL
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// edges (which races at ACK boundaries when input-clock
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// resolution is only 2× the controller-clock period).
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// ----------------------------------------------------------
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wire slave_in_ack_phase =
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(u_dut.u0.phase == 6'd11) || // PH_ACK0
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(u_dut.u0.phase == 6'd20) || // PH_ACK1
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(u_dut.u0.phase == 6'd29); // PH_ACK2
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assign sda = slave_in_ack_phase ? 1'b0 : 1'bz;
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// ----------------------------------------------------------
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// Ch167 byte-sequence lock. Bus-level decoder: between
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// START and STOP, sample SDA on each SCL rising edge and
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// assemble three 8-bit data bytes (skipping the ACK windows
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// at edges 8, 17, 26). On STOP, append the 24-bit
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// {dev_addr, reg, data} payload to a captured[] log. A
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// parallel snoop on `mI2C_GO` rising edges captures the
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// FSM's intent (`u_dut.mI2C_DATA[23:0]`) into expected[].
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// After the first LUT walk completes (Phase 1), the test
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// asserts captured[i] === expected[i] for i = 0..LUT_SIZE-1.
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// ----------------------------------------------------------
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bit bus_capture_enable;
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initial bus_capture_enable = 1'b1;
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typedef enum logic [0:0] { DEC_IDLE, DEC_TXN } dec_state_t;
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dec_state_t dec_state;
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int dec_bit_count;
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logic [23:0] dec_payload;
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int captured_count;
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logic [23:0] captured [0:63];
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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dec_state <= DEC_IDLE;
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dec_bit_count <= 0;
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dec_payload <= 24'h0;
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captured_count <= 0;
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end else if (bus_capture_enable) begin
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case (dec_state)
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DEC_IDLE: begin
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if (sda_fall_during_scl_high) begin
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dec_state <= DEC_TXN;
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dec_bit_count <= 0;
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dec_payload <= 24'h0;
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end
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end
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DEC_TXN: begin
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if (sda_rise_during_scl_high &&
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!slave_in_ack_phase &&
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dec_bit_count >= 27) begin
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// STOP — record the captured payload.
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if (captured_count < 64)
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captured[captured_count] <= dec_payload;
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captured_count <= captured_count + 1;
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dec_state <= DEC_IDLE;
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end else if (scl_rise && dec_bit_count < 27) begin
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// Map SCL-rise position within transaction
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// to a bit slot in the 24-bit payload
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// (MSB-first per byte). Edges 8/17/26 are
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// ACK windows - sample but discard.
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case (dec_bit_count)
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0: dec_payload[23] <= sda;
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1: dec_payload[22] <= sda;
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2: dec_payload[21] <= sda;
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3: dec_payload[20] <= sda;
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4: dec_payload[19] <= sda;
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5: dec_payload[18] <= sda;
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6: dec_payload[17] <= sda;
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7: dec_payload[16] <= sda;
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// 8 = ACK0
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9: dec_payload[15] <= sda;
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10: dec_payload[14] <= sda;
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11: dec_payload[13] <= sda;
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12: dec_payload[12] <= sda;
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13: dec_payload[11] <= sda;
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14: dec_payload[10] <= sda;
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15: dec_payload[9] <= sda;
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16: dec_payload[8] <= sda;
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// 17 = ACK1
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18: dec_payload[7] <= sda;
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19: dec_payload[6] <= sda;
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20: dec_payload[5] <= sda;
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21: dec_payload[4] <= sda;
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22: dec_payload[3] <= sda;
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23: dec_payload[2] <= sda;
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24: dec_payload[1] <= sda;
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25: dec_payload[0] <= sda;
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// 26 = ACK2
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default: ;
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endcase
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dec_bit_count <= dec_bit_count + 1;
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end
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end
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endcase
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end
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end
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// FSM-intent snoop: capture u_dut.mI2C_DATA on each rising
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// edge of u_dut.mI2C_GO. The FSM raises GO once per LUT
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// entry's first attempt (and again on each retry, but
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// expected_count is gated to LUT_SIZE so retries don't
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// overflow).
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reg mi2c_go_d;
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int expected_count;
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logic [23:0] expected_seq [0:63];
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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mi2c_go_d <= 1'b0;
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expected_count <= 0;
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end else begin
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mi2c_go_d <= u_dut.mI2C_GO;
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if (u_dut.mI2C_GO && !mi2c_go_d && bus_capture_enable) begin
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if (expected_count < 64)
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expected_seq[expected_count] <= u_dut.mI2C_DATA[23:0];
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expected_count <= expected_count + 1;
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end
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end
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end
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// The DUT. Tiny CLK_Freq/I2C_Freq ratio (≈ 1) collapses the
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// controller-clock divider so the LUT walks in microseconds
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// instead of tens of milliseconds. NACK_LIMIT shrunk from
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// production 16 → 4 so Phase 4 (forced-NACK error trigger)
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// finishes in microseconds rather than tens of ms.
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logic ready;
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logic dut_error;
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I2C_HDMI_Config #(
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.CLK_Freq (2),
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.I2C_Freq (1),
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.LUT_SIZE (38),
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.NACK_LIMIT (4)
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) u_dut (
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.iCLK (clk),
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.iRST_N (rst_n),
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.I2C_SCLK (scl),
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.I2C_SDAT (sda),
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.HDMI_TX_INT(hdmi_tx_int),
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.READY (ready),
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.ERROR (dut_error)
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);
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// ----------------------------------------------------------
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// Phase 1: reset, watch the FSM walk LUT_INDEX 0 → 37.
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// ----------------------------------------------------------
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int errors;
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int lut_index_max_seen;
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int ready_rise_cycles;
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bit saw_lut_full_walk;
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bit saw_ready_rise;
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bit saw_error_during_happy_path;
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// Hoisted out of the Phase-2/Phase-3/Phase-4 initial block below so
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// iverilog 12 (which rejects mid-block declarations after executable
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// statements) accepts the file. Module-scope `bit`/`int` initialize
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// to 0 / 1'b0.
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bit saw_restart;
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int lut_idx_after_int;
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int sda_high_obs;
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bit saw_error_rise;
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initial begin
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errors = 0;
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lut_index_max_seen = 0;
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ready_rise_cycles = 0;
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saw_lut_full_walk = 1'b0;
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saw_ready_rise = 1'b0;
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rst_n = 1'b0;
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hdmi_tx_int = 1'b1; // deasserted (active-low)
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repeat (10) @(posedge clk);
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rst_n = 1'b1;
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end
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// Track the highest LUT_INDEX ever observed, and whether the
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// ERROR output ever rose during the "happy path" (Phases 1-3,
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// before the explicit NACK-injection Phase 4 begins).
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bit happy_path_active;
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initial happy_path_active = 1'b1;
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always_ff @(posedge clk) begin
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if (rst_n) begin
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if (int'(u_dut.LUT_INDEX) > lut_index_max_seen)
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lut_index_max_seen <= int'(u_dut.LUT_INDEX);
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if (u_dut.LUT_INDEX == u_dut.LUT_SIZE - 1)
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saw_lut_full_walk <= 1'b1;
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if (ready && !saw_ready_rise) begin
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saw_ready_rise <= 1'b1;
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ready_rise_cycles <= 0;
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end else if (saw_ready_rise) begin
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ready_rise_cycles <= ready_rise_cycles + 1;
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end
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if (happy_path_active && dut_error)
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saw_error_during_happy_path <= 1'b1;
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end
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end
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// ----------------------------------------------------------
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// Slave-side ACK behavior is implicit in the SDA pulldown:
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// when the master releases SDA at the 9th bit, the bus reads
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// LOW, the controller's mI2C_ACK samples 0, and the wake-up
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// FSM advances to LUT_INDEX+1. Sanity-check that the bus is
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// actually toggling (master drives SCL) — if SCL never
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// toggles, the FSM is stuck and we'd time out below.
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int scl_edge_count;
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initial scl_edge_count = 0;
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always @(scl) if (rst_n) scl_edge_count = scl_edge_count + 1;
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// ----------------------------------------------------------
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// Phase 2: once READY, pull HDMI_TX_INT LOW briefly and
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// assert the LUT walk restarts (LUT_INDEX returns to 0;
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// READY falls).
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// ----------------------------------------------------------
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initial begin
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// Wait for the first LUT walk to complete.
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wait (rst_n);
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fork
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begin
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wait (ready == 1'b1);
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end
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begin
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#5_000_000; // 5 ms wall budget
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$error("Phase 1: READY never asserted in 5 ms (LUT walk stuck or too slow)");
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errors = errors + 1;
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end
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join_any
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disable fork;
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// Phase 1 asserts. LUT_INDEX walks 0..LUT_SIZE-1 inside the
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// case() loop, then the post-step increments it to LUT_SIZE
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// (38) on the cycle the FSM falls through to the READY-high
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// branch — so the max value ever observed is LUT_SIZE, not
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// LUT_SIZE-1. The full-walk evidence comes from the separate
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// `saw_lut_full_walk` flag (LUT_INDEX == LUT_SIZE-1).
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if (lut_index_max_seen != 38) begin
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$error("Phase 1: LUT_INDEX max seen = %0d, expected 38 (LUT_SIZE)", lut_index_max_seen);
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errors = errors + 1;
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end
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if (!saw_lut_full_walk) begin
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$error("Phase 1: never observed LUT_INDEX == LUT_SIZE-1 (37)");
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errors = errors + 1;
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end
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if (!ready) begin
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$error("Phase 1: READY low after wait — fork race");
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errors = errors + 1;
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end
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if (scl_edge_count < 100) begin
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$error("Phase 1: only %0d SCL edges seen — bus is stuck", scl_edge_count);
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errors = errors + 1;
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end
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// ------------------------------------------------------
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// Ch167 byte-sequence lock. Compare every captured
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// 24-bit transaction (assembled from the wire) against
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// the FSM-intent snapshot (assembled at mI2C_GO rise).
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// Both should be exactly LUT_SIZE entries long; mismatch
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// means either the controller miswired the data path or
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// the FSM tried to send something unexpected.
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// ------------------------------------------------------
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// Settle a few extra cycles so the last STOP gets recorded.
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repeat (32) @(posedge clk);
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if (captured_count != int'(u_dut.LUT_SIZE)) begin
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$error("Ch167: captured %0d transactions on the wire, expected %0d",
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captured_count, u_dut.LUT_SIZE);
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errors = errors + 1;
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end
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if (expected_count != int'(u_dut.LUT_SIZE)) begin
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$error("Ch167: snooped %0d FSM-intent payloads, expected %0d",
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expected_count, u_dut.LUT_SIZE);
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errors = errors + 1;
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end
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for (int i = 0; i < int'(u_dut.LUT_SIZE); i++) begin
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if (captured[i] !== expected_seq[i]) begin
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$error("Ch167: txn %0d mismatch: bus=24'h%06h fsm=24'h%06h",
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i, captured[i], expected_seq[i]);
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errors = errors + 1;
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end
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end
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// First byte of every transaction must be 8'h72 = ADV7513
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// write address (7-bit 0x39 << 1, R/W=0). Cross-check the
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// captured stream directly so we lock the dev_addr too.
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for (int i = 0; i < int'(u_dut.LUT_SIZE); i++) begin
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if (captured[i][23:16] !== 8'h72) begin
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$error("Ch167: txn %0d dev_addr=8'h%02h, expected 8'h72",
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i, captured[i][23:16]);
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errors = errors + 1;
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end
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end
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// Disable bus capture for the rest of the test —
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// Phase 2 retriggers the LUT (would overflow captured[])
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// and Phase 4 forces NACKs (broken bus by design).
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bus_capture_enable = 1'b0;
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// Phase 2: HDMI_TX_INT retrigger. Pull INT low while
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// READY is high; the FSM should reset LUT_INDEX to 0
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// and re-walk.
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@(posedge clk); hdmi_tx_int = 1'b0;
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// Hold long enough for the FSM to sample it.
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repeat (8) @(posedge clk);
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hdmi_tx_int = 1'b1;
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// Wait for LUT_INDEX to dip back below the max (proves
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// the FSM restarted) and then for READY to come back up.
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saw_restart = 1'b0;
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fork
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begin
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wait (u_dut.LUT_INDEX == 0);
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saw_restart = 1'b1;
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end
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begin
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#5_000_000;
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$error("Phase 2: LUT_INDEX never returned to 0 after HDMI_TX_INT pulse");
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errors = errors + 1;
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end
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join_any
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disable fork;
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if (!saw_restart) begin
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// (already errored above)
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end else begin
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// Wait for the second walk to complete.
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fork
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begin
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wait (ready == 1'b1 && u_dut.LUT_INDEX >= u_dut.LUT_SIZE);
|
||
end
|
||
begin
|
||
#5_000_000;
|
||
$error("Phase 2: READY did not reassert after retrigger walk");
|
||
errors = errors + 1;
|
||
end
|
||
join_any
|
||
disable fork;
|
||
end
|
||
|
||
// Phase 3: open-drain shape check. With the Ch167 pullup
|
||
// + slave-ACK bus model, the line is HIGH at idle and
|
||
// LOW only when the master drives a 0 or when the slave
|
||
// drives the ACK. The relevant violation is that no two
|
||
// drivers ever simultaneously drive strong-HIGH (which
|
||
// would resolve to 'x' on a tri-state wire). Sample SDA
|
||
// repeatedly and assert it is never 'x'.
|
||
// (Reusing `sda_high_obs` as the violation counter.)
|
||
sda_high_obs = 0;
|
||
repeat (50) begin
|
||
@(posedge clk);
|
||
if (sda === 1'bx) sda_high_obs = sda_high_obs + 1;
|
||
end
|
||
if (sda_high_obs > 0) begin
|
||
$error("Phase 3: SDA was 'x' on %0d/50 sample cycles (driver conflict / open-drain violation)",
|
||
sda_high_obs);
|
||
errors = errors + 1;
|
||
end
|
||
|
||
// Happy-path ERROR check: across Phases 1-3 the bus was
|
||
// healthy (pulldown → ACK=0), so the NACK watchdog must
|
||
// never have fired.
|
||
if (saw_error_during_happy_path) begin
|
||
$error("Happy path: ERROR rose during normal walk (NACK watchdog false-positive)");
|
||
errors = errors + 1;
|
||
end
|
||
if (dut_error) begin
|
||
$error("Happy path: ERROR is HIGH at end of Phase 3 (expected LOW)");
|
||
errors = errors + 1;
|
||
end
|
||
|
||
// ----------------------------------------------------------
|
||
// Phase 4: forced-NACK error trigger. The healthy bus
|
||
// produced ACK=0 every byte (master sees the pulldown
|
||
// win the release window). Force `mI2C_ACK = 1'b1` to
|
||
// simulate a slave that doesn't ACK — every transaction
|
||
// bounces back to mSetup_ST=0 and retries the same LUT
|
||
// entry. After NACK_LIMIT consecutive retries (overridden
|
||
// to 4 above) the watchdog must latch ERROR.
|
||
//
|
||
// We also pulse HDMI_TX_INT so the FSM restarts the walk
|
||
// at LUT_INDEX=0 → predictable retry counter starting
|
||
// point.
|
||
happy_path_active = 1'b0;
|
||
@(posedge clk); hdmi_tx_int = 1'b0;
|
||
repeat (8) @(posedge clk);
|
||
hdmi_tx_int = 1'b1;
|
||
wait (u_dut.LUT_INDEX == 0);
|
||
force u_dut.mI2C_ACK = 1'b1;
|
||
|
||
saw_error_rise = 1'b0;
|
||
fork
|
||
begin
|
||
wait (dut_error == 1'b1);
|
||
saw_error_rise = 1'b1;
|
||
end
|
||
begin
|
||
#5_000_000;
|
||
$error("Phase 4: ERROR never asserted within 5 ms after forced NACK");
|
||
errors = errors + 1;
|
||
end
|
||
join_any
|
||
disable fork;
|
||
|
||
// ERROR is sticky. Releasing the force (slave starts ACKing
|
||
// again) must NOT clear it — only iRST_N would.
|
||
release u_dut.mI2C_ACK;
|
||
repeat (200) @(posedge clk);
|
||
if (!dut_error) begin
|
||
$error("Phase 4: ERROR was not sticky — went LOW after force released");
|
||
errors = errors + 1;
|
||
end
|
||
|
||
$display("[tb_hdmi_i2c_wake_smoke] lut_index_max=%0d saw_full_walk=%0b saw_ready_rise=%0b scl_edges=%0d saw_error_rise=%0b errors=%0d",
|
||
lut_index_max_seen, saw_lut_full_walk, saw_ready_rise,
|
||
scl_edge_count, saw_error_rise, errors);
|
||
if (errors == 0) $display("[tb_hdmi_i2c_wake_smoke] PASS");
|
||
else $display("[tb_hdmi_i2c_wake_smoke] FAIL");
|
||
$finish;
|
||
end
|
||
|
||
// Hard timeout — bound the whole test.
|
||
initial begin
|
||
#20_000_000;
|
||
$error("[tb_hdmi_i2c_wake_smoke] hard timeout");
|
||
$finish;
|
||
end
|
||
|
||
endmodule : tb_hdmi_i2c_wake_smoke
|