thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
130 lines
5.8 KiB
Bash
Executable File
130 lines
5.8 KiB
Bash
Executable File
#!/bin/sh
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# retroDE_ps2 LPDDR framebuffer write/readback test — Ch318 operator helper.
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#
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# Drives the runtime LPDDR test controls in `ps2_hps_bridge` and verifies the
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# tile-flush writer reached real LPDDR. ONE bitstream (GS_TILE_PSMCT16FB_DEMO +
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# GS_LPDDR_FB); all control is at runtime — no rebuild between stages.
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#
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# Same style/contract as ps2_status.sh: PS2 HPS-bridge base + busybox devmem
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# (busybox avoids the devmem2 "Bus error" quirk on 0x?4-suffixed offsets — and
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# LPDDR_BURSTS sits at 0x...34). See rtl/platform/ps2_hps_bridge.sv and
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# docs/ch318-lpddr-fb-bringup.md.
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#
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# Usage (run from HPS Linux after loading the .core.rbf):
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# ./ps2_lpddr_test.sh # read-only LPDDR status (safe; no arming)
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# ./ps2_lpddr_test.sh --canary # arm canary (1 line), re-render, prove via counters
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# ./ps2_lpddr_test.sh --full # arm full frame, re-render, prove via counters
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# ./ps2_lpddr_test.sh --disarm # write LPDDR_CTRL = 0x2 (disarmed, canary)
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#
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# PROOF METHOD = bridge counters, NOT /dev/mem. The Ch318 writer targets the HPS
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# LPDDR (f2sdram) at 0x80000000, which is a firmware-RESERVED region: reading it
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# with `dd /dev/mem` HARD-CRASHES the fabric (needs a power cycle). So this script
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# NEVER touches /dev/mem. It proves the write reached LPDDR by reading LPDDR_BYTES/
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# LPDDR_BURSTS/LPDDR_STATUS over the HPS bridge (safe register reads). Byte-level
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# CONTENT verification needs the Ch318b bridge-register readback path (ported from
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# ao486 lpddr4b_loader.sv) — until that lands, content is not checked here.
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#
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# ONE-SHOT FIX: the EE bootlet renders once at boot (before you can arm), then
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# halts -> BYTES stays 0. So --canary/--full arm FIRST, then pulse the core reset
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# (CORE_CTRL[0]) to re-run the bootlet and flush a frame WHILE ARMED.
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#
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# Defaults are SAFE: the bitstream boots disarmed; this script only writes when
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# you pass --canary/--full, and always leaves the writer disarmed on exit.
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set -u
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BASE="${PS2_BRIDGE_BASE:-0x40000000}"
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DEVMEM="${DEVMEM:-busybox devmem}"
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MODE="${1:-status}"
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# Register offsets (see ps2_hps_bridge.sv).
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OFF_CORE_CTRL=0x010 # RW [0]=core reset (pulse 1->0 re-runs the EE bootlet)
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OFF_LPDDR_CTRL=0x018 # RW [0]=arm [1]=canary (reset 0x2)
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OFF_LPDDR_FB_BASE=0x01C # RW LPDDR byte base (reset 0x80000000)
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OFF_LPDDR_STATUS=0x02C # R [0]=idle [1]=bresp_err [2]=fifo_ovf
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OFF_LPDDR_BYTES=0x030 # R total bytes written
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OFF_LPDDR_BURSTS=0x034 # R total 32-byte bursts
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OFF_LPDDR_BRESP_ERRS=0x038 # R count of bursts with non-OKAY response (1=reset-race phantom; 256=all refused)
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# Expected byte counts (canary = 1 top line = 32 B; full = 64x64 PSMCT16 = 8 KiB).
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EXP_CANARY_BYTES=32
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EXP_FULL_BYTES=8192
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read_reg() { $DEVMEM "$(printf '0x%08x' $(( BASE + $1 )) )" w; }
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write_reg() { $DEVMEM "$(printf '0x%08x' $(( BASE + $1 )) )" w "$2"; }
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bit_set() { if [ $(( ($1 >> $2) & 1 )) -eq 1 ]; then echo 1; else echo 0; fi; }
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show_status() {
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local ctrl base st by bu
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ctrl=$(read_reg $OFF_LPDDR_CTRL); base=$(read_reg $OFF_LPDDR_FB_BASE)
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st=$(read_reg $OFF_LPDDR_STATUS); by=$(read_reg $OFF_LPDDR_BYTES); bu=$(read_reg $OFF_LPDDR_BURSTS)
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printf "LPDDR writer status\n"
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printf " LPDDR_CTRL : %s (arm=%d canary=%d)\n" "$ctrl" "$(bit_set $((ctrl)) 0)" "$(bit_set $((ctrl)) 1)"
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printf " LPDDR_FB_BASE: %s\n" "$base"
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printf " LPDDR_STATUS : %s (idle=%d bresp_err=%d fifo_ovf=%d)\n" \
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"$st" "$(bit_set $((st)) 0)" "$(bit_set $((st)) 1)" "$(bit_set $((st)) 2)"
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printf " LPDDR_BYTES : %s\n LPDDR_BURSTS : %s\n" "$by" "$bu"
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printf " LPDDR_BRESP_ERRS: %s\n" "$(read_reg $OFF_LPDDR_BRESP_ERRS)"
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}
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err_bits_clear() { # 1 if bresp_err and fifo_ovf both 0
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local st=$(( $(read_reg $OFF_LPDDR_STATUS) ))
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[ "$(bit_set $st 1)" = "0" ] && [ "$(bit_set $st 2)" = "0" ]
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}
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# Re-run the EE bootlet so it renders a frame WHILE the writer is armed.
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# (The bootlet is one-shot; it renders once at boot, before you can arm.)
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rerender_pulse() {
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write_reg $OFF_CORE_CTRL 0x1 # assert core reset
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sleep 1
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write_reg $OFF_CORE_CTRL 0x0 # release -> bootlet re-runs, flushes a frame
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sleep 3 # ~2 s DMAC-drain render cadence + margin
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}
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# Arm, re-render, and prove the write reached LPDDR via the bridge counters.
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# $1 = LPDDR_CTRL arm value (0x3 canary / 0x1 full), $2 = expected byte count, $3 = label
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prove_via_counters() {
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local armval=$1 expbytes=$2 label=$3 by bu
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write_reg $OFF_LPDDR_CTRL "$armval" # arm
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rerender_pulse # render a frame while armed
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by=$(( $(read_reg $OFF_LPDDR_BYTES) ))
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bu=$(( $(read_reg $OFF_LPDDR_BURSTS) ))
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be=$(( $(read_reg $OFF_LPDDR_BRESP_ERRS) ))
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write_reg $OFF_LPDDR_CTRL 0x2 # DISARM
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printf "after re-render: LPDDR_BYTES=%d (expect %d) LPDDR_BURSTS=%d BRESP_ERRS=%d\n" "$by" "$expbytes" "$bu" "$be"
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if [ "$by" -ge "$expbytes" ] && err_bits_clear; then
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printf "%s: PASS (fabric delivered %d B to LPDDR; no AXI/FIFO errors)\n" "$label" "$by"
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return 0
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else
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printf "%s: FAIL (BYTES=%d < %d, or error bits set)\n" "$label" "$by" "$expbytes"
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show_status; return 1
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fi
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}
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case "$MODE" in
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status)
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show_status
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;;
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--canary)
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printf "== LPDDR CANARY (32-byte top-line write, counter proof) ==\n"
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printf "defaults: LPDDR_CTRL=%s (expect 0x00000002) LPDDR_FB_BASE=%s (expect 0x80000000)\n" \
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"$(read_reg $OFF_LPDDR_CTRL)" "$(read_reg $OFF_LPDDR_FB_BASE)"
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prove_via_counters 0x3 "$EXP_CANARY_BYTES" CANARY; exit $?
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;;
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--full)
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printf "== LPDDR FULL FRAME (%d B, counter proof) ==\n" "$EXP_FULL_BYTES"
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prove_via_counters 0x1 "$EXP_FULL_BYTES" FULL; exit $?
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;;
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--disarm)
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write_reg $OFF_LPDDR_CTRL 0x2
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printf "disarmed (LPDDR_CTRL=0x2)\n"
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;;
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*)
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printf "usage: %s [--canary|--full|--disarm] (no arg = status)\n" "$0"; exit 2
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;;
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esac
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