thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
79 lines
2.0 KiB
Markdown
79 lines
2.0 KiB
Markdown
# Memory Contract
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Status: `Draft`
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## Purpose
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Define the memory-visible contract of the system before any CPU or DMA block is
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implemented.
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## Scope
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- EE main RAM visibility and mirrors,
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- IOP RAM visibility,
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- scratchpad behavior,
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- BIOS ROM visibility,
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- GS VRAM abstraction,
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- SPU2 RAM abstraction,
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- arbitration between masters,
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- access ordering and observability requirements.
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## Explicitly owns
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- BIOS ROM storage, mapping, and address visibility.
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## Explicitly does not own
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- BIOS boot sequencing behavior after reset,
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- `IOPBOOT` / `IOPBTCONF` parsing and module-load execution flow,
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- interrupt-controller policy.
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## Must represent
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- 32 MiB EE main RAM with cached/uncached/mirrored views as required by the
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chosen bring-up scope,
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- 2 MiB IOP RAM,
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- 16 KiB scratchpad RAM,
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- 4 MiB BIOS ROM windowing,
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- 4 MiB GS VRAM,
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- 2 MiB SPU2 RAM.
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## Consumers / masters
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- EE core
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- EE DMAC
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- VIF/VU path
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- GIF/GS path
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- IOP core
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- IOP DMA
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- SPU2 path
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- optional HPS debug/service access
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## Contract questions to lock
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- Is there one central arbitration layer or separate local memories with bridges?
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- What ordering guarantees are required between CPU stores, DMA, and GS-visible
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operations?
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- Does the initial project model TLB/cache behavior directly, or only enough
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address translation to support staged bring-up?
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- Which regions are cycle-sensitive in Phase 1 versus functionally-correct only?
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## Required debug visibility
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- access trace: master, address, width, read/write, data when practical,
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- arbitration trace: grant decisions,
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- fault trace: unmapped or illegal accesses.
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## Allowed early stubs
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- BIOS ROM backed by placeholder image interface,
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- functionally-correct RAM without final timing,
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- GS VRAM as a simpler backing store before final internal organization is set.
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## Exit criteria for first implementation
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- BIOS fetch addresses resolve correctly,
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- EE RAM mirrors behave consistently for the chosen boot path,
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- scratchpad region is distinguishable from main RAM,
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- DMA and CPU accesses can be traced and correlated.
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