thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
54 lines
1.5 KiB
Markdown
54 lines
1.5 KiB
Markdown
# INTC Contract
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Status: `Draft`
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## Purpose
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Define interrupt-controller ownership explicitly so interrupt routing, masking,
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and acknowledgement do not become scattered across unrelated subsystem
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contracts.
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## Owns
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- EE interrupt controller register-visible behavior,
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- interrupt status accumulation,
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- interrupt mask behavior,
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- presentation of interrupt state to the EE,
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- acknowledgement / clear semantics visible through the INTC register block.
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## Inputs
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- interrupt sources from EE-side timers,
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- DMAC interrupt sources,
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- GIF/GS-visible interrupt sources where applicable,
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- IPU-visible interrupt sources where applicable,
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- any additional EE-side sources that target `INTC_STAT`.
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## Outputs
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- interrupt-pending state to the EE core,
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- register-visible status/mask values,
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- trace events for assertion, masking, and clearing.
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## Questions to lock
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- Which interrupt sources are required for the first BIOS-progress milestone?
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- Which sources may be stubbed as permanently inactive in Phase 1?
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- How will interrupt timing be modeled in early bring-up:
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- functionally-correct first
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- cycle-shaped from day one
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## Allowed early stubs
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- register-visible INTC with a reduced source set,
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- synthetic interrupt injection for directed tests,
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- simplified assertion timing so long as ordering is deterministic.
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## Required debug visibility
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- source assertion,
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- source masking,
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- pending-to-serviced transitions,
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- EE acknowledge/clear events,
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- dropped or unimplemented interrupt attempts.
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