thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
51 lines
1.3 KiB
Markdown
51 lines
1.3 KiB
Markdown
# EE Contract
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Status: `Draft`
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## Purpose
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Define what the Emotion Engine-facing block must provide to the rest of the
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system, independent of the eventual core implementation strategy.
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## Owns
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- R5900 execution core,
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- COP0-visible system behavior owned by the EE block,
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- FPU/MMI behavior as implemented by the EE-side compute engine,
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- exception and interrupt intake on the EE side,
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- request generation onto EE-visible memory and I/O space.
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## Inputs
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- clocks/resets,
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- interrupts,
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- memory read/write responses,
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- DMAC/VIF/VU/GS-visible status signals as needed by software-facing I/O.
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## Outputs
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- instruction fetches,
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- data reads/writes,
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- coprocessor-side requests,
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- interrupt acknowledge / exception state transitions,
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- debug trace events.
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## Questions to lock
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- Is the EE treated as an imported core behind a wrapper or as locally-owned RTL?
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- What minimum COP0/TLB behavior is required for the first BIOS milestone?
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- Which FPU edge cases are correctness-critical versus deferrable?
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## Allowed early stubs
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- fetch-only or reduced decode EE stub for memory-map bring-up,
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- reduced exception model for pre-BIOS milestones,
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- trace-only execution harness.
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## Required debug visibility
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- PC stream,
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- exception vector entries,
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- uncached/cached access origin tags when applicable,
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- selected register snapshots around traps and branches.
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