thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
72 lines
1.5 KiB
Markdown
72 lines
1.5 KiB
Markdown
# DMAC Contract
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Status: `Draft`
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## Purpose
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Define the EE DMA controller as a first-class subsystem with explicit channel
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behavior and traceability.
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## Owns
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- channel register state,
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- channel start/stop logic,
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- priority / scheduling policy,
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- interrupt generation,
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- transfer-side coordination to VIF, GIF, SIF, IPU, and scratchpad-related
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endpoints.
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## EE channels in scope
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- ch0 VIF0
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- ch1 VIF1
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- ch2 GIF
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- ch3 IPU_FROM
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- ch4 IPU_TO
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- ch5 SIF0
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- ch6 SIF1
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- ch7 SIF2
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- ch8 SPR_FROM
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- ch9 SPR_TO
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## Inputs
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- CPU writes to DMAC registers,
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- memory responses,
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- endpoint ready/busy signals,
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- reset/interrupt masking controls.
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## Outputs
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- memory read/write traffic,
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- endpoint transfers,
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- stall/busy signals,
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- interrupt status updates,
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- channel-level trace events.
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## Questions to lock
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- What is the minimum channel set for first visible output?
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- How much of stall/ring behavior is required before BIOS or homebrew becomes
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meaningful?
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- Will the internal datapath be modeled around 128-bit transfers from day one?
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## Allowed early stubs
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- channel register file with no data movement,
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- one-channel functional path for GIF-first testing,
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- simplified arbitration before full priority behavior.
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## Required debug visibility
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- per-channel start/stop,
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- source/destination context,
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- transfer counts,
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- interrupts,
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- blocked-on-endpoint reasons.
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## First meaningful milestone
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- ch2 GIF path can move a known-good packet stream from memory into a GS/GIF
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test endpoint while producing deterministic traces.
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