thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
161 lines
7.5 KiB
Markdown
161 lines
7.5 KiB
Markdown
# Ch283 closeout — 128-bit GPR shadow + PCPYUD (the upper-half MMI op)
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**Status:** Closed. **Verdict from re-running qbert.elf:**
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`elf_first_unsupported_opcode (pc=0x00113378 instr=0xdfbf0000)` —
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opcode 0x37 = **LD (Load Doubleword)**, encoding `ld $ra, 0($ra)`.
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This is the end-of-function return-address restore pattern, hit
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*after* the byte-walker PCPYUD path completes and the function
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returns. qbert retire_count: 27,024 → **27,067** (+43). The Ch283
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chapter introduced the
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architectural seam Codex framed as the right middle path between
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"fake PCPYUD as zero" (silent divergence) and "widen the whole EE
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core to 128 bits" (multi-chapter cross-cutting work): a parallel
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**128-bit GPR shadow** (`gpr128`) that LQ/SQ/SD and every MMI op now
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flow through, while the legacy 32-bit `regfile` remains the canonical
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scalar surface.
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## What landed (architectural summary)
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The EE core now has two parallel GPR storages:
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| | width | who writes it | who reads it |
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|---|---|---|---|
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| `regfile [0:31]` | 32 | every scalar op (unchanged) | scalar decode, branches, ALU operands |
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| `gpr128 [0:31]` | 128 | every scalar op (via mirror — zero-extended); MMI ops; LQ | MMI ops needing upper bits; SQ/SD per-beat sources |
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**Invariant:** `gpr128[i][31:0] === regfile[i]` always. Scalar writes
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zero-extend into `gpr128[i][127:32]`; MMI/LQ writes can land non-zero
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bits there. This is the R5900 rule that scalar ops clear the upper
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bits of their destination — Codex framed it as "define upper bits
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conservatively," and zero is the conservative answer.
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## RTL — surgical edits in `ee_core_stub.sv`
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1. **Declaration + reset** — `logic [127:0] gpr128 [0:31];` next to
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`regfile`. Reset clears all 32 to 128'd0.
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2. **Read helpers** — `rs128_val` / `rt128_val` next to `rs_val` /
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`rt_val`, both with the `$0 → 0` guard.
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3. **Scalar-write mirrors** — every existing `regfile[X] <= Y` now
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has a paired `gpr128[X] <= {96'd0, Y}`. Sites touched: SYSCALL HLE
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(3), I-type ALU writeback, R-type ALU writeback, MFHI/MFLO,
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JAL/JALR link, MFC0, Ch215 jmp_buf restore (12) + final $v0,
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LW/LB/LBU/LH/LHU load returns. Load path was refactored to compute
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`load_wb` once and write both stores.
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4. **MMI 128-bit writeback** — new `rtype_alu128_wb` combinational
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block computes the full 128-bit MMI result for PCPYLD/PSUBB/PNOR/
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PAND/PCPYUD. The R-type writeback site picks between the full
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128-bit value (when `is_mmi_wb`) and the zero-extended scalar
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value (every other R-type op). The existing 32-bit `rtype_alu_wb`
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still lands the correct low 32 into `regfile`.
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5. **LQ 4-beat FSM** — `is_lq` now takes a dedicated dispatch arm
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that initializes `sq_beat <= 0` and re-uses S_MEM_REQ/S_MEM_WAIT
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four times. Beat N's `map_rd_addr = ea + N*4`. Each beat captures
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`map_rd_data` into the matching 32-bit lane of `gpr128[rt]`. Last
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beat mirrors `gpr128[rt][31:0]` to `regfile[rt]` and retires once.
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Replaces the Ch279 single-beat LW-style approximation.
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6. **SQ/SD per-beat source upgrade** — beats now pull from
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`gpr128[rt][lane]` instead of "low 32 then zero": SQ emits all
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four lanes, SD emits the low two.
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7. **PCPYUD decode + arms** — `localparam MMI3_PCPYUD = 5'h0E`,
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`is_pcpyud` decode (MMI3 / sa 0x0E), added to `is_rtype_alu` and
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`is_nop_class` exclusion. Low-32 arm in `rtype_alu_wb` uses
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`rt128_val[95:64]` (= low 32 of $rt's upper doubleword); full
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128-bit arm in `rtype_alu128_wb` is `{rs128[127:64],
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rt128[127:64]}`.
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## Focused TB — `tb_ee_core_pcpyud.sv`
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Three cases:
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1. **Exact qbert encoding asserted** == 0x704923A9. `pcpyud $a0, $v0,
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$t1` with $v0 and $t1 set by scalar LUI+ORI (upper halves
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architecturally 0). PCPYUD's low-32 result = 0 — exactly what
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qbert sees on every byte-walker iteration.
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2. **PCPYLD-then-PCPYUD round-trip.** `pcpyld $t2, $t0, $t1` puts
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$t0[31:0] = 0xAABBCCDD into `gpr128[$t2][95:64]`. `pcpyud $t3,
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$t2, $t2` then extracts $t2's upper-D into both halves of $t3.
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Verified: `regfile[$t3] == 0xAABBCCDD` *and* peeked
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`gpr128[$t3][127:64] == 0x00000000_AABBCCDD`. Proves the gpr128
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shadow is actually carrying upper bits.
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3. **PCPYUD with rt=$0.** Exercises the rs-upper-D path alone. $t5
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low = 0, gpr128[$t5][127:64] inherits $t2's upper-D.
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Result: `retired=23 halt=1 trap=0 pc=0xbfc00150 errors=0 PASS`.
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## Makefile + regression
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- `tb_ee_core_pcpyud` target with build + run rules.
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- Added to both the PHONY target list (line 407) and the `run:`
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master list (line 2510) — per the dual-list rule.
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- Regression: 170 → **171**.
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## qbert progression
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| Chapter | Blocker | qbert retire_count |
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|---------|---------|---------------------|
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| Post-Ch281 (PNOR) | PAND at 0x00112C98 | 27,022 |
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| Post-Ch282 (PAND) | PCPYUD at 0x00112CA0 | 27,024 |
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| **Post-Ch283 (PCPYUD)** | **LD at 0x00113378** | **27,067** |
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+43 retires past Ch282. qbert finished the byte-walker MMI sequence
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(`LQ → PSUBB → PNOR → PAND → PCPYUD → reduce/branch`), returned from
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that branch, did a chunk of follow-on work, then hit `ld $ra,
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0($ra)` — the end-of-function return-address restore. LD is the
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read-side of SD and is now the Ch284 candidate.
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Side-effect check: the new full-128-bit LQ feeds real upper-half
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data into PCPYUD. The fact that qbert advanced through the PCPYUD
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site and 43 more instructions means the byte-walker's downstream
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logic accepts the actual data (not zero), and made a real branch
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decision based on it. Snapshot at halt:
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- `$a0 = 0x33323130` — ASCII `"0123"`, which strongly suggests
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qbert is mid-string processing (the byte-walker did its job).
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- `$v1 = 0x0012c2c6`, `$a1 = 0x0011c326`, `$a2/$a3 = 0x0012c2c0`.
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This is the first chapter where the qbert run produces visible
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*content-shaped* state (ASCII bytes in registers) rather than just
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opcode-blocker telemetry.
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## Pattern review (13 chapters)
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| Ch | Blocker | Edits | Pattern |
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|-----|--------------|-------|---------|
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| 271 | SQ | 5 | NEW 4-beat write |
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| 272 | DADDU | 4 | NEW ALU-low-32 |
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| 273 | SYSCALL HLE | 2 | NEW gated dispatcher |
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| 274 | BEQL | 6 | NEW branch+squash |
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| 275 | SD | 7 | REUSE SQ counter |
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| 276 | DSLL | 4 | REUSE DADDU |
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| 277 | BNEL | 6 | REUSE BEQL squash |
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| 278 | PCPYLD | 4 | NEW MMI narrow-decode |
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| 279 | LQ | 5 | REUSE LW path |
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| 280 | PSUBB | 5 | REUSE MMI narrow (byte-SIMD new) |
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| 281 | PNOR | 5 | REUSE MMI narrow + NOR arm |
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| 282 | PAND | 5 | REUSE MMI narrow + AND arm |
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| **283** | **PCPYUD + gpr128** | **architectural** | **NEW 128-bit shadow** |
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Ch283 breaks the surgical-one-opcode cadence because it has to: this
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is the first chapter that the "low-32-only" approximation could not
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keep absorbing. The MMI narrow-decode pattern from Ch278 still works
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(PCPYUD adds the same 3-way is_mmi+func+sa decode), but the
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*writeback* now needs full-128 storage, which retroactively forced
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LQ/SQ/SD/PCPYLD/PSUBB/PNOR/PAND to also flow through `gpr128`.
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That's a one-time investment. Future MMI ops that need upper bits
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(PCPYH, PINTEH, PCEQB, PMADDH, etc.) can ride the existing seam:
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read `rs128_val`/`rt128_val`, write `rtype_alu128_wb`. No more
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architectural work to add upper-half ops.
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## Files changed
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- `rtl/ee/ee_core_stub.sv` — declarations + 36 scalar-write mirrors
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+ MMI 128-bit writeback + PCPYUD decode + LQ 4-beat FSM + SQ/SD
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per-beat sources.
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- `sim/tb/integration/tb_ee_core_pcpyud.sv` — new focused TB.
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- `sim/Makefile` — target + both regression lists.
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## Regression
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**171/171 PASS** (was 170/170 in Ch282).
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