Files
retroDE_ps2/sim/tb
thejayman77 ba74bbd5aa Snapshot: fog implementation + fidelity tooling baseline (pre bilinear-clamp fix)
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder
XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog
TBs, fidelity attribution tooling. Functional baseline before removing the dead
bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail).

Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
2026-07-20 19:56:46 -04:00
..

sim/tb — Testbenches

Per-subsystem SystemVerilog / Verilog testbenches.

Planned layout (created as each subsystem lands its first stub):

  • tb/memory/ — memory map and arbitration tests.
  • tb/dmac/ — EE DMAC channel tests.
  • tb/gif_gs/ — GIF packet intake and GS register decode tests.
  • tb/sif/ — EE<->IOP mailbox/DMA tests.
  • tb/ee/ — EE core directed tests.
  • tb/iop/ — IOP core and IOP-DMA directed tests.
  • tb/vif_vu/ — VIF unpack and VU microprogram tests.

Rule: no testbench directory is created until the matching subsystem has a contract in docs/contracts/ and a stub in rtl/.