thejayman77
ba74bbd5aa
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog TBs, fidelity attribution tooling. Functional baseline before removing the dead bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
78 lines
3.6 KiB
Markdown
78 lines
3.6 KiB
Markdown
# Ch422 — registered bilinear output boundary (prefit)
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## Trigger
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Ch421 closed the 310 MHz EMIF/request family at `+0.155 ns`, but its owner GUI
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fit exposed a design-clock path from a captured bilinear tap through both lerp
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levels, the texture output mux, TEX0 vertex modulation, and finally
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`raster_pixel_color_q`. The worst of ten identical-family paths had 30 logic
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levels, 41.955 ns data delay, and `-1.993 ns` slack against the 40 ns clock.
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## Root cause
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`gs_texture_unit` already captured `tex_color_blend` into `tex_color_hold` while
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leaving `BS_DONE`. However, during that same `BS_DONE` cycle its external
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`tex_color` selected the live combinational blend and `out_valid` asserted.
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Consequently, the perspective palette-bilinear emit path could consume the
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unregistered value and append four channel-modulation multipliers before the
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`raster_pixel_color_q` register. The intended hold register was present but
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was bypassed at the only cycle that mattered for this caller.
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## Structural cut
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The bilinear FSM now has a distinct `BS_OUT` state after `BS_DONE`:
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1. `BS_DONE` evaluates the unchanged two-stage bilinear math and captures it in
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`tex_color_hold`;
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2. `BS_OUT` asserts `out_valid` and exposes only `tex_color_hold`;
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3. the FSM then returns to `BS_IDLE`.
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This adds one internal sampler cycle but changes no pixel arithmetic and no
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external handshake. Existing consumers already wait on `out_valid` or the
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`busy` level, so their natural stalls absorb the cycle. The former 30-level
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tap-to-emit path is split at `tex_color_hold`: bilinear arithmetic ends there,
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while TEX0 modulation starts from a register on the following cycle.
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## Prefit verification
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- standalone PSMCT32/PSMT8/PSMT4 bilinear suite: all 12 cases PASS;
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- tile PSMCT32 bilinear integration: PASS;
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- tile palette-bilinear integration: PASS;
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- full 283-epoch production-control replay: PASS;
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- 1,177,489 fragments fed, 984,845 passed Z, zero drops/errors;
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- final Z mismatch `0 / 307,200`, color mismatch `0 / 235,963`;
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- framebuffer SHA-256 remains exactly
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`a88f1f6c926dd0db2b72ae2873c399e7dc5666f8003190184c34d360b13a5f44`.
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## Owner fit gate
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Ready for one owner-controlled Quartus 26.1 GUI compile. Acceptance requires:
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- no `g_bilinear.tap[*] -> raster_pixel_color_q[*]` setup family;
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- bilinear tap paths terminate at `tex_color_hold` and close at 25 MHz;
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- the already-clean 310 MHz EMIF/request family remains non-negative;
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- setup, hold, recovery, removal, and minimum pulse all close;
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- RAM inference and device fit remain within the existing budget.
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Do not deploy the timing-unclean Ch421 RBF. Deploy and board-test Ch422 only if
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the complete timing report is clean.
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## Owner fit result
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The owner-controlled Quartus 26.1 GUI fit confirmed that the Ch422 structural
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cut worked. The design clock closed at `+8.604 ns`, the reference clock closed
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at `+7.564 ns`, and hold, recovery, removal, and minimum-pulse checks were
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clean. The former bilinear tap-to-`raster_pixel_color_q` family was absent.
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The only remaining failure was the 310 MHz EMIF clock at WNS `-0.012 ns`, TNS
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`-0.047 ns`, across six endpoints. Five endpoints were color-align tuple data
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register enables (`ca_wdata_q[21/24/25/28/30]|ena`) reached through
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`ca_tail -> ca_full -> feed_ok`. The sixth was
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`req_stage_packet[79]|ena`, whose enable cone included the synchronized EMIF
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calibration reset. These are independent control-to-data-enable artifacts;
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Ch423 removes both in one combined structural closeout.
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Ch422 is therefore functionally verified and its intended timing family is
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closed, but its RBF remains non-deployable because the complete fit was not
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timing-clean.
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