thejayman77
ba74bbd5aa
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog TBs, fidelity attribution tooling. Functional baseline before removing the dead bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
114 lines
5.7 KiB
Markdown
114 lines
5.7 KiB
Markdown
# Ch416 — native XYZ 12.4 coverage
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## Objective
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Carry the captured GS fractional screen coordinates through the fixture,
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primitive FIFO, and raster coverage test. This is a fidelity chapter: draw
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population, texture state, fog fold, bilinear filtering, Z behavior, and
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chronological ordering remain the Ch415 baseline.
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## RTL cut
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- `gs_stub` has an opt-in `SUBPIXEL_XY` path that retains each vertex's four
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X/Y fractional bits alongside the existing small primitive FIFO.
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- Edge equations use 12.4 endpoints and sample the pixel center at `+8` in
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that domain. The operands are bounded to signed 17-bit coordinates and
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signed 35-bit edge results.
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- The production `GS_SH3_LPDDR_FB` profile enables the path. Legacy profiles
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retain integer corner-sampled coverage.
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- Attribute gradients remain on the proven integer coordinate basis for this
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first structural cut. Moving gradient setup to 12.4 is explicitly deferred
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and is not hidden inside this coverage change.
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## Fixture and generator controls
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`--subpixel-xy` emits native XYZ2 low-half 12.4 coordinates. Capacity
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scheduling measures the same 12.4 pixel-center coverage so narrow visible
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triangles cannot be discarded after integer collapse. Runtime-CLUT fixtures
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retain the proven single staging CBP and adjacent identical assets without the
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obsolete preloaded-palette uniqueness gate.
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The full `zsrt139f17` fixture uses `--legacy-strip-kicks` to preserve the exact
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Ch415 strip population. This makes the experiment one-variable: changing the
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newer strip-population interpretation at the same time would remove broad
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scene layers and invalidate the A/B comparison.
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## Evidence so far
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- Legacy raster regression: 16/16 pixels PASS.
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- Directed subpixel raster regression: 3/3 pixel-center samples PASS.
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- Authentic three-draw integration: 5,909 fragments fed, 5,907 Z-passing,
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zero drops, 0/307,200 Z mismatches, and 0/5,858 color mismatches.
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- Full software reconstruction versus PCSX2 improves from Ch415 MAE 21.0852 /
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RMSE 32.3385 to Ch416 MAE 19.8099 / RMSE 28.8334. Lit RGB pixels rise from
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174,167 to 212,915.
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- Full 263-epoch RTL integration PASS: 1,139,213 fragments fed, 969,301
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Z-passing, zero drops, 263 markers and ordered drains, no color FIFO or AXI
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response errors, 0/307,200 final Z mismatches, and 0/235,942 final color
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mismatches.
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- The Ch416 RTL framebuffer improves against PCSX2 to MAE 20.4941 / RMSE
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30.0163 with 199,104 lit RGB pixels. This is a large improvement over the
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Ch415 board result at MAE 23.6438 / RMSE 35.0255 and 110,329 lit RGB pixels.
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- RTL versus the Ch416 software reconstruction measures MAE 10.1578 / RMSE
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19.1650. Native coverage closes a substantial part of the hardware/software
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gap, but fractional attribute-gradient setup remains visible fidelity debt.
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Artifact SHA-256 identities:
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- full epoch descriptor: `ba1484d23cc9a0caba9d4f82af7ed157fbe692c54a9138d5c0aa02f5ca9f3d87`;
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- RTL framebuffer MEM: `6aa98a68ee59b5df8457b651baf12decbbb7b71c70c4029ff2cb144a3defa1de`;
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- RTL framebuffer PNG: `709d6a1438355531b38723654f27b0b07e49524af10d33388fdbb744739cf7b3`;
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- software reference PNG: `63944f31b8c5f55b70bbddbb89db4ac0ed782a4daf8bd6dad8bb8ad8ec9ad006`.
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## First owner fit and timing repair
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The first owner-controlled Quartus 26.1 GUI fit completed, but is not eligible
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for deployment. EMIF user-clock setup was -0.433 ns WNS / -6.069 ns TNS;
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hold was 0.000 ns with zero TNS, and recovery, removal, and minimum-pulse checks
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were clean. The top-ten setup failures were one physical family from the EMIF
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`lock_sync_inst|dreg[1]` reset source into duplicated
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`u_zc_emit|u_req|...|address_reg_b[2]` registers. This was reset routing into
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the request FIFO's synchronous-read RAM implementation, not the new subpixel
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coverage datapath.
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`gs_async_fifo` no longer resets `rdata_q` in `REGISTERED_READ` mode. That
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value is invalid until an accepted read and every consumer already qualifies it
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with the read transaction, so the reset value had no functional meaning. The
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cut removes the 5,331-fanout EMIF lock/reset route from the duplicated RAM
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registers without adding a timing exception or changing FIFO latency.
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Post-repair evidence:
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- generic asynchronous FIFO scoreboard PASS: 3,284 writes and reads, zero
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duplicate/drop/order errors;
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- Z/color emitter PASS: 1,500 fragments across three epochs plus directed
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`ZTST=ALWAYS`, exact final Z/color, `col_ovf=0`, `bresp_err=0`;
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- three-epoch native-subpixel integration PASS: 5,909 fed, 5,907 passed, zero
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drops, exact 0/307,200 Z and 0/5,858 color mismatches.
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## Owner fit gate
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The repaired owner-controlled Quartus 26.1 GUI fit closed cleanly: EMIF setup
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is +0.047 ns WNS / 0.000 ns TNS, hold is 0.000 ns WNS / 0.000 ns TNS, and
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recovery, removal, and minimum-pulse checks are clean. The fit uses 37,959 /
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46,800 ALMs (81%), 5,261,744 / 7,331,840 memory bits (72%), 336 / 358 RAM
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blocks (94%), and 157 / 376 DSP blocks (42%). The deployed RBF SHA-256 is
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`965e15eabdba5260a8d3c795b39a39bebc707d31fee70e3af857ec7e03f94f82`.
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## Board acceptance
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The full 263-epoch board run passed every texture CRC, runtime-palette sum,
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staging-record count, ordered drain, and fragment-drop gate. The scheduler
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finished `rc=0`; the FPGA manager remained `operating`. The captured board
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framebuffer has 235,346 nonzero words, bounds `(0,0)..(511,479)`, sum32
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`0x19291e79`, and xor32 `0x05d6395b`.
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Most importantly, the board framebuffer is bit-for-bit identical to the full
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RTL simulation. Both MEM files have SHA-256
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`6aa98a68ee59b5df8457b651baf12decbbb7b71c70c4029ff2cb144a3defa1de`,
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and both PNG files have SHA-256
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`709d6a1438355531b38723654f27b0b07e49524af10d33388fdbb744739cf7b3`.
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Board versus the bilinearly resized PCSX2 frame measures MAE 20.4941 / RMSE
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30.0163 with 199,104 lit RGB pixels. Ch416 therefore realizes its simulated
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fidelity gain on hardware and is accepted.
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