thejayman77
a72aaded22
The fog blend's tex_color*F multiply landed on the texture->color critical path (u_texcache RAM -> u_tex|tex_color -> mult_126 -> raster_pixel_color_q, 46ns, -6.165ns setup). Fog is a proven no-op for the current board scene (96.5% F=255), so pay zero for it here. FOG_ENABLE (default 1, byte-identical fog) added to gs_stub; each fog mux gated (FOG_ENABLE && ras_fge) so FOG_ENABLE=0 constant-folds the entire fog cone away (multiply, FOGCOL adders, s2_fog_f/persp_fog_f5 interp). Threaded through top_psmct32_raster_demo_bram; set FOG_ENABLE(1'b0) on the active GS_SH3_LPDDR_FB board arm (elsif at :1086, the one the QSF profile compiles). Fog stays default-on everywhere else. Verified: FOG_ENABLE=1 fog TBs unchanged PASS; FOG_ENABLE=0 (new tb_gs_fog_disabled + board scene TB) emits raw color = pre-fog datapath; board elaborates clean. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
sim/tb — Testbenches
Per-subsystem SystemVerilog / Verilog testbenches.
Planned layout (created as each subsystem lands its first stub):
tb/memory/— memory map and arbitration tests.tb/dmac/— EE DMAC channel tests.tb/gif_gs/— GIF packet intake and GS register decode tests.tb/sif/— EE<->IOP mailbox/DMA tests.tb/ee/— EE core directed tests.tb/iop/— IOP core and IOP-DMA directed tests.tb/vif_vu/— VIF unpack and VU microprogram tests.
Rule: no testbench directory is created until the matching subsystem has a
contract in docs/contracts/ and a stub in rtl/.