thejayman77
ba74bbd5aa
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog TBs, fidelity attribution tooling. Functional baseline before removing the dead bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
56 lines
2.8 KiB
Markdown
56 lines
2.8 KiB
Markdown
# Ch406 — deep request-FIFO timing repair (pre-fit gate)
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## Trigger
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The owner Quartus 26.1 GUI compile for Ch405 fit in the device but failed the
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310 MHz EMIF clock by 0.267 ns, with design-wide TNS of -4.802 ns. All 77
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failing endpoints belong to `u_zc_emit|u_req`. The leading path is the
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registered empty flag through the 15-bit binary-pointer increment, Gray
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conversion, equality reduction, and back into the empty flag. Secondary
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violations are the same empty/pointer cone feeding the 16K FIFO RAM address,
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plus the asynchronous RAM bank mux feeding request-head decode.
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This is a local consequence of increasing the Ch405 request FIFO from 4K to
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16K. Hold timing, Gray-pointer skew constraints, and all other clock domains
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pass.
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## Structural repair
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- Treat `gs_async_fifo.rd` according to its existing interface contract: it is
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an accepted read, already qualified by `!rempty` in each wrapper. Remove the
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redundant internal `!rempty` gate from the read-pointer increment. This
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removes the empty-to-pointer feedback and the empty-to-RAM-address fanout.
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- Add an optional synchronous/registered read port to `gs_async_fifo`.
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- Enable that port only for the 16K x 92-bit Z/color request FIFO. Keep the
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smaller existing users on their original FWFT interface.
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- Add a one-cycle pending bit in `gs_lpddr_zc_emit` so its request-head stage
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captures the registered FIFO word on the following cycle and cannot issue a
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second pop while a word is in flight.
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- Make the standalone FIFO testbench explicitly qualify its randomized read
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requests, matching the documented production interface.
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No clock, SDC, FIFO depth, fixture, draw, texture, blend, or Z behavior changes.
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## Pre-fit proof
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- Async FIFO scoreboard: 3,284 writes / 3,284 reads, zero order, duplicate, or
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drop errors, final empty asserted, PASS.
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- Ch405 worst three epochs, empty Z: 43,680 fed and passed, zero drops,
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high-water 12,953/16,384, exact color, exact Z, PASS.
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- Ch405 worst three epochs, checkerboard Z: 43,680 fed, 21,839 passed, zero
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drops, high-water 11,389/16,384, exact color, exact unchanged Z at all
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307,200 pixels, PASS.
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- A sequential production sweep additionally replayed epochs 0 through 19:
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291,597 fragments, zero drops, and every scene drain completed. It was
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stopped after this redundant prefix because the complete 287-epoch run would
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consume more than an hour; the maximum-pressure tail and both Z outcomes had
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already passed exact comparisons above.
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- Production RTL elaborates with the 16K request FIFO and registered-read path.
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## Owner fit gate
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Run the next compile only in the owner-controlled Quartus 26.1 GUI. The fit
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must confirm that the request RAM remains inferred in device memory, resources
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still fit, setup and hold both pass, and the previous `rempty` feedback family
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is absent. Do not deploy an RBF unless those checks pass.
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