thejayman77
ba74bbd5aa
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog TBs, fidelity attribution tooling. Functional baseline before removing the dead bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
152 lines
6.2 KiB
Markdown
152 lines
6.2 KiB
Markdown
# Ch437 — zero-line-RAM horizontal-linear presentation prefit
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## Purpose
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Ch436 made the captured 15:14 vertical presentation linear while retaining the
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Ch418 nearest-neighbour 5:4 horizontal map. The accepted framebuffer and board
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replay are exact, so this chapter changes presentation only: it reconstructs
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the fractional horizontal samples that nearest presentation repeats.
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For output column `x`, the exact source coordinate is:
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- `x0 = floor(x*4/5)`;
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- `xf = (x*4) mod 5`;
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- `x1 = min(x0+1, 511)`.
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The existing five-state mapper already produces both `x0` and `xf`; no divider
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or new wide coordinate cone is introduced.
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## Architecture
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The rejected Ch436 horizontal prototype mirrored both complete line buffers to
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obtain an `x+1` read port. Quartus implemented the mirrors as 30,720 registers
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and rejected the design at 6,270 required LABs. Ch437 does not restore those
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arrays.
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Instead, each physical line buffer retains one video read address. Two
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256-bit register slots hold the current and next beat for each of the two
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resident source rows. Horizontal blanking alternately primes beats 0 and 1.
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When active scanout enters beat K, the retired parity slot is refilled with
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beat K+1. The 5:4 cadence provides ten output clocks for each eight-source-pixel
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beat, so the next beat is resident well before the single lane-7 boundary
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sample needs it.
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The interpolation order is separable and matches the software oracle:
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1. blend row L and L+1 at x0 with denominator 15;
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2. blend row L and L+1 at x1 with denominator 15;
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3. blend those two results with denominator 5.
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The source-right edge clamps at pixel 511. Other profiles retain their existing
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nearest/1:1 path through default-off parameters.
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## Evidence before owner fit
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Directed and legacy regressions:
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- `tb_gs_lpddr_scanout_lb_hstretch`: 2,400 checked, zero errors, zero underflow,
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across eight 256-bit beats and the clamped right edge;
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- `tb_gs_lpddr_scanout_lb_psm32`: 49,152 checked, zero errors/underflow;
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- `tb_gs_lpddr_scanout_lb_psm32_256`: 196,608 checked, zero errors/underflow;
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- `tb_gs_lpddr_scanout_fb`: 105,968 checked, zero errors/underflow;
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- Verilator lint: no errors;
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- relevant `git diff --check`: pass.
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The exact software presentation model improves the accepted f52 framebuffer's
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PCSX2 comparison again:
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- Ch436 vertical-linear: MAE/RMSE `14.2678 / 21.3085`;
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- Ch437 separable-linear: MAE/RMSE `13.9525 / 20.6568`.
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This is a visible smoothing of the horizontal staircase/noise without changing
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framebuffer bytes, render ordering, LPDDR traffic, or draw count.
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## Owner GUI compile acceptance
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### Rejected first fit
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The first owner fit rejected the initial cache implementation at placement:
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6,337 LABs were required on the 4,680-LAB device. The synthesis/netlist report,
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not the summary alone, showed the exact cause:
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- `u_lpddr_scan_lb` contained 32,312 registers;
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- the SDC line-buffer reset collection found 30,720 destinations;
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- `lb0[0..79]` and `lb1[0..79]` appeared as individual flip-flop nodes;
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- no line-buffer M20K payload remained in the scanout hierarchy.
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The conditional reads used to prime/refill the cache prevented Quartus from
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recognizing the dual-clock RAM template. This was the same physical failure
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mode as the rejected Ch436 mirrors, despite the source-level arrays not being
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duplicated.
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### Corrected inference-safe candidate
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Each physical array now has exactly one unconditional video-clock read:
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```systemverilog
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lb0_video_rd_q <= lb0[video_rd_addr_q];
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lb1_video_rd_q <= lb1[video_rd_addr_q];
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```
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Address, valid, and beat tag are registered beside those outputs. A separate
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control process fills the two-beat register cache only from the registered
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RAM outputs. It never indexes `lb0` or `lb1` directly. This is the canonical
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simple-dual-port, dual-clock inference form already proven by the accepted
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line-buffer implementation.
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The corrected candidate retains identical horizontal results: the expanded
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2,400-pixel test, all PSMCT32 legacy regressions, Verilator lint, and relevant
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`git diff --check` pass again.
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The corrected RTL was accepted by an owner-controlled Quartus 26.1 GUI compile.
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The generated core is:
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- `retroDE_ps2.core.rbf`, 4,132,864 bytes;
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- SHA-256
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`3dd624cd34e56cf553fc92c47c3a0d47dc6a9c0513f37cbf72f2c4f6f9c71559`.
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All report gates pass:
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- fitter successful at 39,077 / 46,800 ALMs (83%), 56,526 registers,
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5,327,792 block-memory bits, 344 / 358 RAM blocks, and 163 / 376 DSPs;
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- both line buffers are inferred as simple-dual-port, dual-clock
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`altera_syncram` instances, five M20Ks and 15,360 bits apiece;
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- the scanout hierarchy contains 1,602 registers rather than the rejected
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implementation's 32,312;
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- EMIF setup slack is +0.069 ns with zero TNS;
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- the 25 MHz design-clock setup slack is +5.473 ns with zero TNS;
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- all hold classes have zero TNS and minimum slack 0.000 ns;
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- minimum recovery, removal, and pulse-width slack are respectively
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+1.056 ns, +0.164 ns, and +0.200 ns.
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## Hardware acceptance
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The accepted core was installed on the DE25-Nano and loaded successfully.
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The live fabric reported the expected core ID/ABI, healthy status, active HDMI
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scanout, an advancing frame counter, and zero raster overflow.
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The complete f52 scheduler replay then passed on hardware:
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- all 311 epochs completed;
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- all fresh texture CRCs matched and resident reuse checks passed;
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- every epoch reported zero fragment drops;
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- `DONE rc=0 (all gates passed)`;
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- the dump contained 307,200 words, `sum32=0xaad0b94d`,
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`xor32=0x33138181`, 245,155 nonzero pixels, and bounds `(0,0)..(511,479)`.
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The retrieved Ch437 board framebuffer has SHA-256
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`d0047677371a0f6e4e319458926f604a8599c92baaf34d09b8e1fd452e31662b`
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and is byte-identical to the accepted Ch436 framebuffer. This is the intended
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result: Ch437 changes only the HDMI presentation filter, after framebuffer
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storage, while preserving the proven renderer and replay output.
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Ch437 is accepted. Its closure criteria were:
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- fitter completes within the device's 4,680-LAB capacity;
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- line buffers remain inferred M20Ks and total RAM stays at 344 / 358 blocks;
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- all setup, hold, recovery, removal, and pulse-width classes are nonnegative;
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- the narrow EMIF request-address family remains clean;
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- the 25 MHz presentation domain remains clean.
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All five criteria passed before deployment.
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