thejayman77
ba74bbd5aa
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog TBs, fidelity attribution tooling. Functional baseline before removing the dead bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
439 lines
27 KiB
Systemverilog
439 lines
27 KiB
Systemverilog
// retroDE_ps2 — gs_lpddr_axi_master (Ch318)
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//
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// HARDWARE-facing wrapper that takes the PSMCT16 tile-FLUSH pixel stream (GS clock)
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// and writes it to real LPDDR over the qsys f2sdram AXI4 port (f2sdram clock). It
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// does NOT modify the proven gs_lpddr_fb_writer (the Ch317 sim model) — it is a
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// sibling hardware path with the same input stream.
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//
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// Pipeline (per the Ch318 directive):
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// GS clock : PACKER — accumulate 16 PSMCT16 pixels of a tile-row into one 256-bit
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// (32-byte) beat {addr, data, strb}. A tile-row is exactly 16 px on a
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// 32-byte-aligned line, so a beat completes naturally on its 16th px
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// (no dangling partial beat). On completion, push to the async FIFO.
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// async FIFO: gray-code CDC, carries {addr[31:0], data[255:0], strb[31:0]} (320b).
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// f2sdram : AXI burst FSM — pop a beat and issue a single-beat INCR write
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// (AWSIZE=5 = 32 B, AWLEN=0, AWBURST=INCR, full per-byte WSTRB, never
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// crossing a 4 KiB boundary since each beat is one 32-byte line). AW
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// then W then B, all with backpressure (await ready/valid).
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//
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// Address: awaddr = FB_BASE + packet_addr (packet_addr is the FB-relative byte addr
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// from raster_pixel_fb_addr_q). FB_BASE must point at a LINUX-SAFE reserved LPDDR
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// region before any board run — the qsys aperture proves fabric CAN address SDRAM,
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// not which physical range is safe to scribble on (Ch318 board gate).
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//
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// Counters (f2sdram domain, TB/status readable): beats, bursts, bresp_err, fifo
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// overflow, done-ish (idle && fifo empty). enable=0 → fully inert.
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module gs_lpddr_axi_master #(
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parameter int FIFO_DEPTH = 16,
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// Ch353 — pixel width in BYTES: 2 = PSMCT16 (default, byte-identical to Ch318), 4 = PSMCT32.
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// A 32-byte (256-bit) beat holds 32/PIX_BYTES lanes (16 for PSMCT16, 8 for PSMCT32). The
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// &ns beat-complete test is unchanged (a full beat is always 32 strobe bits either way).
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parameter int PIX_BYTES = 2,
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// Ch357 (Codex) — ELASTIC_BACKPRESSURE: when 1, insert a one-entry elastic (skid) stage between the packer and the
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// async FIFO and expose real producer backpressure via px_ready (= the stage can accept a beat this cycle). The packer
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// then advances ONLY on px_emit && px_ready, and the partial/EOF flushes retry until the stage accepts — so a beat is
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// NEVER dropped even if the FIFO momentarily fills, WITHOUT relying on the "packer never outruns the drain" invariant.
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// Default 0 = the legacy direct-write packer, byte-identical (px_ready tied 1). Only u_zc_emit|u_c sets this to 1.
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parameter bit ELASTIC_BACKPRESSURE = 1'b0
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) (
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// GS clock domain — flush pixel stream
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input logic gs_clk,
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input logic gs_rst_n,
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input logic enable,
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// ---- RUNTIME controls (driven by the HPS bridge register, axi_clk domain) ----
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// arm: HARD SAFETY GATE — no AXI write can issue unless high. Defaults LOW at the
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// bridge register, so the booted core is inert until the HPS explicitly arms it.
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// Synced into gs_clk for the packer; used directly in the axi_clk FSM.
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input logic arm,
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// canary: when high, write ONLY the offset-0 beat (the 32-byte top-of-frame line)
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// and discard all others — a deterministic, blast-radius-limited first test.
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input logic canary,
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// fb_base: LPDDR byte base address for the framebuffer (e.g. 0x8000_0000). awaddr
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// = fb_base + frame-relative offset. Runtime so a wrong base is re-targetable
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// without a rebuild.
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input logic [31:0] fb_base,
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// Ch352 CDC (Codex) — {arm,canary,fb_base} arrive RAW from the HPS bridge (CLOCK2_50), NOT axi_clk as the
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// legacy comment above implies. ctrl_commit is a TOGGLE the bridge flips on any control write; we sync it
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// into axi_clk and latch the controls on its edge, so the multi-bit fb_base crosses COHERENTLY (the CDC
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// lives here, at the receiving boundary, so no caller can supply raw controls into the AW path).
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input logic ctrl_commit,
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input logic px_emit,
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input logic [31:0] px_addr, // FB-relative byte address (raster_pixel_fb_addr_q)
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input logic [31:0] px_pix32, // pixel data; PSMCT16 callers drive {16'd0, pix16} (low PIX_BITS used)
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// Ch357 (Codex) — producer backpressure. ELASTIC_BACKPRESSURE=1: high when the packer can accept px_emit this cycle
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// (the elastic stage can take a beat); the producer must HOLD px_emit/px_addr/px_pix32 until px_ready. Tied 1 for the
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// legacy packer (no backpressure), so legacy producers that leave it unconnected are unaffected.
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output logic px_ready,
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// Ch353 — end-of-scene partial-beat flush (pulse). Sparse triangle coverage may leave the final
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// beat incomplete; pulse `flush` after the last px_emit to push the dangling partial beat. The
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// PSMCT16 tile path always completes beats on tile-row boundaries, so it ties this to 0.
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input logic flush,
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// f2sdram (LPDDR AXI) clock domain
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input logic axi_clk,
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input logic axi_rst_n,
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// AXI4 write-address
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output logic [31:0] awaddr,
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output logic [7:0] awlen,
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output logic [2:0] awsize,
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output logic [1:0] awburst,
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output logic [4:0] awid,
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output logic awvalid,
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input logic awready,
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// AXI4 write-data
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output logic [255:0] wdata,
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output logic [31:0] wstrb,
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output logic wlast,
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output logic wvalid,
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input logic wready,
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// AXI4 write-response
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input logic bvalid,
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output logic bready,
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input logic [1:0] bresp,
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// status / counters (axi domain)
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output logic [31:0] beats_written,
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output logic [31:0] bursts_issued,
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output logic [31:0] bresp_err_count,
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output logic [31:0] fifo_overflow_count,
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output logic idle,
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// Ch353 (Codex) — ORDERED drain ack: high after the EOF marker pops (i.e. after the last data beat's BRESP).
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// Coherent in the axi_clk domain — the scanout gate uses THIS, not a GS-domain sample of fbw_idle.
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output logic frame_drained
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);
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localparam int PW = 321; // {marker, addr[31:0], data[255:0], strb[31:0]}
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localparam int MARK = PW-1; // Ch353 (Codex) — ordered EOF marker bit. A flush pushes any partial beat then an
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// EOF marker; the AXI FSM sets frame_drained when it POPS the marker — which, by the
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// in-order FIFO + per-beat B handshake, happens only AFTER the last data beat's BRESP.
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// This is a coherent same-(axi)-domain drain ack for the scanout gate (no GS-domain
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// sampling of fbw_idle, no pointer-in-flight race).
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// Ch353 — pixel-width derived params. At PIX_BYTES=2 these reproduce the exact Ch318 PSMCT16 logic.
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localparam int PIX_BITS = PIX_BYTES * 8; // 16 or 32
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localparam int LANE_LO = (PIX_BYTES == 4) ? 2 : 1; // low addr bits inside one pixel ($clog2 PIX_BYTES)
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localparam logic [PIX_BYTES-1:0] STRB1 = '1; // per-pixel byte-strobe mask (2'b11 or 4'b1111)
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localparam logic [255:0] PIX_MASK = {{(256-PIX_BITS){1'b0}}, {PIX_BITS{1'b1}}};
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// ============================ GS-clock PACKER ============================
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logic [31:0] cur_addr;
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logic [255:0] cur_data;
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logic [31:0] cur_strb;
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logic has_data;
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logic flush_pending; // Ch353 — latched end-of-scene flush request (pushes partial then EOF marker)
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logic fifo_wr;
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logic [PW-1:0] fifo_wdata;
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logic fifo_wfull;
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// Ch352 — axi_clk control snapshot: sync the bridge commit toggle and latch {arm,canary,fb_base} on its
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// edge. Init to the bridge's SAFE defaults (arm=0, canary=1, fb_base=0x8000_0000) so the booted core is
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// inert until the HPS arms it, even before the first commit. All axi_clk uses + the gs_clk arm-sync read
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// these coherent latched copies instead of the raw bridge buses.
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logic [2:0] commit_sync;
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logic arm_axi, canary_axi;
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logic [31:0] fb_base_axi;
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always_ff @(posedge axi_clk or negedge axi_rst_n) begin
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if (!axi_rst_n) begin
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commit_sync <= 3'd0; arm_axi <= 1'b0; canary_axi <= 1'b1; fb_base_axi <= 32'h8000_0000;
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end else begin
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commit_sync <= {commit_sync[1:0], ctrl_commit};
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if (commit_sync[2] != commit_sync[1]) begin // commit edge: bridge buses are stable, latch them
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arm_axi <= arm;
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canary_axi <= canary;
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fb_base_axi <= fb_base;
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end
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end
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end
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// arm crosses from axi_clk into gs_clk — 2-FF synchronizer (from the COHERENT latched arm).
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logic arm_s1, arm_gs;
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always_ff @(posedge gs_clk or negedge gs_rst_n) begin
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if (!gs_rst_n) begin arm_s1 <= 1'b0; arm_gs <= 1'b0; end
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else begin arm_s1 <= arm_axi; arm_gs <= arm_s1; end
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end
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// Ch357 (Codex) — effective FIFO write bus (muxed by the generate below) + one-entry elastic stage (elastic mode only).
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logic fifo_wr_ram; // drive to u_fifo.wr (already ANDed with !fifo_wfull in both modes)
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logic [PW-1:0] fifo_wdata_ram; // drive to u_fifo.wdata
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logic stage_valid; // elastic: a beat waits in the skid stage
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logic [PW-1:0] stage_data; // elastic: the staged beat
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wire stage_ready = !stage_valid || !fifo_wfull; // elastic: stage can accept a beat THIS cycle
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wire stage_drain = stage_valid && !fifo_wfull; // elastic: staged beat enters FIFO THIS cycle
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generate
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if (!ELASTIC_BACKPRESSURE) begin : g_legacy
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// ------- LEGACY packer (byte-identical to the pre-Ch357 direct-write path) -------
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assign px_ready = 1'b1; // no backpressure exposed
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assign fifo_wr_ram = fifo_wr && !fifo_wfull;
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assign fifo_wdata_ram = fifo_wdata;
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always_ff @(posedge gs_clk or negedge gs_rst_n) begin
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if (!gs_rst_n) begin
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cur_addr <= '0; cur_data <= '0; cur_strb <= '0; has_data <= 1'b0;
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fifo_wr <= 1'b0; fifo_wdata <= '0; fifo_overflow_count <= '0; flush_pending <= 1'b0;
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end else begin
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fifo_wr <= 1'b0;
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if (flush) flush_pending <= 1'b1; // Ch353 — latch the end-of-scene flush request
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if (enable && arm_gs && px_emit) begin // gate: no accumulation until armed
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logic [31:0] abeat;
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logic [4:0] lane; // 0..LANES-1 (which PIX_BYTES-wide lane in the 32-byte beat)
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logic [255:0] nd;
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logic [31:0] ns;
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abeat = {px_addr[31:5], 5'd0};
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lane = px_addr[4:0] >> LANE_LO;
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if (has_data && (abeat != cur_addr)) begin
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// line changed before the previous beat filled — flush it (marker=0), restart
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fifo_wdata <= {1'b0, cur_addr, cur_data, cur_strb};
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fifo_wr <= 1'b1;
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cur_addr <= abeat;
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cur_data <= (256'(px_pix32[PIX_BITS-1:0]) << ({27'd0, lane} * PIX_BITS));
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cur_strb <= (32'(STRB1) << ({27'd0, lane} * PIX_BYTES));
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has_data <= 1'b1;
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end else begin
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nd = has_data ? cur_data : 256'd0;
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ns = has_data ? cur_strb : 32'd0;
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nd[ ({27'd0, lane} * PIX_BITS) +: PIX_BITS ] = px_pix32[PIX_BITS-1:0];
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ns[ ({27'd0, lane} * PIX_BYTES) +: PIX_BYTES ] = STRB1;
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if (&ns) begin
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// beat complete (all lanes strobed) — flush (marker=0), beat consumed
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fifo_wdata <= {1'b0, abeat, nd, ns};
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fifo_wr <= 1'b1;
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has_data <= 1'b0;
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end else begin
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cur_addr <= abeat;
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cur_data <= nd;
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cur_strb <= ns;
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has_data <= 1'b1;
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end
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end
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end else if (enable && arm_gs && flush_pending && has_data && !fifo_wr && !fifo_wfull) begin
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// Ch353 — end-of-scene partial-beat flush: push the dangling beat (marker=0) so no pixels are
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// stranded. Codex — gate on `!fifo_wr && !fifo_wfull`: a PRIOR registered push may still be entering
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// the FIFO this cycle (fifo_wfull is REGISTERED, lags a cycle), so wait until no push is in flight
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// AND not full, then the !wfull check is accurate. Covers a scene ending on a full beat, a partial
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// right after a line-change, and (since the marker also waits for fifo_wr to clear) partial->marker.
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// If gated, state is RETAINED and retried — the partial is never dropped.
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fifo_wdata <= {1'b0, cur_addr, cur_data, cur_strb};
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fifo_wr <= 1'b1;
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has_data <= 1'b0;
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end else if (enable && arm_gs && flush_pending && !has_data && !fifo_wr && !fifo_wfull) begin
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// Ch353 (Codex) — partial (if any) is pushed; now push the ordered EOF MARKER (payload irrelevant),
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// same `!fifo_wr && !fifo_wfull` gate. flush_pending retained until accepted. The AXI FSM sets
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// frame_drained when it pops this, i.e. after the last data beat's BRESP.
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fifo_wdata <= {1'b1, cur_addr, cur_data, cur_strb};
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fifo_wr <= 1'b1;
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flush_pending <= 1'b0;
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end
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// overflow witness: a push attempt while the FIFO is full (must stay 0)
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if (fifo_wr && fifo_wfull)
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fifo_overflow_count <= fifo_overflow_count + 32'd1;
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end
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end
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end else begin : g_elastic
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// ------- ELASTIC packer (Codex): full producer backpressure via a one-entry skid stage -------
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// px_ready: the input stage can accept a pixel THIS cycle. The packer advances (accumulates, produces a
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// beat, retries a flush) ONLY when stage_ready, so every produced beat lands in the stage the SAME cycle
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// it is produced -> never dropped. The stage drains into the FIFO whenever !fifo_wfull; simultaneous
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// drain+refill keeps the stage full with the new beat (the drain writes the OLD stage_data to the FIFO
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// first, via fifo_wr_ram below).
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//
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// Ch358 (Codex) — REGISTERED INPUT STAGE: capture {derived beat address, lane, pixel} into in_* registers
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// BEFORE the packer. The high-address equality (beat-change) compare and the lane shifts then run off
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// LOCAL in_* registers instead of gating stage_data[255:0] straight from the producer's cross-module
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// px_addr register — the Ch358 fit's failing setup cone (col_out_addr -> stage_data, WNS -0.176). +1 cycle
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// pixel latency; ordering preserved: flush_pending is serviced only when in_valid is EMPTY, so the
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// partial/EOF marker can never overtake a captured pixel.
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logic in_valid;
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logic [31:0] in_beat; // {px_addr[31:5], 5'd0} — derived beat address (low 5 bits constant 0)
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logic [4:0] in_lane; // px_addr[4:0] >> LANE_LO
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logic [PIX_BITS-1:0] in_pix;
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// Ch358 (Codex) — PRE-REGISTERED beat-change decision (the 26.1 fit's residual -0.012 family was
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// in_beat -> the compare -> stage_data[255:0]): in_same_q = (this pixel's beat == the PREVIOUSLY captured
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// pixel's beat, last_beat_q), registered at capture. Exact by invariant: the packer reads the compare ONLY
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// when has_data=1 at consumption, and has_data=1 implies the preceding captured pixel MERGED into cur_addr
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// (beat-complete and flush both clear has_data and never read it) -> cur_addr == last_beat_q at capture.
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// A pending flush cannot intervene while in_valid holds a pixel. No latency change.
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logic in_same_q;
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logic [31:0] last_beat_q;
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// Ch367 — map the lane-selected pixel into full beat masks in a distinct registered stage. The beat
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// accumulator below then sees only registered masks, not in_lane driving cur_data[255:0] directly.
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logic map_valid, map_same_q;
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logic [31:0] map_beat;
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logic [255:0] map_data;
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logic [255:0] map_mask;
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logic [31:0] map_strb;
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wire map_ready = !map_valid || stage_ready;
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wire in_advance = in_valid && map_ready; // input stage advances into the map stage
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assign px_ready = !in_valid || map_ready;
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assign fifo_wr_ram = stage_drain; // drains the CURRENT stage_data (already implies !fifo_wfull)
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assign fifo_wdata_ram = stage_data;
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always_ff @(posedge gs_clk or negedge gs_rst_n) begin
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if (!gs_rst_n) begin
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cur_addr <= '0; cur_data <= '0; cur_strb <= '0; has_data <= 1'b0;
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stage_valid <= 1'b0; stage_data <= '0; fifo_overflow_count <= '0; flush_pending <= 1'b0;
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in_valid <= 1'b0; in_beat <= '0; in_lane <= '0; in_pix <= '0;
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in_same_q <= 1'b0; last_beat_q <= '0;
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map_valid <= 1'b0; map_same_q <= 1'b0; map_beat <= '0; map_data <= '0; map_mask <= '0; map_strb <= '0;
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end else begin
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logic stage_load; // a beat is being loaded into the stage this cycle
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stage_load = 1'b0;
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// (0) INPUT STAGE: consume first; a same-cycle capture below overrides (set wins) — classic
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// pipeline advance. Capture is gated on px_ready so an occupied, non-advancing stage is never
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// overwritten (the producer must HOLD px_emit/px_addr/px_pix32 until px_ready, as before).
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if (in_advance) in_valid <= 1'b0;
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if (enable && arm_gs && px_emit && px_ready) begin
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in_valid <= 1'b1;
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in_beat <= {px_addr[31:5], 5'd0};
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in_lane <= px_addr[4:0] >> LANE_LO;
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in_pix <= px_pix32[PIX_BITS-1:0];
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in_same_q <= ({px_addr[31:5], 5'd0} == last_beat_q); // vs the PREVIOUS captured pixel's beat
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last_beat_q <= {px_addr[31:5], 5'd0};
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end
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// (1) MAP: a drain and refill can coincide; the refill wins and preserves throughput.
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if (in_advance) begin
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map_valid <= 1'b1;
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map_same_q <= in_same_q;
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map_beat <= in_beat;
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map_data <= (256'(in_pix) << ({27'd0, in_lane} * PIX_BITS));
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map_mask <= (PIX_MASK << ({27'd0, in_lane} * PIX_BITS));
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map_strb <= (32'(STRB1) << ({27'd0, in_lane} * PIX_BYTES));
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end else if (stage_ready && map_valid) begin
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map_valid <= 1'b0;
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end
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// (2) DRAIN: the staged beat enters the FIFO if there is room (may be re-loaded below same cycle).
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if (stage_drain) stage_valid <= 1'b0;
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// (3) latch the flush request UNCONDITIONALLY so it is never lost while backpressured.
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if (flush) flush_pending <= 1'b1;
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// (4) PACKER: only when the stage can accept a beat this cycle; consumes the mapped input.
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if (stage_ready) begin
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if (map_valid) begin
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logic [255:0] nd; logic [31:0] ns;
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if (has_data && !map_same_q) begin
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stage_data <= {1'b0, cur_addr, cur_data, cur_strb}; stage_valid <= 1'b1; stage_load = 1'b1;
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cur_addr <= map_beat;
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cur_data <= map_data;
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cur_strb <= map_strb;
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has_data <= 1'b1;
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end else begin
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nd = has_data ? cur_data : 256'd0;
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ns = has_data ? cur_strb : 32'd0;
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// Preserve the legacy packer's last-writer-wins behavior when two accepted
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// fragments target one pixel in the same beat. map_data is sparse, so OR
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// would corrupt a later color whose bit pattern overlaps the earlier one.
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nd = (nd & ~map_mask) | map_data;
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ns = ns | map_strb;
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if (&ns) begin
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stage_data <= {1'b0, map_beat, nd, ns}; stage_valid <= 1'b1; stage_load = 1'b1;
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has_data <= 1'b0;
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end else begin
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cur_addr <= map_beat; cur_data <= nd; cur_strb <= ns; has_data <= 1'b1;
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|
end
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|
end
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|
end else if (!in_valid && enable && arm_gs && flush_pending && has_data) begin
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|
// partial-beat flush — retries here every cycle until stage_ready (guaranteed inside this if)
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|
stage_data <= {1'b0, cur_addr, cur_data, cur_strb}; stage_valid <= 1'b1; stage_load = 1'b1;
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has_data <= 1'b0;
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|
end else if (!in_valid && enable && arm_gs && flush_pending && !has_data) begin
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// ordered EOF marker — retries until accepted (in_valid empty => no pixel can be overtaken)
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stage_data <= {1'b1, cur_addr, cur_data, cur_strb}; stage_valid <= 1'b1; stage_load = 1'b1;
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flush_pending <= 1'b0;
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|
end
|
|
end
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// overflow witness (accepted-write accounting): a stage load while the stage is occupied AND not
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// draining would DROP the previous beat. Gating on stage_ready makes this impossible; the witness
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|
// fires only if that invariant is ever violated. Must stay 0 (asserted by the saturation TB).
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if (stage_load && stage_valid && !stage_drain)
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fifo_overflow_count <= fifo_overflow_count + 32'd1;
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end
|
|
end
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|
end
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endgenerate
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|
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// ============================ async FIFO (CDC) ============================
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logic [PW-1:0] fifo_rdata;
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|
logic fifo_rempty;
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|
logic fifo_rd;
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// Ch323 — reset BOTH FIFO pointers from the STABLE axi_rst_n (assert async, deassert
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|
// synced into gs_clk). gs_rst_n (= core reset) toggles on every CORE_CTRL re-render; if
|
|
// the write pointer reset followed it while the read pointer stayed, the gray pointers
|
|
// would desync → FIFO corruption (phantom beats, no commit). Same fix as gs_z_flush_writer.
|
|
reg [1:0] wrst_sync;
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always_ff @(posedge gs_clk or negedge axi_rst_n) begin
|
|
if (!axi_rst_n) wrst_sync <= 2'b00;
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|
else wrst_sync <= {wrst_sync[0], 1'b1};
|
|
end
|
|
wire fifo_wrst_n = wrst_sync[1];
|
|
gs_async_fifo #(.WIDTH(PW), .DEPTH(FIFO_DEPTH)) u_fifo (
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|
.wclk(gs_clk), .wrst_n(fifo_wrst_n), .wr(fifo_wr_ram), .wdata(fifo_wdata_ram), .wfull(fifo_wfull),
|
|
.rclk(axi_clk), .rrst_n(axi_rst_n), .rd(fifo_rd), .rdata(fifo_rdata), .rempty(fifo_rempty)
|
|
);
|
|
|
|
// ============================ f2sdram-clock AXI FSM ============================
|
|
localparam logic [1:0] S_IDLE=2'd0, S_AW=2'd1, S_W=2'd2, S_B=2'd3;
|
|
logic [1:0] state;
|
|
logic [31:0] beat_addr;
|
|
logic [255:0] beat_data;
|
|
logic [31:0] beat_strb;
|
|
logic [31:0] awaddr_q; // Ch352 — full AW address latched at admission, held stable AW->W->B
|
|
|
|
assign awsize = 3'd5; // 32 bytes/beat (256-bit)
|
|
assign awburst = 2'b01; // INCR
|
|
assign awid = 5'd0;
|
|
assign awlen = 8'd0; // single beat per line (tile-rows aren't contiguous)
|
|
assign awaddr = awaddr_q; // Ch352 — latched at admission; STABLE through AW->W->B (AXI requires it)
|
|
assign wdata = beat_data;
|
|
assign wstrb = beat_strb;
|
|
assign wlast = 1'b1; // 1-beat burst
|
|
// Ch352 — AXI transaction stability (Codex): arm_axi/commit gate ADMISSION ONLY (S_IDLE pop). Once a beat is
|
|
// admitted, awvalid/wvalid are driven by STATE alone and run to completion, so a later arm-deassert or a
|
|
// fb_base commit can never drop VALID mid-handshake or move awaddr while AWVALID && !AWREADY.
|
|
assign awvalid = (state == S_AW);
|
|
assign wvalid = (state == S_W);
|
|
assign bready = (state == S_B);
|
|
// A commit and a FIFO admission may coincide safely: S_IDLE latches the full address and canary decision
|
|
// from the OLD snapshot at that edge, then AW/W/B runs solely from those registered values. The next
|
|
// admission sees the NEW snapshot. Do not gate this with the raw commit synchronizer: that turns the
|
|
// control edge into a read-pointer/rempty timing cone inside the async FIFO.
|
|
assign fifo_rd = (state == S_IDLE) && !fifo_rempty && arm_axi;
|
|
assign idle = (state == S_IDLE) && fifo_rempty;
|
|
|
|
always_ff @(posedge axi_clk or negedge axi_rst_n) begin
|
|
if (!axi_rst_n) begin
|
|
state <= S_IDLE; beat_addr <= '0; beat_data <= '0; beat_strb <= '0; awaddr_q <= '0;
|
|
beats_written <= '0; bursts_issued <= '0; bresp_err_count <= '0; frame_drained <= 1'b0;
|
|
end else begin
|
|
unique case (state)
|
|
S_IDLE: if (!fifo_rempty && arm_axi) begin
|
|
if (fifo_rdata[MARK]) begin
|
|
// Ch353 — ordered EOF marker popped: every prior data beat's BRESP has completed (in-order
|
|
// FIFO + per-beat B). Assert the drain ack; consume the marker (fifo_rd pops it, no AXI).
|
|
frame_drained <= 1'b1;
|
|
state <= S_IDLE;
|
|
end else begin
|
|
frame_drained <= 1'b0; // new frame data in flight — drop the ack
|
|
beat_addr <= fifo_rdata[319:288]; // {marker, addr, data, strb}
|
|
beat_data <= fifo_rdata[287:32];
|
|
beat_strb <= fifo_rdata[31:0];
|
|
awaddr_q <= fb_base_axi + fifo_rdata[319:288]; // latch FULL AW addr from the STABLE base
|
|
// canary: write ONLY the offset-0 (top-of-frame) 32-byte line; discard every other beat.
|
|
if (canary_axi && (fifo_rdata[319:288] != 32'd0))
|
|
state <= S_IDLE;
|
|
else
|
|
state <= S_AW;
|
|
end
|
|
end
|
|
S_AW: if (awready) begin
|
|
bursts_issued <= bursts_issued + 32'd1;
|
|
state <= S_W;
|
|
end
|
|
S_W: if (wready) begin
|
|
beats_written <= beats_written + 32'd1;
|
|
state <= S_B;
|
|
end
|
|
default: if (bvalid) begin // S_B
|
|
if (bresp != 2'b00) bresp_err_count <= bresp_err_count + 32'd1;
|
|
state <= S_IDLE;
|
|
end
|
|
endcase
|
|
end
|
|
end
|
|
endmodule : gs_lpddr_axi_master
|