thejayman77
dd7ca4fb8e
Cuts the lone remaining EMIF setup fail (-0.016 ns, -0.259 skew): the combinational EMIF gen_p2c_ff -> wr_arb s2_wready -> gs_lpddr_z_rmw next-state (st, endpoint labelled S_FILL_R via the shared encoded state register). New gs_axi_w_regbuf: fully-registered one-entry W buffer (Option B per Codex). - u_wready = !full ONLY (registered occupancy) -> EMIF WREADY never reaches the Z FSM combinationally. NOT a fall-through skid (no !full-OR-d_wready term). - Buffers WDATA/WSTRB/WLAST; downstream held stable until accepted; exactly-once. - AW/B untouched; arbiter bready_q unchanged (still arms on real EMIF W handshake). - z_rmw may enter B-wait once the beat is buffered -- safe: EMIF cannot return B until the buffered beat reaches it. Single-beat writes -> the 1-beat/2-cycle buffer rate is far above the Z write rate (no new FIFO pressure). Wired in zc_emit between u_z W output (zi_*) and the z_w* ports. New file in sim Makefile RTL_SRCS + synth QSF (both). Focused tb_gs_axi_w_regbuf: exactly-once/order/ payload scoreboard + no-combinational-bypass check (u_wready===!full incl. full && d_wready) + downstream-stable check; standalone target + in make run. Texture-cache +0.016 paths NOT touched. No simulations or Quartus run. Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
79 lines
3.5 KiB
Systemverilog
79 lines
3.5 KiB
Systemverilog
// retroDE_ps2 — gs_axi_w_regbuf (Ch441)
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//
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// Fully-registered ONE-ENTRY AXI W-channel buffer. Inserted between the Z RMW
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// master's (gs_lpddr_z_rmw) W OUTPUT and the write arbiter's s2 W INPUT to cut
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// the combinational path EMIF gen_p2c_ff -> fbr wready -> wr_arb s2_wready ->
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// gs_lpddr_z_rmw next-state (`st`) — the -0.016 ns / -0.259 ns-skew setup family.
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//
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// CONTRACT (per Codex review, must hold exactly):
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// - FULLY REGISTERED, not a fall-through skid: u_wready depends ONLY on the
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// registered occupancy `full`, never on d_wready. Downstream (EMIF) WREADY
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// therefore can never propagate combinationally back into the upstream FSM.
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// (i.e. NOT `u_wready = !full || d_wready`.)
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// - Buffers the complete {WDATA, WSTRB, WLAST} payload and holds it stable on
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// the downstream side until the arbiter accepts it.
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// - Exactly-once: a beat accepted upstream is delivered downstream exactly once.
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// One beat in flight (the Z RMW issues single-beat writes, AWLEN=0/WLAST=1).
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// - AW and B channels are NOT touched (they pass straight through, outside this
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// module). The write arbiter's bready_q is unaffected: it still arms only on
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// the REAL downstream m_wvalid && m_wready && m_wlast, because this buffer
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// sits UPSTREAM of the arbiter and presents a clean registered W to it.
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// - The upstream FSM may enter its B-wait state once the beat is accepted here;
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// that is safe because EMIF cannot return B until the buffered beat reaches it.
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`timescale 1ns/1ps
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module gs_axi_w_regbuf #(
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parameter int WDATA_W = 256,
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parameter int WSTRB_W = 32
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) (
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input logic clk,
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input logic rst_n,
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// upstream — from the Z RMW master's W output
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input logic [WDATA_W-1:0] u_wdata,
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input logic [WSTRB_W-1:0] u_wstrb,
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input logic u_wlast,
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input logic u_wvalid,
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output logic u_wready,
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// downstream — to the write arbiter's s2 W input
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output logic [WDATA_W-1:0] d_wdata,
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output logic [WSTRB_W-1:0] d_wstrb,
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output logic d_wlast,
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output logic d_wvalid,
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input logic d_wready
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);
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logic full;
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logic [WDATA_W-1:0] wdata_q;
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logic [WSTRB_W-1:0] wstrb_q;
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logic wlast_q;
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// Upstream ready = registered occupancy ONLY (no d_wready term) -> EMIF WREADY
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// never reaches the upstream FSM combinationally.
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assign u_wready = !full;
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// Downstream presents the held beat, stable until the arbiter accepts it.
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assign d_wvalid = full;
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assign d_wdata = wdata_q;
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assign d_wstrb = wstrb_q;
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assign d_wlast = wlast_q;
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// One-entry register. Accept an offered upstream beat only while empty;
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// release only when the arbiter accepts the held beat. When full and accepted
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// in the same cycle, u_wready is still 0 (full is registered), so the next
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// beat waits one cycle -> a swap/drop/dup is impossible. Payload registers
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// deliberately have no reset (qualified by `full`/d_wvalid; the writer cannot
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// present a beat until reset releases), avoiding a wide reset fanout.
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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full <= 1'b0;
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end else if (!full) begin
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if (u_wvalid) begin
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full <= 1'b1;
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wdata_q <= u_wdata;
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wstrb_q <= u_wstrb;
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wlast_q <= u_wlast;
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end
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end else begin
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if (d_wready) full <= 1'b0;
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end
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end
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endmodule : gs_axi_w_regbuf
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