thejayman77
6319d7ca85
Closes the last currently-visible EMIF-handshake -> FSM setup family the
Ch443c fit exposed (-0.043/-0.022/-0.005 ns), the read-response analogue
of the AW/W buffers.
- gs_axi_r_regbuf: one-entry FULLY-registered AXI R buffer (the R twin of
gs_axi_w_regbuf). Buffers the complete {rdata,rresp,rlast}; u_rready =
!full only (NO combinational dependence on the texture FSM's d_rready);
captures on u_rvalid && u_rready; d_rvalid = full with the payload held
stable until d_rvalid && d_rready; resets only . Inserted between
read-arbiter s2 and gs_texture_cache (u_texf_rbuf). The arbiter is
unchanged -- it completes its R transaction into the buffer, which then
owns delivery to the fill FSM. Cuts EMIF rvalid/rdata -> fst.F_R.
- gs_texture_cache: drop the unobservable fill_data_q reset. F_DRAIN (its
only reader) is reachable only after F_R loads it, so the reset value is
never observed; removing it kills the separate lock_sync|dreg[1] ->
fill_data_q[80] setup path (-0.005 ns).
- New tb_gs_axi_r_regbuf: exactly-once/in-order, randomized responses +
stalls, full backpressure, the full && d_rready no-fall-through case,
{rdata,rresp,rlast} stability, reset-while-empty AND reset-while-full.
All green: r-buffer TB, texture_cache, texture_psmt8_clut, scanout_lb,
scanout_restart, scanout_diag, ps2_hps_bridge, rd_arb, and the complete
f52 replay BYTE-IDENTICAL (Z 0/307200, COLOR 0/245760). No Quartus/board/
push from here.
Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
79 lines
3.5 KiB
Systemverilog
79 lines
3.5 KiB
Systemverilog
// retroDE_ps2 — gs_axi_r_regbuf (Ch443d)
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//
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// Fully-registered ONE-ENTRY AXI R-channel (read-response) buffer. The R twin of
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// gs_axi_w_regbuf / gs_axi_aw_regbuf. Inserted between the read arbiter's s2 R
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// OUTPUT and the texture-cache fill FSM's R INPUT to cut the combinational path
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// EMIF gen_p2c_ff[*] (rvalid/rdata) -> gs_texture_cache F_R next-state (`fst`)
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// + fill_data_q capture — the -0.043 ns / -0.022 ns EMIF setup family.
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//
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// CONTRACT (per Codex review, identical shape to gs_axi_w_regbuf):
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// - FULLY REGISTERED, not a fall-through skid: u_rready depends ONLY on the
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// registered occupancy `full`, never on the texture FSM's downstream d_rready.
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// EMIF RVALID therefore can never propagate combinationally into the fill FSM.
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// (i.e. NOT `u_rready = !full || d_rready`.)
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// - Buffers the COMPLETE {RDATA, RRESP, RLAST} payload and holds it stable on the
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// downstream side until the texture FSM accepts it.
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// - Capture only on u_rvalid && u_rready; exactly-once, in-order (one in flight —
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// the texture fill issues single-beat reads, ARLEN=0/RLAST=1, but RRESP/RLAST
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// are preserved regardless).
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// - Downstream VALID is `full`; payload held stable until d_rvalid && d_rready.
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// - Reset only `full`; payload registers deliberately unreset (qualified by full).
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// - The arbiter is unchanged: it completes its R transaction when the response is
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// accepted into this buffer (s2_rready = u_rready = !full); the buffer then owns
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// delivery to the texture FSM.
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`timescale 1ns/1ps
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module gs_axi_r_regbuf #(
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parameter int RDATA_W = 256,
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parameter int RRESP_W = 2
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) (
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input logic clk,
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input logic rst_n,
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// upstream — from the read arbiter's s2 R output (EMIF read return)
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input logic [RDATA_W-1:0] u_rdata,
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input logic [RRESP_W-1:0] u_rresp,
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input logic u_rlast,
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input logic u_rvalid,
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output logic u_rready,
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// downstream — to the texture-cache fill FSM's R input
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output logic [RDATA_W-1:0] d_rdata,
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output logic [RRESP_W-1:0] d_rresp,
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output logic d_rlast,
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output logic d_rvalid,
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input logic d_rready
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);
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logic full;
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logic [RDATA_W-1:0] rdata_q;
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logic [RRESP_W-1:0] rresp_q;
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logic rlast_q;
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// Upstream ready = registered occupancy ONLY (no d_rready term) -> EMIF RVALID
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// never reaches the texture fill FSM combinationally.
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assign u_rready = !full;
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// Downstream presents the held response, stable until the texture FSM accepts it.
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assign d_rvalid = full;
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assign d_rdata = rdata_q;
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assign d_rresp = rresp_q;
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assign d_rlast = rlast_q;
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// One-entry register. Accept an offered upstream response only while empty;
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// release only when the texture FSM accepts the held response. When full and
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// accepted in the same cycle, u_rready is still 0 (full is registered), so the
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// next response waits one cycle -> a swap/drop/dup is impossible. Payload
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// registers deliberately have no reset (qualified by `full`/d_rvalid).
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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full <= 1'b0;
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end else if (!full) begin
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if (u_rvalid) begin
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full <= 1'b1;
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rdata_q <= u_rdata;
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rresp_q <= u_rresp;
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rlast_q <= u_rlast;
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end
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end else begin
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if (d_rready) full <= 1'b0;
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end
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end
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endmodule : gs_axi_r_regbuf
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