thejayman77
ba74bbd5aa
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog TBs, fidelity attribution tooling. Functional baseline before removing the dead bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
71 lines
3.1 KiB
Markdown
71 lines
3.1 KiB
Markdown
# Ch421 — complete request-packet boundary (prefit)
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## Trigger
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Ch420 successfully removed the direct request-pointer-to-RAM-address family.
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Its fit exposed ten paths from the wide request RAM's registered data output,
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through scene-bit decode, into separate fragment/marker valid registers. The
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worst was `-0.273 ns`; no address-stage path appeared in the violated top ten.
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## Structural cut
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`gs_lpddr_zc_emit` now captures all `PW` request bits, including the scene bit,
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into one `req_stage_packet` register. A single `req_stage_valid` occupancy bit
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is driven only by the already-registered `req_read_pending` control.
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Fragment versus marker selection is decoded after that complete packet
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boundary:
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```
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req_stage_frag_valid = req_stage_valid && !req_stage_packet.scene
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req_stage_marker_valid = req_stage_valid && req_stage_packet.scene
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```
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Therefore no request RAM output bit feeds stage occupancy or two competing
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valid-register D cones. The packet register intentionally has no reset;
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`req_stage_valid=0` makes it unobservable until a complete read is captured.
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Pop, pending, consume, marker ordering, and external latency are unchanged.
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## Prefit verification
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- async FIFO randomized CDC test: 3,284 writes/reads exact;
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- Z/color emit: 1,500 fragments exact across three epochs;
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- concurrent scanout/reload/probe: 16,384 pixels exact;
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- full 283-epoch production-control replay: PASS;
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- 1,177,489 fragments fed, 984,845 passed Z, zero drops/errors;
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- final Z mismatch `0 / 307,200`, color mismatch `0 / 235,963`;
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- framebuffer SHA-256 remains exactly
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`a88f1f6c926dd0db2b72ae2873c399e7dc5666f8003190184c34d360b13a5f44`;
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- relevant `git diff --check`: PASS.
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## Owner fit gate
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Ready for one owner-controlled Quartus 26.1 GUI compile. Acceptance requires:
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- no request RAM output path to stage occupancy/fragment/marker valid state;
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- any RAM-output-to-`req_stage_packet` data path is timing-clean;
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- setup, hold, recovery, removal, and minimum pulse all close;
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- request FIFO RAM inference remains intact at the existing device budget.
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Do not deploy the Ch420 RBF. If Ch421 closes, deploy that RBF and execute the
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already-verified 283-epoch board scene before accepting the chapter.
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## Owner fit result — request path closed, design path exposed
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The owner-controlled Quartus 26.1 GUI fit completed successfully. Ch421 did
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close the intended 310 MHz EMIF/request family:
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- EMIF setup WNS `+0.155 ns`, TNS `0`;
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- EMIF hold slack `0.000 ns` and all other timing classes clean;
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- no request FIFO path appeared in the violated setup paths;
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- 38,332 ALMs (82%), 55,712 registers, 336/358 RAM blocks (94%), 160 DSPs.
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The fit is nevertheless **not deployable** because placement exposed a separate
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25 MHz design-clock failure: setup WNS `-1.993 ns`, TNS `-14.856 ns`. All ten
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reported paths launch at `u_tex|g_bilinear.tap[0][8/9]` and terminate at
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`raster_pixel_color_q[16/18]`. The worst path contains 30 logic levels and
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41.955 ns of data delay: both bilinear interpolation stages plus TEX0 vertex
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modulation were being evaluated in one cycle. That is an independent, real
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combinational boundary defect, not a reason to undo the now-clean request
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packet cut. Ch422 addresses it structurally.
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