thejayman77
ba74bbd5aa
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog TBs, fidelity attribution tooling. Functional baseline before removing the dead bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
169 lines
8.2 KiB
Markdown
169 lines
8.2 KiB
Markdown
# Ch436 — vertical-linear authentic-display reconstruction prefit
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## Root cause
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The accepted Ch435 framebuffer is byte-identical between production RTL and
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the DE25, and its mean RGB is already close to the PCSX2 frame. The remaining
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high-frequency defect is also present in the independent software
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reconstruction, so it is not a board-transfer or framebuffer-write error.
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The Ch418 presentation path reduced the captured 512x448 display to the
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board's 640x480 raster with nearest-neighbour selection:
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- `source_x = floor(output_x * 4 / 5)`;
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- `source_y = 32 + floor(output_y * 14 / 15)`.
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That repeats source samples at both axes and exposes the already-granular base
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scene more harshly than linear display reconstruction.
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## RTL correction
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`gs_lpddr_scanout_lb` now optionally uses the existing 15-state vertical
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presentation phase as the exact interpolation numerator. It reads the
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current and already-prefetched next row from the two alternating line buffers.
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This adds no LPDDR traffic, line-buffer storage, or scheduler/render ordering
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change.
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The AXI prefetch side is notified of a source-row advance during horizontal
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blanking. This gives it the full blank interval to refill the retired parity
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buffer before the next active line requires the adjacent row. The directed
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test explicitly models that interval and checks all 600 samples against the
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same rounded separable equations as RTL, with zero errors or underflow.
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Legacy profiles retain nearest/1:1 behavior through a default-off parameter.
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Only the full-frame SH3 profile enables vertical linear reconstruction.
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Horizontal presentation retains the proven Ch418 nearest mapper.
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An initially simulated horizontal-linear extension duplicated the line-buffer
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storage to obtain an `x+1` read port. Quartus implemented those mirrors as
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30,720 registers instead of M20Ks, making the design require 6,270 LABs on a
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4,680-LAB device. That architecture was removed completely before this
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prefit candidate; none of the mirrored arrays or horizontal blend logic remain.
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## Measured preview and regression evidence
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On the accepted Ch435 board framebuffer, the exact RTL presentation model
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improves the PCSX2 comparison from nearest MAE/RMSE `14.7226/22.3097` to
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`14.2678/21.3085`. Mean RGB remains effectively unchanged at
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`(26.38, 23.33, 21.19)`, so this is a spatial reconstruction improvement, not
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a brightness retune.
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Passing directed regressions:
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- `tb_gs_lpddr_scanout_lb_hstretch`: 600 checked, zero errors, zero underflow;
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- `tb_gs_lpddr_scanout_lb`: pass;
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- `tb_gs_lpddr_scanout_lb_psm32`: 49,152 checked, zero errors/underflow;
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- `tb_gs_lpddr_scanout_lb_psm32_256`: 196,608 checked, zero errors/underflow.
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The framebuffer itself remains unchanged by construction, so the existing
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Ch435 22-epoch native-FBMSK and 311-epoch full-scene scoreboards remain the
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render-data acceptance baselines. The next owner GUI fit must establish RAM
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cost and signoff timing before board deployment.
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## First owner fit — resources recovered, narrow EMIF setup miss
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The vertical-only candidate fit successfully and recovered the exact Ch435
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memory/DSP budget: 5,327,792 block-memory bits, 344 / 358 RAM blocks, and
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160 / 376 DSPs. The 25 MHz presentation domain was comfortably clean at
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`+4.611 ns`; hold, recovery, removal, and minimum-pulse checks were also clean.
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The RBF is not deployable because EMIF setup finished at `-0.086 ns`. The
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actual post-fit top paths contained two unrelated 310 MHz routing families:
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- the high-fanout synchronized EMIF calibration reset driving duplicated
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texture-cache `drain_idx_q` payload registers (`-0.086 ns`);
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- one request-FIFO `raddr_q` copy driving the complete 93-bit by 16K physical
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RAM address network (`-0.073 ns` / `-0.062 ns`).
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Neither path contains the vertical filter or its 25 MHz arithmetic. This is
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therefore a structural timing repair, not a presentation rollback or another
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placement-only reroll.
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## First timing-repair fit — rejected RAM banking
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The texture fill's selected word/index boundary is now control-free and
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unreset. `F_WRITE` is reachable only after `F_DRAIN` has loaded both payload
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registers, so their reset values were unobservable; removing reset eliminates
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the EMIF calibration-reset launch family without changing fill ordering.
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The first repair also split the production request memory into three explicit
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31-bit by 16K banks. Although the logical storage remained 1,523,712 bits,
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each bank rounded up to 25 physical M20Ks. The request memory therefore used
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75 blocks instead of the packed macro's 59, raising the complete design from
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344 to 360 / 358 blocks. Fitter correctly rejected it before routing. This
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banked-memory architecture has been removed completely.
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## Current zero-RAM-cost compile candidate
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The request FIFO is back to its original single packed 93-bit by 16K memory,
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restoring the proven 59-block request-macro shape and expected 344 / 358 total
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RAM budget. Its existing unreset RAM-facing `raddr_q` now carries a
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`maxfan=64` synthesis directive. Quartus therefore duplicates only the
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address launch register as needed; the storage remains one efficiently packed
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memory and the pointer/read latency are unchanged.
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Verification after both cuts:
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- asynchronous FIFO: 3,284 writes/reads exact, zero errors;
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- texture cache: 64 words exact, refill error injection exact;
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- Z/color emitter: 1,500 fragments across three epochs, zero errors;
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- complete 311-epoch `zsrt139f52` production replay: 2,339,914 fragments fed,
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2,286,292 passed Z, zero drops/overflows/AXI errors, final Z mismatch
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`0 / 307,200`, final color mismatch `0 / 245,760`;
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- framebuffer SHA-256 remains exactly
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`d0047677371a0f6e4e319458926f604a8599c92baaf34d09b8e1fd452e31662b`,
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byte-identical to both accepted Ch435 board dumps;
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- relevant `git diff --check`: PASS.
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This zero-RAM-cost RTL is ready for a new owner-controlled Quartus 26.1 GUI
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compile. Acceptance requires all timing classes nonnegative, the request FIFO
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to return to the 59-block packed macro / 344-block total design budget, and the
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retired reset-to-`drain_idx_q` / high-fanout request-address families to be
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absent. Do not deploy either prior Ch436 RBF.
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## Accepted fit
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The owner-controlled Quartus 26.1 GUI compile completed successfully on
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2026-07-19. The packed request-memory shape and the complete Ch435 memory/DSP
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budget were restored. All timing classes are nonnegative:
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- EMIF setup WNS `+0.050 ns`, TNS `0.000 ns`;
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- 25 MHz design setup WNS `+2.387 ns`, TNS `0.000 ns`;
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- reference-clock setup WNS `+8.985 ns`, TNS `0.000 ns`;
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- hold minimum `0.000 ns`, with zero TNS;
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- recovery minimum `+1.054 ns`;
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- removal minimum `+0.163 ns`;
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- minimum-pulse-width minimum `+0.200 ns`.
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Final resources are 38,522 / 46,800 ALMs (82%), 5,327,792 / 7,331,840
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block-memory bits (73%), 344 / 358 RAM blocks (96%), and 160 / 376 DSPs
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(43%). Quartus explicitly ignored the `maxfan` directive because every load
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is a RAM address. The request-address family remains the clean EMIF limiter
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at `+0.050 ns`; the reset-to-`drain_idx_q` family is absent. Closure therefore
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comes from the valid reset cut and the resulting legal placement, not from a
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claimed address-register duplication.
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The accepted RBF is 4,100,096 bytes with SHA-256
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`1c8945e3e8ad85d91a682aa7a068cee487a1459a7f2b899600b24ff7d9751294`.
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## Hardware acceptance
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The RBF checksum was verified on the DE25-Nano, the accepted Ch435 image was
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preserved as `retroDE_ps2.pre_ch436.core.rbf`, and `core_loader.sh` loaded the
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new artifact successfully with `fpga0: operating`. Live preflight passed:
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- `CORE_ID=0x50533200`, ABI `0x00000100`, status `0x0000001f`;
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- HDMI initialization complete and no I2C error;
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- frame counter advanced from `0x0000117c` to `0x00001302`;
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- raster-overflow count remained zero.
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The complete 311-epoch `zsrt139f52` scene then passed every texture CRC,
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runtime-palette sum, staged-record count, fresh-drain, and zero-fragment-drop
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gate. The scheduler dumped all 307,200 framebuffer words and ended
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`DONE rc=0`. Board SHA-256 is
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`d0047677371a0f6e4e319458926f604a8599c92baaf34d09b8e1fd452e31662b`,
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byte-identical to the complete production simulation and both accepted Ch435
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board dumps. HDMI is live on the Ch436 vertical-linear presentation of that
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accepted f52 framebuffer. Ch436 is timing-, simulation-, and
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hardware-accepted.
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