thejayman77
ba74bbd5aa
Per-vertex GS fog end-to-end (gs_stub emit incl. persp_emit5, gs_prim_list_feeder XYZ2->XYZF2 on PRIM.FGE, gs_make_sh3_scheduler_fixture.py F/FGE packing), new fog TBs, fidelity attribution tooling. Functional baseline before removing the dead bilinear lerp8 clamps (Codex: 161-node comb loop -> -0.042ns setup fail). Co-Authored-By: Claude Opus 4.8 (1M context) <noreply@anthropic.com>
84 lines
3.1 KiB
Markdown
84 lines
3.1 KiB
Markdown
# Ch400 — chronological base geometry plus bounded alpha tail
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## Goal
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Move fidelity forward by replaying the missing in-bounds opaque draws before a
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small authentic alpha-blended tail, rather than darkening the incomplete Ch399
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base with the full alpha family.
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## Fixture
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- Tag: `sh3_zsrt139a6`
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- 35 authentic draws in chronological order
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- 20 epochs: 17 base epochs followed by 3 alpha epochs
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- Independent reference coverage: 83,596 framebuffer pixels
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- Simulation target: `make -C sim tb_top_psmct32_sh3_zint640rt139a6`
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- Board loader: `tools/scp_zsrt139a6_to_board.sh`
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## Blend ordering correction
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The first full replay found two wrong color pixels with exact Z. Repeated ABE
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fragments could begin their destination read after the previous blended result
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entered the color writer, but before that partial beat received an AXI BRESP.
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Waiting on the writer's raw `idle` signal is not sufficient because the elastic
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packer may retain a partial beat while its AXI FIFO is empty.
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`gs_lpddr_zc_emit` now treats each ABE result as an ordered dependency:
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1. accept one ABE input and hold subsequent color inputs;
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2. enqueue its blended output and pulse the color writer flush;
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3. wait for the ordered drain acknowledgement to transition low then high;
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4. admit the next color input only after the preceding write is memory-visible.
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Opaque flow remains unrestricted outside an active ABE dependency.
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## Simulation acceptance
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Final full replay:
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- fragments fed: 279,134
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- fragments passing Z: 234,373
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- scene markers: 20
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- request drops: 0
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- color FIFO overflows: 0
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- AXI BRESP errors: 0
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- Z mismatches: 0 / 307,200
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- color mismatches: 0 / 83,596
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- framebuffer MEM SHA-256:
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`38095a6c9136eb6618876c4cf2bf9a72c494a6f8161c247f2e1a36dcd0474bb8`
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## Hardware gate
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The RTL correction postdates the 2026-07-16 06:17 Quartus artifact. A fresh
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owner-run Quartus 26.1 GUI compile is required before board deployment. After
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that compile, accept Ch400 only if timing is clean, the RBF is fresh, the board
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run completes all 20 epochs with zero drops/errors, and the board framebuffer is
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byte-exact to `sh3_zsrt139a6_sim_fb.mem`.
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## Silicon acceptance (2026-07-16)
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The owner-run Quartus 26.1 GUI compile completed successfully after the final
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RTL correction. The fit used 37,148/46,800 ALMs and 284/358 RAM blocks. Setup
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slack was `+0.107 ns`, hold slack was `0.000 ns`, and all reported TNS values
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were zero.
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The fresh deploy RBF was written at 08:34:52, is 3,919,872 bytes, and has
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SHA-256
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`4619653217c8946b7ba4cd847a17f5e5b020c449ac4837784f72f9a7abed0b7d`.
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The hash matched on the DE25 before loading, and `fpga0` reported `operating`.
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The board completed all 20 epochs with every texture CRC, palette checksum,
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staged-word count, triangle-record count, preclear, drain, and zero-drop gate
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passing. The host returned `rc=0` and dumped all 307,200 framebuffer words.
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Board and simulation are byte-exact across the complete framebuffer:
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- board MEM SHA-256:
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`38095a6c9136eb6618876c4cf2bf9a72c494a6f8161c247f2e1a36dcd0474bb8`
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- simulation MEM SHA-256: same
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- board PNG SHA-256:
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`1785875df7c4c17fbf94ce1543fa3777be5601c874f5319ce4e2a20c828cecd0`
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- simulation PNG SHA-256: same
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Ch400 is accepted on silicon.
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