thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
197 lines
12 KiB
Systemverilog
197 lines
12 KiB
Systemverilog
// retroDE_ps2 — tb_gs_tile_spill_reload (Ch323 Brick 1c — two-batch DEPTH-survival proof)
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//
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// THE acceptance proof: tile-local color+Z can leave the chip and come back, and
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// the reloaded Z affects a LATER render. Two TME+ABE+ZTE triangles (payload_tile_spill)
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// render as two tile batches (single-prim mode); batch 2 reloads batch 1's flushed
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// color+Z before rendering. The TB models the LPDDR backing (captured FROM the actual
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// z_flush_* + color-flush streams — round-trip, not preloaded) and serves it on reload.
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//
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// Z scheme (CLEAR=0x4000, GEQUAL): P1 region A (top-left tri) Z=0x8000 color1(red);
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// P2 region A+B (large tri) Z=0x6000 color2(blue). Region A pixel (1,1) overlaps both;
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// region B pixel (10,2) is P2-only.
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//
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// NEGATIVE/POSITIVE flip (the real proof — Codex): two render passes via CORE_CTRL
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// re-render. POSITIVE: batch-2 reload serves the captured backing → region A reloads
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// P1's Z=0x8000 → P2(0x6000) FAILS → region A = color1. NEGATIVE: batch-2 reload serves
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// CLEAR (0x4000) → P2 PASSES → region A = color2. The color1<->color2 flip in region A,
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// with region B = color2 in BOTH, proves the result depends on Z reload, not stale state.
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`timescale 1ns/1ps
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module tb_gs_tile_spill_reload;
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localparam int H_ACTIVE = 16, V_ACTIVE = 16;
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localparam logic [2:0] TP_CLEAR=3'd1, TP_RENDER=3'd2, TP_FLUSH=3'd3, TP_RELOAD=3'd5, TP_ZFLUSH=3'd6;
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localparam logic [31:0] CLEAR_Z = 32'h0000_4000, CLEAR_COLOR = 32'hFF00_8000;
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localparam logic [31:0] COLOR1 = 32'hFF0000FF, COLOR2 = 32'hFFFF0000; // red / blue (ABGR)
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logic clk=0; always #5 clk=~clk;
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logic rst_n, core_go;
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logic [7:0] r,g,b; logic hsync,vsync,de;
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logic core_halt, dma_done_seen, frame_seen, raster_overflow, frame_toggle, dma_done_toggle;
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logic z_flush_emit; logic [31:0] z_flush_addr, z_flush_data;
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logic flush_emit; logic [31:0] flush_addr, flush_color32;
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logic reload_start; logic [7:0] tile_reload_raddr;
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logic [31:0] tile_reload_color, tile_reload_z;
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logic tile_reload_ready; // TB staging always warm (de25 adds fill latency in Brick 2)
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// ---- behavioral LPDDR backing, captured FROM the flush streams (round-trip) ----
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logic [31:0] z_backing [0:2047];
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logic [31:0] c_backing [0:2047];
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logic seen [0:2047];
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logic neg_mode; // 1 = serve CLEAR (negative control)
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// reload serve: register the raddr 1 cyc (gs_stub writes the tile RAM the cycle AFTER
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// presenting raddr). map tile index -> screen index = y*64 + x (single tile @ origin, fbw=1).
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// Procedural (not continuous `&&`) to avoid an iverilog vvp gate-elaboration quirk.
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logic [7:0] sreg_raddr;
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always_ff @(posedge clk) sreg_raddr <= tile_reload_raddr;
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always_comb begin
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logic [10:0] sidx;
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logic ub;
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tile_reload_ready = 1'b1;
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sidx = (11'(sreg_raddr[7:4]) << 6) + 11'(sreg_raddr[3:0]); // screen index = y*64 + x
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ub = (!neg_mode) && (seen[sidx] === 1'b1);
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tile_reload_z = ub ? z_backing[sidx] : CLEAR_Z;
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tile_reload_color = ub ? c_backing[sidx] : CLEAR_COLOR;
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end
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top_psmct32_raster_demo_bram #(
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.H_ACTIVE(H_ACTIVE), .V_ACTIVE(V_ACTIVE),
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.VRAM_BYTES(8*1024), .PSMCT32_SWIZZLE(1'b0),
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.COMBINED_TAZ(1'b1), .TILE_LOCAL(1'b1), .TILE_SPILL_ENABLE(1'b1)
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) dut (
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.clk(clk), .rst_n(rst_n), .core_go(core_go),
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.r(r), .g(g), .b(b), .hsync(hsync), .vsync(vsync), .de(de),
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.core_halt(core_halt), .dma_done_seen(dma_done_seen),
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.frame_seen(frame_seen), .raster_overflow(raster_overflow),
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.frame_toggle(frame_toggle), .dma_done_toggle(dma_done_toggle),
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.joy_a_pressed_i(1'b0), .joy_b_pressed_i(1'b0),
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.flush_emit_o(flush_emit), .flush_addr_o(flush_addr), .flush_color32_o(flush_color32),
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.z_flush_emit_o(z_flush_emit), .z_flush_addr_o(z_flush_addr), .z_flush_data_o(z_flush_data),
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.reload_start_o(reload_start), .tile_reload_raddr_o(tile_reload_raddr),
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.tile_reload_ready_i(tile_reload_ready), .tile_reload_color_i(tile_reload_color),
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.tile_reload_z_i(tile_reload_z)
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);
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// ---- phase + counter snoops (per pass; reset by clr_counters) ----
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int col_reload_w, z_reload_w, col_flush_e, z_flush_e, clear_z_w;
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bit saw_reload, saw_flush, saw_zflush, backing_before_2nd_reload;
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int z_flush_seen_count, reload_starts;
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bit clr_counters;
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always_ff @(posedge clk) begin
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if (clr_counters) begin
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col_reload_w<=0; z_reload_w<=0; col_flush_e<=0; z_flush_e<=0; clear_z_w<=0;
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saw_reload<=0; saw_flush<=0; saw_zflush<=0; backing_before_2nd_reload<=0;
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z_flush_seen_count<=0; reload_starts<=0;
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end else if (rst_n) begin
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// capture flush streams into the backing (round-trip).
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if (z_flush_emit) begin z_backing[z_flush_addr[12:2]]<=z_flush_data; seen[z_flush_addr[12:2]]<=1'b1;
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z_flush_e<=z_flush_e+1; z_flush_seen_count<=z_flush_seen_count+1; end
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if (flush_emit) begin c_backing[flush_addr[12:2]]<=flush_color32; col_flush_e<=col_flush_e+1; end
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// tile-RAM write attribution by phase.
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if (dut.u_gs.tile_phase==TP_CLEAR && dut.u_gs.tile_z_we) clear_z_w<=clear_z_w+1;
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if (dut.u_gs.tile_phase==TP_RELOAD) begin
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saw_reload<=1'b1;
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if (dut.u_gs.tile_color_we) col_reload_w<=col_reload_w+1;
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if (dut.u_gs.tile_z_we) z_reload_w<=z_reload_w+1;
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end
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if (dut.u_gs.tile_phase==TP_FLUSH) saw_flush<=1'b1;
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if (dut.u_gs.tile_phase==TP_ZFLUSH) saw_zflush<=1'b1;
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// Ch323 clean-Z BOOTSTRAP: batch-1 (no valid backing) does NOT reload — it renders
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// from the local CLEAR. Only batch-2 reloads, and by then batch-1's spill must have
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// populated the backing. So there is exactly ONE reload_start, and z_flush has fired.
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if (reload_start) begin
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reload_starts <= reload_starts + 1;
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if (z_flush_seen_count>0) backing_before_2nd_reload<=1'b1;
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end
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end
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end
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// ---- scanout capture ----
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logic [7:0] cap_r[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_g[0:V_ACTIVE-1][0:H_ACTIVE-1], cap_b[0:V_ACTIVE-1][0:H_ACTIVE-1];
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bit capture_armed; logic [31:0] hcnt_d, vcnt_d;
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always_ff @(posedge clk) begin
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if (!rst_n) begin hcnt_d<=0; vcnt_d<=0; end
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else begin hcnt_d<=32'(dut.u_pcrtc.hcnt); vcnt_d<=32'(dut.u_pcrtc.vcnt); end
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end
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always_ff @(posedge clk)
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if (rst_n && capture_armed && de && (vcnt_d<V_ACTIVE) && (hcnt_d<H_ACTIVE)) begin
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cap_r[vcnt_d][hcnt_d]<=r; cap_g[vcnt_d][hcnt_d]<=g; cap_b[vcnt_d][hcnt_d]<=b; end
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int errors;
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task automatic chk(input bit c, input string m);
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if (!c) begin errors++; $display("[spill] FAIL: %s", m); end endtask
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function automatic logic [23:0] px(input int y, input int x); px={cap_b[y][x],cap_g[y][x],cap_r[y][x]}; endfunction
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// run one render pass: full DUT reset + fresh boot (the bootlet re-uploads the texture
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// and re-renders both prims), then capture region A/B. seen[] is cleared so batch-1's
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// reload serves clear; the backing is repopulated from THIS pass's batch-1 flush.
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task automatic run_pass(output logic [23:0] rA, output logic [23:0] rB);
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for (int i=0;i<2048;i++) seen[i]=1'b0;
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rst_n<=1'b0; repeat(4) @(posedge clk); rst_n<=1'b1; repeat(8) @(posedge clk);
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clr_counters<=1'b1; @(posedge clk); clr_counters<=1'b0;
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@(negedge clk); core_go<=1'b1; @(negedge clk); core_go<=1'b0;
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$display("[spill] @%0t booted, waiting core_halt", $time);
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wait (core_halt==1'b1); repeat(4) @(posedge clk);
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$display("[spill] @%0t core_halt, waiting dma_done", $time);
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wait (dma_done_seen==1'b1); repeat(10) @(posedge clk);
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$display("[spill] @%0t dma_done, xfer_busy=%0d", $time, dut.xfer_busy);
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if (dut.xfer_busy==1'b1) wait (dut.xfer_busy==1'b0);
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$display("[spill] @%0t waiting raster_active rise", $time);
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wait (dut.u_gs.raster_active==1'b1); // level-sensitive (robust to an already-passed edge)
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$display("[spill] @%0t raster_active high, waiting fall", $time);
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wait (dut.u_gs.raster_active==1'b0); repeat(10) @(posedge clk);
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$display("[spill] @%0t raster done, waiting end_of_frame", $time);
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@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed<=1'b1;
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@(posedge dut.u_pcrtc.end_of_frame); @(posedge clk); capture_armed<=1'b0;
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$display("[spill] @%0t frame captured", $time);
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rA = px(1,1); rB = px(10,2);
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endtask
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logic [23:0] posA, posB, negA, negB;
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int p_creload, p_zreload, p_cflush, p_zflush;
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initial begin
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errors=0; rst_n=1; core_go=0; neg_mode=0; clr_counters=0;
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// ---- POSITIVE pass: batch-2 reload serves the captured backing ----
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$display("[spill] starting POSITIVE pass ...");
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neg_mode<=1'b0;
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run_pass(posA, posB);
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$display("[spill] POSITIVE pass done: regionA=%06x regionB=%06x", posA, posB);
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p_creload=col_reload_w; p_zreload=z_reload_w; p_cflush=col_flush_e; p_zflush=z_flush_e;
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chk(saw_reload, "FSM never entered TP_RELOAD");
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chk(saw_flush, "FSM never entered TP_FLUSH");
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chk(saw_zflush, "FSM never entered TP_ZFLUSH");
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chk(backing_before_2nd_reload, "backing not populated before batch-2 reload");
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chk(clear_z_w >= 256, $sformatf("batch-2 CLEAR didn't clobber tile Z (clear_z_w=%0d)", clear_z_w));
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// BOOTSTRAP: only batch-2 reloads (batch-1 renders from clear) -> 256 reload writes, not 512.
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chk(p_creload==256, $sformatf("color reload writes=%0d exp 256 (batch-2 only; batch-1 boots from clear)", p_creload));
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chk(p_zreload==256, $sformatf("Z reload writes=%0d exp 256", p_zreload));
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chk(p_cflush ==512, $sformatf("color flush emits=%0d exp 512 (both batches flush)", p_cflush));
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chk(p_zflush ==512, $sformatf("Z flush emits=%0d exp 512", p_zflush));
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// ---- NEGATIVE pass: batch-2 reload serves CLEAR (control) ----
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$display("[spill] starting NEGATIVE pass ...");
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neg_mode<=1'b1;
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run_pass(negA, negB);
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$display("[spill] NEGATIVE pass done: regionA=%06x regionB=%06x", negA, negB);
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// ---- the flip: region A must change with reload, region B stays P2 ----
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chk(posA===COLOR1[23:0], $sformatf("POSITIVE region A=%06x exp color1 %06x (Z reload should make P2 fail)", posA, COLOR1[23:0]));
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chk(negA===COLOR2[23:0], $sformatf("NEGATIVE region A=%06x exp color2 %06x (no reload -> P2 passes)", negA, COLOR2[23:0]));
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chk(posB===COLOR2[23:0], $sformatf("POSITIVE region B=%06x exp color2 %06x (control)", posB, COLOR2[23:0]));
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chk(negB===COLOR2[23:0], $sformatf("NEGATIVE region B=%06x exp color2 %06x (control)", negB, COLOR2[23:0]));
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chk(posA!==negA, "region A did NOT flip between reload-on and reload-off (proof void)");
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$display("=== Ch323 tile spill/reload two-batch proof ===");
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$display(" counts(positive): color_reload=%0d Z_reload=%0d (exp 256, batch-2 only) color_flush=%0d Z_flush=%0d (exp 512)",
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p_creload, p_zreload, p_cflush, p_zflush);
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$display(" FSM: reload=%0d flush=%0d zflush=%0d backing_before_2nd_reload=%0d clear_clobber=%0d",
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saw_reload, saw_flush, saw_zflush, backing_before_2nd_reload, clear_z_w);
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$display(" region A: positive=%06x negative=%06x (exp color1=%06x / color2=%06x)", posA, negA, COLOR1[23:0], COLOR2[23:0]);
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$display(" region B: positive=%06x negative=%06x (exp color2=%06x both)", posB, negB, COLOR2[23:0]);
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if (errors==0) $display("[tb_gs_tile_spill_reload] PASS");
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else $display("[tb_gs_tile_spill_reload] FAIL (%0d errors)", errors);
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$finish;
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end
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initial begin #100000000; $display("[tb_gs_tile_spill_reload] TIMEOUT"); $finish; end
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endmodule
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