thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
509 lines
21 KiB
Systemverilog
509 lines
21 KiB
Systemverilog
// retroDE_ps2 — tb_gs_raster_psmt4 (Ch106)
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//
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// Locks the contract for gs_stub's WRITE-side PSMT4 emit. PSMT4
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// packs 2 pixels per byte (low nibble = even pixel, high nibble =
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// odd pixel within a row), so each emit is a sub-byte write — the
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// nibble NOT being written must be preserved.
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//
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// The Ch106 mechanism: gs_stub places the 4-bit index in the
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// targeted nibble position of write_data[7:0], drives
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// `raster_pixel_be_q = 4'b0001` (1-byte commit) and
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// `raster_pixel_mask_q = 32'h0000_000F` (low nibble) or
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// `32'h0000_00F0` (high nibble). vram_stub commits each byte as
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// mem[addr] <= (mem[addr] & ~mask[7:0]) | (data[7:0] & mask[7:0])
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// which is the read-modify-write the indexed format requires.
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// Back-to-back same-byte emits chain through NBA semantics — the
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// second NBA samples mem[addr] AFTER the first commit applies.
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//
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// This TB is INTENTIONALLY adversarial about preservation:
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// - VRAM is preloaded with a non-zero pattern (0xA5 everywhere
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// in the sprite's row range) BEFORE raster runs, so a buggy
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// full-byte write would visibly clobber the un-touched
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// nibble.
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// - The sprite spans both an even-x start (low-nibble first
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// within each pair-of-pixels) AND an odd-x start (high-
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// nibble first), exercising both nibble positions as the
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// leading pixel of a pair.
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// - A single-pixel SPRITE drawn on top of the preloaded byte
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// proves that ONE nibble update preserves the OTHER nibble
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// even with NO companion pixel in the same emit run.
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//
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// Setup (Phase A — even-aligned, full-byte coverage):
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// PRIM = SPRITE
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// FRAME_1: FBP=0, FBW=1, PSM=PSMT4 (0x14)
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// FBW=1 at bit 16 → 0x0001_0000
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// PSM=0x14 at bit 24 → 0x1400_0000
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// RGBAQ A=0xCC B=0xBB G=0xAA R=0x05 → PSMT4 index = R[3:0] = 5.
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// v1 = (0,0); v2 = (3,1) → 4×2 sprite, all pairs (x even / x+1
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// odd) land in the same byte → emits both nibbles of each
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// byte and the full byte ends up = 0x55. fb_addr formula:
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// pixel_index = y*64 + x
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// byte_addr = pixel_index >> 1
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// So row 0 sprite spans bytes 0..1, row 1 spans bytes 32..33.
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//
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// Setup (Phase B — odd-aligned start, isolated high-nibble write):
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// New SPRITE with v1=(5,2) → v2=(5,2), single pixel at x=5
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// (odd → high nibble). Index = R[3:0] = 7. Targets byte 2 of
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// row 2: byte_addr = (2*64 + 5) >> 1 = 66; nibble = high.
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// Pre-load mem[66] = 0xA5. Expected after: mem[66] = 0x75 (low
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// nibble 5 preserved; high nibble updated to 7).
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//
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// Setup (Phase C — odd-aligned start, isolated low-nibble write):
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// SPRITE v1=(4,3)..v2=(4,3), single pixel at x=4 (even → low
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// nibble). Index = 0x9. Pre-load mem[(3*64+4)>>1=98] = 0xA5.
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// Expected after: mem[98] = 0xA9 (high nibble A preserved; low
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// nibble updated to 9).
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//
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// Setup (Phase D — distinct adjacent nibbles in the SAME byte,
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// composed across two emits with DIFFERENT index values):
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// SPRITE is flat-color, so we use TWO single-pixel SPRITEs at
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// adjacent x coords landing in the same byte, each with a
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// different R. SPRITE 1: (36, 1) with R=0x3 → low nibble.
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// SPRITE 2: (37, 1) with R=0xC → high nibble. Both target
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// byte_addr = (1*64 + 36) >> 1 = 50. Pre-load mem[50] = 0xA5.
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// Expected after the two emits: mem[50] = 0xC3 — a composed
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// byte with NON-IDENTICAL nibbles, proving that the second
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// emit (high) does not stomp the first emit's freshly-written
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// low nibble. Phase A's all-5s pattern proved accumulation but
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// not distinct composition; Phase D ties that race down by
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// forcing the result to encode the order-independent merge.
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//
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// PASS criteria:
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// - 8 + 1 + 1 + 2 = 12 raster_pixel_emit pulses total across phases
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// - raster_pixel_psm_q == 6'h14 on every emit
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// - raster_pixel_be_q == 4'b0001 on every emit
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// - raster_pixel_mask_q ∈ {0x0F, 0xF0} on every emit
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// - Phase A: each sprite byte ends at 0x55, neighbouring bytes
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// stay at 0xA5 (preload preserved).
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// - Phase B: mem[66] = 0x75 (high nibble updated, low nibble
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// preserved at 5).
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// - Phase C: mem[98] = 0xA9 (low nibble updated, high nibble
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// preserved at A).
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// - No 0xAA / 0xBB / 0xCC byte appears anywhere — channel
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// isolation: only R[3:0] reaches VRAM.
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`timescale 1ns/1ps
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module tb_gs_raster_psmt4;
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logic clk;
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logic rst_n;
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initial clk = 1'b0;
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always #5 clk = ~clk;
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logic gif_reg_wr_en;
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logic [7:0] gif_reg_num;
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logic [63:0] gif_reg_data;
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logic [7:0] bg_r, bg_g, bg_b;
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logic [63:0] pmode_q, dispfb1_q, display1_q;
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logic [63:0] prim_q, rgbaq_q, xyz2_q, xyzf2_q, frame_1_q, zbuf_1_q;
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logic prim_complete;
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logic [31:0] prim_complete_count;
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logic [63:0] prim_v0_q, prim_v1_q, prim_v2_q;
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logic [63:0] prim_color_q;
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logic [63:0] prim_color_v0_q, prim_color_v1_q, prim_color_v2_q;
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trace_pkg::vertex_t prim_v0_decoded_q, prim_v1_decoded_q, prim_v2_decoded_q;
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trace_pkg::color_t prim_v0_color_decoded_q, prim_v1_color_decoded_q, prim_v2_color_decoded_q;
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logic pixel_emit;
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logic [31:0] pixel_emit_count;
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logic [11:0] pixel_x_q, pixel_y_q;
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logic [63:0] pixel_color_q;
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logic [8:0] pixel_fbp_q;
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logic [5:0] pixel_fbw_q, pixel_psm_q;
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logic [31:0] pixel_fb_addr_q;
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logic raster_pixel_emit;
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logic [31:0] raster_pixel_emit_count;
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logic [11:0] raster_pixel_x_q, raster_pixel_y_q;
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logic [63:0] raster_pixel_color_q;
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logic [31:0] raster_pixel_fb_addr_q;
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logic [3:0] raster_pixel_be_q;
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logic [31:0] raster_pixel_mask_q;
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logic [5:0] raster_pixel_psm_q;
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logic raster_active;
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logic raster_overflow;
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logic raster_degenerate;
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logic gs_ev_valid;
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trace_pkg::subsys_e gs_ev_subsys;
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trace_pkg::event_e gs_ev_event;
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logic [63:0] gs_ev_arg0, gs_ev_arg1, gs_ev_arg2, gs_ev_arg3;
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logic [31:0] gs_ev_flags;
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gs_stub u_gs (
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.clk(clk), .rst_n(rst_n),
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.reg_wr_en(1'b0), .reg_wr_addr(16'd0), .reg_wr_data(64'd0),
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.gif_reg_wr_en(gif_reg_wr_en),
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.gif_reg_num(gif_reg_num),
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.gif_reg_data(gif_reg_data),
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.bg_r(bg_r), .bg_g(bg_g), .bg_b(bg_b),
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.pmode_q(pmode_q), .dispfb1_q(dispfb1_q), .display1_q(display1_q),
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.prim_q(prim_q), .rgbaq_q(rgbaq_q),
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.xyz2_q(xyz2_q), .xyzf2_q(xyzf2_q),
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.frame_1_q(frame_1_q), .zbuf_1_q(zbuf_1_q),
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.prim_complete(prim_complete),
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.prim_complete_count(prim_complete_count),
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.prim_v0_q(prim_v0_q), .prim_v1_q(prim_v1_q), .prim_v2_q(prim_v2_q),
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.prim_color_q(prim_color_q),
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.prim_color_v0_q(prim_color_v0_q),
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.prim_color_v1_q(prim_color_v1_q),
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.prim_color_v2_q(prim_color_v2_q),
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.prim_v0_decoded_q(prim_v0_decoded_q),
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.prim_v1_decoded_q(prim_v1_decoded_q),
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.prim_v2_decoded_q(prim_v2_decoded_q),
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.prim_v0_color_decoded_q(prim_v0_color_decoded_q),
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.prim_v1_color_decoded_q(prim_v1_color_decoded_q),
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.prim_v2_color_decoded_q(prim_v2_color_decoded_q),
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.pixel_emit(pixel_emit),
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.pixel_emit_count(pixel_emit_count),
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.pixel_x_q(pixel_x_q), .pixel_y_q(pixel_y_q),
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.pixel_color_q(pixel_color_q),
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.pixel_fbp_q(pixel_fbp_q),
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.pixel_fbw_q(pixel_fbw_q),
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.pixel_psm_q(pixel_psm_q),
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.pixel_fb_addr_q(pixel_fb_addr_q),
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.raster_pixel_emit(raster_pixel_emit),
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.raster_pixel_emit_count(raster_pixel_emit_count),
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.raster_pixel_x_q(raster_pixel_x_q),
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.raster_pixel_y_q(raster_pixel_y_q),
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.raster_pixel_color_q(raster_pixel_color_q),
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.raster_pixel_fb_addr_q(raster_pixel_fb_addr_q),
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.raster_pixel_be_q(raster_pixel_be_q),
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.raster_pixel_mask_q(raster_pixel_mask_q),
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.raster_pixel_psm_q(raster_pixel_psm_q),
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.raster_active(raster_active),
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.raster_overflow(raster_overflow),
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.raster_degenerate(raster_degenerate),
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.ev_valid(gs_ev_valid),
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.ev_subsys(gs_ev_subsys),
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.ev_event(gs_ev_event),
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.ev_arg0(gs_ev_arg0), .ev_arg1(gs_ev_arg1),
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.ev_arg2(gs_ev_arg2), .ev_arg3(gs_ev_arg3),
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.ev_flags(gs_ev_flags)
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);
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// VRAM with TB-side preload mux: we drive synthetic preload
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// writes into vram_stub's write port BEFORE raster runs by
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// muxing the TB's preload signals onto write_*. During raster,
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// gs_stub drives write_*. A single-bit `tb_preload_active` flag
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// selects.
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logic tb_preload_active;
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logic tb_preload_en;
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logic [31:0] tb_preload_addr;
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logic [31:0] tb_preload_data;
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logic [3:0] tb_preload_be;
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logic [31:0] tb_preload_mask;
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logic vram_write_en;
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logic [31:0] vram_write_addr;
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logic [31:0] vram_write_data;
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logic [3:0] vram_write_be;
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logic [31:0] vram_write_mask;
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assign vram_write_en = tb_preload_active ? tb_preload_en : raster_pixel_emit;
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assign vram_write_addr = tb_preload_active ? tb_preload_addr : raster_pixel_fb_addr_q;
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assign vram_write_data = tb_preload_active ? tb_preload_data : raster_pixel_color_q[31:0];
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assign vram_write_be = tb_preload_active ? tb_preload_be : raster_pixel_be_q;
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assign vram_write_mask = tb_preload_active ? tb_preload_mask : raster_pixel_mask_q;
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logic [31:0] vram_read_addr;
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logic [31:0] vram_read_data;
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vram_stub #(.BYTES(4096)) u_vram (
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.clk(clk), .rst_n(rst_n),
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.write_en (vram_write_en),
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.write_addr(vram_write_addr),
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.write_data(vram_write_data),
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.write_be (vram_write_be),
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.write_mask(vram_write_mask),
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.read_addr (vram_read_addr),
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.read_data (vram_read_data),
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.read2_addr(32'd0),
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.read2_data()
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);
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int errors;
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int psmt4_emit_seen;
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initial begin
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errors = 0;
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psmt4_emit_seen = 0;
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end
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// Continuous observer for PSMT4 emits.
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always_ff @(posedge clk) begin
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if (rst_n && !tb_preload_active && raster_pixel_emit) begin
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psmt4_emit_seen <= psmt4_emit_seen + 1;
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if (raster_pixel_psm_q !== 6'h14) begin
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$error("emit %0d: raster_pixel_psm_q=0x%02x (expected 0x14 PSMT4)",
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psmt4_emit_seen, raster_pixel_psm_q);
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errors <= errors + 1;
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end
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if (raster_pixel_be_q !== 4'b0001) begin
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$error("emit %0d: raster_pixel_be_q=%b (expected 4'b0001)",
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psmt4_emit_seen, raster_pixel_be_q);
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errors <= errors + 1;
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end
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if (raster_pixel_mask_q !== 32'h0000_000F &&
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raster_pixel_mask_q !== 32'h0000_00F0) begin
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$error("emit %0d: raster_pixel_mask_q=0x%08x (expected 0x0F or 0xF0)",
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psmt4_emit_seen, raster_pixel_mask_q);
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errors <= errors + 1;
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end
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end
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end
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task automatic step_drive(input logic wr_en,
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input logic [7:0] num,
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input logic [63:0] data);
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@(negedge clk);
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gif_reg_wr_en = wr_en;
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gif_reg_num = num;
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gif_reg_data = data;
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@(posedge clk);
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endtask
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task automatic drive_reg(input logic [7:0] num, input logic [63:0] data);
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step_drive(1'b1, num, data);
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endtask
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task automatic drive_idle();
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step_drive(1'b0, 8'd0, 64'd0);
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endtask
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task automatic preload_byte(input logic [31:0] byte_addr,
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input logic [7:0] val);
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// Write a single byte using vram_stub's per-byte be.
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@(negedge clk);
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tb_preload_active = 1'b1;
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tb_preload_en = 1'b1;
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tb_preload_addr = byte_addr;
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tb_preload_data = {24'd0, val};
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tb_preload_be = 4'b0001;
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tb_preload_mask = 32'hFFFF_FFFF;
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@(posedge clk);
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@(negedge clk);
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tb_preload_en = 1'b0;
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tb_preload_active = 1'b0;
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endtask
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function automatic logic [63:0] xyz2_data(input logic [11:0] x_int,
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input logic [11:0] y_int);
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return {32'd0, y_int, 4'd0, x_int, 4'd0};
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endfunction
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task automatic check_byte(input logic [31:0] byte_addr,
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input logic [7:0] expected,
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input string tag);
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logic [7:0] got;
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vram_read_addr = byte_addr & ~32'd3;
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#1;
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unique case (byte_addr[1:0])
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2'd0: got = vram_read_data[7:0];
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2'd1: got = vram_read_data[15:8];
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2'd2: got = vram_read_data[23:16];
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2'd3: got = vram_read_data[31:24];
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endcase
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if (got !== expected) begin
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$error("[%s] @byte 0x%08x got 0x%02x expected 0x%02x",
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tag, byte_addr, got, expected);
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errors = errors + 1;
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end
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endtask
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localparam logic [7:0] R_PRIM = 8'h00;
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localparam logic [7:0] R_RGBAQ = 8'h01;
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localparam logic [7:0] R_XYZ2 = 8'h05;
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localparam logic [7:0] R_FRAME_1 = 8'h4C;
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localparam logic [63:0] PRIM_SPRITE = 64'd6;
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// FRAME_1: FBP=0 / FBW=1 / PSM=0x14 (PSMT4).
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localparam logic [63:0] FRAME_1_VAL = 64'h0000_0000_1401_0000;
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initial begin
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rst_n = 1'b0;
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gif_reg_wr_en = 1'b0;
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gif_reg_num = 8'd0;
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gif_reg_data = 64'd0;
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vram_read_addr = 32'd0;
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tb_preload_active = 1'b0;
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tb_preload_en = 1'b0;
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tb_preload_addr = 32'd0;
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tb_preload_data = 32'd0;
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tb_preload_be = 4'd0;
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tb_preload_mask = 32'hFFFF_FFFF;
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repeat (4) @(posedge clk);
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rst_n = 1'b1;
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repeat (2) @(posedge clk);
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// ----------------------------------------------------------------
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// Pre-load adversarial pattern at every byte we'll touch (and
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// a couple bytes adjacent for neighbour-preservation).
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// ----------------------------------------------------------------
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for (int a = 0; a < 4; a++) preload_byte(32'(a), 8'hA5); // Phase A row 0 + neighbours
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for (int a = 32; a < 36; a++) preload_byte(32'(a), 8'hA5); // Phase A row 1 + neighbours
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preload_byte(32'd66, 8'hA5); // Phase B target byte
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preload_byte(32'd98, 8'hA5); // Phase C target byte
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preload_byte(32'd50, 8'hA5); // Phase D target byte
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// ----------------------------------------------------------------
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// Phase A: 4×2 sprite at (0,0)..(3,1). Index = R[3:0] = 5.
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// 8 emits across bytes 0,0,1,1,32,32,33,33. Each pair
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// (low+high) of the same byte should accumulate to 0x55.
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// ----------------------------------------------------------------
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drive_reg(R_PRIM, PRIM_SPRITE);
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drive_reg(R_FRAME_1, FRAME_1_VAL);
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drive_reg(R_RGBAQ, 64'h0000_0000_CCBB_AA05);
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drive_reg(R_XYZ2, xyz2_data(12'd0, 12'd0));
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drive_reg(R_XYZ2, xyz2_data(12'd3, 12'd1));
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drive_idle();
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wait (raster_active == 1'b1);
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wait (raster_active == 1'b0);
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repeat (5) @(posedge clk);
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// Phase A asserts.
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check_byte(32'd0, 8'h55, "phaseA-byte0");
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check_byte(32'd1, 8'h55, "phaseA-byte1");
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check_byte(32'd32, 8'h55, "phaseA-byte32");
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check_byte(32'd33, 8'h55, "phaseA-byte33");
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// Neighbour bytes should still be the preload value.
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check_byte(32'd2, 8'hA5, "phaseA-byte2-untouched");
|
||
check_byte(32'd3, 8'hA5, "phaseA-byte3-untouched");
|
||
check_byte(32'd34, 8'hA5, "phaseA-byte34-untouched");
|
||
check_byte(32'd35, 8'hA5, "phaseA-byte35-untouched");
|
||
|
||
// ----------------------------------------------------------------
|
||
// Phase B: single pixel at (5, 2). x=5 odd → high nibble.
|
||
// pixel_index = 2*64 + 5 = 133; byte_addr = 66; nibble=high.
|
||
// Index = R[3:0] = 7. Expected mem[66] = 0x75 (low nibble
|
||
// 5 from preload preserved; high nibble updated from A→7).
|
||
// ----------------------------------------------------------------
|
||
drive_reg(R_PRIM, PRIM_SPRITE);
|
||
drive_reg(R_FRAME_1, FRAME_1_VAL);
|
||
drive_reg(R_RGBAQ, 64'h0000_0000_CCBB_AA07);
|
||
drive_reg(R_XYZ2, xyz2_data(12'd5, 12'd2));
|
||
drive_reg(R_XYZ2, xyz2_data(12'd5, 12'd2));
|
||
drive_idle();
|
||
|
||
wait (raster_active == 1'b1);
|
||
wait (raster_active == 1'b0);
|
||
repeat (5) @(posedge clk);
|
||
|
||
// Wait — the preload was 0xA5 (high=A, low=5). After
|
||
// overwriting high nibble with 7, expect 0x75.
|
||
check_byte(32'd66, 8'h75, "phaseB-high-nibble-rmw");
|
||
|
||
// ----------------------------------------------------------------
|
||
// Phase C: single pixel at (4, 3). x=4 even → low nibble.
|
||
// pixel_index = 3*64 + 4 = 196; byte_addr = 98; nibble=low.
|
||
// Index = R[3:0] = 9. Expected mem[98] = 0xA9 (high nibble
|
||
// A from preload preserved; low nibble updated from 5→9).
|
||
// ----------------------------------------------------------------
|
||
drive_reg(R_PRIM, PRIM_SPRITE);
|
||
drive_reg(R_FRAME_1, FRAME_1_VAL);
|
||
drive_reg(R_RGBAQ, 64'h0000_0000_CCBB_AA09);
|
||
drive_reg(R_XYZ2, xyz2_data(12'd4, 12'd3));
|
||
drive_reg(R_XYZ2, xyz2_data(12'd4, 12'd3));
|
||
drive_idle();
|
||
|
||
wait (raster_active == 1'b1);
|
||
wait (raster_active == 1'b0);
|
||
repeat (5) @(posedge clk);
|
||
|
||
check_byte(32'd98, 8'hA9, "phaseC-low-nibble-rmw");
|
||
|
||
// ----------------------------------------------------------------
|
||
// Phase D: distinct adjacent nibbles in the same byte, written
|
||
// across TWO emits with DIFFERENT R values. SPRITE is flat-
|
||
// color so we issue two single-pixel SPRITEs back-to-back.
|
||
// - sprite 1 at (36, 1) with R=0x3 → byte 50 low nibble = 3
|
||
// - sprite 2 at (37, 1) with R=0xC → byte 50 high nibble = C
|
||
// Preload mem[50] = 0xA5. Expected after both emits: 0xC3 (a
|
||
// distinct-nibble composition that NO single uniform R could
|
||
// produce, locking the per-emit nibble-merge claim tighter
|
||
// than Phase A's all-5s accumulation).
|
||
// ----------------------------------------------------------------
|
||
drive_reg(R_PRIM, PRIM_SPRITE);
|
||
drive_reg(R_FRAME_1, FRAME_1_VAL);
|
||
drive_reg(R_RGBAQ, 64'h0000_0000_CCBB_AA03);
|
||
drive_reg(R_XYZ2, xyz2_data(12'd36, 12'd1));
|
||
drive_reg(R_XYZ2, xyz2_data(12'd36, 12'd1));
|
||
drive_idle();
|
||
|
||
wait (raster_active == 1'b1);
|
||
wait (raster_active == 1'b0);
|
||
repeat (5) @(posedge clk);
|
||
|
||
// Spot-check after sprite 1: low nibble updated 5→3, high
|
||
// nibble still A.
|
||
check_byte(32'd50, 8'hA3, "phaseD-after-sprite1-low-write");
|
||
|
||
drive_reg(R_PRIM, PRIM_SPRITE);
|
||
drive_reg(R_FRAME_1, FRAME_1_VAL);
|
||
drive_reg(R_RGBAQ, 64'h0000_0000_CCBB_AA0C);
|
||
drive_reg(R_XYZ2, xyz2_data(12'd37, 12'd1));
|
||
drive_reg(R_XYZ2, xyz2_data(12'd37, 12'd1));
|
||
drive_idle();
|
||
|
||
wait (raster_active == 1'b1);
|
||
wait (raster_active == 1'b0);
|
||
repeat (5) @(posedge clk);
|
||
|
||
// Final composed byte: high nibble updated A→C, low nibble
|
||
// preserved from the sprite-1 write at 3.
|
||
check_byte(32'd50, 8'hC3, "phaseD-distinct-nibble-composition");
|
||
|
||
// ----------------------------------------------------------------
|
||
// Aggregate counts.
|
||
// ----------------------------------------------------------------
|
||
if (raster_pixel_emit_count != 32'd12) begin
|
||
$error("expected 12 emits total, got %0d", raster_pixel_emit_count);
|
||
errors = errors + 1;
|
||
end
|
||
if (psmt4_emit_seen != 12) begin
|
||
$error("PSMT4 emit observer count=%0d (expected 12)", psmt4_emit_seen);
|
||
errors = errors + 1;
|
||
end
|
||
|
||
// ----------------------------------------------------------------
|
||
// Channel-isolation sweep: the only non-preload bytes ever
|
||
// committed should be the sprite pixels. Walk all 4 KiB and
|
||
// assert NO byte equals 0xAA / 0xBB / 0xCC (G/B/A leaks).
|
||
// ----------------------------------------------------------------
|
||
begin
|
||
int leak;
|
||
leak = 0;
|
||
for (int addr = 0; addr < 4096; addr += 4) begin
|
||
vram_read_addr = addr[31:0];
|
||
#1;
|
||
for (int b = 0; b < 4; b++) begin
|
||
logic [7:0] v;
|
||
v = vram_read_data[b*8 +: 8];
|
||
if (v == 8'hAA || v == 8'hBB || v == 8'hCC) begin
|
||
$error("leak: byte 0x%08x = 0x%02x (G/B/A leaked into VRAM)",
|
||
addr + b, v);
|
||
leak = leak + 1;
|
||
end
|
||
end
|
||
end
|
||
if (leak != 0) errors = errors + leak;
|
||
end
|
||
|
||
$display("[tb_gs_raster_psmt4] phaseA=4x2 phaseB=high-rmw phaseC=low-rmw phaseD=distinct-compose emits=%0d",
|
||
raster_pixel_emit_count);
|
||
|
||
if (errors == 0) $display("[tb_gs_raster_psmt4] PASS");
|
||
else $display("[tb_gs_raster_psmt4] FAIL");
|
||
$finish;
|
||
end
|
||
|
||
initial begin
|
||
#5000000;
|
||
$error("[tb_gs_raster_psmt4] timeout");
|
||
$finish;
|
||
end
|
||
|
||
endmodule : tb_gs_raster_psmt4
|