thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
263 lines
10 KiB
Systemverilog
263 lines
10 KiB
Systemverilog
// retroDE_ps2 — tb_gs_raster_pipeline (Ch88)
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//
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// White-box TB pinning down the Ch88 pixel-pipeline contract:
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//
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// * Throughput: 1 candidate pixel/cycle once the pipeline is
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// primed. For a fully-inside primitive this means 1 emit/cycle
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// for N consecutive cycles, where N is the bbox pixel count.
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//
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// * Latency: from the v2-close cycle (push) to first observed
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// raster_pixel_emit, exactly 5 posedges:
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// v_close v2 commits, push_ok=1 (FIFO 0→1)
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// v_close+1 R_IDLE+nonempty → pop_ok=1, state ← R_SCAN
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// v_close+2 state=R_SCAN, S0 produces pix(0,0); s1 ← (0,0)
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// v_close+3 s2 ← (0,0)
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// v_close+4 emit register fires (raster_pixel_emit ← 1)
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// v_close+5 raster_pixel_emit visible to observer
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// i.e., 3 stages of pipeline + 1 cycle for the FIFO turn-
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// around + 1 cycle for the registered emit output.
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//
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// * After last S0 coord, the pipeline drains for 2 more cycles
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// so all in-flight pixels still emit (no truncation).
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//
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// Flow: drive PRIM/FRAME_1/RGBAQ then a single 4×4 SPRITE
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// (16 pixels). Capture the cycle index of every raster_pixel_emit
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// pulse and assert:
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// - exactly 16 pulses
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// - every adjacent pair is on consecutive cycles (delta == 1)
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// - first pulse lands EXACTLY 3 cycles after the pop_ok cycle
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// - raster_overflow stays low
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`timescale 1ns/1ps
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module tb_gs_raster_pipeline;
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logic clk;
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logic rst_n;
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initial clk = 1'b0;
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always #5 clk = ~clk;
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// gs_stub inputs
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logic gif_reg_wr_en;
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logic [7:0] gif_reg_num;
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logic [63:0] gif_reg_data;
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// gs_stub outputs (most are tied off — we only watch raster_*)
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logic [7:0] bg_r, bg_g, bg_b;
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logic [63:0] prim_q, rgbaq_q, xyz2_q, xyzf2_q, frame_1_q, zbuf_1_q;
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logic prim_complete;
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logic [31:0] prim_complete_count;
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logic [63:0] prim_v0_q, prim_v1_q, prim_v2_q;
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logic [63:0] prim_color_q;
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logic [63:0] prim_color_v0_q, prim_color_v1_q, prim_color_v2_q;
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trace_pkg::vertex_t prim_v0_decoded_q, prim_v1_decoded_q, prim_v2_decoded_q;
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trace_pkg::color_t prim_v0_color_decoded_q, prim_v1_color_decoded_q, prim_v2_color_decoded_q;
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logic pixel_emit;
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logic [31:0] pixel_emit_count;
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logic [11:0] pixel_x_q, pixel_y_q;
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logic [63:0] pixel_color_q;
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logic [8:0] pixel_fbp_q;
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logic [5:0] pixel_fbw_q, pixel_psm_q;
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logic [31:0] pixel_fb_addr_q;
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logic raster_pixel_emit;
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logic [31:0] raster_pixel_emit_count;
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logic [11:0] raster_pixel_x_q, raster_pixel_y_q;
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logic [63:0] raster_pixel_color_q;
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logic [31:0] raster_pixel_fb_addr_q;
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logic raster_active;
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logic raster_overflow;
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logic raster_degenerate;
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logic ev_valid;
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trace_pkg::subsys_e ev_subsys;
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trace_pkg::event_e ev_event;
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logic [63:0] ev_arg0, ev_arg1, ev_arg2, ev_arg3;
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logic [31:0] ev_flags;
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gs_stub u_gs (
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.clk(clk), .rst_n(rst_n),
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.reg_wr_en(1'b0), .reg_wr_addr(16'd0), .reg_wr_data(64'd0),
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.gif_reg_wr_en(gif_reg_wr_en),
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.gif_reg_num(gif_reg_num),
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.gif_reg_data(gif_reg_data),
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.bg_r(bg_r), .bg_g(bg_g), .bg_b(bg_b),
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.prim_q(prim_q), .rgbaq_q(rgbaq_q),
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.xyz2_q(xyz2_q), .xyzf2_q(xyzf2_q),
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.frame_1_q(frame_1_q), .zbuf_1_q(zbuf_1_q),
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.prim_complete(prim_complete),
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.prim_complete_count(prim_complete_count),
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.prim_v0_q(prim_v0_q), .prim_v1_q(prim_v1_q), .prim_v2_q(prim_v2_q),
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.prim_color_q(prim_color_q),
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.prim_color_v0_q(prim_color_v0_q),
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.prim_color_v1_q(prim_color_v1_q),
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.prim_color_v2_q(prim_color_v2_q),
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.prim_v0_decoded_q(prim_v0_decoded_q),
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.prim_v1_decoded_q(prim_v1_decoded_q),
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.prim_v2_decoded_q(prim_v2_decoded_q),
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.prim_v0_color_decoded_q(prim_v0_color_decoded_q),
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.prim_v1_color_decoded_q(prim_v1_color_decoded_q),
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.prim_v2_color_decoded_q(prim_v2_color_decoded_q),
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.pixel_emit(pixel_emit),
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.pixel_emit_count(pixel_emit_count),
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.pixel_x_q(pixel_x_q), .pixel_y_q(pixel_y_q),
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.pixel_color_q(pixel_color_q),
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.pixel_fbp_q(pixel_fbp_q),
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.pixel_fbw_q(pixel_fbw_q),
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.pixel_psm_q(pixel_psm_q),
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.pixel_fb_addr_q(pixel_fb_addr_q),
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.raster_pixel_emit(raster_pixel_emit),
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.raster_pixel_emit_count(raster_pixel_emit_count),
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.raster_pixel_x_q(raster_pixel_x_q),
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.raster_pixel_y_q(raster_pixel_y_q),
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.raster_pixel_color_q(raster_pixel_color_q),
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.raster_pixel_fb_addr_q(raster_pixel_fb_addr_q),
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.raster_active(raster_active),
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.raster_overflow(raster_overflow),
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.raster_degenerate(raster_degenerate),
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.ev_valid(ev_valid), .ev_subsys(ev_subsys), .ev_event(ev_event),
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.ev_arg0(ev_arg0), .ev_arg1(ev_arg1),
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.ev_arg2(ev_arg2), .ev_arg3(ev_arg3),
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.ev_flags(ev_flags)
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);
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// Per-cycle index. Increments every posedge clk after rst_n.
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int cycle_idx;
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initial cycle_idx = 0;
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always_ff @(posedge clk) if (rst_n) cycle_idx <= cycle_idx + 1;
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// Capture the cycle of the v2 close (last drive_reg call) and
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// the cycle every raster_pixel_emit pulse fires.
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int v_close_cycle;
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int emit_cycles [0:31];
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int emit_count;
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int errors;
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initial begin
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v_close_cycle = -1;
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emit_count = 0;
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errors = 0;
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end
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always_ff @(posedge clk) begin
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if (rst_n && raster_pixel_emit && emit_count < 32) begin
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emit_cycles[emit_count] <= cycle_idx;
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emit_count <= emit_count + 1;
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end
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end
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task automatic step_drive(input logic wr_en,
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input logic [7:0] num,
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input logic [63:0] data);
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@(negedge clk);
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gif_reg_wr_en = wr_en;
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gif_reg_num = num;
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gif_reg_data = data;
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@(posedge clk);
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endtask
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task automatic drive_reg(input logic [7:0] num, input logic [63:0] data);
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step_drive(1'b1, num, data);
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endtask
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task automatic drive_idle();
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step_drive(1'b0, 8'd0, 64'd0);
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endtask
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function automatic logic [63:0] xyz2_data(input logic [11:0] x_int,
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input logic [11:0] y_int);
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return {32'd0, y_int, 4'd0, x_int, 4'd0};
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endfunction
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localparam logic [7:0] R_PRIM = 8'h00;
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localparam logic [7:0] R_RGBAQ = 8'h01;
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localparam logic [7:0] R_XYZ2 = 8'h05;
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localparam logic [7:0] R_FRAME_1 = 8'h4C;
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localparam logic [63:0] PRIM_SPRITE = 64'd6;
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localparam logic [63:0] FRAME_1_VAL = 64'h0000_0000_000A_0002;
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localparam logic [63:0] RGBAQ_VAL = 64'h0000_0000_FF00_30FF;
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initial begin
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rst_n = 1'b0;
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gif_reg_wr_en = 1'b0;
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gif_reg_num = 8'd0;
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gif_reg_data = 64'd0;
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repeat (4) @(posedge clk);
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rst_n = 1'b1;
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repeat (2) @(posedge clk);
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drive_reg(R_PRIM, PRIM_SPRITE);
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drive_reg(R_FRAME_1, FRAME_1_VAL);
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drive_reg(R_RGBAQ, RGBAQ_VAL);
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// 4×4 sprite — bbox=[0..3]×[0..3] = 16 pixels.
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drive_reg(R_XYZ2, xyz2_data(12'd0, 12'd0)); // v1
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drive_reg(R_XYZ2, xyz2_data(12'd3, 12'd3)); // v2 — close S1
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v_close_cycle = cycle_idx; // capture posedge index of v2 close
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// Stop driving (deassert gif_reg_wr_en) and let the
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// pipeline run. Without this idle, gif_reg_wr_en stays
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// high and re-commits the v2 vertex every cycle, kicking
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// off extra sprites and overflowing the FIFO.
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drive_idle();
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repeat (40) @(posedge clk);
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// ---- Assertions ----
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$display("[tb_gs_raster_pipeline] v_close_cycle=%0d emit_count=%0d raster_pixel_emit_count=%0d raster_overflow=%b",
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v_close_cycle, emit_count, raster_pixel_emit_count, raster_overflow);
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for (int i = 0; i < emit_count; i++) begin
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$display("[tb_gs_raster_pipeline] emit[%0d] @ cyc=%0d", i, emit_cycles[i]);
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end
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if (emit_count != 16) begin
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$error("emit_count=%0d (expected 16 for 4×4 sprite)", emit_count);
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errors = errors + 1;
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end
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if (raster_pixel_emit_count != 32'd16) begin
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$error("raster_pixel_emit_count=%0d (expected 16)", raster_pixel_emit_count);
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errors = errors + 1;
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end
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if (raster_overflow !== 1'b0) begin
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$error("raster_overflow=%b (expected 0)", raster_overflow);
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errors = errors + 1;
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end
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// Throughput: every consecutive pair of emits must be on
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// adjacent cycles (delta == 1). 1 pixel/cycle.
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for (int i = 1; i < emit_count; i++) begin
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int d;
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d = emit_cycles[i] - emit_cycles[i-1];
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if (d != 1) begin
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$error("throughput break: emit[%0d]@%0d vs emit[%0d]@%0d (delta=%0d, expected 1)",
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i-1, emit_cycles[i-1], i, emit_cycles[i], d);
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errors = errors + 1;
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end
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end
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// Latency: 5 posedges from v_close to first observed
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// raster_pixel_emit (see header for breakdown).
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if (emit_count > 0) begin
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int expected_first;
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int actual_first;
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expected_first = v_close_cycle + 5;
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actual_first = emit_cycles[0];
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if (actual_first != expected_first) begin
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$error("first-emit latency: emit[0]@cyc=%0d (expected %0d = v_close+5)",
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actual_first, expected_first);
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errors = errors + 1;
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end
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end
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if (errors == 0) $display("[tb_gs_raster_pipeline] PASS");
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else $display("[tb_gs_raster_pipeline] FAIL");
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$finish;
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end
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initial begin
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#5000000;
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$error("[tb_gs_raster_pipeline] timeout");
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$finish;
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end
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endmodule : tb_gs_raster_pipeline
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