thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
50 lines
2.0 KiB
Markdown
50 lines
2.0 KiB
Markdown
# rtl/intc
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Interrupt controller scaffolding. Matches `docs/contracts/intc.md`.
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## Current contents
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- `intc_stub.sv` — generic PS2-style INTC register shell.
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Register-visible INTC_STAT / INTC_MASK (offsets parameterized) plus a
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16-source injection port `irq_src[15:0]`. The aggregate output
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`cpu_irq` is polarity-neutral: the same module is instantiated both
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as the EE INTC and as the IOP INTC (with appropriate offsets and a
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different set of wired sources in each case).
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## Register semantics
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- `INTC_STAT` (offset is a parameter; default 0x00): W1C on writes;
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sticky until cleared. `irq_src` sets bits on each cycle they're
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observed; same-cycle inject-over-W1C collisions keep the pending bit
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— interrupts are never silently swallowed.
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- `INTC_MASK` (offset is a parameter; default 0x10): plain write-to-set.
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Real PS2 uses XOR/toggle semantics on mask writes; stub uses plain
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write for simplicity. Escalate if a BIOS trace demands it.
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## Instantiation conventions
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- **EE INTC**: default offsets (STAT=0x00, MASK=0x10). Instantiated
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stand-alone in most benches; the EE memory map does not route INTC
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addresses yet (deferred).
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- **IOP INTC**: parameterized to STAT=0x70, MASK=0x74 to match real
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PS2 IOP INTC placement. Reached through `iop_memory_map_stub` at
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physical address 0x1F80_1070+ (region id = 5).
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## Wired sources (current)
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- EE INTC bit 0 = EE DMAC completion (`dmac_reg_stub.irq_completion_o`).
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- IOP INTC bit 0 = IOP DMAC ch9 completion
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(`iop_dmac_reg_stub.irq_completion_o`).
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Both are one-cycle pulses driven from the respective DMAC's `S_DONE`
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state. The INTC latches them into its own pending bit; software (the
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TB, for now) reads STAT through the architectural register port and
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acks with a W1C write.
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## Scope boundary
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Module is side-neutral by design. Source-routing from other real
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subsystems (timers, GIF/GS, IPU, SPU2, bridge `last_seen_o`) is the
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next natural expansion. Re-arm / re-assertion ordering is already
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proven in the integration benches.
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