thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
237 lines
13 KiB
Systemverilog
237 lines
13 KiB
Systemverilog
// ============================================================================
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// gs_z_flush_writer.sv (Ch323 Brick 2 — tile color/Z-flush LPDDR writer; PACKED)
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//
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// Writes a gs_stub tile-flush stream (one 32-bit word per tile pixel on design_clk —
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// either the TP_ZFLUSH Z stream or the TP_FLUSH color stream) to an FPGA-private
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// LPDDR4B scratch region (emif_clk). Used twice in the de25 top: once for Z, once for
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// the 32-bit color spill (the module is generic — it writes the 32-bit `data` at
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// BASE + `addr`).
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//
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// PACKED (Ch323 board fix): the FIRST cut did ONE single-32-bit-lane AXI write PER
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// pixel through a strictly-sequential AW->W->B FSM. The tile sweep emits one pixel per
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// design_clk (256 back-to-back), but each isolated write pays the full LPDDR round-trip
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// latency, so the drain fell far behind the emit rate and the 16-deep async FIFO
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// OVERFLOWED within ~16 px — dropping most of the spilled tile (grey-with-specks on
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// HDMI, spill_ovf=1). The proven framebuffer writer (gs_lpddr_axi_master) avoids this by
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// PACKING pixels into 256-bit beats; this writer now does the same with 32-bit lanes:
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//
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// design_clk : PACKER — accumulate 8 consecutive 32-bit pixels of a tile-row into one
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// 256-bit (32-byte) beat {block_off, data, strb}, keyed by the 32-byte
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// block address (addr[29:5]). A 16-px tile-row is exactly two 32-byte-
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// aligned blocks, so each beat completes naturally on its 8th px (no
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// dangling partial); a block-address change flushes the in-flight beat.
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// One FIFO push per 8 px => 8x fewer AXI writes => the sequential drain
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// keeps up with the same small FIFO.
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// async FIFO : gray-code CDC, carries {block_off[29:0], data[255:0], strb[31:0]}.
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// emif_clk : AXI FSM — pop a beat, issue a single-beat INCR write (AWSIZE=5 = 32 B,
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// AWLEN=0, full WSTRB on the populated lanes) at BASE + block_off.
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//
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// The packed beats land at exactly the offsets gs_tile_reload reads back (row r at
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// BASE + r*STRIDE, two 32-byte beats), so the reload side is unchanged.
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//
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// SEPARATE base (Codex): BASE is distinct from the color FB and the other scratch
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// region. A synthesis-off CANARY asserts no beat lands inside the canary-guard regions.
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//
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// Counters (Codex, distinct per instance): z_write_beats (256-bit beats written),
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// z_wr_errs (non-OKAY responses), fifo_overflow (sticky).
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//
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// NOTE (parity with gs_lpddr_axi_master): assumes the flush stream produces FULL 8-lane
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// beats (true for a tile width that is a multiple of 8 — the 16-wide spill tile). A
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// trailing partial beat at end-of-stream is NOT flushed.
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// ============================================================================
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`timescale 1ns/1ps
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module gs_z_flush_writer #(
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parameter [29:0] Z_BASE = 30'h0010_0000, // LPDDR byte base of this scratch region (DISTINCT)
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parameter [29:0] FB_BASE = 30'd0, // color framebuffer base (canary guard)
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parameter int FB_BYTES = 32'h0001_0000, // color framebuffer size (canary guard)
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parameter [29:0] TEX_BASE = 30'h0020_0000, // other scratch base (canary guard)
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parameter int TEX_BYTES = 32'h0000_8000, // other scratch size (canary guard)
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parameter int FIFO_DEPTH = 16
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)(
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// ---- GS / design clock domain: the flush emit stream ----
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input logic gs_clk,
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input logic gs_rst_n,
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input logic enable, // 1 = accept emits (default off => inert)
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input logic z_flush_emit, // one pulse per tile pixel
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input logic [31:0] z_flush_addr, // scratch-RELATIVE byte offset (pixel_index*4)
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input logic [31:0] z_flush_data, // 32-bit word for this pixel (Z or color)
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// ---- status (emif_clk domain unless noted) ----
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output logic [31:0] z_write_beats, // 256-bit beats written (cumulative)
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output logic [31:0] z_wr_errs, // non-OKAY write responses (cumulative)
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output logic fifo_overflow, // sticky (gs domain): an emit dropped (FIFO full)
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// Pipeline-split counters (Codex): emit/push (GS, reset by gs_rst_n=per-render core reset) and
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// pop/beats (EMIF, reset by trace_clear) localize any spill divergence: healthy = 512/64/64/64;
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// push>64 = packer partial beats; pop/beats>push = FIFO/reset broken; beats!=pop = AXI-FSM bug.
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input logic trace_clear, // resets the EMIF-domain counters (beats/pop) per render
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output logic [31:0] dbg_beat_count, // beats committed (B handshakes) since the last trace_clear
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output logic [31:0] dbg_emit_count, // GS: enable&&z_flush_emit accepted (per render)
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output logic [31:0] dbg_push_count, // GS: beats pushed into the FIFO (per render)
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output logic [31:0] dbg_pop_count, // EMIF: beats popped from the FIFO (since trace_clear)
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output logic [31:0] dbg_aw_count, // EMIF: AW handshakes (since trace_clear)
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output logic [31:0] dbg_w_count, // EMIF: W handshakes (since trace_clear)
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// ---- AXI4 write channel to the EMIF user port (emif_clk, 256-bit) ----
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input logic axi_clk,
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input logic axi_rst_n,
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output logic [29:0] awaddr,
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output logic [1:0] awburst,
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output logic [6:0] awid,
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output logic [7:0] awlen,
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output logic [2:0] awsize,
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output logic awvalid,
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input logic awready,
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output logic [255:0] wdata,
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output logic [31:0] wstrb,
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output logic wlast,
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output logic wvalid,
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input logic wready,
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input logic [1:0] bresp,
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input logic bvalid,
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output logic bready
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);
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assign awburst = 2'b01; // INCR
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assign awid = 7'd6; // distinct from FB writer(0)/probes/reload(6 too; arb priority disambiguates)
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assign awlen = 8'd0; // single beat
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assign awsize = 3'b101; // 32 bytes (256-bit)
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assign bready = 1'b1;
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localparam int PW = 318; // {block_off[29:0], data[255:0], strb[31:0]}
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// ============================ design_clk PACKER ============================
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// Accumulate 8 consecutive 32-bit pixels into one 256-bit beat keyed by the 32-byte
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// block address; push a COMPLETE beat to the FIFO (one push per 8 px, not per px).
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logic [29:0] cur_off;
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logic [255:0] cur_data;
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logic [31:0] cur_strb;
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logic has_data;
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logic fifo_wr;
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logic [PW-1:0] fifo_wdata;
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wire fifo_full, fifo_empty;
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wire [PW-1:0] fifo_rdata;
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logic fifo_rd;
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always_ff @(posedge gs_clk or negedge gs_rst_n) begin
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if (!gs_rst_n) begin
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cur_off <= '0; cur_data <= '0; cur_strb <= '0; has_data <= 1'b0;
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fifo_wr <= 1'b0; fifo_wdata <= '0; fifo_overflow <= 1'b0;
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dbg_emit_count <= 32'd0; dbg_push_count <= 32'd0;
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end else begin
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fifo_wr <= 1'b0;
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if (enable && z_flush_emit) dbg_emit_count <= dbg_emit_count + 32'd1;
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if (fifo_wr && !fifo_full) dbg_push_count <= dbg_push_count + 32'd1;
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if (enable && z_flush_emit) begin
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logic [29:0] block_off;
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logic [2:0] lane; // 0..7 (which 32-bit lane)
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logic [255:0] nd;
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logic [31:0] ns;
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block_off = {z_flush_addr[29:5], 5'd0};
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lane = z_flush_addr[4:2];
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if (has_data && (block_off != cur_off)) begin
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// block changed before the previous beat filled — flush it, restart.
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fifo_wdata <= {cur_off, cur_data, cur_strb};
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fifo_wr <= 1'b1;
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cur_off <= block_off;
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cur_data <= (256'd0 | (256'(z_flush_data) << ({29'd0, lane} * 32)));
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cur_strb <= (32'hF << ({29'd0, lane} * 4));
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has_data <= 1'b1;
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end else begin
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nd = has_data ? cur_data : 256'd0;
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ns = has_data ? cur_strb : 32'd0;
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nd[ ({29'd0, lane} * 32) +: 32 ] = z_flush_data;
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ns[ ({29'd0, lane} * 4) +: 4 ] = 4'hF;
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if (&ns) begin
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// beat complete (all 8 lanes) — flush, beat consumed.
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fifo_wdata <= {block_off, nd, ns};
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fifo_wr <= 1'b1;
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has_data <= 1'b0;
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end else begin
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cur_off <= block_off;
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cur_data <= nd;
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cur_strb <= ns;
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has_data <= 1'b1;
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end
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end
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end
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// overflow witness: a push attempt while the FIFO is full (must stay 0).
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if (fifo_wr && fifo_full) fifo_overflow <= 1'b1;
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end
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end
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// CRITICAL (Ch323 board bug): the async FIFO's two pointers MUST reset together. The
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// packer side uses gs_rst_n (= core reset, which a CORE_CTRL pulse toggles EVERY render);
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// the read side uses axi_rst_n (= EMIF cal, power-on only). If wrst_n followed gs_rst_n,
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// each render's core-reset pulse would reset ONLY the write pointer → gray-code pointer
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// desync → FIFO corruption (garbage data, spurious overflow, writes that never commit).
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// Sim missed it (single reset, both sides together). So reset BOTH FIFO sides from the
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// STABLE axi_rst_n: assert async on axi_rst_n, deassert synchronized into gs_clk.
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reg [1:0] wrst_sync;
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always_ff @(posedge gs_clk or negedge axi_rst_n) begin
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if (!axi_rst_n) wrst_sync <= 2'b00;
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else wrst_sync <= {wrst_sync[0], 1'b1};
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end
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wire fifo_wrst_n = wrst_sync[1];
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gs_async_fifo #(.WIDTH(PW), .DEPTH(FIFO_DEPTH)) u_fifo (
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.wclk(gs_clk), .wrst_n(fifo_wrst_n), .wr(fifo_wr && !fifo_full), .wdata(fifo_wdata), .wfull(fifo_full),
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.rclk(axi_clk), .rrst_n(axi_rst_n), .rd(fifo_rd), .rdata(fifo_rdata), .rempty(fifo_empty)
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);
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// ============================ emif_clk AXI FSM ============================
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wire [29:0] beat_block = fifo_rdata[PW-1 -: 30]; // block_off[29:0]
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wire [255:0] beat_data = fifo_rdata[287:32];
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wire [31:0] beat_strb = fifo_rdata[31:0];
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wire [29:0] full_addr = Z_BASE + beat_block;
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typedef enum logic [1:0] { W_IDLE, W_AW, W_W, W_B } wstate_t;
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wstate_t wst;
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logic [29:0] lat_addr;
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logic [255:0] lat_data;
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logic [31:0] lat_strb;
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always_ff @(posedge axi_clk or negedge axi_rst_n) begin
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if (!axi_rst_n) begin
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wst <= W_IDLE; awaddr <= '0; awvalid <= 1'b0; wdata <= '0; wstrb <= '0;
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wlast <= 1'b0; wvalid <= 1'b0; fifo_rd <= 1'b0;
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z_write_beats <= 32'd0; z_wr_errs <= 32'd0;
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dbg_beat_count <= 32'd0;
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dbg_pop_count <= 32'd0; dbg_aw_count <= 32'd0; dbg_w_count <= 32'd0;
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lat_addr <= '0; lat_data <= '0; lat_strb <= '0;
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end else begin
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fifo_rd <= 1'b0;
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if (trace_clear) begin
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dbg_beat_count <= 32'd0;
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dbg_pop_count <= 32'd0; dbg_aw_count <= 32'd0; dbg_w_count <= 32'd0;
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end
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if (fifo_rd) dbg_pop_count <= dbg_pop_count + 32'd1;
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if (awvalid && awready) dbg_aw_count <= dbg_aw_count + 32'd1;
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if (wvalid && wready) dbg_w_count <= dbg_w_count + 32'd1;
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case (wst)
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W_IDLE: if (!fifo_empty) begin
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lat_addr <= full_addr; lat_data <= beat_data; lat_strb <= beat_strb;
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fifo_rd <= 1'b1; // pop this beat
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awaddr <= {full_addr[29:5], 5'd0}; // 32-byte aligned
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awvalid <= 1'b1;
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wst <= W_AW;
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// synthesis translate_off
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if (((full_addr >= FB_BASE) && (full_addr < FB_BASE + FB_BYTES[29:0])) ||
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((full_addr >= TEX_BASE) && (full_addr < TEX_BASE + TEX_BYTES[29:0])))
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$error("gs_z_flush_writer CANARY: beat addr 0x%07x overlaps a canary-guard region", full_addr);
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// synthesis translate_on
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end
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W_AW: if (awready) begin
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awvalid <= 1'b0; wdata <= lat_data;
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wstrb <= lat_strb; wlast <= 1'b1; wvalid <= 1'b1; wst <= W_W;
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end
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W_W: if (wready) begin wvalid <= 1'b0; wlast <= 1'b0; wst <= W_B; end
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W_B: if (bvalid) begin
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if (bresp != 2'b00) z_wr_errs <= z_wr_errs + 32'd1;
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z_write_beats <= z_write_beats + 32'd1;
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dbg_beat_count <= dbg_beat_count + 32'd1;
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wst <= W_IDLE;
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end
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default: wst <= W_IDLE;
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endcase
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end
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end
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endmodule
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