thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
49 lines
2.0 KiB
Systemverilog
49 lines
2.0 KiB
Systemverilog
// retroDE_ps2 — gs_tile_ram (Ch303)
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//
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// Generic on-chip TILE-LOCAL RAM for the tiled GS renderer: a single-write /
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// single-read scratchpad sized to one render tile (e.g. 16x16 = 256 entries).
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// Instantiated TWICE by the tile renderer — once as the color tile, once as the
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// Z tile — so a combined textured+alpha+depth pixel resolves its color/Z
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// read-modify-write entirely ON CHIP (per docs/decisions/0008 §6), with only the
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// texture fetch and the per-tile flush crossing to VRAM/LPDDR.
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//
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// Contract (matches vram_bram_stub.read2 so the raster FSM retarget is minimal):
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// - 1 write port (we/waddr/wdata), committed this cycle.
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// - 1 read port (raddr), data REGISTERED → valid ONE cycle later (rdata).
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// - Same-address read+write in the same cycle is NOT used by the tile renderer
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// (the FSM reads Z at beat 0 and writes Z at beat 4 of a 5-beat pixel; color
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// read at beat 2, write at beat 3 — never the same cycle), so no R/W-collision
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// forwarding is needed; this stays a plain 1W1R inferred BRAM.
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//
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// The memory is NOT reset (BRAM-friendly); the renderer's CLEAR phase initializes
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// every entry (color=clear color, Z=clear/far Z) before the first primitive.
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`timescale 1ns/1ps
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module gs_tile_ram #(
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parameter int ADDR_W = 8, // 256 entries = one 16x16 tile
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parameter int DATA_W = 32
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) (
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input logic clk,
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input logic rst_n,
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// write port (1 cycle, committed)
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input logic we,
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input logic [ADDR_W-1:0] waddr,
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input logic [DATA_W-1:0] wdata,
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// read port (registered, valid 1 cycle after raddr presented)
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input logic [ADDR_W-1:0] raddr,
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output logic [DATA_W-1:0] rdata
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);
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logic [DATA_W-1:0] mem [0:(1<<ADDR_W)-1];
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always_ff @(posedge clk) begin
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if (!rst_n) begin
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rdata <= '0;
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end else begin
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if (we) mem[waddr] <= wdata;
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rdata <= mem[raddr]; // 1-cycle registered read
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end
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end
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endmodule : gs_tile_ram
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