thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
75 lines
3.0 KiB
Systemverilog
75 lines
3.0 KiB
Systemverilog
// retroDE_ps2 — gs_texel_addr
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//
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// Texture-sampling address generator (brick 1, step 1 of GS texturing).
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//
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// Given a texture coordinate (u,v) and the TEX0 texture descriptor, computes
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// the LINEAR VRAM byte address of that texel — the read-side mirror of the
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// rasterizer's existing framebuffer-address math (gs_stub.sv ~line 530:
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// fb_addr = base + (Y*FBW*64 + X) * bytes_per_pixel ).
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//
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// Linear (non-swizzled) only, on purpose: the swizzle paths in gs_stub are
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// param-gated OFF by default, so linear is the baseline. Swizzled texel
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// addressing will reuse the existing gs_swizzle_* modules later.
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//
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// `base_byte_addr` is the texture base in VRAM, ALREADY scaled to bytes by
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// the caller from TEX0.TBP0. Keeping the base as a byte input (rather than
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// scaling TBP0 here) isolates the one thing that must be reconciled with the
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// texture-UPLOAD path (gif_image_xfer_stub / BITBLTBUF) — so we read texels
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// from exactly where BITBLT wrote them. That reconciliation is tracked as the
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// next integration step; this module's (u,v)->offset math is unambiguous and
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// unit-tested below.
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`timescale 1ns/1ps
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module gs_texel_addr #(
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parameter int ADDR_W = 32
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) (
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input logic [31:0] base_byte_addr, // texture base in VRAM (bytes)
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input logic [10:0] u, // texel column (0..2047)
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input logic [10:0] v, // texel row (0..2047)
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input logic [13:0] tbw, // TEX0.TBW — texels-per-row / 64
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input logic [5:0] psm, // pixel storage mode
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output logic [ADDR_W-1:0] texel_byte_addr,
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output logic nibble_hi // PSMT4: high nibble of the byte?
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);
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localparam logic [5:0] PSMCT32 = 6'h00;
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localparam logic [5:0] PSMCT16 = 6'h02;
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localparam logic [5:0] PSMT8 = 6'h13;
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localparam logic [5:0] PSMT4 = 6'h14;
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// texels per row = TBW * 64
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logic [19:0] row_texels;
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// linear texel index = v * row_texels + u
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logic [31:0] texel_offset;
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always_comb begin
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row_texels = {tbw, 6'b000000}; // tbw * 64
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texel_offset = (v * row_texels) + {21'd0, u};
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unique case (psm)
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PSMCT32: begin
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texel_byte_addr = base_byte_addr + (texel_offset << 2); // 4 B/texel
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nibble_hi = 1'b0;
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end
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PSMCT16: begin
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texel_byte_addr = base_byte_addr + (texel_offset << 1); // 2 B/texel
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nibble_hi = 1'b0;
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end
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PSMT8: begin
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texel_byte_addr = base_byte_addr + texel_offset; // 1 B/texel
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nibble_hi = 1'b0;
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end
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PSMT4: begin
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texel_byte_addr = base_byte_addr + (texel_offset >> 1); // 4 b/texel
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nibble_hi = texel_offset[0];
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end
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default: begin
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texel_byte_addr = base_byte_addr + (texel_offset << 2);
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nibble_hi = 1'b0;
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end
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endcase
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end
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endmodule : gs_texel_addr
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