thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
110 lines
4.2 KiB
Systemverilog
110 lines
4.2 KiB
Systemverilog
// retroDE_ps2 — gs_persp_uv (Ch301)
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//
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// Per-pixel PERSPECTIVE-CORRECT texture-coordinate divide. Given the three
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// affinely-interpolated perspective attributes at a pixel —
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//
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// uq = (u/w) * 2**FRAC (u-over-w, fixed-point)
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// vq = (v/w) * 2**FRAC (v-over-w, fixed-point)
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// q = (1/w) * 2**FRAC (one-over-w, fixed-point)
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//
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// — this recovers the integer texel coordinates:
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//
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// w_recip = 1/q (= w, via the pipelined gs_reciprocal_stub LUT, NO divider)
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// u_texel = (uq * w_recip) >> SCALE (= (u/w) * w = u)
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// v_texel = (vq * w_recip) >> SCALE (= (v/w) * w = v)
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//
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// gs_reciprocal_stub returns recip = floor(2**SCALE / q). With q = (1/w)<<FRAC
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// that is recip = w << (SCALE-FRAC). Then uq*recip = (u/w<<FRAC)*(w<<(SCALE-FRAC))
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// = u << SCALE, so (uq*recip) >> SCALE = u. (The FRAC scaling cancels.)
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//
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// Pipeline (NO divider, ~1 result/cycle):
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// recip: RLAT cycles (gs_reciprocal_stub, 3).
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// uq/vq: delayed RLAT cycles to align with recip.
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// mul: 1 cycle (uq*recip, vq*recip) + shift + clamp.
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// total latency = RLAT + 1.
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//
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// Output texel coords are clamped to [0, TEXEL_MAX] (saturating), matching the
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// integer-coord clamp the affine path already applies.
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`timescale 1ns/1ps
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module gs_persp_uv #(
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parameter int ATTR_W = 24, // width of uq/vq ((u/w)<<FRAC)
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parameter int Q_W = 24, // width of q ((1/w)<<FRAC)
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parameter int FRAC = 12, // fixed-point fraction bits of the attributes
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parameter int SCALE = 24, // gs_reciprocal scale (recip = floor(2**SCALE/q))
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parameter int RECIP_W = 25,
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parameter int TEXEL_W = 11,
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parameter int TEXEL_MAX = 2047,
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// Ch351 — reciprocal LUT mantissa width. Default 8 (256-entry) is byte-identical to Ch301/342/348.
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// Far-W perspective draws (small Q at high PERSP_FRAC) want more: 11 (2048-entry) ~ 0.05% rel error.
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parameter int RECIP_IDX_BITS = 8
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) (
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input logic clk,
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input logic rst_n,
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input logic in_valid,
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input logic [ATTR_W-1:0] uq,
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input logic [ATTR_W-1:0] vq,
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input logic [Q_W-1:0] q,
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output logic out_valid,
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output logic [TEXEL_W-1:0] u,
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output logic [TEXEL_W-1:0] v
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);
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localparam int RLAT = 3; // gs_reciprocal_stub latency
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// --- reciprocal of q (= w), pipelined LUT, no divider ---
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logic recip_valid;
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logic [RECIP_W-1:0] w_recip;
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gs_reciprocal_stub #(
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.Q_W(Q_W), .IDX_BITS(RECIP_IDX_BITS), .SCALE(SCALE), .OUT_W(RECIP_W)
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) u_recip (
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.clk(clk), .rst_n(rst_n),
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.in_valid(in_valid), .q(q),
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.out_valid(recip_valid), .recip(w_recip)
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);
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// --- delay uq/vq by RLAT to align with w_recip ---
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logic [ATTR_W-1:0] uq_pipe [0:RLAT-1];
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logic [ATTR_W-1:0] vq_pipe [0:RLAT-1];
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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for (int i = 0; i < RLAT; i++) begin
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uq_pipe[i] <= '0;
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vq_pipe[i] <= '0;
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end
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end else begin
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uq_pipe[0] <= uq;
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vq_pipe[0] <= vq;
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for (int i = 1; i < RLAT; i++) begin
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uq_pipe[i] <= uq_pipe[i-1];
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vq_pipe[i] <= vq_pipe[i-1];
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end
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end
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end
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// --- multiply + shift + clamp (1 reg stage) ---
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localparam int PROD_W = ATTR_W + RECIP_W;
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function automatic logic [TEXEL_W-1:0] clamp_texel(input logic [PROD_W-1:0] prod);
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logic [PROD_W-1:0] shifted;
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shifted = prod >> SCALE;
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if (shifted > PROD_W'(TEXEL_MAX)) clamp_texel = TEXEL_W'(TEXEL_MAX);
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else clamp_texel = shifted[TEXEL_W-1:0];
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endfunction
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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out_valid <= 1'b0;
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u <= '0;
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v <= '0;
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end else begin
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logic [PROD_W-1:0] u_prod, v_prod;
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out_valid <= recip_valid;
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u_prod = uq_pipe[RLAT-1] * w_recip;
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v_prod = vq_pipe[RLAT-1] * w_recip;
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u <= clamp_texel(u_prod);
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v <= clamp_texel(v_prod);
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end
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end
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endmodule : gs_persp_uv
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