thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
180 lines
8.6 KiB
Systemverilog
180 lines
8.6 KiB
Systemverilog
// ============================================================================
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// gs_lpddr_wr_arb.sv (Ch322 Brick 3; Ch323 extended 2:1 -> 3:1)
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//
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// 3:1 AXI4 WRITE-channel arbiter for the FPGA-private LPDDR4B EMIF user port.
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// The write twin of gs_lpddr_rd_arb. Lets the GS framebuffer writer
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// (gs_lpddr_axi_master, port 0, PRIORITY), the Ch323 tile Z-flush writer
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// (gs_z_flush_writer, port 2) and the Ch322 HPS write-probe
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// (gs_lpddr_wr_probe, port 1) share the single EMIF write channel.
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//
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// EXPLICIT priority (Ch323, Codex): FB-writer > Z-writer > wr-probe — i.e.
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// s0 > s2 > s1. The active render's color (FB) and Z spill outrank the debug
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// write-probe so a debug write can never starve a render flush. Leave s2_*
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// unconnected (awvalid=0) on builds without a Z writer — the arbiter is then
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// bit-for-bit the old 2:1 behavior.
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//
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// Per-transaction grant held AW->W->B (single-beat writes, AWLEN=0, so B
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// completes one transaction). Watchdog force-release guards a lost B.
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// All single-clock (emif_clk).
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// ============================================================================
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`timescale 1ns/1ps
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module gs_lpddr_wr_arb (
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input logic clk,
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input logic rst_n,
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// ---- Port 0: GS framebuffer writer (priority) ----
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input logic [29:0] s0_awaddr,
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input logic [1:0] s0_awburst,
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input logic [6:0] s0_awid,
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input logic [7:0] s0_awlen,
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input logic [2:0] s0_awsize,
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input logic s0_awvalid,
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output logic s0_awready,
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input logic [255:0] s0_wdata,
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input logic [31:0] s0_wstrb,
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input logic s0_wlast,
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input logic s0_wvalid,
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output logic s0_wready,
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output logic [1:0] s0_bresp,
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output logic s0_bvalid,
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input logic s0_bready,
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// ---- Port 1: HPS write-probe ----
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input logic [29:0] s1_awaddr,
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input logic [1:0] s1_awburst,
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input logic [6:0] s1_awid,
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input logic [7:0] s1_awlen,
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input logic [2:0] s1_awsize,
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input logic s1_awvalid,
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output logic s1_awready,
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input logic [255:0] s1_wdata,
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input logic [31:0] s1_wstrb,
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input logic s1_wlast,
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input logic s1_wvalid,
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output logic s1_wready,
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output logic [1:0] s1_bresp,
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output logic s1_bvalid,
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input logic s1_bready,
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// ---- Port 2: tile Z-flush writer (Ch323; priority ABOVE probe, below FB writer) ----
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input logic [29:0] s2_awaddr,
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input logic [1:0] s2_awburst,
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input logic [6:0] s2_awid,
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input logic [7:0] s2_awlen,
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input logic [2:0] s2_awsize,
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input logic s2_awvalid,
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output logic s2_awready,
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input logic [255:0] s2_wdata,
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input logic [31:0] s2_wstrb,
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input logic s2_wlast,
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input logic s2_wvalid,
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output logic s2_wready,
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output logic [1:0] s2_bresp,
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output logic s2_bvalid,
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input logic s2_bready,
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// ---- Port 3: HPS write-probe (Ch323 diag; LOWEST priority — debug staging) ----
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input logic [29:0] s3_awaddr,
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input logic [1:0] s3_awburst,
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input logic [6:0] s3_awid,
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input logic [7:0] s3_awlen,
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input logic [2:0] s3_awsize,
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input logic s3_awvalid,
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output logic s3_awready,
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input logic [255:0] s3_wdata,
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input logic [31:0] s3_wstrb,
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input logic s3_wlast,
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input logic s3_wvalid,
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output logic s3_wready,
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output logic [1:0] s3_bresp,
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output logic s3_bvalid,
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input logic s3_bready,
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// ---- Master out: EMIF write channel ----
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output logic [29:0] m_awaddr,
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output logic [1:0] m_awburst,
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output logic [6:0] m_awid,
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output logic [7:0] m_awlen,
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output logic [2:0] m_awsize,
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output logic m_awvalid,
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input logic m_awready,
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output logic [255:0] m_wdata,
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output logic [31:0] m_wstrb,
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output logic m_wlast,
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output logic m_wvalid,
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input logic m_wready,
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input logic [1:0] m_bresp,
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input logic m_bvalid,
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output logic m_bready
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);
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// grant: 0=idle, 1=s0 FB writer, 2=s1 color spill, 3=s2 Z spill, 4=s3 HPS write-probe.
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// EXPLICIT priority: FB-writer > Z-spill > color-spill > wr-probe — i.e. s0 > s2 > s1 > s3.
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reg [2:0] grant;
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// Ch326 — NON-ABORTING ARBITER (Codex), same protocol fix as gs_lpddr_rd_arb. Once
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// m_awvalid && m_awready, the write is COMMITTED (the slave will return B); abandoning it on
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// a watchdog would orphan the B / leave the slave mid-write. So the watchdog gates ONLY the
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// pre-AW wait; after AW acceptance the grant is held until m_bvalid && selected_bready. (The
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// FB/spill writers never tripped the old 2^10 watchdog in practice, but the latent bug is the
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// same — fixed for safety.)
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// "committed" = EITHER the AW or a W beat has handshaked. The current writers send AW-then-W
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// so AW sets it first, but tracking either makes this a GENERAL AXI write arbiter that never
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// abandons a transaction regardless of AW/W ordering (Codex audit note).
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reg aw_done; // a write beat/addr accepted for the active grant -> never abort past here
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reg [21:0] watchdog; // pre-commit only; ~6.7 ms @ 310 MHz dead-bus backstop
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wire wd_expired = watchdog[21];
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wire sel_bready = (grant==3'd1)?s0_bready:(grant==3'd2)?s1_bready:
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(grant==3'd3)?s2_bready:(grant==3'd4)?s3_bready:1'b1;
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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grant <= 3'd0; aw_done <= 1'b0; watchdog <= '0;
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end else if (grant == 3'd0) begin
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aw_done <= 1'b0; watchdog <= '0;
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if (s0_awvalid) grant <= 3'd1; // FB writer (highest)
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else if (s2_awvalid) grant <= 3'd3; // Z spill (render-flush)
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else if (s1_awvalid) grant <= 3'd2; // color spill (render-flush)
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else if (s3_awvalid) grant <= 3'd4; // HPS write-probe (debug, lowest)
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end else begin
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if ((m_awvalid && m_awready) || (m_wvalid && m_wready)) aw_done <= 1'b1; // AW or W accepted -> COMMITTED
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if (m_bvalid && sel_bready) begin
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grant <= 3'd0; aw_done <= 1'b0; watchdog <= '0; // B delivered -> release
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end else if (!aw_done) begin // still waiting for AW (nothing owed)
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if (wd_expired) begin grant <= 3'd0; aw_done <= 1'b0; watchdog <= '0; end
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else watchdog <= watchdog + 22'd1;
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end
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// aw_done && B not yet seen: HOLD the grant, never abort.
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end
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end
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// AW mux
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assign m_awaddr = (grant==3'd4)?s3_awaddr :(grant==3'd3)?s2_awaddr :(grant==3'd2)?s1_awaddr :s0_awaddr;
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assign m_awburst = (grant==3'd4)?s3_awburst:(grant==3'd3)?s2_awburst:(grant==3'd2)?s1_awburst:s0_awburst;
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assign m_awid = (grant==3'd4)?s3_awid :(grant==3'd3)?s2_awid :(grant==3'd2)?s1_awid :s0_awid;
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assign m_awlen = (grant==3'd4)?s3_awlen :(grant==3'd3)?s2_awlen :(grant==3'd2)?s1_awlen :s0_awlen;
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assign m_awsize = (grant==3'd4)?s3_awsize :(grant==3'd3)?s2_awsize :(grant==3'd2)?s1_awsize :s0_awsize;
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assign m_awvalid = (grant==3'd1)?s0_awvalid:(grant==3'd2)?s1_awvalid:(grant==3'd3)?s2_awvalid:(grant==3'd4)?s3_awvalid:1'b0;
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assign s0_awready = (grant==3'd1)?m_awready:1'b0;
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assign s1_awready = (grant==3'd2)?m_awready:1'b0;
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assign s2_awready = (grant==3'd3)?m_awready:1'b0;
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assign s3_awready = (grant==3'd4)?m_awready:1'b0;
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// W mux
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assign m_wdata = (grant==3'd4)?s3_wdata:(grant==3'd3)?s2_wdata:(grant==3'd2)?s1_wdata:s0_wdata;
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assign m_wstrb = (grant==3'd4)?s3_wstrb:(grant==3'd3)?s2_wstrb:(grant==3'd2)?s1_wstrb:s0_wstrb;
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assign m_wlast = (grant==3'd4)?s3_wlast:(grant==3'd3)?s2_wlast:(grant==3'd2)?s1_wlast:s0_wlast;
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assign m_wvalid = (grant==3'd1)?s0_wvalid:(grant==3'd2)?s1_wvalid:(grant==3'd3)?s2_wvalid:(grant==3'd4)?s3_wvalid:1'b0;
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assign s0_wready = (grant==3'd1)?m_wready:1'b0;
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assign s1_wready = (grant==3'd2)?m_wready:1'b0;
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assign s2_wready = (grant==3'd3)?m_wready:1'b0;
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assign s3_wready = (grant==3'd4)?m_wready:1'b0;
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// B demux (idle: bready=1 drains any stale/late response)
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assign s0_bresp = m_bresp; assign s1_bresp = m_bresp; assign s2_bresp = m_bresp; assign s3_bresp = m_bresp;
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assign s0_bvalid = (grant==3'd1)?m_bvalid:1'b0;
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assign s1_bvalid = (grant==3'd2)?m_bvalid:1'b0;
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assign s2_bvalid = (grant==3'd3)?m_bvalid:1'b0;
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assign s3_bvalid = (grant==3'd4)?m_bvalid:1'b0;
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assign m_bready = (grant==3'd1)?s0_bready:(grant==3'd2)?s1_bready:(grant==3'd3)?s2_bready:(grant==3'd4)?s3_bready:1'b1;
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endmodule
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