thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
214 lines
11 KiB
Systemverilog
214 lines
11 KiB
Systemverilog
// ============================================================================
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// gs_lpddr_scanout_lb.sv (Ch321 Brick 2)
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//
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// LINE-BUFFER LPDDR4B scanout — the architectural successor to the whole-frame
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// cache (gs_lpddr_scanout). Instead of mirroring the entire framebuffer in
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// on-chip RAM (which defeats the point of putting the FB in LPDDR), this holds
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// just TWO scanlines: it displays row L from one buffer while prefetching row
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// L+1 into the other. On-chip cost is O(width), not O(width*height).
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//
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// NARROW SCOPE (Ch321): the 128x128 PSMCT16 demo. The frame is LINEAR (the GS
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// writer mirrors the rasterizer's linear flush addresses), display window at
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// origin, 1:1 (MAG off) — so the reader serves pixel (col=pixel_x, line=pixel_y)
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// directly when inside the window. No general MAG/window handling beyond that.
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//
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// Two clock domains:
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// axi_clk (emif_clk) — AXI4 burst-read one row (ROW_BEATS beats) into a buffer
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// video_clk (design) — pixel_x/pixel_y index the active line buffer -> r/g/b
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//
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// Prefetch handshake: on each new display line (and at frame start) the video
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// side requests the next FB row via a toggle; the axi side fills the OTHER
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// buffer. `underflow` flags any pixel read before its row finished loading.
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// ============================================================================
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`timescale 1ns/1ps
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module gs_lpddr_scanout_lb #(
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parameter [29:0] FB_BASE = 30'd0,
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parameter int STRIDE_BYTES = 256, // PSMCT16 128px*2B=256; PSMCT32 128px*4B=512
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parameter int ROW_BEATS = 8, // STRIDE_BYTES / 32 (PSMCT16 128px=8; PSMCT32 128px=16)
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parameter int N_ROWS = 128,
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// Ch327a — PSMCT32 (ABGR8888, 8 px/256-bit beat) vs the original PSMCT16 (RGBA5551,
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// 16 px/beat). The Ch326 LPDDR-only spill framebuffer is PSMCT32 @ COLOR_SPILL_BASE, so the
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// line-buffer must decode it — NOT a config flip of the Ch321 PSMCT16/FB-at-0 path.
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parameter bit PSMCT32 = 1'b0
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)(
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// ---- AXI read clock domain (emif_clk) ----
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input logic axi_clk,
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input logic axi_rst_n,
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input logic enable, // 1 = active (prefetch + serve)
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// ---- video clock domain (design_clk) ----
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input logic video_clk,
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input logic frame_start, // vsync pulse/level (synced internally)
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input logic [11:0] pixel_x, // raster column (display)
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input logic [11:0] pixel_y, // raster line (display)
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input logic in_window, // PCRTC displayed-frame window gate
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output logic [7:0] r,
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output logic [7:0] g,
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output logic [7:0] b,
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// ---- status (axi_clk domain; bridge syncs) ----
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output logic line_valid, // at least one row has been loaded
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output logic underflow, // a pixel was read before its row was ready (sticky)
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output logic [31:0] rd_errs, // non-OKAY read responses (cumulative)
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// ---- AXI4 read channel to the EMIF user port (axi_clk, 256-bit) ----
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output logic [29:0] araddr,
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output logic [1:0] arburst,
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output logic [6:0] arid,
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output logic [7:0] arlen,
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output logic [2:0] arsize,
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output logic arvalid,
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input logic arready,
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input logic [255:0] rdata,
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input logic [1:0] rresp,
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input logic rlast,
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input logic rvalid,
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output logic rready
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);
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localparam int RB_BITS = $clog2(ROW_BEATS); // 3 for 8
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assign arburst = 2'b01; // INCR
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assign arid = 7'd3; // distinct: writer=0, probe=1, frame-cache=2, line-buf=3
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assign arlen = 8'd0; // SINGLE-BEAT per read — the only AXI read pattern proven on this
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// EMIF (writer/probe/frame-cache all use arlen=0). A multi-beat
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// burst (arlen=ROW_BEATS-1) was untested and garbled on hardware.
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assign arsize = 3'b101; // 32 bytes
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// Two line buffers, ROW_BEATS x 256-bit each (one display row).
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logic [255:0] lb0 [0:ROW_BEATS-1];
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logic [255:0] lb1 [0:ROW_BEATS-1];
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// ================= video side (video_clk) =================
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// No miss-prone request toggle. The video side just exposes the current
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// in-window display row; the axi side free-runs, fetching rows sequentially
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// and staying one row ahead (see below). disp_row_v resets on vsync.
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logic [$clog2(N_ROWS):0] disp_row_v;
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logic [2:0] fs_sync_v;
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wire fs_edge_v = (fs_sync_v[2] != fs_sync_v[1]);
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// The buffer holding display line L is L&1 (row L is fetched into L&1). Select
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// it DIRECTLY from pixel_y[0] (tracks the current pixel) — a separately-registered
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// "disp_buf" lags by one cycle and corrupts col 0 of each line.
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wire disp_buf = pixel_y[0];
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always_ff @(posedge video_clk) begin
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if (!enable) begin
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disp_row_v <= '0; fs_sync_v <= 3'd0;
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end else begin
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fs_sync_v <= {fs_sync_v[1:0], frame_start};
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if (fs_edge_v) disp_row_v <= '0;
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else if (in_window && (pixel_y < N_ROWS)) disp_row_v <= ($clog2(N_ROWS)+1)'(pixel_y);
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end
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end
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// Registered (sync-read) pixel: pick buffer + beat + within-beat lane from pixel_x.
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// PSMCT32: 8 px/256-bit beat -> beat = pixel_x>>3, lane = pixel_x[2:0] (32-bit).
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// PSMCT16: 16 px/beat -> beat = pixel_x>>4, lane = pixel_x[3:0] (16-bit).
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localparam int PXSH = PSMCT32 ? 3 : 4; // px-per-beat shift
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localparam int PX_PER_ROW = PSMCT32 ? (STRIDE_BYTES/4) : (STRIDE_BYTES/2);
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wire [RB_BITS-1:0] col_beat = pixel_x[RB_BITS+PXSH-1 -: RB_BITS];
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wire [3:0] col_lane = PSMCT32 ? {1'b0, pixel_x[2:0]} : pixel_x[3:0];
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logic [255:0] word_q; logic [3:0] lane_q; logic in_q;
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always_ff @(posedge video_clk) begin
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word_q <= disp_buf ? lb1[col_beat] : lb0[col_beat];
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lane_q <= col_lane;
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in_q <= in_window && (pixel_x < PX_PER_ROW) && (pixel_y < N_ROWS);
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end
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// PSMCT32 ABGR8888 (r=[7:0],g=[15:8],b=[23:16]) — matches gs_lpddr_scanout (frame-cache).
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wire [31:0] px32 = word_q[lane_q[2:0]*32 +: 32]; // 3-bit lane: always in-range (0..224)
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wire [7:0] r32 = px32[7:0], g32 = px32[15:8], b32 = px32[23:16];
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// PSMCT16 RGBA5551 5-bit lanes expanded to 8-bit.
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wire [15:0] px16 = word_q[lane_q*16 +: 16];
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wire [4:0] r5 = px16[4:0], g5 = px16[9:5], b5 = px16[14:10];
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assign r = !in_q ? 8'd0 : (PSMCT32 ? r32 : {r5, r5[4:2]});
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assign g = !in_q ? 8'd0 : (PSMCT32 ? g32 : {g5, g5[4:2]});
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assign b = !in_q ? 8'd0 : (PSMCT32 ? b32 : {b5, b5[4:2]});
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// ================= axi side (axi_clk) — row fill FSM =================
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// free-running prefetcher: fetch rows sequentially, staying <= disp_row+1 ahead.
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// disp_row crosses video->axi (slowly-changing; the +1 throttle tolerates a 1-off
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// transient). frame_start is edge-detected here to reset next_fetch every frame.
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logic [2:0] fs_sync_e;
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wire fs_edge_e = (fs_sync_e[2] != fs_sync_e[1]);
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logic [$clog2(N_ROWS):0] disp_row_s0, disp_row_e;
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logic [$clog2(N_ROWS):0] next_fetch; // next row to load (0..N_ROWS)
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typedef enum logic [1:0] { L_IDLE, L_AR, L_R } lstate_t;
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lstate_t lst;
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logic [$clog2(N_ROWS):0] cur_row;
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logic cur_buf;
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logic [RB_BITS:0] beat;
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logic fs_pending; // a vsync restart is pending; applied in L_IDLE (never mid-read)
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always_ff @(posedge axi_clk) begin
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if (!axi_rst_n) begin
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fs_sync_e <= 3'd0; disp_row_s0 <= '0; disp_row_e <= '0; next_fetch <= '0;
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lst <= L_IDLE; araddr <= '0; arvalid <= 1'b0; rready <= 1'b0;
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cur_row <= '0; cur_buf <= 1'b0; beat <= '0;
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line_valid <= 1'b0; rd_errs <= 32'd0; fs_pending <= 1'b0;
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end else begin
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fs_sync_e <= {fs_sync_e[1:0], frame_start};
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disp_row_s0 <= disp_row_v; // 2-FF sync of the display row
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disp_row_e <= disp_row_s0;
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// vsync: mark a prefetch restart. DEFER it to L_IDLE so an in-flight AXI
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// read is never aborted mid-handshake (which would deadlock the slave).
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if (fs_edge_e) fs_pending <= 1'b1;
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case (lst)
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L_IDLE: begin
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if (fs_pending) begin
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next_fetch <= '0; // restart prefetch sequence from row 0
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fs_pending <= 1'b0;
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end else if (enable && (next_fetch < N_ROWS) && (next_fetch <= disp_row_e + 1'b1)) begin
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cur_row <= next_fetch;
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cur_buf <= next_fetch[0];
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araddr <= FB_BASE + (next_fetch * STRIDE_BYTES);
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beat <= '0;
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arvalid <= 1'b1;
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lst <= L_AR;
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end
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end
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L_AR: begin
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if (arready) begin
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arvalid <= 1'b0;
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rready <= 1'b1;
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lst <= L_R;
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end
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end
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L_R: begin
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if (rvalid) begin
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if (cur_buf) lb1[beat[RB_BITS-1:0]] <= rdata;
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else lb0[beat[RB_BITS-1:0]] <= rdata;
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if (rresp != 2'b00) rd_errs <= rd_errs + 32'd1;
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rready <= 1'b0;
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if (beat == ROW_BEATS-1) begin
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line_valid <= 1'b1;
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next_fetch <= next_fetch + 1'b1; // advance prefetch (rows 0..next_fetch-1 loaded)
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lst <= L_IDLE;
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end else begin
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// next single-beat read of this row (arlen=0 each).
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beat <= beat + 1'b1;
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araddr <= araddr + 30'd32;
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arvalid <= 1'b1;
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lst <= L_AR;
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end
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end
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end
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default: lst <= L_IDLE;
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endcase
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end
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end
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// underflow (sticky, video domain): an in-window pixel for line pixel_y is read
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// before that row was prefetched. The axi side loads rows 0..next_fetch-1, so row
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// pixel_y is ready iff pixel_y < next_fetch. next_fetch crosses axi->video synced
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// (slowly-changing; a 1-off transient is harmless). Resets on vsync.
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logic [$clog2(N_ROWS):0] nf_s0, nf_v;
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logic underflow_v;
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always_ff @(posedge video_clk) begin
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nf_s0 <= next_fetch; nf_v <= nf_s0;
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if (!enable || fs_edge_v) underflow_v <= 1'b0;
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else if (in_window && (pixel_y < N_ROWS) && (($clog2(N_ROWS)+1)'(pixel_y) >= nf_v))
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underflow_v <= 1'b1;
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end
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assign underflow = underflow_v;
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endmodule
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