thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
174 lines
7.8 KiB
Systemverilog
174 lines
7.8 KiB
Systemverilog
// ============================================================================
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// gs_lpddr_scanout.sv (Ch320 Brick 1)
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//
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// LPDDR4B-backed scanout for the SMALL framebuffer demo (explicitly scoped to
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// a tiny frame — default 64x64 PSMCT16 = 8 KiB). Instead of ao486-style line
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// buffering/streaming, it copies the WHOLE framebuffer from LPDDR4B into a
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// small on-chip cache once per frame, then serves scanout pixels from the
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// cache. When the framebuffer grows past "tiny demo", revisit ao486's
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// vga_fb_ddr line-buffer approach.
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//
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// Pixel mapping is automatic: the GS writer mirrors BRAM VRAM byte-for-byte
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// into LPDDR4B, so cache[addr] == BRAM_VRAM[addr]. We index the cache by the
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// PCRTC's own `vram_read_addr`, so the decoded pixel is identical to the BRAM
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// scanout pixel for the same raster position — the video-source mux is seamless
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// regardless of swizzle/MAG.
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//
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// Two clock domains:
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// axi_clk (emif_clk, ~310 MHz) — fill the cache from LPDDR4B over AXI4
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// video_clk (design_clk) — index the cache by vram_read_addr -> r/g/b
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//
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// Fill happens on frame_start (vsync) and completes during vblank (256 single
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// beats ~ 1 us); scanout reads the stable cache during the active region. The
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// read channel is shared with the Ch319 read-probe via an external arbiter.
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// ============================================================================
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`timescale 1ns/1ps
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module gs_lpddr_scanout #(
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parameter [29:0] FB_BASE = 30'd0, // LPDDR byte base to FETCH the framebuffer from
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parameter int CACHE_BEATS = 256, // 256 * 32 B = 8 KiB = 64x64 PSMCT16
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// Ch324 — the LPDDR fetch base (FB_BASE) and the PCRTC vram_read_addr base can DIFFER:
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// the spill framebuffer lives at COLOR_SPILL_BASE in LPDDR but the PCRTC addresses it
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// BRAM-relative (0-based). VRAM_BASE is the vram_read_addr origin (defaults to FB_BASE
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// for the Ch320/321 mirror case where they coincide).
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parameter [29:0] VRAM_BASE = FB_BASE,
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// Ch324 — pixel format: 0 = PSMCT16 (RGBA5551, 16 px/beat), 1 = PSMCT32 (ABGR, 8 px/beat).
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parameter bit PSMCT32 = 1'b0
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)(
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// ---- AXI read clock domain (emif_clk) ----
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input logic axi_clk,
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input logic axi_rst_n,
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input logic enable, // 1 = refill the cache on frame_start
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input logic frame_start, // video-domain pulse/level (vsync); synced internally
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// ---- video clock domain (design_clk) ----
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input logic video_clk,
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input logic [31:0] vram_read_addr,
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output logic [7:0] r,
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output logic [7:0] g,
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output logic [7:0] b,
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// ---- status (axi_clk domain; the bridge syncs these) ----
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output logic cache_valid, // a full frame has been loaded
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output logic [31:0] rd_beats, // beats read (cumulative)
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output logic [31:0] rd_errs, // non-OKAY read responses (cumulative)
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// ---- AXI4 read channel to the EMIF user port (axi_clk, 256-bit) ----
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output logic [29:0] araddr,
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output logic [1:0] arburst,
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output logic [6:0] arid,
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output logic [7:0] arlen,
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output logic [2:0] arsize,
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output logic arvalid,
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input logic arready,
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input logic [255:0] rdata,
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input logic [1:0] rresp,
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input logic rlast,
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input logic rvalid,
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output logic rready
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);
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localparam int BEAT_BITS = $clog2(CACHE_BEATS); // 8 for 256
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localparam int FB_SPAN = CACHE_BEATS * 32; // 8192 bytes
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assign arburst = 2'b01; // INCR
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assign arid = 7'd2; // distinct from writer (0) and read-probe (1)
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assign arlen = 8'd0; // single beat
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assign arsize = 3'b101; // 32 bytes
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// Frame cache: one 256-bit word per 32-byte beat.
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logic [255:0] cache [0:CACHE_BEATS-1];
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// ---------------- fill side (axi_clk) ----------------
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logic [2:0] fs_sync;
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wire fs_edge = (fs_sync[2] != fs_sync[1]);
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typedef enum logic [1:0] { F_IDLE, F_AR, F_R } fstate_t;
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fstate_t fst;
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logic [BEAT_BITS:0] beat; // 0..CACHE_BEATS (extra bit for the terminal compare)
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always_ff @(posedge axi_clk) begin
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if (!axi_rst_n) begin
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fs_sync <= 3'd0; fst <= F_IDLE; beat <= '0;
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araddr <= '0; arvalid <= 1'b0; rready <= 1'b0;
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cache_valid <= 1'b0; rd_beats <= 32'd0; rd_errs <= 32'd0;
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end else begin
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fs_sync <= {fs_sync[1:0], frame_start};
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case (fst)
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F_IDLE: begin
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if (fs_edge && enable) begin
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beat <= '0;
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cache_valid <= 1'b0;
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araddr <= FB_BASE;
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arvalid <= 1'b1;
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fst <= F_AR;
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end
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end
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F_AR: begin
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if (arready) begin
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arvalid <= 1'b0;
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rready <= 1'b1;
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fst <= F_R;
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end
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end
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F_R: begin
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if (rvalid) begin
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cache[beat[BEAT_BITS-1:0]] <= rdata;
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rready <= 1'b0;
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rd_beats <= rd_beats + 32'd1;
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if (rresp != 2'b00) rd_errs <= rd_errs + 32'd1;
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if (beat == CACHE_BEATS-1) begin
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cache_valid <= 1'b1;
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fst <= F_IDLE;
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end else begin
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beat <= beat + 1'b1;
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araddr <= FB_BASE + (({{(30-BEAT_BITS-1){1'b0}}, (beat + 1'b1)}) << 5);
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arvalid <= 1'b1;
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fst <= F_AR;
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end
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end
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end
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default: fst <= F_IDLE;
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endcase
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end
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end
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// ---------------- scanout side (video_clk) ----------------
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// Byte offset of the requested pixel within the framebuffer (vram_read_addr is BRAM-relative
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// = VRAM_BASE-origin; the cache holds the SAME bytes fetched from FB_BASE in LPDDR).
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wire [31:0] off = vram_read_addr - {2'b00, VRAM_BASE};
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wire [BEAT_BITS-1:0] beat_ix = off[BEAT_BITS+4 -: BEAT_BITS]; // off>>5, low BEAT_BITS
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wire [3:0] hw_sel = off[4:1]; // PSMCT16: 16 halfwords / beat
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wire [2:0] w_sel = off[4:2]; // PSMCT32: 8 words / beat
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wire in_range = cache_valid
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&& (vram_read_addr >= {2'b00, VRAM_BASE})
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&& (off < FB_SPAN);
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// Registered (sync-read) cache lookup — 1-cycle latency to match the PCRTC's
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// VRAM_SYNC_READ pixel timing so the muxed output aligns with PCRTC de/sync.
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// Split the array-index and the part-select across the register boundary
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// (chained index+part-select in one expr trips iverilog-12).
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logic [255:0] word_q;
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logic [3:0] hw_q;
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logic [2:0] w_q;
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logic in_range_q;
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always_ff @(posedge video_clk) begin
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word_q <= cache[beat_ix];
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hw_q <= hw_sel;
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w_q <= w_sel;
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in_range_q <= in_range;
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end
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wire [15:0] px16_q = word_q[hw_q*16 +: 16];
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wire [31:0] px32_q = word_q[w_q*32 +: 32];
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// PSMCT16 (RGBA5551): R[4:0] G[9:5] B[14:10], 5->8 by bit-replication ({c5,c5[4:2]}).
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wire [4:0] r5 = px16_q[4:0];
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wire [4:0] g5 = px16_q[9:5];
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wire [4:0] b5 = px16_q[14:10];
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wire [7:0] r16 = {r5, r5[4:2]}, g16 = {g5, g5[4:2]}, b16 = {b5, b5[4:2]};
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// PSMCT32 (ABGR8888): R[7:0] G[15:8] B[23:16] (A discarded) — identical decode to gs_pcrtc.
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wire [7:0] r32 = px32_q[7:0], g32 = px32_q[15:8], b32 = px32_q[23:16];
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assign r = !in_range_q ? 8'd0 : (PSMCT32 ? r32 : r16);
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assign g = !in_range_q ? 8'd0 : (PSMCT32 ? g32 : g16);
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assign b = !in_range_q ? 8'd0 : (PSMCT32 ? b32 : b16);
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endmodule
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