thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
156 lines
7.7 KiB
Systemverilog
156 lines
7.7 KiB
Systemverilog
// ============================================================================
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// gs_lpddr_rd_arb.sv (Ch320 Brick 2; Ch322 extended 2:1 -> 3:1)
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//
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// 3:1 AXI4 READ-channel arbiter for the FPGA-private LPDDR4B EMIF user port.
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// Lets the Ch320 scanout reader (port 0, priority), the Ch319 HPS read-probe
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// (port 1), and the Ch322 texture-cache fill (port 2, lowest priority) share the
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// single EMIF read channel. The write channel is arbitrated separately
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// (gs_lpddr_wr_arb). Adapted from ao486 axi_fb_arbiter (read half): grant held
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// for a whole transaction, watchdog force-release, idle-drain rready so a late
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// response can't wedge the bus. All single-clock (emif_clk).
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//
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// Port 2 (texture fill) is a ONE-SHOT prefill before raster; scanout (port 0)
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// keeps priority. Leave s2_* unconnected (arvalid=0) on builds without a texture
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// cache — the arbiter is then bit-for-bit the old 2:1 behavior.
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//
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// Single-beat transactions (ARLEN=0), so a response completes on rvalid&rlast.
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// ============================================================================
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`timescale 1ns/1ps
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module gs_lpddr_rd_arb (
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input logic clk,
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input logic rst_n,
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// ---- Port 0: scanout reader (priority) ----
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input logic [29:0] s0_araddr,
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input logic [1:0] s0_arburst,
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input logic [6:0] s0_arid,
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input logic [7:0] s0_arlen,
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input logic [2:0] s0_arsize,
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input logic s0_arvalid,
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output logic s0_arready,
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output logic [255:0] s0_rdata,
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output logic [1:0] s0_rresp,
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output logic s0_rlast,
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output logic s0_rvalid,
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input logic s0_rready,
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// ---- Port 1: HPS read-probe ----
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input logic [29:0] s1_araddr,
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input logic [1:0] s1_arburst,
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input logic [6:0] s1_arid,
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input logic [7:0] s1_arlen,
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input logic [2:0] s1_arsize,
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input logic s1_arvalid,
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output logic s1_arready,
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output logic [255:0] s1_rdata,
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output logic [1:0] s1_rresp,
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output logic s1_rlast,
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output logic s1_rvalid,
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input logic s1_rready,
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// ---- Port 2: texture-cache fill (lowest priority; Ch322) ----
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input logic [29:0] s2_araddr,
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input logic [1:0] s2_arburst,
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input logic [6:0] s2_arid,
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input logic [7:0] s2_arlen,
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input logic [2:0] s2_arsize,
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input logic s2_arvalid,
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output logic s2_arready,
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output logic [255:0] s2_rdata,
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output logic [1:0] s2_rresp,
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output logic s2_rlast,
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output logic s2_rvalid,
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input logic s2_rready,
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// ---- Port 3: tile-reload fill (Ch323; priority ABOVE probe/texfill, below scanout) ----
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input logic [29:0] s3_araddr,
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input logic [1:0] s3_arburst,
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input logic [6:0] s3_arid,
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input logic [7:0] s3_arlen,
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input logic [2:0] s3_arsize,
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input logic s3_arvalid,
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output logic s3_arready,
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output logic [255:0] s3_rdata,
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output logic [1:0] s3_rresp,
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output logic s3_rlast,
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output logic s3_rvalid,
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input logic s3_rready,
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// ---- Master out: EMIF read channel ----
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output logic [29:0] m_araddr,
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output logic [1:0] m_arburst,
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output logic [6:0] m_arid,
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output logic [7:0] m_arlen,
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output logic [2:0] m_arsize,
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output logic m_arvalid,
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input logic m_arready,
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input logic [255:0] m_rdata,
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input logic [1:0] m_rresp,
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input logic m_rlast,
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input logic m_rvalid,
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output logic m_rready
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);
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// grant: 0=idle, 1=s0 scanout, 2=s1 probe, 3=s2 texfill, 4=s3 tile-reload.
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// EXPLICIT priority (Ch323, Codex): scanout > tile_reload > probe > texture_fill — i.e.
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// s0 > s3 > s1 > s2. Render-display (scanout) highest; the render-prep tile reload above
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// the debug read-probe so a debug read can never starve a render's Z/color reload.
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reg [2:0] grant;
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// Ch326 — NON-ABORTING ARBITER (Codex). The OLD design force-released the grant on a
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// watchdog (was 2^10 ~3.3us) at ANY point in the transaction; when it fired AFTER the AR had
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// handshaked, the idle state's m_rready=1 drained the now-orphaned response and the requester
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// hung forever (blank HDMI + stuck HPS probe under the always-on-scanout traffic). Once
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// m_arvalid && m_arready, the read is COMMITTED and its response BELONGS to that requester —
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// there is no AXI-legal way to abandon it. So: the watchdog gates ONLY the pre-AR wait (no
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// transaction committed yet — safe to drop); after AR acceptance the grant is held until
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// m_rvalid && m_rlast && selected_rready, regardless of how long the read takes.
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reg ar_done; // AR handshake captured for the active grant -> never abort past here
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reg [21:0] watchdog; // pre-AR only (waiting for m_arready); ~6.7 ms @ 310 MHz dead-bus backstop
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wire wd_expired = watchdog[21];
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wire sel_rready = (grant==3'd1)?s0_rready:(grant==3'd2)?s1_rready:
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(grant==3'd3)?s2_rready:(grant==3'd4)?s3_rready:1'b1;
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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grant <= 3'd0; ar_done <= 1'b0; watchdog <= '0;
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end else if (grant == 3'd0) begin
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ar_done <= 1'b0; watchdog <= '0;
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if (s0_arvalid) grant <= 3'd1; // scanout (highest)
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else if (s3_arvalid) grant <= 3'd4; // tile reload (render-prep)
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else if (s1_arvalid) grant <= 3'd2; // read probe (debug)
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else if (s2_arvalid) grant <= 3'd3; // texture fill (lowest)
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end else begin
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if (m_arvalid && m_arready) ar_done <= 1'b1; // AR accepted -> COMMITTED
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if (m_rvalid && m_rlast && sel_rready) begin
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grant <= 3'd0; ar_done <= 1'b0; watchdog <= '0; // response delivered -> release
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end else if (!ar_done) begin // still waiting for AR (nothing owed)
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if (wd_expired) begin grant <= 3'd0; ar_done <= 1'b0; watchdog <= '0; end
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else watchdog <= watchdog + 22'd1;
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end
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// ar_done && response not yet complete: HOLD the grant, never abort.
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end
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end
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// AR mux
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assign m_araddr = (grant==3'd4)?s3_araddr :(grant==3'd3)?s2_araddr :(grant==3'd2)?s1_araddr :s0_araddr;
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assign m_arburst = (grant==3'd4)?s3_arburst:(grant==3'd3)?s2_arburst:(grant==3'd2)?s1_arburst:s0_arburst;
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assign m_arid = (grant==3'd4)?s3_arid :(grant==3'd3)?s2_arid :(grant==3'd2)?s1_arid :s0_arid;
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assign m_arlen = (grant==3'd4)?s3_arlen :(grant==3'd3)?s2_arlen :(grant==3'd2)?s1_arlen :s0_arlen;
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assign m_arsize = (grant==3'd4)?s3_arsize :(grant==3'd3)?s2_arsize :(grant==3'd2)?s1_arsize :s0_arsize;
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assign m_arvalid = (grant==3'd1)?s0_arvalid:(grant==3'd2)?s1_arvalid:(grant==3'd3)?s2_arvalid:(grant==3'd4)?s3_arvalid:1'b0;
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assign s0_arready = (grant==3'd1)?m_arready:1'b0;
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assign s1_arready = (grant==3'd2)?m_arready:1'b0;
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assign s2_arready = (grant==3'd3)?m_arready:1'b0;
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assign s3_arready = (grant==3'd4)?m_arready:1'b0;
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// R demux (idle: rready=1 drains any stale/late response)
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assign s0_rdata=m_rdata; assign s1_rdata=m_rdata; assign s2_rdata=m_rdata; assign s3_rdata=m_rdata;
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assign s0_rresp=m_rresp; assign s1_rresp=m_rresp; assign s2_rresp=m_rresp; assign s3_rresp=m_rresp;
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assign s0_rlast=m_rlast; assign s1_rlast=m_rlast; assign s2_rlast=m_rlast; assign s3_rlast=m_rlast;
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assign s0_rvalid = (grant==3'd1)?m_rvalid:1'b0;
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assign s1_rvalid = (grant==3'd2)?m_rvalid:1'b0;
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assign s2_rvalid = (grant==3'd3)?m_rvalid:1'b0;
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assign s3_rvalid = (grant==3'd4)?m_rvalid:1'b0;
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assign m_rready = (grant==3'd1)?s0_rready:(grant==3'd2)?s1_rready:(grant==3'd3)?s2_rready:(grant==3'd4)?s3_rready:1'b1;
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endmodule
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