thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
249 lines
12 KiB
Systemverilog
249 lines
12 KiB
Systemverilog
// retroDE_ps2 — gs_lpddr_axi_master (Ch318)
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//
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// HARDWARE-facing wrapper that takes the PSMCT16 tile-FLUSH pixel stream (GS clock)
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// and writes it to real LPDDR over the qsys f2sdram AXI4 port (f2sdram clock). It
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// does NOT modify the proven gs_lpddr_fb_writer (the Ch317 sim model) — it is a
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// sibling hardware path with the same input stream.
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//
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// Pipeline (per the Ch318 directive):
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// GS clock : PACKER — accumulate 16 PSMCT16 pixels of a tile-row into one 256-bit
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// (32-byte) beat {addr, data, strb}. A tile-row is exactly 16 px on a
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// 32-byte-aligned line, so a beat completes naturally on its 16th px
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// (no dangling partial beat). On completion, push to the async FIFO.
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// async FIFO: gray-code CDC, carries {addr[31:0], data[255:0], strb[31:0]} (320b).
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// f2sdram : AXI burst FSM — pop a beat and issue a single-beat INCR write
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// (AWSIZE=5 = 32 B, AWLEN=0, AWBURST=INCR, full per-byte WSTRB, never
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// crossing a 4 KiB boundary since each beat is one 32-byte line). AW
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// then W then B, all with backpressure (await ready/valid).
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//
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// Address: awaddr = FB_BASE + packet_addr (packet_addr is the FB-relative byte addr
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// from raster_pixel_fb_addr_q). FB_BASE must point at a LINUX-SAFE reserved LPDDR
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// region before any board run — the qsys aperture proves fabric CAN address SDRAM,
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// not which physical range is safe to scribble on (Ch318 board gate).
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//
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// Counters (f2sdram domain, TB/status readable): beats, bursts, bresp_err, fifo
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// overflow, done-ish (idle && fifo empty). enable=0 → fully inert.
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module gs_lpddr_axi_master #(
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parameter int FIFO_DEPTH = 16
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) (
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// GS clock domain — flush pixel stream
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input logic gs_clk,
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input logic gs_rst_n,
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input logic enable,
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// ---- RUNTIME controls (driven by the HPS bridge register, axi_clk domain) ----
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// arm: HARD SAFETY GATE — no AXI write can issue unless high. Defaults LOW at the
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// bridge register, so the booted core is inert until the HPS explicitly arms it.
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// Synced into gs_clk for the packer; used directly in the axi_clk FSM.
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input logic arm,
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// canary: when high, write ONLY the offset-0 beat (the 32-byte top-of-frame line)
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// and discard all others — a deterministic, blast-radius-limited first test.
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input logic canary,
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// fb_base: LPDDR byte base address for the framebuffer (e.g. 0x8000_0000). awaddr
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// = fb_base + frame-relative offset. Runtime so a wrong base is re-targetable
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// without a rebuild.
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input logic [31:0] fb_base,
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// Ch352 CDC (Codex) — {arm,canary,fb_base} arrive RAW from the HPS bridge (CLOCK2_50), NOT axi_clk as the
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// legacy comment above implies. ctrl_commit is a TOGGLE the bridge flips on any control write; we sync it
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// into axi_clk and latch the controls on its edge, so the multi-bit fb_base crosses COHERENTLY (the CDC
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// lives here, at the receiving boundary, so no caller can supply raw controls into the AW path).
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input logic ctrl_commit,
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input logic px_emit,
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input logic [31:0] px_addr, // FB-relative byte address (raster_pixel_fb_addr_q)
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input logic [15:0] px_pix16,
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// f2sdram (LPDDR AXI) clock domain
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input logic axi_clk,
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input logic axi_rst_n,
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// AXI4 write-address
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output logic [31:0] awaddr,
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output logic [7:0] awlen,
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output logic [2:0] awsize,
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output logic [1:0] awburst,
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output logic [4:0] awid,
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output logic awvalid,
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input logic awready,
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// AXI4 write-data
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output logic [255:0] wdata,
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output logic [31:0] wstrb,
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output logic wlast,
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output logic wvalid,
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input logic wready,
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// AXI4 write-response
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input logic bvalid,
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output logic bready,
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input logic [1:0] bresp,
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// status / counters (axi domain)
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output logic [31:0] beats_written,
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output logic [31:0] bursts_issued,
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output logic [31:0] bresp_err_count,
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output logic [31:0] fifo_overflow_count,
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output logic idle
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);
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localparam int PW = 320; // {addr[31:0], data[255:0], strb[31:0]}
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// ============================ GS-clock PACKER ============================
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logic [31:0] cur_addr;
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logic [255:0] cur_data;
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logic [31:0] cur_strb;
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logic has_data;
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logic fifo_wr;
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logic [PW-1:0] fifo_wdata;
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logic fifo_wfull;
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// Ch352 — axi_clk control snapshot: sync the bridge commit toggle and latch {arm,canary,fb_base} on its
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// edge. Init to the bridge's SAFE defaults (arm=0, canary=1, fb_base=0x8000_0000) so the booted core is
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// inert until the HPS arms it, even before the first commit. All axi_clk uses + the gs_clk arm-sync read
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// these coherent latched copies instead of the raw bridge buses.
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logic [2:0] commit_sync;
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logic arm_axi, canary_axi;
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logic [31:0] fb_base_axi;
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always_ff @(posedge axi_clk or negedge axi_rst_n) begin
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if (!axi_rst_n) begin
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commit_sync <= 3'd0; arm_axi <= 1'b0; canary_axi <= 1'b1; fb_base_axi <= 32'h8000_0000;
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end else begin
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commit_sync <= {commit_sync[1:0], ctrl_commit};
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if (commit_sync[2] != commit_sync[1]) begin // commit edge: bridge buses are stable, latch them
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arm_axi <= arm;
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canary_axi <= canary;
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fb_base_axi <= fb_base;
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end
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end
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end
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// High for the one cycle the snapshot updates. Admission is blocked then so the FSM never consumes a beat
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// straddling a config change (old base/arm on the pop cycle, new on the next).
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wire commit_edge = (commit_sync[2] != commit_sync[1]);
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// arm crosses from axi_clk into gs_clk — 2-FF synchronizer (from the COHERENT latched arm).
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logic arm_s1, arm_gs;
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always_ff @(posedge gs_clk or negedge gs_rst_n) begin
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if (!gs_rst_n) begin arm_s1 <= 1'b0; arm_gs <= 1'b0; end
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else begin arm_s1 <= arm_axi; arm_gs <= arm_s1; end
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end
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always_ff @(posedge gs_clk or negedge gs_rst_n) begin
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if (!gs_rst_n) begin
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cur_addr <= '0; cur_data <= '0; cur_strb <= '0; has_data <= 1'b0;
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fifo_wr <= 1'b0; fifo_wdata <= '0; fifo_overflow_count <= '0;
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end else begin
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fifo_wr <= 1'b0;
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if (enable && arm_gs && px_emit) begin // gate: no accumulation until armed
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logic [31:0] abeat;
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logic [3:0] lane; // 0..15 (which 16-bit lane)
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logic [255:0] nd;
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logic [31:0] ns;
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abeat = {px_addr[31:5], 5'd0};
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lane = px_addr[4:1];
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if (has_data && (abeat != cur_addr)) begin
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// line changed before the previous beat filled — flush it, restart
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fifo_wdata <= {cur_addr, cur_data, cur_strb};
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fifo_wr <= 1'b1;
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cur_addr <= abeat;
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cur_data <= (256'(px_pix16) << ({28'd0, lane} * 16));
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cur_strb <= (32'd3 << ({28'd0, lane} * 2));
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has_data <= 1'b1;
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end else begin
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nd = has_data ? cur_data : 256'd0;
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ns = has_data ? cur_strb : 32'd0;
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nd[ ({28'd0, lane} * 16) +: 16 ] = px_pix16;
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ns[ ({28'd0, lane} * 2) +: 2 ] = 2'b11;
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if (&ns) begin
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// beat complete (all 16 lanes) — flush, beat consumed
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fifo_wdata <= {abeat, nd, ns};
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fifo_wr <= 1'b1;
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has_data <= 1'b0;
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end else begin
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cur_addr <= abeat;
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cur_data <= nd;
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cur_strb <= ns;
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has_data <= 1'b1;
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end
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end
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end
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// overflow witness: a push attempt while the FIFO is full (must stay 0)
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if (fifo_wr && fifo_wfull)
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fifo_overflow_count <= fifo_overflow_count + 32'd1;
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end
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end
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// ============================ async FIFO (CDC) ============================
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logic [PW-1:0] fifo_rdata;
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logic fifo_rempty;
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logic fifo_rd;
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// Ch323 — reset BOTH FIFO pointers from the STABLE axi_rst_n (assert async, deassert
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// synced into gs_clk). gs_rst_n (= core reset) toggles on every CORE_CTRL re-render; if
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// the write pointer reset followed it while the read pointer stayed, the gray pointers
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// would desync → FIFO corruption (phantom beats, no commit). Same fix as gs_z_flush_writer.
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reg [1:0] wrst_sync;
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always_ff @(posedge gs_clk or negedge axi_rst_n) begin
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if (!axi_rst_n) wrst_sync <= 2'b00;
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else wrst_sync <= {wrst_sync[0], 1'b1};
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end
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wire fifo_wrst_n = wrst_sync[1];
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gs_async_fifo #(.WIDTH(PW), .DEPTH(FIFO_DEPTH)) u_fifo (
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.wclk(gs_clk), .wrst_n(fifo_wrst_n), .wr(fifo_wr && !fifo_wfull), .wdata(fifo_wdata), .wfull(fifo_wfull),
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.rclk(axi_clk), .rrst_n(axi_rst_n), .rd(fifo_rd), .rdata(fifo_rdata), .rempty(fifo_rempty)
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);
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// ============================ f2sdram-clock AXI FSM ============================
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localparam logic [1:0] S_IDLE=2'd0, S_AW=2'd1, S_W=2'd2, S_B=2'd3;
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logic [1:0] state;
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logic [31:0] beat_addr;
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logic [255:0] beat_data;
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logic [31:0] beat_strb;
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logic [31:0] awaddr_q; // Ch352 — full AW address latched at admission, held stable AW->W->B
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assign awsize = 3'd5; // 32 bytes/beat (256-bit)
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assign awburst = 2'b01; // INCR
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assign awid = 5'd0;
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assign awlen = 8'd0; // single beat per line (tile-rows aren't contiguous)
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assign awaddr = awaddr_q; // Ch352 — latched at admission; STABLE through AW->W->B (AXI requires it)
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assign wdata = beat_data;
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assign wstrb = beat_strb;
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assign wlast = 1'b1; // 1-beat burst
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// Ch352 — AXI transaction stability (Codex): arm_axi/commit gate ADMISSION ONLY (S_IDLE pop). Once a beat is
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// admitted, awvalid/wvalid are driven by STATE alone and run to completion, so a later arm-deassert or a
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// fb_base commit can never drop VALID mid-handshake or move awaddr while AWVALID && !AWREADY.
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assign awvalid = (state == S_AW);
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assign wvalid = (state == S_W);
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assign bready = (state == S_B);
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assign fifo_rd = (state == S_IDLE) && !fifo_rempty && arm_axi && !commit_edge;
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assign idle = (state == S_IDLE) && fifo_rempty;
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always_ff @(posedge axi_clk or negedge axi_rst_n) begin
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if (!axi_rst_n) begin
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state <= S_IDLE; beat_addr <= '0; beat_data <= '0; beat_strb <= '0; awaddr_q <= '0;
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beats_written <= '0; bursts_issued <= '0; bresp_err_count <= '0;
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end else begin
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unique case (state)
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S_IDLE: if (!fifo_rempty && arm_axi && !commit_edge) begin
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beat_addr <= fifo_rdata[319:288]; // {addr, data, strb}
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beat_data <= fifo_rdata[287:32];
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beat_strb <= fifo_rdata[31:0];
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awaddr_q <= fb_base_axi + fifo_rdata[319:288]; // latch FULL AW addr from the STABLE base
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// canary: write ONLY the offset-0 (top-of-frame) 32-byte line;
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// discard every other beat (fifo_rd still pops it this cycle).
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if (canary_axi && (fifo_rdata[319:288] != 32'd0))
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state <= S_IDLE;
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else
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state <= S_AW;
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end
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S_AW: if (awready) begin
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bursts_issued <= bursts_issued + 32'd1;
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state <= S_W;
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end
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S_W: if (wready) begin
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beats_written <= beats_written + 32'd1;
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state <= S_B;
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end
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default: if (bvalid) begin // S_B
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if (bresp != 2'b00) bresp_err_count <= bresp_err_count + 32'd1;
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state <= S_IDLE;
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end
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endcase
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end
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end
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endmodule : gs_lpddr_axi_master
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