thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
89 lines
4.4 KiB
Systemverilog
89 lines
4.4 KiB
Systemverilog
// ============================================================================
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// gs_grad_divider.sv (Ch352 — sequential signed divider for the triangle-setup gradient solve)
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//
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// Replaces the single combinational `grad_num_q[grad_step] / grad_det_q` in gs_stub. That combinational
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// divider is a ~6700-cell, ~100ns cone at the 25MHz design clock — the worst setup path, and (the real lesson)
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// it CANNOT be covered by any SDC timing exception: both a multicycle and a false_path made the Quartus fitter
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// grind on its cone indefinitely (Place stuck <1% for hours). A sequential divider has REGISTERED iterations and
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// no combinational cone, so every internal path is an ordinary single-cycle path that closes timing normally —
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// no exception needed, no grind.
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//
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// BIT-EXACT to SystemVerilog signed `/`:
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// * truncation toward zero (divide magnitudes, then apply the XOR-of-signs);
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// * den == 0 -> quotient 0 (matches the gs_stub `if (grad_det_q==0) grad_quo=0` guard).
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// Restoring division of the W-bit magnitudes (W iterations), one iteration per clock.
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//
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// Handshake: pulse `start` with num/den stable -> `busy` high for the solve -> `done` pulses for one cycle
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// with `quo` valid (and stays valid until the next start). The gs_stub gradient FSM waits on `done`.
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// ============================================================================
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`timescale 1ns/1ps
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module gs_grad_divider #(
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parameter int W = 56 // operand width (gs_stub: grad_num_q / sign-extended grad_det)
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)(
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input logic clk,
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input logic rst_n,
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input logic start, // pulse: begin a divide (num/den sampled this cycle)
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input logic signed [W-1:0] num,
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input logic signed [W-1:0] den,
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output logic signed [W-1:0] quo, // truncate-toward-zero quotient (== $signed(num)/$signed(den))
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output logic busy,
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output logic done // 1-cycle pulse when quo is valid
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);
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localparam int CW = $clog2(W+1);
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// magnitude + sign capture
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function automatic logic [W-1:0] absval(input logic signed [W-1:0] v);
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absval = v[W-1] ? (~v + 1'b1) : v; // |v| (the most-negative wraps to 2^(W-1), which fits unsigned W)
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endfunction
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logic [W:0] rem; // remainder, W+1 bits for the compare/subtract
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logic [W-1:0] qbuild; // quotient under construction (also shifts the dividend out of its top)
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logic [W-1:0] den_mag; // |den|
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logic qsign; // result sign = num_sign ^ den_sign
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logic [CW-1:0] iter;
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logic run;
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// one restoring step: bring the next dividend bit into rem, conditionally subtract |den|.
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wire [W:0] rem_sh = {rem[W-1:0], qbuild[W-1]}; // rem<<1 | dividend MSB
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wire sub_ok = (rem_sh >= {1'b0, den_mag});
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wire [W:0] rem_nxt = sub_ok ? (rem_sh - {1'b0, den_mag}) : rem_sh;
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always_ff @(posedge clk or negedge rst_n) begin
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if (!rst_n) begin
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rem <= '0; qbuild <= '0; den_mag <= '0; qsign <= 1'b0; iter <= '0;
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run <= 1'b0; busy <= 1'b0; done <= 1'b0; quo <= '0;
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end else begin
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done <= 1'b0;
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if (start && !busy) begin
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if (den == '0) begin
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// den == 0 -> quotient 0 (matches the gs_stub guard), available next cycle
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quo <= '0;
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done <= 1'b1;
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busy <= 1'b0;
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run <= 1'b0;
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end else begin
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rem <= '0;
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qbuild <= absval(num);
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den_mag <= absval(den);
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qsign <= num[W-1] ^ den[W-1];
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iter <= CW'(W);
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run <= 1'b1;
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busy <= 1'b1;
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end
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end else if (run) begin
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rem <= rem_nxt;
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qbuild <= {qbuild[W-2:0], sub_ok}; // shift dividend out, shift quotient bit in
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iter <= iter - 1'b1;
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if (iter == CW'(1)) begin
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// final iteration: qbuild now holds the W-bit magnitude quotient -> apply sign
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run <= 1'b0;
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busy <= 1'b0;
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done <= 1'b1;
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quo <= qsign ? (~{qbuild[W-2:0], sub_ok} + 1'b1) : {qbuild[W-2:0], sub_ok};
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end
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end
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end
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end
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endmodule
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