thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
90 lines
4.0 KiB
Systemverilog
90 lines
4.0 KiB
Systemverilog
// retroDE_ps2 — gs_async_fifo (Ch318)
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//
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// Generic dual-clock (asynchronous) FIFO with gray-code pointers and 2-FF pointer
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// synchronizers — the standard CDC-safe ring buffer. Used by gs_lpddr_axi_master to
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// cross 256-bit framebuffer-row packets {addr,data,strb} from the GS clock domain to
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// the f2sdram (LPDDR AXI) clock domain. Both domains are treated as GENUINELY async
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// even when nominally the same frequency (GS = PLL design_clk; f2sdram = raw board
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// clock), per the Ch318 directive.
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//
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// DEPTH must be a power of two. `wr`/`rd` are single-cycle handshakes gated by
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// !full / !empty. Standard caveats: do NOT assert wr when full or rd when empty
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// (the wrapper gates both). One-deep gray pointers, single 2-FF synchronizer each
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// way — adequate for the modest packet rate (one 32-byte beat per 16 flushed pixels).
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module gs_async_fifo #(
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parameter int WIDTH = 320, // {addr[31:0], data[255:0], strb[31:0]}
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parameter int DEPTH = 16 // power of two
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) (
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// write domain
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input logic wclk,
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input logic wrst_n,
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input logic wr,
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input logic [WIDTH-1:0] wdata,
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output logic wfull,
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// read domain
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input logic rclk,
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input logic rrst_n,
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input logic rd,
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output logic [WIDTH-1:0] rdata,
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output logic rempty
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);
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localparam int AW = $clog2(DEPTH);
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logic [WIDTH-1:0] mem [0:DEPTH-1];
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// ---- binary + gray pointers (one extra MSB for full/empty disambiguation) ----
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logic [AW:0] wbin, wgray, wbin_nxt, wgray_nxt;
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logic wfull_nxt; // Ch352 — combinational next-value for the now-REGISTERED wfull
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logic [AW:0] rbin, rgray, rbin_nxt, rgray_nxt;
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// synchronized opposite-domain gray pointers (2-FF)
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logic [AW:0] rgray_s1, rgray_s2; // read gray -> write domain
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logic [AW:0] wgray_s1, wgray_s2; // write gray -> read domain
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function automatic logic [AW:0] bin2gray(input logic [AW:0] b);
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bin2gray = b ^ (b >> 1);
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endfunction
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// ---------------- write domain ----------------
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assign wbin_nxt = wbin + (wr && !wfull);
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assign wgray_nxt = bin2gray(wbin_nxt);
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// full: next write gray == read gray with top two bits inverted. Ch352 — wfull is now a REGISTERED flag
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// (Cummings canonical). The previous `assign wfull = (wgray_nxt == ...)` was combinational, and since
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// wgray_nxt <- wbin_nxt <- wfull, it formed a wbin_nxt->wgray_nxt->wfull->wbin_nxt COMBINATIONAL LOOP that
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// Quartus reports and that made Place churn. Registering it breaks the loop with no overflow-behavior change:
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// wfull still asserts the cycle after the filling write (full is computed from wgray_nxt = the pointer AFTER
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// the current write), so the (DEPTH+1)th write is still blocked. rempty is intentionally left unchanged.
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assign wfull_nxt = (wgray_nxt == {~rgray_s2[AW:AW-1], rgray_s2[AW-2:0]});
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always_ff @(posedge wclk or negedge wrst_n) begin
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if (!wrst_n) begin
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wbin <= '0; wgray <= '0; wfull <= 1'b0;
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rgray_s1 <= '0; rgray_s2 <= '0;
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end else begin
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wbin <= wbin_nxt;
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wgray <= wgray_nxt;
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wfull <= wfull_nxt;
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rgray_s1 <= rgray; // sync read gray into write domain
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rgray_s2 <= rgray_s1;
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end
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end
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always_ff @(posedge wclk) if (wr && !wfull) mem[wbin[AW-1:0]] <= wdata;
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// ---------------- read domain ----------------
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assign rbin_nxt = rbin + (rd && !rempty);
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assign rgray_nxt = bin2gray(rbin_nxt);
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always_ff @(posedge rclk or negedge rrst_n) begin
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if (!rrst_n) begin
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rbin <= '0; rgray <= '0;
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wgray_s1 <= '0; wgray_s2 <= '0;
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end else begin
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rbin <= rbin_nxt;
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rgray <= rgray_nxt;
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wgray_s1 <= wgray; // sync write gray into read domain
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wgray_s2 <= wgray_s1;
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end
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end
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assign rdata = mem[rbin[AW-1:0]];
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assign rempty = (rgray == wgray_s2);
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endmodule : gs_async_fifo
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