ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
41 lines
1.7 KiB
Markdown
41 lines
1.7 KiB
Markdown
# rtl/dmac
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EE DMAC. Matches `docs/contracts/dmac.md`.
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## Wave 2 / Wave 2.5 contents
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- `dmac_reg_stub.sv` — channel-2-focused register shell + single-transfer
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state machine. Wave 2.5 revision is memory-backed: DMAC now issues real
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memory reads via the `mem_rd_*` port (connected directly to
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`ee_ram_stub` in the current topology; routing through
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`ee_memory_map_stub` is deferred). State flow: IDLE → FETCH_WAIT →
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ACTIVE_SEND → DONE. MADR is the real fetch source address.
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See `docs/wave25_memory_backed_dma_plan.md`.
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**EE-core chapter 3** added a CPU write path: the EE memory map's
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new `ee_dmac_ch2_wr_*` port drives `reg_wr_en` / `reg_offset` /
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`reg_wr_data`, so the EE core can program MADR/QWC/CHCR from a
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MIPS bootstrap via `SW`.
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**EE-core chapter 4** added a CPU read path (`reg_rd_en` /
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`reg_rd_data` / `reg_rd_valid`, 1-cycle latency) plus a DONE_COUNT
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monotonic counter at offset 0x40. CHCR/MADR/QWC/TADR read back
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their stored values; DONE_COUNT increments each time the state
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machine enters S_DONE. The EE map forwards CPU reads in the same
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DMAC window through a new `ee_dmac_ch2_rd_*` pair, so software
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can now poll CHCR.start or compare DONE_COUNT before/after a
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transfer without needing INTC.
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## Explicit non-goals (Wave 2 / 2.5)
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- Multi-channel arbitration or fairness.
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- Chain mode (normal / chain / interleaved transfer modes).
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- Stall / ring / suspend semantics.
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- Interrupt routing to INTC.
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- QWC > 1 multi-beat transfers (state machine is shaped for it; initial
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signoff is QWC == 1 per Wave 2.5 plan).
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- Routing through `ee_memory_map_stub` (current topology is direct to
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`ee_ram_stub`).
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Each of these is a future-wave concern, not a stub-plan shortcut.
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