thejayman77
ec82764bef
RTL (GS rasterizer, EE core stub, platform bridge, LPDDR4B path), sim regression (272 TBs), docs, and tooling. Copyrighted PS2 content (BIOS, game code, GS dumps, and all dump-derived textures/traces) is excluded via .gitignore and stays local. Co-Authored-By: Claude Opus 4.8 <noreply@anthropic.com>
148 lines
16 KiB
Verilog
148 lines
16 KiB
Verilog
module qsys_top (
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input wire clk_100_clk, // clk_100.clk
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input wire reset_reset_n, // reset.reset_n
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output wire ninit_done_ninit_done, // ninit_done.ninit_done
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output wire h2f_reset_reset, // h2f_reset.reset
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output wire [3:0] subsys_hps_hps2fpga_awid, // subsys_hps_hps2fpga.awid
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output wire [37:0] subsys_hps_hps2fpga_awaddr, // .awaddr
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output wire [7:0] subsys_hps_hps2fpga_awlen, // .awlen
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output wire [2:0] subsys_hps_hps2fpga_awsize, // .awsize
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output wire [1:0] subsys_hps_hps2fpga_awburst, // .awburst
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output wire subsys_hps_hps2fpga_awlock, // .awlock
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output wire [3:0] subsys_hps_hps2fpga_awcache, // .awcache
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output wire [2:0] subsys_hps_hps2fpga_awprot, // .awprot
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output wire subsys_hps_hps2fpga_awvalid, // .awvalid
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input wire subsys_hps_hps2fpga_awready, // .awready
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output wire [127:0] subsys_hps_hps2fpga_wdata, // .wdata
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output wire [15:0] subsys_hps_hps2fpga_wstrb, // .wstrb
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output wire subsys_hps_hps2fpga_wlast, // .wlast
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output wire subsys_hps_hps2fpga_wvalid, // .wvalid
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input wire subsys_hps_hps2fpga_wready, // .wready
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input wire [3:0] subsys_hps_hps2fpga_bid, // .bid
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input wire [1:0] subsys_hps_hps2fpga_bresp, // .bresp
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input wire subsys_hps_hps2fpga_bvalid, // .bvalid
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output wire subsys_hps_hps2fpga_bready, // .bready
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output wire [3:0] subsys_hps_hps2fpga_arid, // .arid
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output wire [37:0] subsys_hps_hps2fpga_araddr, // .araddr
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output wire [7:0] subsys_hps_hps2fpga_arlen, // .arlen
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output wire [2:0] subsys_hps_hps2fpga_arsize, // .arsize
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output wire [1:0] subsys_hps_hps2fpga_arburst, // .arburst
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output wire subsys_hps_hps2fpga_arlock, // .arlock
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output wire [3:0] subsys_hps_hps2fpga_arcache, // .arcache
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output wire [2:0] subsys_hps_hps2fpga_arprot, // .arprot
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output wire subsys_hps_hps2fpga_arvalid, // .arvalid
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input wire subsys_hps_hps2fpga_arready, // .arready
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input wire [3:0] subsys_hps_hps2fpga_rid, // .rid
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input wire [127:0] subsys_hps_hps2fpga_rdata, // .rdata
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input wire [1:0] subsys_hps_hps2fpga_rresp, // .rresp
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input wire subsys_hps_hps2fpga_rlast, // .rlast
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input wire subsys_hps_hps2fpga_rvalid, // .rvalid
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output wire subsys_hps_hps2fpga_rready, // .rready
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output wire subsys_hps_h2f_warm_reset_handshake_reset_req, // subsys_hps_h2f_warm_reset_handshake.reset_req
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input wire subsys_hps_h2f_warm_reset_handshake_reset_ack, // .reset_ack
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input wire hps_io_hps_osc_clk, // hps_io.hps_osc_clk
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inout wire hps_io_sdmmc_data0, // .sdmmc_data0
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inout wire hps_io_sdmmc_data1, // .sdmmc_data1
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output wire hps_io_sdmmc_cclk, // .sdmmc_cclk
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inout wire hps_io_sdmmc_data2, // .sdmmc_data2
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inout wire hps_io_sdmmc_data3, // .sdmmc_data3
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inout wire hps_io_sdmmc_cmd, // .sdmmc_cmd
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input wire hps_io_usb0_clk, // .usb0_clk
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output wire hps_io_usb0_stp, // .usb0_stp
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input wire hps_io_usb0_dir, // .usb0_dir
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inout wire hps_io_usb0_data0, // .usb0_data0
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inout wire hps_io_usb0_data1, // .usb0_data1
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input wire hps_io_usb0_nxt, // .usb0_nxt
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inout wire hps_io_usb0_data2, // .usb0_data2
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inout wire hps_io_usb0_data3, // .usb0_data3
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inout wire hps_io_usb0_data4, // .usb0_data4
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inout wire hps_io_usb0_data5, // .usb0_data5
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inout wire hps_io_usb0_data6, // .usb0_data6
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inout wire hps_io_usb0_data7, // .usb0_data7
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output wire hps_io_emac0_tx_clk, // .emac0_tx_clk
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output wire hps_io_emac0_tx_ctl, // .emac0_tx_ctl
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input wire hps_io_emac0_rx_clk, // .emac0_rx_clk
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input wire hps_io_emac0_rx_ctl, // .emac0_rx_ctl
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output wire hps_io_emac0_txd0, // .emac0_txd0
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output wire hps_io_emac0_txd1, // .emac0_txd1
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input wire hps_io_emac0_rxd0, // .emac0_rxd0
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input wire hps_io_emac0_rxd1, // .emac0_rxd1
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output wire hps_io_emac0_txd2, // .emac0_txd2
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output wire hps_io_emac0_txd3, // .emac0_txd3
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input wire hps_io_emac0_rxd2, // .emac0_rxd2
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input wire hps_io_emac0_rxd3, // .emac0_rxd3
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inout wire hps_io_mdio0_mdio, // .mdio0_mdio
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output wire hps_io_mdio0_mdc, // .mdio0_mdc
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output wire hps_io_uart1_tx, // .uart1_tx
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input wire hps_io_uart1_rx, // .uart1_rx
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inout wire hps_io_i2c1_sda, // .i2c1_sda
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inout wire hps_io_i2c1_scl, // .i2c1_scl
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inout wire hps_io_gpio28, // .gpio28
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inout wire hps_io_gpio34, // .gpio34
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inout wire hps_io_gpio40, // .gpio40
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inout wire hps_io_gpio41, // .gpio41
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input wire [31:0] f2h_irq1_in_irq, // f2h_irq1_in.irq
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input wire [31:0] f2sdram_araddr, // f2sdram.araddr
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input wire [1:0] f2sdram_arburst, // .arburst
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input wire [3:0] f2sdram_arcache, // .arcache
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input wire [4:0] f2sdram_arid, // .arid
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input wire [7:0] f2sdram_arlen, // .arlen
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input wire f2sdram_arlock, // .arlock
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input wire [2:0] f2sdram_arprot, // .arprot
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input wire [3:0] f2sdram_arqos, // .arqos
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output wire f2sdram_arready, // .arready
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input wire [2:0] f2sdram_arsize, // .arsize
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input wire f2sdram_arvalid, // .arvalid
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input wire [31:0] f2sdram_awaddr, // .awaddr
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input wire [1:0] f2sdram_awburst, // .awburst
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input wire [3:0] f2sdram_awcache, // .awcache
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input wire [4:0] f2sdram_awid, // .awid
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input wire [7:0] f2sdram_awlen, // .awlen
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input wire f2sdram_awlock, // .awlock
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input wire [2:0] f2sdram_awprot, // .awprot
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input wire [3:0] f2sdram_awqos, // .awqos
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output wire f2sdram_awready, // .awready
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input wire [2:0] f2sdram_awsize, // .awsize
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input wire f2sdram_awvalid, // .awvalid
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output wire [4:0] f2sdram_bid, // .bid
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input wire f2sdram_bready, // .bready
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output wire [1:0] f2sdram_bresp, // .bresp
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output wire f2sdram_bvalid, // .bvalid
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output wire [255:0] f2sdram_rdata, // .rdata
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output wire [4:0] f2sdram_rid, // .rid
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output wire f2sdram_rlast, // .rlast
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input wire f2sdram_rready, // .rready
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output wire [1:0] f2sdram_rresp, // .rresp
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output wire f2sdram_rvalid, // .rvalid
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input wire [255:0] f2sdram_wdata, // .wdata
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input wire f2sdram_wlast, // .wlast
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output wire f2sdram_wready, // .wready
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input wire [31:0] f2sdram_wstrb, // .wstrb
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input wire f2sdram_wvalid, // .wvalid
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input wire [7:0] f2sdram_aruser, // .aruser
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input wire [7:0] f2sdram_awuser, // .awuser
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input wire [7:0] f2sdram_wuser, // .wuser
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output wire [7:0] f2sdram_buser, // .buser
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input wire [3:0] f2sdram_arregion, // .arregion
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output wire [7:0] f2sdram_ruser, // .ruser
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input wire [3:0] f2sdram_awregion, // .awregion
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output wire [0:0] emif_hps_emif_mem_0_mem_cs, // emif_hps_emif_mem_0.mem_cs
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output wire [5:0] emif_hps_emif_mem_0_mem_ca, // .mem_ca
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output wire [0:0] emif_hps_emif_mem_0_mem_cke, // .mem_cke
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inout wire [31:0] emif_hps_emif_mem_0_mem_dq, // .mem_dq
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inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_t, // .mem_dqs_t
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inout wire [3:0] emif_hps_emif_mem_0_mem_dqs_c, // .mem_dqs_c
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inout wire [3:0] emif_hps_emif_mem_0_mem_dmi, // .mem_dmi
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output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_t, // emif_hps_emif_mem_ck_0.mem_ck_t
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output wire [0:0] emif_hps_emif_mem_ck_0_mem_ck_c, // .mem_ck_c
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output wire emif_hps_emif_mem_reset_n_mem_reset_n, // emif_hps_emif_mem_reset_n.mem_reset_n
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input wire emif_hps_emif_oct_0_oct_rzqin, // emif_hps_emif_oct_0.oct_rzqin
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input wire emif_hps_emif_ref_clk_0_clk, // emif_hps_emif_ref_clk_0.clk
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input wire [3:0] button_pio_external_connection_export, // button_pio_external_connection.export
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input wire [3:0] dipsw_pio_external_connection_export, // dipsw_pio_external_connection.export
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input wire [2:0] led_pio_external_connection_in_port, // led_pio_external_connection.in_port
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output wire [2:0] led_pio_external_connection_out_port // .out_port
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endmodule
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